TW201933586A - Method for manufacturing array substrate - Google Patents

Abstract

A method for manufacturing an array substrate includes forming a transparent conductive material layer on a substrate, wherein the substrate has a pixel region and a peripheral region; patterning the transparent conductive material layer to become a first pattern layer in the pixel region and a second pattern layer in the peripheral region by a first mask; and removing the second pattern layer by a second mask.

Description

Method of manufacturing array substrate

The present invention relates to a method of fabricating an array substrate, and more particularly to a method of fabricating an array substrate using a photomask.

The demand for flat-panel displays (such as liquid crystal displays) has become more and more popular in modern times, and research on array substrates in flat-panel displays is also changing rapidly. Since the transparent conductive oxide material has the advantages of both conductivity and high light transmittance, a transparent conductive oxide material is generally used as a film layer in a part of the array substrate of the flat display, and in the process of manufacturing the array substrate, Whether or not the transparent conductive oxide material meets the requirements of the original circuit design and maintains the excellent operational characteristics of the flat display through appropriate manufacturing methods is still an important factor in determining the quality of the flat display.

Therefore, there is still an urgent need to develop a method of manufacturing an excellent array substrate.

The present disclosure relates to a method of fabricating an array substrate. One embodiment of the present disclosure uses the first reticle and the second reticle to pattern the transparent conductive material layer of the array substrate, reducing the chance of the transparent conductive material layer remaining in the trenches of the peripheral region, compared to the trenches. In the comparative example having the residue of the transparent conductive material layer, the sealant of one embodiment of the present invention has better adhesion to the array substrate, prevents moisture intrusion, and maintains excellent operational characteristics of the flat display.

In accordance with an embodiment of the present disclosure, a method of fabricating an array substrate is provided. The method includes the following steps. First, a layer of transparent conductive material is formed on the substrate, the substrate having a pixel region and a peripheral region. Next, the transparent conductive material layer is patterned by the first photomask into a first pattern layer located in the pixel region and a second pattern layer located in the peripheral region. Thereafter, the second pattern layer is removed by the second mask.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The present disclosure provides a method of fabricating an array substrate. One embodiment of the present disclosure uses a first photomask to pattern a transparent conductive material layer of the array substrate into a first pattern layer and a second pattern layer, and removes a trench located in the peripheral region by the second mask. The second pattern layer prevents the residual layer of the transparent conductive material from remaining in the trench, and the sealant has better adhesion to the array substrate, prevents moisture from invading, and maintains excellent operational characteristics of the flat panel display.

1A, 2A, 3A, 4A, 5A, and 6A are top views of a method of manufacturing the array substrate 100 according to an embodiment of the present disclosure. Figs. 1B, 2B, 3B, 4B, 5B, and 6B are cross-sectional views taken along line A-A' in Figs. 1A, 2A, 3A, 4A, 5A, and 6A, respectively. 2C is a top view of a method of fabricating an array substrate according to still another embodiment of the present disclosure. FIG. 4C is a top view of a method of fabricating an array substrate according to still another embodiment of the present disclosure. Fig. 4D is a cross-sectional view taken along line A-A' in Fig. 4C.

Referring to FIGS. 1A and 1B simultaneously, a substrate 110 having a pixel area AA and a peripheral area AB is provided. The active array layer 120 is formed on the substrate 110. The active array layer 120 corresponds to the pixel area AA, and includes a plurality of data lines, scan lines, and pixel arrays (not shown). The insulating layer 130 is formed on the substrate 110 and covers the active array layer 120. A portion of the insulating layer 130 may be located in the peripheral region AB and may directly contact the substrate 110. The insulating layer 130 may have a multi-layer structure, but is not limited thereto.

Referring to FIGS. 2A and 2B simultaneously, a via hole 130u is formed to expose the active array layer 120, and at least one trench 140 is formed in the insulating layer 130 and located in the sealant region 150 in the peripheral region AB. In one embodiment, the trench 140 includes a first trench 141 and a second trench 142. The width W of the first trench 141 and the second trench 142 may be 10 micrometers to 50 micrometers, and the trench 140 is advantageously disposed. In order to block the invasion of water vapor. In this embodiment, the first trench 141 and the second trench 142 are respectively C-shaped structures. The C-shaped notch portion of the first trench 141 and the second trench 142 corresponds to the spacer 150u of the insulating layer, and the spacer 150u does not have the trench 140, which can provide a space for forming a line. The trench 140 may be a single trench or a plurality of trenches, and the invention is not limited thereto. Please refer to FIG. 2C. In other embodiments, the trench 140 may be a closed ring, but is not limited thereto.

Referring to FIGS. 3A and 3B, a transparent conductive material layer 160 is formed on the substrate 110 and covers the insulating layer 130. One portion of the transparent conductive material layer 160 is filled in the via hole 130u to be electrically connected to the active array layer 120. A crystal (not shown), another portion of the transparent conductive material layer 160 is filled in the trench 140. The material of the transparent conductive material layer 160 is, for example, indium tin oxide. A photoresist layer (not shown) may be formed on the transparent conductive material layer 160 to facilitate subsequent patterning processes.

Referring to FIGS. 4A and 4B simultaneously, the transparent conductive material layer 160 is patterned by the first mask 170 into a first pattern layer 161 located in the pixel area AA and a second pattern layer 162 located in the peripheral area AB. For example, the first pattern layer 161 includes a plurality of pixel electrodes PE1, PE2, PE3, PE4, PE5, and PE6 respectively connected to the corresponding transistor of the active array layer 120 through the via hole 130u. For example, only six pixel electrodes are drawn, but not limited thereto. At least a portion of the second pattern layer 162 is located within the trench 140. Referring to FIG. 2A, FIG. 4A and FIG. 4B, the area occupied by the second pattern layer 162 in the sealant region 150 is the total area of the sealant region 150 (including the second pattern layer 162 and the second layer). The ratio of the area of the pattern layer 162 is about 2% to 6%, or about 2.65% to 5.33%. In the present embodiment, the first region 171 of the first mask 170 corresponds to the pixel area AA, and the second area 172 corresponds to the peripheral area AB. The first zone 171 and the second zone 172 do not accurately depict the actual exposure pattern. For example, the first region 171 has a pattern in which the first pattern layer 161 can be patterned to include a plurality of pixel electrodes, and a slit (not shown) can be included in the pixel electrode.

In other embodiments, as shown in FIG. 4D, the first mask 270 may have a first region 271 corresponding to the pixel area AA, which differs from the embodiment of FIG. 4B only in that the first mask 270 does not have The second zone 172 corresponds to the peripheral zone AB as in Fig. 4B. The first mask 270 only patterns the transparent conductive material layer 160 located in the pixel area AA by the first region 271 to form the first pattern layer 261, and the second pattern layer 262 substantially covers the peripheral region AB.

Referring to FIG. 4B, FIG. 5A and FIG. 5B simultaneously, the second mask 180 has a second region 182 corresponding to the peripheral region AB, and the second region 182 is exemplified by an opening pattern and overlaps the trench 140 by the second The photomask 180 removes the second pattern layer 162. There is substantially no transparent conductive material remaining in the trench 140, which is beneficial to the subsequent bonding process of the sealant. Since the second mask 180 does not have an opening area corresponding to the pixel area AA, the photoresist in the pixel area AA is not exposed, and the purpose of clearing the second pattern layer 162 is achieved, and the corresponding The layer of transparent conductive material in the pixel area meets the original design requirements, and there is no need to increase the exposure.

Referring to FIG. 2A, FIG. 6A and FIG. 6B, the sealant 190 is formed in the sealant region 150. The sealant region 150 is substantially covered with the sealant 190, and a portion of the sealant 190 is located in the groove 140. Since there is substantially no transparent conductive material in the trench 140, the bonding degree between the sealant 190 and the array substrate 100 can be increased, and the array substrate 100 and the upper substrate 210 are closely bonded together by the sealant 190. The upper substrate 210 may include a color filter (not shown).

FIG. 7A is a top view of the first reticle 170 in the method of fabricating the array substrate according to an embodiment of the present disclosure. FIG. 7B is a top view of the second reticle 180 in the method of fabricating the array substrate according to an embodiment of the present disclosure.

Referring to FIG. 7A, the first mask 170 includes a first region 171 corresponding to the pixel area AA and a second region 172 corresponding to the peripheral area AB. The first zone 171 does not accurately depict the actual exposure pattern. In this embodiment, the second region 172 includes a first sub-region 172a adjacent to the pixel region AA and a second sub-region 172b remote from the pixel region AA. The first sub-region 172a is substantially located in the pixel region AA and the second region. Between the sub-regions 172b, the first sub-region 172a and the second sub-region 172b are both open patterns, and the first sub-region 172a and the second sub-region 172b may each be C-shaped.

Referring to FIG. 7B, the second reticle 180 includes a first region 181 corresponding to the pixel area AA and a second region 182 corresponding to the peripheral area AB. In the present embodiment, the first region 181 is exemplified by a light shielding pattern, and the second region 182 includes a first sub-region 182a near the pixel region AA and a second sub-region 182b away from the pixel region AA, and the first sub-region 182a It is substantially located between the pixel area AA and the second sub-area 182b. The first sub-region 182a and the second sub-region 182b are both open patterns, and the first sub-region 182a and the second sub-region 182b may each be C-shaped. The first sub-region 182a and the second sub-region 182b at least partially overlap the two trenches 140 of the C-shape, respectively, to substantially or completely remove the second pattern layer 162 remaining in the trench 140.

In an embodiment, after the first photomask 170 is used to simultaneously pattern the transparent conductive material layers of the pixel area AA and the peripheral area AB, the second mask layer 162 is used to remove the second pattern layer 162 for the peripheral area AB. .

FIG. 8A is a top view of the first photomask 370 in the method of fabricating the array substrate according to another embodiment of the present disclosure. FIG. 8B is a top view of the second photomask 380 in the method of fabricating the array substrate according to another embodiment of the present disclosure.

Referring to FIG. 8A, similar to the first reticle 170 of FIG. 7A, the first reticle 370 includes a first region 371 and a second region 372. The second sub-area 372 includes a first sub-area 372a and a second sub-area 372b, which are different from the first reticle 170 only in that, in this embodiment, the first sub-area 372a and the second sub-area 372b are closed loops. .

Referring to FIG. 8B, similar to the second reticle 180 of FIG. 7B, the second reticle 380 includes a first region 381 and a second region 382, and the second region 382 includes a first sub-region 382a and a second sub-region 382b. The difference from the second mask 180 is that, in the embodiment, the first sub-region 382a and the second sub-region 382b are both closed loops.

In an embodiment, after the first photomask 370 is used to simultaneously pattern the transparent conductive material layers of the pixel area AA and the peripheral area AB, the second mask layer is used to remove the second pattern layer for the peripheral area AB.

FIG. 9 is a top view of the first photomask 270 in the method of fabricating the array substrate according to still another embodiment of the present disclosure.

Referring to FIG. 9, the first mask 270 has a first area 271 corresponding to the pixel area AA. For convenience of explanation, the first area 271 does not show a detailed opening pattern to indicate the exposure range, and corresponds to the peripheral area AB. The second zone 272 does not have an opening pattern.

In the present embodiment, the photoresist in the pixel region AA may be patterned using the first mask 270, and then the second mask 180 or 380 as shown in FIG. 7B or FIG. 8B may be used for the peripheral region AB. The step of removing the second pattern layer 162 or 262.

The present disclosure provides a method of fabricating an array substrate. In one embodiment of the present disclosure, the transparent conductive material is patterned and removed by two different masks, and the transparent conductive material layer corresponding to the pixel region can meet the original design requirements without increasing the exposure amount. On the other hand, since the transparent conductive material layer is not substantially left in the trench, the adhesive between the sealant and the insulating layer of the array substrate is better, so that the sealant is closely adhered between the upper substrate and the array substrate. To prevent moisture intrusion and avoid corrosion of the line, and to maintain the excellent operating characteristics of the flat panel display.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Array substrate

110‧‧‧Base

120‧‧‧Active array layer

130‧‧‧Insulation

130u‧‧‧through hole

140, 240‧‧‧ trench

141‧‧‧First trench

142‧‧‧Second trench

150‧‧‧Blocking area

150u‧‧‧spaced area

160‧‧‧Transparent conductive material layer

161, ‧ ‧ ‧ first pattern layer

162, 262‧‧‧ second pattern layer

170, 270, 370‧‧‧ first mask

171, 271, 181, 371, 381‧ ‧ first district

172, 272, 182, 372, 382‧‧‧ second district

172a, 182a, 372a, 382a‧‧‧ first sub-area

172b, 182b, 372b, 382b‧‧‧ second sub-area

180, 380‧‧‧ second mask

190‧‧‧Box glue

210‧‧‧Upper substrate

AA‧‧‧画素区

AB‧‧‧ surrounding area

PE1, PE2, PE3, PE4, PE5, PE6‧‧‧ pixel electrodes

W‧‧‧Width

1A, 2A, 3A, 4A, 5A, and 6A are top views of a method of fabricating an array substrate according to an embodiment of the present disclosure. Figs. 1B, 2B, 3B, 4B, 5B, and 6B are cross-sectional views taken along line A-A' in Figs. 1A, 2A, 3A, 4A, 5A, and 6A, respectively. 2C is a top view of a method of fabricating an array substrate according to still another embodiment of the present disclosure. FIG. 4C is a top view of a method of fabricating an array substrate according to still another embodiment of the present disclosure. Fig. 4D is a cross-sectional view taken along line A-A' in Fig. 4C. FIG. 7A is a top view of a first photomask in a method of fabricating an array substrate according to an embodiment of the present disclosure. FIG. 7B is a top view of a second photomask in a method of fabricating an array substrate according to an embodiment of the present disclosure. 8A is a top view of a first photomask in a method of fabricating an array substrate according to another embodiment of the present disclosure. FIG. 8B is a top view of the second photomask in the method of manufacturing the array substrate according to another embodiment of the present disclosure. FIG. 9 is a top view of a first photomask in a method of fabricating an array substrate according to still another embodiment of the present disclosure.

Claims (10)

A method of fabricating an array substrate, comprising: forming a transparent conductive material layer on a substrate, the substrate having a pixel region and a peripheral region; patterning the transparent conductive material layer by a first mask: a first pattern layer in the pixel region; and a second pattern layer in the peripheral region; and removing the second pattern layer by a second mask. The method of manufacturing an array substrate according to claim 1, wherein before the forming the transparent conductive material layer, the method further comprises: forming an insulating layer on the substrate; and forming at least one trench in the insulating layer And located in one of the surrounding areas of the seal area. The method for manufacturing an array substrate according to claim 2, further comprising: forming a sealant in the sealant region, and one portion of the sealant is located in the trench. The method of manufacturing an array substrate according to claim 2, wherein at least a portion of the second pattern layer is located in the trench. The method of manufacturing an array substrate according to claim 4, wherein the second pattern layer in the sealant region occupies an area ratio of about 2% to 6%. The method of manufacturing an array substrate according to claim 2, wherein before the forming the trench, the method further comprises: forming an active array layer on the substrate. The method of manufacturing an array substrate according to claim 6, wherein the first pattern layer is a pixel electrode electrically connected to a transistor in the active array layer. The method of manufacturing an array substrate according to claim 2, wherein a part of the opening area of the second mask overlaps the groove. The method of manufacturing an array substrate according to claim 2, wherein the groove has a C-shape or a closed ring shape. The method of manufacturing an array substrate according to claim 1, wherein the second pattern layer substantially completely covers the peripheral region before the step of removing the second pattern layer by the second mask.