TW201921824A - High surge transient voltage suppressor cross reference to other applications - Google Patents
High surge transient voltage suppressor cross reference to other applicationsInfo
- Publication number
- TW201921824A TW201921824A TW107134144A TW107134144A TW201921824A TW 201921824 A TW201921824 A TW 201921824A TW 107134144 A TW107134144 A TW 107134144A TW 107134144 A TW107134144 A TW 107134144A TW 201921824 A TW201921824 A TW 201921824A
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- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
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- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
Abstract
Description
本發明涉及一種高突波瞬變電壓抑制器。The invention relates to a high surge transient voltage suppressor.
電壓和電流瞬變是造成電子系統中積體電路故障的主要原因。瞬變由系統內部和外部的各種來源產生。例如，造成瞬變的常見來源包括電源的正常開關操作、交流線路波動、閃電瞬變和電磁放電(ESD)。Voltage and current transients are the main causes of integrated circuit failures in electronic systems. Transients are generated by various sources inside and outside the system. For example, common sources of transients include normal switching operations of power supplies, AC line fluctuations, lightning transients, and electromagnetic discharge (ESD).
瞬變電壓抑制器(TVS)是常用於保護積體電路不被積體電路發生的瞬變或過電壓造成損壞的獨立元件。過電壓保護對於消費類元件或物聯網元件來說非常重要，因為這些元件經常面臨頻繁的人工操作，因此非常容易受ESD或瞬變電壓等影響而使元件受損。Transient voltage suppressor (TVS) is an independent component commonly used to protect integrated circuits from damage caused by transients or overvoltages that occur in integrated circuits. Overvoltage protection is very important for consumer or IoT components, because these components often face frequent manual operations, so they are very susceptible to damage from ESD or transient voltages.
確切地說，電子元件的電源引腳和數據引腳都需要保護，以免受到ESD或開關和閃電瞬變情況的過電壓影響。通常來說，電源引腳需要很高的突波保護，但是可以承受較高電容的保護元件。同時，可以在很高的數據速度下運行的數據引腳，需要保護元件可以提供帶有低電容的突波保護，從而不會影響受保護數據引腳的數據速度。Specifically, both the power and data pins of electronic components need to be protected from ESD or overvoltages from switching and lightning transient conditions. In general, power pins require high surge protection, but can withstand higher capacitance protection components. At the same time, data pins that can operate at very high data speeds need protection components that can provide surge protection with low capacitance, so as not to affect the data speed of the protected data pins.
用於高突波應用的現有的TVS保護電路，在開路基極結構中使用垂直的NPN或PNP雙極電晶體結構，以便雙向閉鎖。當利用TVS保護電源線時，TVS擁有很低的漏電流是非常重要的。流經TVS保護電路的漏電流會產生不必要的功率耗散。現有的高突波TVS保護電路藉由提高雙極電晶體的基極摻雜水平，降低了漏電流。然而，提高基極摻雜會增大雙極電晶體的增益，由於較低的雙極注入效率，而降低鉗位電壓。Existing TVS protection circuits for high surge applications use vertical NPN or PNP bipolar transistor structures in an open-circuit base structure for bidirectional latch-up. When TVS is used to protect the power line, it is very important for TVS to have very low leakage current. Leakage current flowing through the TVS protection circuit will cause unnecessary power dissipation. The existing high surge TVS protection circuit reduces the leakage current by increasing the base doping level of the bipolar transistor. However, increasing the base doping will increase the gain of the bipolar transistor and lower the clamping voltage due to the lower bipolar injection efficiency.
本發明的目的在於提供一種高突波瞬變電壓抑制器，解決習知技術存在的問題。The purpose of the present invention is to provide a high surge transient voltage suppressor, which solves the problems existing in the conventional technology.
本發明的技術方案提供了一種瞬變電壓抑制器，其包括：第一導電類型的半導體基板，半導體基板為重摻雜；第一導電類型的第一外延層，形成在半導體基板上，第一外延層具有第一厚度；第二導電類型的第二外延層，形成在第一外延層上，第二導電類型與第一導電類型相反；第一導電類型的第一掩埋層以及第二導電類型的第二掩埋層形成在第一外延層中，延伸到第二外延層，第二掩埋層形成在瞬變電壓抑制器的中心部分；第二導電類型的第一本體區，形成在瞬變電壓抑制器中心部分的第二外延層的第一表面上；第一導電類型的第一重摻雜區，形成在第二外延層第一表面上的第一本體區中；以及第二導電類型的第三掩埋層的區域，形成在第一外延層中，從第二掩埋層開始延伸到半導體基板，第三掩埋層的區域位於瞬變電壓抑制器的中心部分，在第一重摻雜區下方，其中半導體基板連接到第一電極，第一重摻雜區連接到瞬變電壓抑制器的第二電極。The technical solution of the present invention provides a transient voltage suppressor, which includes: a semiconductor substrate of a first conductivity type, the semiconductor substrate is heavily doped; a first epitaxial layer of a first conductivity type is formed on the semiconductor substrate, and the first epitaxy The layer has a first thickness; a second epitaxial layer of the second conductivity type is formed on the first epitaxial layer, the second conductivity type is opposite to the first conductivity type; the first buried layer of the first conductivity type and the The second buried layer is formed in the first epitaxial layer and extends to the second epitaxial layer. The second buried layer is formed in the center portion of the transient voltage suppressor; the first body region of the second conductivity type is formed in the transient voltage suppression On the first surface of the second epitaxial layer in the center portion of the device; the first heavily doped region of the first conductivity type is formed in the first body region on the first surface of the second epitaxial layer; The area of the three buried layers is formed in the first epitaxial layer and extends from the second buried layer to the semiconductor substrate. The area of the third buried layer is located in the center portion of the transient voltage suppressor. Below the heavily doped region, wherein the semiconductor substrate is connected to a first electrode, a first heavily doped region is connected to the second electrode of the transient voltage suppressor.
可選地，第一掩埋層形成在第二掩埋層外圍附近並且包圍著第二掩埋層。Optionally, the first buried layer is formed near the periphery of the second buried layer and surrounds the second buried layer.
可選地，第二掩埋層形成在第一外延層中比第一掩埋層的結深度更深的結深處。Optionally, the second buried layer is formed at a junction depth that is deeper in the first epitaxial layer than the junction depth of the first buried layer.
可選地，第三掩埋層和半導體基板構成一個集電極-基極結，其中第一擊穿電壓低於第二掩埋層和半導體基板的結處的擊穿電壓。Optionally, the third buried layer and the semiconductor substrate form a collector-base junction, wherein the first breakdown voltage is lower than the breakdown voltage at the junction of the second buried layer and the semiconductor substrate.
可選地，所述的瞬變電壓抑制器進一步包括：第二導電類型的第二本體區，形成在第一重摻雜區和第一本體區的結處，第二本體區比第一本體區更加重摻雜。Optionally, the transient voltage suppressor further includes: a second body region of a second conductivity type formed at a junction between the first heavily doped region and the first body region, and the second body region is smaller than the first body region. The regions are more heavily doped.
可選地，第二本體區和第三掩埋層的區域在瞬變電壓抑制器中心部分的水平方向上空間分佈，水平方向平行於第二外延層的第一表面。Optionally, the second body region and the region of the third buried layer are spatially distributed in a horizontal direction of the center portion of the transient voltage suppressor, and the horizontal direction is parallel to the first surface of the second epitaxial layer.
可選地，選擇第三掩埋層的摻雜水平，使瞬變電壓抑制器的擊穿電壓在正向尖峰方向上優化，選擇第二本體區的摻雜水平，使瞬變電壓抑制器的閉鎖電壓在反向尖峰方向上優化。Optionally, the doping level of the third buried layer is selected to optimize the breakdown voltage of the transient voltage suppressor in the forward spike direction, and the doping level of the second body region is selected to lock the transient voltage suppressor. The voltage is optimized in the reverse spike direction.
可選地，第三掩埋層包括分離的第一複數個摻雜區，分佈在第二掩埋層和半導體基板的結處，第二本體區包括分離的第二複數個摻雜區，分佈在第一重摻雜區和第一本體區的結處，第一複數個摻雜區與第二複數個摻雜區在瞬變電壓抑制器中心部分的水平方向上交替分開。Optionally, the third buried layer includes separated first plurality of doped regions distributed at the junction of the second buried layer and the semiconductor substrate, and the second body region includes separated second plurality of doped regions distributed in the first At the junction of the heavily doped region and the first body region, the first plurality of doped regions and the second plurality of doped regions are alternately separated in the horizontal direction of the center portion of the transient voltage suppressor.
可選地，第一複數個摻雜區和第二複數個摻雜區形成帶狀，第一複數個摻雜區和第二複數個摻雜區在瞬變電壓抑制器的中心部分形成交替的帶狀。Optionally, the first plurality of doped regions and the second plurality of doped regions form a band shape, and the first plurality of doped regions and the second plurality of doped regions form an alternating pattern at the center portion of the transient voltage suppressor Ribbon.
可選地，第一複數個摻雜區和第二複數個摻雜區作為中心圓，第一複數個摻雜區和第二複數個摻雜區在瞬變電壓抑制器的中心部分形成交替圓。Optionally, the first plurality of doped regions and the second plurality of doped regions serve as a center circle, and the first plurality of doped regions and the second plurality of doped regions form an alternating circle at a center portion of the transient voltage suppressor. .
可選地，所述的瞬變電壓抑制器，進一步包括：第一溝槽隔離結構，包圍著瞬變電壓抑制器的主動區，以提供瞬變電壓抑制器的隔離。Optionally, the transient voltage suppressor further includes: a first trench isolation structure surrounding an active region of the transient voltage suppressor to provide isolation of the transient voltage suppressor.
可選地，第一溝槽隔離結構包括形成溝槽，延伸到第一掩埋層。Optionally, the first trench isolation structure includes forming a trench extending to the first buried layer.
可選地，所述的瞬變電壓抑制器進一步包括：第一導電類型的沉降區，形成在瞬變電壓抑制器的主動區中，靠近第一溝槽隔離結構，沉降區延伸到第一掩埋層；以及第二導電類型的第二重摻雜區，形成在第二外延層的第一表面上，並且與沉降區交界。Optionally, the transient voltage suppressor further includes: a first conductive type subsidence region formed in an active region of the transient voltage suppressor, close to the first trench isolation structure, and the subsidence region extends to the first burial Layer; and a second heavily doped region of the second conductivity type, formed on the first surface of the second epitaxial layer and bordering the sinker region.
可選地，所述的瞬變電壓抑制器進一步包括：第二溝槽隔離結構，形成在瞬變電壓抑制器的主動區中，包圍著瞬變電壓抑制器的一部分主動區，第二溝槽隔離結構形成在沉降區和第一重摻雜區之間，沉降區形成在第一溝槽隔離結構和第二溝槽隔離結構之間，其中第二溝槽隔離結構保護瞬變電壓抑制器不受來自沉降區和第二重摻雜區之間的結的橫向注入的影響。Optionally, the transient voltage suppressor further includes: a second trench isolation structure formed in an active region of the transient voltage suppressor, surrounding a portion of the active region of the transient voltage suppressor, the second trench An isolation structure is formed between the settlement region and the first heavily doped region, and the settlement region is formed between the first trench isolation structure and the second trench isolation structure, wherein the second trench isolation structure protects the transient voltage suppressor from Affected by lateral implantation from the junction between the sinker region and the second heavily doped region.
可選地，第二溝槽隔離結構包括形成溝槽，至少延伸到第二外延層中。Optionally, the second trench isolation structure includes forming a trench extending at least into the second epitaxial layer.
可選地，第二溝槽隔離結構與沉降區分開。Optionally, the second trench isolation structure is distinguished from the settlement.
可選地，沉降區和第二重摻雜區形成在距離第一重摻雜區第一距離的地方，選擇第一距離，以保護瞬變電壓抑制器不受沉降區和第二重摻雜區之間的結的橫向注入的影響。Optionally, the subsidence region and the second heavily doped region are formed at a first distance from the first heavily doped region, and the first distance is selected to protect the transient voltage suppressor from the subsided region and the second heavily doped region. Effects of lateral implantation of junctions between regions.
可選地，第二導電類型的第二重摻雜區電連接到瞬變電壓抑制器的第二電極。Optionally, the second heavily doped region of the second conductivity type is electrically connected to the second electrode of the transient voltage suppressor.
可選地，第三掩埋層延伸到第一掩埋層，形成在第二掩埋層外圍附近，並且包圍著第二掩埋層。Optionally, the third buried layer extends to the first buried layer, is formed near the periphery of the second buried layer, and surrounds the second buried layer.
可選地，所述的瞬變電壓抑制器進一步包括：第二導電類型的第二本體區，形成在第二重摻雜區和第一本體區的結處，第二本體區比第一本體區更加重摻雜，第二本體區與沉降區交界。Optionally, the transient voltage suppressor further includes: a second body region of a second conductivity type formed at a junction between the second heavily doped region and the first body region, the second body region being smaller than the first body region The region is more heavily doped, and the second body region and the subsidence region border.
可選地，選擇第三掩埋層的摻雜水平，以優化瞬變電壓抑制器在正向尖峰方向上的擊穿電壓，選擇第二本體區的摻雜水平，以優化瞬變電壓抑制器在反向尖峰方向上的閉鎖電壓。Optionally, the doping level of the third buried layer is selected to optimize the breakdown voltage of the transient voltage suppressor in the forward spike direction, and the doping level of the second body region is selected to optimize the transient voltage suppressor at Latch-up voltage in reverse spike direction.
可選地，所述的瞬變電壓抑制器進一步包括：第二溝槽隔離結構，形成在瞬變電壓抑制器的主動區中，包圍著瞬變電壓抑制器的一部分主動區，第二溝槽隔離結構形成在沉降區和第一重摻雜區之間，沉降區形成在第一溝槽隔離結構和第二溝槽隔離結構之間，其中第一溝槽隔離結構包括形成溝槽，延伸到第一掩埋層的一部分，第二溝槽隔離結構包括形成溝槽，延伸到第一掩埋層的另一部分。Optionally, the transient voltage suppressor further includes: a second trench isolation structure formed in an active region of the transient voltage suppressor, surrounding a portion of the active region of the transient voltage suppressor, the second trench An isolation structure is formed between the settlement region and the first heavily doped region, and the settlement region is formed between the first trench isolation structure and the second trench isolation structure, wherein the first trench isolation structure includes forming a trench extending to A portion of the first buried layer and the second trench isolation structure include forming a trench extending to another portion of the first buried layer.
可選地，第一掩埋層形成在第一外延層中，比第二掩埋層的結深度更淺的地方。Optionally, the first buried layer is formed in the first epitaxial layer at a shallower depth than the junction depth of the second buried layer.
可選地，第一掩埋層延伸到半導體基板中。Optionally, the first buried layer extends into the semiconductor substrate.
本發明的技術方案提供一種瞬變電壓抑制器，其包括：第一導電類型的半導體基板，半導體基板為重摻雜；第一導電類型的第一外延層，形成在半導體基板上，第一外延層具有第一厚度；第二導電類型的第一摻雜區，形成在第一外延層中，第二導電類型與第一導電類型相反，第一摻雜區至少形成在瞬變電壓抑制器的中心部分；第一導電類型的第一重摻雜區，形成在第一摻雜區中，在第一外延層的第一表面上；第二導電類型的第一本體區，形成在第一重摻雜區和第一摻雜區的結處，第一本體區比第一摻雜區更加重摻雜；以及第二導電類型的第二摻雜區，形成在第一外延層中，從第一摻雜區延伸到半導體基板，第二摻雜區位於瞬變電壓抑制器的中心部分，在第一重摻雜區下方，第一本體區和第二摻雜區在瞬變電壓抑制器中心部分的水平方向上空間分佈，水平方向平行於第一外延層的第一表面，其中半導體基板連接到第一電極，第一重摻雜區連接到瞬變電壓抑制器的第二電極。The technical solution of the present invention provides a transient voltage suppressor, which includes: a semiconductor substrate of a first conductivity type, the semiconductor substrate is heavily doped; a first epitaxial layer of the first conductivity type is formed on the semiconductor substrate, and the first epitaxial layer Has a first thickness; a first doped region of a second conductivity type is formed in the first epitaxial layer, the second conductivity type is opposite to the first conductivity type, and the first doped region is formed at least in the center of the transient voltage suppressor Part; a first heavily doped region of the first conductivity type is formed in the first doped region on the first surface of the first epitaxial layer; a first body region of the second conductivity type is formed in the first heavily doped region At the junction of the doped region and the first doped region, the first body region is more heavily doped than the first doped region; and a second doped region of the second conductivity type is formed in the first epitaxial layer from the first The doped region extends to the semiconductor substrate, the second doped region is located in the center portion of the transient voltage suppressor, and under the first heavily doped region, the first body region and the second doped region are in the center portion of the transient voltage suppressor Spatial distribution in the horizontal direction A horizontal direction parallel to the first surface of the first epitaxial layer, wherein the semiconductor substrate is connected to a first electrode, a first heavily doped region is connected to the second electrode of the transient voltage suppressor.
可選地，第一摻雜區包括第二導電類型的全面摻雜區。Optionally, the first doped region includes a fully doped region of the second conductivity type.
可選地，第一摻雜區包括第二導電類型的第一掩埋層，形成在半導體基板上，以及第二導電類型的第二本體區，形成在第一掩埋層上，第二本體區比第一本體區更加重摻雜，第一重摻雜區形成在第二本體區中。Optionally, the first doped region includes a first buried layer of a second conductivity type formed on a semiconductor substrate, and a second body region of a second conductivity type is formed on the first buried layer. The first body region is more heavily doped, and the first heavily doped region is formed in the second body region.
可選地，第二摻雜區包括第二導電類型的第二掩埋層區，第二掩埋層區從第一掩埋層開始延伸到半導體基板中。Optionally, the second doped region includes a second buried layer region of a second conductivity type, and the second buried layer region extends from the first buried layer into the semiconductor substrate.
可選地，所述的瞬變電壓抑制器進一步包括：形成第一溝槽隔離結構，包圍著瞬變電壓抑制器的主動區，以提供瞬變電壓抑制器的隔離。Optionally, the transient voltage suppressor further includes: forming a first trench isolation structure, surrounding the active region of the transient voltage suppressor to provide isolation of the transient voltage suppressor.
本發明的技術方案提供一種瞬變電壓抑制器元件，其包括：第一導電類型的半導體基板，半導體基板為重摻雜；第一導電類型的第一外延層，形成在半導體基板上，第一外延層具有第一厚度；第二導電類型的第一摻雜區，形成在第一外延層中，第二導電類型與第一導電類型相反，第一摻雜區至少形成在瞬變電壓抑制器的中心部分；第一導電類型的第一重摻雜區，形成在第一摻雜區中，在第一外延層的第一表面上；第二導電類型的第二摻雜區，從第一摻雜區開始延伸到半導體基板中，第二摻雜區位於瞬變電壓抑制器的主動區中，並且第二摻雜區比第一摻雜區更加重摻雜；第二導電類型的第二重摻雜區，形成在第一外延層的第一表面上，並且與第一重摻雜區分隔開，第二重摻雜區短接至第一重摻雜區；以及第二導電類型的第一本體區，形成在第二重摻雜區和第一摻雜區的結處，第一本體區比第一摻雜區更加重摻雜。The technical solution of the present invention provides a transient voltage suppressor element, which includes: a semiconductor substrate of a first conductivity type, the semiconductor substrate is heavily doped; a first epitaxial layer of a first conductivity type is formed on the semiconductor substrate, and the first epitaxy The layer has a first thickness; a first doped region of a second conductivity type is formed in the first epitaxial layer, the second conductivity type is opposite to the first conductivity type, and the first doped region is formed at least on the transient voltage suppressor The central portion; a first heavily doped region of the first conductivity type formed in the first doped region on the first surface of the first epitaxial layer; a second doped region of the second conductivity type from the first doped region The doped region begins to extend into the semiconductor substrate, the second doped region is located in the active region of the transient voltage suppressor, and the second doped region is more heavily doped than the first doped region; the second heavily doped region of the second conductivity type A doped region formed on the first surface of the first epitaxial layer and separated from the first heavily doped region; the second heavily doped region is shorted to the first heavily doped region; A body region formed in the second re-doped Junction region and the first doped region, the first body region is more heavily doped than the first doped region.
可選地，第一摻雜區包括第二導電類型的全面摻雜區。Optionally, the first doped region includes a fully doped region of the second conductivity type.
可選地，第一摻雜區包括第二導電類型的第一掩埋層，形成在半導體基板中，以及第二導電類型的第二本體區，形成在第一掩埋層上，第二本體區比第一本體區更加重摻雜，第一重摻雜區形成在第二本體區中。Optionally, the first doped region includes a first buried layer of a second conductivity type formed in a semiconductor substrate, and a second body region of a second conductivity type is formed on the first buried layer. The first body region is more heavily doped, and the first heavily doped region is formed in the second body region.
可選地，第二摻雜區包括第二導電類型的第二掩埋層的區域，第二掩埋層的區域從第一掩埋層開始延伸到半導體基板中，並且形成在瞬變電壓抑制器的整個主動區中，在第二重摻雜區下方延伸到第一重摻雜區。Optionally, the second doped region includes a region of the second buried layer of the second conductivity type, and the region of the second buried layer extends from the first buried layer into the semiconductor substrate and is formed throughout the transient voltage suppressor. In the active region, it extends below the second heavily doped region to the first heavily doped region.
可選地，選擇第二掩埋層的摻雜水平，以優化瞬變電壓抑制器在正向尖峰方向上的擊穿電壓，選擇第一本體區的摻雜水平，以優化瞬變電壓抑制器在反向尖峰方向上的閉鎖電壓。Optionally, the doping level of the second buried layer is selected to optimize the breakdown voltage of the transient voltage suppressor in the forward spike direction, and the doping level of the first body region is selected to optimize the transient voltage suppressor at Latch-up voltage in reverse spike direction.
可選地，所述的瞬變電壓抑制器進一步包括：形成第一溝槽隔離結構，包圍著瞬變電壓抑制器的主動區，以提供瞬變電壓抑制器的隔離。Optionally, the transient voltage suppressor further includes: forming a first trench isolation structure, surrounding the active region of the transient voltage suppressor to provide isolation of the transient voltage suppressor.
可選地，所述的瞬變電壓抑制器進一步包括：第二溝槽隔離結構，形成在瞬變電壓抑制器的主動區中，包圍著瞬變電壓抑制器的一部分主動區，第二溝槽隔離結構形成在第一重摻雜區和第二重摻雜區之間，第二重摻雜區形成在第一溝槽隔離結構和第二溝槽隔離結構之間。Optionally, the transient voltage suppressor further includes: a second trench isolation structure formed in an active region of the transient voltage suppressor, surrounding a portion of the active region of the transient voltage suppressor, the second trench An isolation structure is formed between the first heavily doped region and the second heavily doped region, and a second heavily doped region is formed between the first trench isolation structure and the second trench isolation structure.
可選地，第二溝槽隔離結構延伸到半導體基板中，以隔離瞬變電壓抑制器的主動區。Optionally, the second trench isolation structure is extended into the semiconductor substrate to isolate the active region of the transient voltage suppressor.
本發明的高突波瞬變電壓抑制器，具有以下效果：一種雙向瞬態電壓抑制器配置成一個NPN雙極電晶體，引入優化的集電極-基極結，實現了雪崩模式擊穿。在某些實施例中，雙向瞬變電壓抑制器配置成一個NPN雙極電晶體，引入單獨優化的集電極-基極和發射極-基極結，帶有空間分佈的優化的結。優化的集電極-基極和發射極-基極結都能實現雪崩模式擊穿，以提高電晶體的擊穿電壓。還可選擇，單向瞬變電壓抑制器配置成一個NPN雙極電晶體，其PN結二極體在反向偏壓方向上並聯到受保護的節點上，並且引入單獨優化的雙極電晶體的集電極-基極結和二極體的p-n結。The high surge transient voltage suppressor of the present invention has the following effects: a bidirectional transient voltage suppressor is configured as an NPN bipolar transistor, and an optimized collector-base junction is introduced to achieve avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is configured as an NPN bipolar transistor, and individually optimized collector-base and emitter-base junctions are introduced with optimized spatially distributed junctions. Both the optimized collector-base and emitter-base junctions can achieve avalanche mode breakdown to increase the breakdown voltage of the transistor. Alternatively, the unidirectional transient voltage suppressor is configured as an NPN bipolar transistor, and its PN junction diode is connected in parallel to the protected node in the reverse bias direction, and a separately optimized bipolar transistor is introduced Collector-base junction and diode pn junction.
本發明可以各種方式實現，包括作為一個技術；一種器件；一個系統；一種物質合成物；一個嵌入在計算機可讀取存儲介質中的計算機程序產品；和/或一個處理器，例如一個對存儲在和/或由耦合到處理器上的內存提供的說明而配置的處理器。在本說明書中，這些實現方式或本發明可能採用的任意一種其他方式，都可以稱為技術。一般來說，可以在本發明的範圍內變換所述技術步驟的順序。除非特別說明，否則處理器或內存等用於進行配置任務的在特定時間臨時配置元件，或用於執行任務而製造的專用元件。文中所用的術語「處理器」是指一種或多種元件、電路和/或處理核心，用於處理計算機程序指令等數據。The invention can be implemented in various ways, including as a technology; a device; a system; a substance composition; a computer program product embedded in a computer-readable storage medium; and / or a processor, such as a And / or a processor configured with instructions provided by memory coupled to the processor. In this specification, these implementation manners or any other manner that the present invention may adopt may be referred to as technologies. In general, the order of the technical steps can be changed within the scope of the invention. Unless otherwise specified, a processor or a memory, such as a processor or a memory, is used to temporarily configure a component at a specific time, or a dedicated component manufactured to perform a task. The term "processor" as used herein refers to one or more components, circuits, and / or processing cores used to process data such as computer program instructions.
本發明的一個或多個實施例的詳細說明以及圖式解釋了本發明的原理。雖然，本發明與這些實施例一起提出，但是本發明的範圍並不局限於任何實施例。本發明的範圍僅由申請專利範圍限定，本發明包含多種可選方案、修正以及等效方案。在以下說明中，所提出的各種具體細節用於全面理解本發明。這些細節用於解釋說明，無需這些詳細細節中的部分細節或全部細節，依據申請專利範圍，就可以實現本發明。為了簡便，本發明相關技術領域中眾所周知的技術材料並沒有詳細說明，以免對本發明產生不必要的混淆。The detailed description and the drawings of one or more embodiments of the invention explain the principles of the invention. Although the present invention is proposed together with these embodiments, the scope of the present invention is not limited to any embodiment. The scope of the present invention is limited only by the scope of the patent application, and the present invention includes various alternatives, modifications, and equivalents. In the following description, various specific details are provided for a comprehensive understanding of the present invention. These details are used for explanation, and some or all of these detailed details are not required, and the present invention can be implemented according to the scope of patent application. For the sake of simplicity, technical materials that are well known in the technical field related to the present invention have not been described in detail, so as not to cause unnecessary confusion to the present invention.
在本發明的實施例中，雙向瞬變電壓抑制器(TVS)包括一個NPN雙極電晶體引入了一個優化的集電極-基極結，實現了雪崩模式擊穿。在一個較佳實施例中，雙向瞬變電壓抑制器(TVS)包括一個NPN雙極電晶體，引入單獨優化的集電極-基極和發射極-基極結，帶有空間分佈的優化結。優化的集電極-基極和發射極-基極結都實現了雪崩模式擊穿，以提高電晶體的擊穿電壓。NPN雙極電晶體是一個開路基極結構，其基極電阻耦合到PN結二極體上，PN結二極體以反向偏置方向耦合到受保護的節點上。在某些實施例中，優化的集電極-基極結將優化的發射極-基極結水平插入到半導體基板中。在這種情況下，TVS元件結構實現了兩個並聯NPN雙極電晶體的等效電路，NPN雙極電晶體的正尖峰電壓和負尖峰電壓進行了單獨優化。本發明所述的雙向TVS元件利用很低的漏電流和穩定的鉗位電壓，實現了雙向高突波保護。另外，本發明所述的雙向TVS實現了可調節的擊穿電壓，允許擊穿電壓對要保護的電子元件做出優化。In the embodiment of the present invention, the bidirectional transient voltage suppressor (TVS) includes an NPN bipolar transistor, and an optimized collector-base junction is introduced to achieve avalanche mode breakdown. In a preferred embodiment, the Bidirectional Transient Voltage Suppressor (TVS) includes an NPN bipolar transistor, introducing individually optimized collector-base and emitter-base junctions with an optimized junction with spatial distribution. Both the optimized collector-base and emitter-base junctions achieve avalanche mode breakdown to increase the breakdown voltage of the transistor. The NPN bipolar transistor is an open-circuited base structure, the base of which is resistively coupled to the PN junction diode, and the PN junction diode is coupled to the protected node in a reverse bias direction. In some embodiments, the optimized collector-base junction inserts the optimized emitter-base junction level into the semiconductor substrate. In this case, the TVS element structure realizes the equivalent circuit of two parallel NPN bipolar transistors, and the positive and negative peak voltages of the NPN bipolar transistors are optimized separately. The bidirectional TVS element according to the present invention utilizes a very low leakage current and a stable clamping voltage to achieve bidirectional high surge protection. In addition, the bidirectional TVS according to the present invention achieves an adjustable breakdown voltage, allowing the breakdown voltage to be optimized for electronic components to be protected.
在本發明的實施例中，單向瞬變電壓抑制器(TVS)配置成一個NPN雙極電晶體，其並聯的PN結二極管與受保護節點的偏置方向相反，並且引入單獨優化的雙極電晶體的集電極-基極結以及二極體的p-n結。NPN雙極電晶體處於開路基極結構中，其基極電阻耦合到參考電勢，PN結二極體的陽極耦合到參考電勢。在這種情況下，TVS元件包括NPN雙極電晶體和PN結二極體，NPN雙極電晶體和PN結二極體都單獨優化，用於正尖峰電壓和負尖峰電壓，兩個電壓都帶有雪崩模式擊穿。本發明所述的單向TVS元件利用很低的漏電流和穩定的鉗位電壓，實現了高突波保護。另外，本發明所述的單向TVS實現了可調節的擊穿電壓，允許擊穿電壓對要保護的電子元件進行優化。In the embodiment of the present invention, the unidirectional transient voltage suppressor (TVS) is configured as an NPN bipolar transistor, the parallel PN junction diode is opposite the bias direction of the protected node, and a separately optimized bipolar is introduced. The collector-base junction of a transistor and the pn junction of a diode. The NPN bipolar transistor is in an open circuit base structure, and its base is resistance-coupled to the reference potential, and the anode of the PN junction diode is coupled to the reference potential. In this case, TVS components include NPN bipolar transistors and PN junction diodes. Both NPN bipolar transistors and PN junction diodes are individually optimized for positive and negative spike voltages. Both voltages are Breakdown with avalanche mode. The unidirectional TVS element according to the present invention utilizes a very low leakage current and a stable clamping voltage to achieve high surge protection. In addition, the unidirectional TVS according to the present invention realizes an adjustable breakdown voltage, allowing the breakdown voltage to optimize the electronic components to be protected.
在本說明書中，瞬變電壓抑制器(TVS)是指耦合的一種保護元件或保護電路，用於保護積體電路節點(受保護的節點)不受過電壓瞬變情況影響，例如電壓突波或電壓尖峰等。當受保護節點上的突波電壓超過TVS元件的擊穿電壓時，TVS元件會將受保護節點上的多餘電流進行分流。TVS元件通常將受保護節點處的電壓鉗位在遠低於電壓突波的電壓值以下的鉗位電壓，同時安全地傳導出突波電流。In this specification, transient voltage suppressor (TVS) refers to a type of protection element or protection circuit coupled to protect integrated circuit nodes (protected nodes) from overvoltage transient conditions, such as voltage surges or Voltage spikes, etc. When the surge voltage on the protected node exceeds the breakdown voltage of the TVS element, the TVS element will shunt the excess current on the protected node. The TVS element usually clamps the voltage at the protected node to a clamping voltage that is well below the voltage value of the voltage surge, while safely conducting a surge current.
TVS元件可以是一個單向元件，也可以是一個雙向元件。單向TVS元件具有一個非對稱的電流-電壓屬性，通常用於保護單向訊號的電路節點——也就是說，訊號始終高於或低於特定的參考電壓，例如地電壓。例如，單向TVS元件可以用於保護常用訊號是從0V到5V正電壓的電路節點。另一方面，雙向TVS元件具有對稱的電流-電壓屬性，通常用於保護雙向訊號的電路節點，或者具有高於和低於參考電壓(例如地電壓)的電壓電平。例如，雙向TVS元件可以用於保護常用訊號在地電壓以上和地電壓以下(從-12V到12V)對稱變化的電路節點。在這種情況下，雙向TVS保護電路節點不受低於-12V或高於12V突波電壓的影響。The TVS element can be a unidirectional element or a bidirectional element. Unidirectional TVS components have an asymmetrical current-voltage property and are usually used to protect the circuit nodes of unidirectional signals-that is, the signal is always above or below a certain reference voltage, such as ground voltage. For example, unidirectional TVS components can be used to protect circuit nodes where the common signal is a positive voltage from 0V to 5V. Bidirectional TVS elements, on the other hand, have symmetrical current-voltage properties and are typically used to protect circuit nodes of bidirectional signals or have voltage levels above and below a reference voltage (such as ground voltage). For example, a two-way TVS element can be used to protect circuit nodes where common signals change symmetrically above and below ground voltage (from -12V to 12V). In this case, the bidirectional TVS protection circuit node is not affected by a surge voltage lower than -12V or higher than 12V.
在運行過程中，當受保護節點處的電壓低於TVS元件的擊穿電壓(有時也稱為反向關斷電壓)時，除了可能的漏電流之外，TVS元件處於閉鎖模式並且不導電。也就是說，當受保護節點處的電壓在受保護節點處的工作電壓範圍內時，除了很低的漏電流之外，TVS元件是不導電的並且處於閉鎖模式。當電壓瞬變時，TVS元件進入導電模式，將電壓鉗制在受保護的節點處，同時傳導與電壓瞬變有關的電流。During operation, when the voltage at the protected node is lower than the breakdown voltage of the TVS element (sometimes referred to as the reverse turn-off voltage), the TVS element is in a latched mode and is not conductive except for possible leakage currents . That is, when the voltage at the protected node is within the operating voltage range at the protected node, in addition to a very low leakage current, the TVS element is non-conductive and is in a latched mode. When a voltage transient occurs, the TVS element enters a conductive mode, clamps the voltage at the protected node, and conducts the current related to the voltage transient.
在一個示例中，受保護的電子元件具有5V的工作電壓，製備TVS期間的擊穿電壓為6至7.5V。因此，受保護節點處的電壓超過6至7.5V的擊穿電壓，將觸發TVS元件傳導來自受保護節點處的電壓，同時將受保護節點處的鉗制在鉗位電壓。在本發明的實施例中，TVS元件的擊穿電壓可以調節，以適應受保護的電子元件的工作電壓值。In one example, the protected electronic component has an operating voltage of 5V, and the breakdown voltage during TVS preparation is 6 to 7.5V. Therefore, the voltage at the protected node exceeds the breakdown voltage of 6 to 7.5V, which will trigger the TVS element to conduct the voltage from the protected node, while clamping the clamped voltage at the protected node. In the embodiment of the present invention, the breakdown voltage of the TVS element can be adjusted to adapt to the working voltage value of the protected electronic element.
在本發明的實施例中，本發明所述的單向或雙向TVS元件耦合到電子元件的受保護節點上，為電子元件提供系統級突波保護。在本說明書中，受保護節點可以是電子元件的電源線或電源引腳，以及電子元件的數據引腳或輸入-輸出(I/O)引腳。在一個示例中，本發明所述的TVS元件耦合到在印刷電路板電平或在電子元件的連接器上的電子元件的電源線或電源引腳上，作為受保護的節點。在另一個示例中，依據國際電工委員會標準IEC 610004-5，規定的高突波保護，以抵抗8us上升時間和20us脈衝寬度的突波脈衝，TVS元件提供高突波保護。In the embodiment of the present invention, the unidirectional or bidirectional TVS element according to the present invention is coupled to the protected node of the electronic component, and provides system-level surge protection for the electronic component. In this specification, the protected node may be a power line or a power pin of an electronic component, and a data pin or an input-output (I / O) pin of the electronic component. In one example, the TVS element according to the present invention is coupled to a power line or power pin of an electronic component at a printed circuit board level or at a connector of the electronic component as a protected node. In another example, according to the International Electrotechnical Commission standard IEC 610004-5, high surge protection is provided to resist surge pulses with 8us rise time and 20us pulse width, and TVS elements provide high surge protection.
第1圖表示在本發明的實施例中，一種單向TVS保護元件1的電路圖。參見第1圖，單向TVS保護元件1(TVS器件)配置成一個NPN雙極結型電晶體(NPN電晶體Q1)，在反向偏壓方向上與一個PN結二極體D1並聯。NPN電晶體Q1的集電極連接到受保護的節點2，而NPN電晶體Q1的發射極連接到參考電勢，通常是地電勢。NPN電晶體Q1處於開路基極結構中，但是NPN電晶體的基極電阻偏置到地電勢。同時，PN結二極體D1具有一個陽極，連接到地電勢，陰極連接到受保護的節點2。受保護的節點2可以是耦合電子元件的一個電源節點或一個數據引腳或I/O引腳。FIG. 1 shows a circuit diagram of a unidirectional TVS protection element 1 in an embodiment of the present invention. Referring to FIG. 1, the unidirectional TVS protection element 1 (TVS device) is configured as an NPN bipolar junction transistor (NPN transistor Q1), and is connected in parallel with a PN junction diode D1 in a reverse bias direction. The collector of NPN transistor Q1 is connected to protected node 2, and the emitter of NPN transistor Q1 is connected to a reference potential, usually a ground potential. The NPN transistor Q1 is in an open circuit base structure, but the base resistance of the NPN transistor is biased to the ground potential. At the same time, the PN junction diode D1 has an anode connected to the ground potential and a cathode connected to the protected node 2. The protected node 2 may be a power node or a data pin or an I / O pin of the coupled electronic component.
第2圖表示在本發明的實施例中，雙向TVS保護元件5的電路圖。參見第2圖，雙向TVS保護元件5(TVS元件)配置成一個NPN雙極結型電晶體(NPN電晶體Q2)，在開路基極結構中，其基極電阻耦合到一個PN結二極體，PN結二極體在反向偏壓方向上連接到受保護節點。NPN電晶體Q2的集電極連接到受保護的節點6，而NPN電晶體Q2的發射極連接到參考電勢，通常是地電勢。NPN電晶體Q2的基極電阻耦合到PN結二極體D2的陽極，二極體D2的陰極連接到受保護的節點6上。受保護的節點6可以是耦合電子元件的一個電源節點或一個數據引腳或I/O引腳。在本發明的實施例中，NPN電晶體Q2的集電極-基極結和發射極-基極結單獨優化，並且空間分佈，以降低NPN雙極電晶體的擊穿電壓觸發，在正向尖峰方向(正尖峰)和反向尖峰方向(負尖峰)上。FIG. 2 shows a circuit diagram of a bidirectional TVS protection element 5 in the embodiment of the present invention. Referring to Fig. 2, the bidirectional TVS protection element 5 (TVS element) is configured as an NPN bipolar junction transistor (NPN transistor Q2). In an open-circuit base structure, its base resistance is coupled to a PN junction diode. The PN junction diode is connected to the protected node in the reverse bias direction. The collector of the NPN transistor Q2 is connected to a protected node 6, and the emitter of the NPN transistor Q2 is connected to a reference potential, usually a ground potential. The base resistance of the NPN transistor Q2 is coupled to the anode of the PN junction diode D2, and the cathode of the diode D2 is connected to the protected node 6. The protected node 6 may be a power node or a data pin or an I / O pin of the coupled electronic component. In the embodiment of the present invention, the collector-base junction and emitter-base junction of the NPN transistor Q2 are individually optimized and spatially distributed to reduce the breakdown voltage of the NPN bipolar transistor. Direction (positive spike) and reverse peak direction (negative spike).
要說明的是，用於製備本發明所述的TVS元件的雙極電晶體結構，本來是對稱的，集電極和發射極端是可以互換的。使用集電極和發射極的說法是指TVS元件的特定電極或端口，僅用於解釋說明，不用於局限。確切地說，如果雙極電晶體端口互換的話，TVS元件在受保護的節點處可以承受正或負瞬變，TVS元件可以對正或負極性的瞬變做出響應。It should be noted that the bipolar transistor structure used to prepare the TVS element according to the present invention is originally symmetrical, and the collector and the emitter are interchangeable. The term collector and emitter is used to refer to a specific electrode or port of a TVS element. It is used for explanation only and not for limitation. Specifically, if the bipolar transistor ports are interchanged, the TVS element can withstand positive or negative transients at the protected node, and the TVS element can respond to positive or negative transients.
第3圖表示依據本發明的第一實施例，帶有空間分佈和單獨優化的集電極-發射極和發射極-基極結的雙向TVS元件10的剖面圖。參見第3圖，雙向TVS元件(TVS元件10)形成在重摻雜的N+基板102上。輕摻雜的N-型外延層(N-外延層104)形成在N+基板102上。N-型掩埋層(NBL)106和P-型掩埋層(PBL)108形成在N-外延層104上。P-型掩埋層108形成在TVS元件10的中心部分或主動區中，而N-型掩埋層106形成在P-型掩埋層108的外圍附近，作為隔離勢壘。在某一實施例中，N-型掩埋層106是利用重N-型摻雜物(例如銻(Sb))製成的，P-型掩埋層108由硼(B)製成的。因此，P-型掩埋層108可以形成在比N-型掩埋層106更深的結深處。FIG. 3 shows a cross-sectional view of a bidirectional TVS element 10 with a spatially distributed and individually optimized collector-emitter and emitter-base junction according to a first embodiment of the present invention. Referring to FIG. 3, a bidirectional TVS element (TVS element 10) is formed on a heavily doped N + substrate 102. A lightly doped N-type epitaxial layer (N-epitaxial layer 104) is formed on the N + substrate 102. An N-type buried layer (NBL) 106 and a P-type buried layer (PBL) 108 are formed on the N-epitaxial layer 104. The P-type buried layer 108 is formed in the center portion or the active region of the TVS element 10, and the N-type buried layer 106 is formed near the periphery of the P-type buried layer 108 as an isolation barrier. In one embodiment, the N-type buried layer 106 is made of a heavy N-type dopant, such as antimony (Sb), and the P-type buried layer 108 is made of boron (B). Therefore, the P-type buried layer 108 may be formed at a deeper junction depth than the N-type buried layer 106.
輕摻雜P-型外延層(P-型外延層112)形成在N-外延層104、N-型掩埋層106以及P-型掩埋層108上。P-本體區114形成在P-型外延層112中，例如藉由離子注入和驅進。P-本體區114比P-型外延層112更加重摻雜。重摻雜N+區116形成在P-本體區114中，以完成NPN雙極電晶體。A lightly doped P-type epitaxial layer (P-type epitaxial layer 112) is formed on the N-epitaxial layer 104, the N-type buried layer 106, and the P-type buried layer 108. A P-body region 114 is formed in the P-type epitaxial layer 112, for example, by ion implantation and driving. The P-body region 114 is more heavily doped than the P-type epitaxial layer 112. A heavily doped N + region 116 is formed in the P-body region 114 to complete the NPN bipolar transistor.
這樣一來，TVS元件10配置成一個NPN雙極電晶體，包括一個由N+基板102形成的集電極、一個由P-型掩埋層108、P-型外延層112和P-本體區114形成的基極以及一個由N+區116形成的發射極。電介質層118形成在半導體結構上方，以覆蓋和保護半導體元件。一個開口形成在電介質層118中，一個發射極電極形成在開口中，用於與N+區116形成歐姆接觸。用於與N+基板102形成電接觸的集電極電極，也形成在基板背面。發射極電極和集電極電極通常由金屬層等導電材料製成。在本發明的實施例中，集電極和發射極電極可以互換，也可以指TVS元件10的第一電極和第二電極。In this way, the TVS element 10 is configured as an NPN bipolar transistor, including a collector formed by an N + substrate 102, a P-type buried layer 108, a P-type epitaxial layer 112, and a P-body region 114. A base and an emitter formed by the N + region 116. A dielectric layer 118 is formed over the semiconductor structure to cover and protect the semiconductor elements. An opening is formed in the dielectric layer 118 and an emitter electrode is formed in the opening for forming an ohmic contact with the N + region 116. A collector electrode for making electrical contact with the N + substrate 102 is also formed on the back surface of the substrate. Emitter and collector electrodes are usually made of a conductive material such as a metal layer. In the embodiment of the present invention, the collector electrode and the emitter electrode may be interchanged, and may also refer to the first electrode and the second electrode of the TVS element 10.
在本說明書中，TVS元件10由溝槽隔離結構111隔開，使得相同的TVS元件10的一個陣列可以形成在基板上，或者TVS元件10可以帶有其他元件，以實現積體電路所需的保護電路。在本實施例中，製備一個延伸到N-型掩埋層106上的溝槽隔離結構111，以隔離TVS元件10，溝槽內襯氧化層109，並用多晶矽層110填充。在其他實施例中，可以使用氧化物填充溝槽隔離結構111。在第3圖中，兩個溝槽隔離結構111表示在TVS元件10的兩邊上。在實際的結構中，溝槽隔離結構111可以是一個單獨的溝槽隔離結構111，包圍著TVS元件10的中心部分和主動區。In this specification, the TVS elements 10 are separated by a trench isolation structure 111, so that an array of the same TVS elements 10 can be formed on a substrate, or the TVS elements 10 can be provided with other elements to implement the integrated circuit. protect the circuit. In this embodiment, a trench isolation structure 111 extending to the N-type buried layer 106 is prepared to isolate the TVS element 10, the trench is lined with an oxide layer 109, and is filled with a polycrystalline silicon layer 110. In other embodiments, the trench isolation structure 111 may be filled with an oxide. In FIG. 3, two trench isolation structures 111 are shown on both sides of the TVS element 10. In an actual structure, the trench isolation structure 111 may be a single trench isolation structure 111 that surrounds the central portion and the active area of the TVS element 10.
TVS元件10進一步包括N+沉降區128，以便將N-型掩埋層106連接到形成在半導體結構表面上的一個重摻雜的P+區126上。P+區126保持浮動，或者沒有電連接到或偏置到任意電勢上。藉由使用N+沉降區128，集電極-基極結擊穿被提高到半導體結構的背面，在N+沉降區128和P+區126之間的結合處。確切地說，隨著受保護節點120比參考節點122更加正向偏置，N+沉降區128到P+區126結決定了正向尖峰方向上的擊穿電壓，參考節點122處於本實施例中的地電勢。在第3圖中，兩個N+沉降區128和P+區126可以是一個單獨結構，包圍著TVS元件10的中心部分或主動區。The TVS element 10 further includes an N + sinker region 128 to connect the N-type buried layer 106 to a heavily doped P + region 126 formed on the surface of the semiconductor structure. The P + region 126 remains floating or is not electrically connected or biased to any potential. By using the N + sinker region 128, the collector-base junction breakdown is improved to the back of the semiconductor structure at the junction between the N + sinker region 128 and the P + region 126. Specifically, as the protected node 120 is more forward-biased than the reference node 122, the junction between the N + subsidence region 128 and the P + region 126 determines the breakdown voltage in the forward spike direction. The reference node 122 is in this embodiment. Ground potential. In FIG. 3, the two N + settling regions 128 and the P + region 126 may be a single structure, surrounding the central portion or the active region of the TVS element 10.
在TVS元件10中，N+沉降區128形成在TVS元件10的外圍，額外的溝槽隔離結構130用於使N+沉降區128與TVS元件10的主動區隔離，TVS元件10的主動區由N+區116限定。溝槽隔離結構130用於終止N+沉降區128/P+區126結橫向注入到TVS元件10的發射極-基極區中。在本實施例中，溝槽隔離結構130是帶有電介質側壁的多晶矽填充溝槽。在其他實施例中，溝槽隔離結構130可以是氧化物填充溝槽。然而，在另一個實施例中，水平隔離可以藉由增大N+沉降區128和N+區116之間的距離完成，代替使用溝槽隔離。使用溝槽隔離結構130是可選的，在其他實施例中可以省略。另外，溝槽隔離結構130可以作為單獨的溝槽隔離結構130，包圍著TVS元件10的主動區的內部。In the TVS element 10, an N + subsidence region 128 is formed on the periphery of the TVS element 10, and an additional trench isolation structure 130 is used to isolate the N + subsidence region 128 from the active region of the TVS element 10. 116 limited. The trench isolation structure 130 is used to terminate the N + sinker region 128 / P + region 126 junction from being laterally implanted into the emitter-base region of the TVS element 10. In this embodiment, the trench isolation structure 130 is a polycrystalline silicon filled trench with a dielectric sidewall. In other embodiments, the trench isolation structure 130 may be an oxide-filled trench. However, in another embodiment, horizontal isolation may be accomplished by increasing the distance between the N + sinker region 128 and the N + region 116, instead of using trench isolation. The use of the trench isolation structure 130 is optional and may be omitted in other embodiments. In addition, the trench isolation structure 130 may serve as a separate trench isolation structure 130 that surrounds the inside of the active region of the TVS element 10.
另外，在TVS元件10中，掩埋的P-本體區114由P-本體一區124構成，P本體一區124形成在N+區116和P-本體區114的結處。P-本體一區124比P-本體區114更加重摻雜，P-本體一區124形成在N+/P-本體結處，作為摻雜區的一個島。在其他實施例中，製備P-本體一區124是藉由在結深處注入P-型摻雜區，然後退火。P-本體一區124具有推動N+至P-本體結的擊穿，發生在掩埋結處，而不是在半導體結構的表面發生。發生在半導體結構表面或表面附近的擊穿有時並不好控制。然而，發生在掩埋結處(例如N+至P-本體一結)的擊穿，可以更好地控制，因此更加有必要。In addition, in the TVS element 10, the buried P-body region 114 is composed of a P-body region 124, and the P-body region 124 is formed at the junction of the N + region 116 and the P-body region 114. The P-body region 124 is more heavily doped than the P-body region 114. The P-body region 124 is formed at the N + / P-body junction as an island of the doped region. In other embodiments, the P-body-region 124 is prepared by implanting a P-type doped region deep in the junction and then annealing. The P-body-one region 124 has a breakdown that pushes the N + to the P-body junction, which occurs at the buried junction rather than at the surface of the semiconductor structure. Breakdowns that occur on or near the surface of semiconductor structures are sometimes not well controlled. However, breakdowns that occur at buried junctions (eg, a junction from N + to P-body) can be better controlled and therefore more necessary.
在運行過程中，當受保護節點120比參考節點122(地電勢)更加反向偏置時，這等效於參考節點122比受保護節點120更加正向偏置，N+區116至P-本體一區124的掩埋結決定了閉鎖模式下的擊穿電壓，在反向尖峰方向上。P-本體一區124用於初始化擊穿，強制擊穿發生在掩埋N+/P-本體1結處。與此同時，結的效率被P-本體一區124外部的輕摻雜P-本體區114提高。也就是說，P-本體區114比P-本體一區124更加重摻雜，注入效率在較重摻雜的P-本體區114和N+區116形成的掩埋結處得到了提高。一旦發生擊穿時，N+區116至P-本體區114的結將承受擊穿動作。During operation, when the protected node 120 is more reverse biased than the reference node 122 (ground potential), this is equivalent to the reference node 122 being more forward biased than the protected node 120, and the N + region 116 to the P- ontology The buried junction of region 124 determines the breakdown voltage in the blocking mode, in the reverse peak direction. The first P-body region 124 is used to initiate the breakdown. The forced breakdown occurs at the buried N + / P-body 1 junction. At the same time, the efficiency of the junction is improved by the lightly doped P-body region 114 outside the P-body region 124. That is, the P-body region 114 is more heavily doped than the P-body region 124, and the implantation efficiency is improved at the buried junction formed by the heavily doped P-body region 114 and the N + region 116. Once a breakdown occurs, the junction from the N + region 116 to the P-body region 114 will undergo a breakdown action.
在TVS元件10中，擊穿電壓由集電極-基極結決定——也就是說，N+基板102和P-型掩埋層108之間的間距以及基板和P-掩埋層的摻雜濃度。在本實施例中，TVS元件10包括一個P-型摻雜區132，形成在P-型掩埋層108和N+基板102的結處。在一個實施例中，P-型摻雜區132作為P-型掩埋層區域，表示為PBL2區132。PBL2區132比P-型掩埋層108更加重摻雜，並且作為摻雜區的一個島，形成在P-型掩埋層108和N+基板102結處。藉由增大P-型摻雜的PBL2區132，集電極-基極結的雪崩擊穿性能得到了提高，降低了TVS元件10在正向尖峰方向上的擊穿電壓。In the TVS element 10, the breakdown voltage is determined by the collector-base junction-that is, the distance between the N + substrate 102 and the P-type buried layer 108 and the doping concentration of the substrate and the P- buried layer. In this embodiment, the TVS element 10 includes a P-type doped region 132 formed at the junction of the P-type buried layer 108 and the N + substrate 102. In one embodiment, the P-type doped region 132 is used as a P-type buried layer region, and is designated as a PBL2 region 132. The PBL2 region 132 is more heavily doped than the P-type buried layer 108 and, as an island of the doped region, is formed at the junction of the P-type buried layer 108 and the N + substrate 102. By increasing the P-type doped PBL2 region 132, the avalanche breakdown performance of the collector-base junction is improved, and the breakdown voltage of the TVS element 10 in the forward spike direction is reduced.
這樣一來，TVS元件10包括一個NPN雙極電晶體，帶有單獨優化的集電極-基極結和發射極-基極結。更確切地說，TVS元件10包括PBL2區132，優化電晶體的集電極-基極結，並且包括P-本體一區124，優化電晶體的發射極-基極結。TVS元件10的一個突出特點是優化的集電極-基極和發射極-基極結都空間分佈在TVS元件10的主動區中。在第3圖所示的實施例中，PBL2區132形成在水平遠離P-本體一區124的地方，使得兩個區域在從半導體結構頂部到底部的垂直方向上沒有對齊。由於空間分兩個優化區域，TVS元件10構成兩個並聯的NPN雙極電晶體的等效電路，等效電路對於正向和負向尖峰瞬變電壓單獨優化。In this way, the TVS element 10 includes an NPN bipolar transistor with individually optimized collector-base junctions and emitter-base junctions. More specifically, the TVS element 10 includes a PBL2 region 132, which optimizes the collector-base junction of the transistor, and includes a P-body-region 124, which optimizes the emitter-base junction of the transistor. A prominent feature of the TVS element 10 is that the optimized collector-base and emitter-base junctions are both spatially distributed in the active region of the TVS element 10. In the embodiment shown in FIG. 3, the PBL2 region 132 is formed away from the P-body first region 124 horizontally, so that the two regions are not aligned in a vertical direction from the top to the bottom of the semiconductor structure. Since the space is divided into two optimization regions, the TVS element 10 constitutes an equivalent circuit of two parallel NPN bipolar transistors, and the equivalent circuit is optimized separately for positive and negative spike transient voltages.
第3a圖表示第圖所示的TVS元件10的等效電路。參見第3a圖，TVS元件10可以看作一個NPN雙極電晶體Q2A和一個NPN雙極電晶體Q2B的並聯。每個雙極電晶體都有它的基極，藉由P-型外延層112和P-本體區114電阻耦合到P +區126上，作為二極體D2的陽極。二極體D2的陰極由N+沉降區128構成，並藉由N-型掩埋層106和N+基板102連接到受保護的節點上。NPN雙極電晶體Q2A具有其集電極-基極結，藉由PBL2區132優化，其中PBL2區132和N+基板102的結決定了TVS元件10在正向尖峰方向上的擊穿電壓——也就是說，受保護節點相當於參考節點或地節點來說更加正向偏置。同時，NPN雙極電晶體Q2B具有其發射極-基極結，藉由P-本體一區124優化，其中P-本體一區和N+區116結決定了TVS元件10在正向尖峰方向上的擊穿電壓——也就是說，受保護節點相當於參考節點或地節點來說更加負向偏置。由於PBL2區132和P-本體一區124的空間分離，TVS元件10用作一對並聯的雙極電晶體，帶有單獨優化的擊穿電壓性能設計，以單獨提高正向和反向尖峰屬性。FIG. 3a shows an equivalent circuit of the TVS element 10 shown in FIG. Referring to FIG. 3a, the TVS element 10 can be regarded as a parallel connection of an NPN bipolar transistor Q2A and an NPN bipolar transistor Q2B. Each bipolar transistor has its base, which is resistively coupled to the P + region 126 through the P-type epitaxial layer 112 and the P-body region 114 as the anode of the diode D2. The cathode of the diode D2 is composed of an N + sink region 128, and is connected to a protected node through an N-type buried layer 106 and an N + substrate 102. The NPN bipolar transistor Q2A has its collector-base junction, which is optimized by the PBL2 region 132, where the junction of the PBL2 region 132 and the N + substrate 102 determines the breakdown voltage of the TVS element 10 in the forward spike direction-also That is, the protected node is more forward biased than the reference or ground node. At the same time, the NPN bipolar transistor Q2B has its emitter-base junction, which is optimized by the P-body one region 124, where the P-body one region and the N + region 116 junction determine the TVS element 10 in the forward spike direction. Breakdown voltage—that is, the protected node is more negatively biased than the reference or ground node. Due to the spatial separation of the PBL2 region 132 and the P-body first region 124, the TVS element 10 is used as a pair of parallel bipolar transistors with individually optimized breakdown voltage performance design to individually improve forward and reverse spike properties .
在本發明的可選實施例中，第3圖所示的TVS元件10可以只引入PBL2區132，以優化TVS元件10之NPN雙極電晶體的集電極-基極結。In an alternative embodiment of the present invention, the TVS element 10 shown in FIG. 3 may only be introduced into the PBL2 region 132 to optimize the collector-base junction of the NPN bipolar transistor of the TVS element 10.
第4圖表示依據本發明的第二實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS期間的剖面圖。參見第4圖，TVS元件20的配置方式除了製成P-本體一區124和PBL2區132之外，其他都與第3圖所示的TVS元件10類似。在第3圖所示的TVS元件10中，一個單獨的P-本體一區124和一個單獨的PBL2區132與兩個相互分隔開的區域一起使用。在第4圖所示的TVS元件20中，掩埋P-本體結由複數個P-本體一區124構成，形成在N+區116和P-本體區114的結處。P-本體一區124比P-本體區114更加重摻雜，並且作為分散在N+區116/P-本體區114之結處分離的摻雜區島。在某些實施例中，P-本體一區124呈長條形排布在N+區116/P-本體區114之結處。與此同時，PBL2區由複數個PBL2區132構成，在P-型掩埋層108島與N+基板102的結處。PBL2區132比P-型掩埋層108更加重摻雜，作為分散在PBL/N-基板結處分離的摻雜區島。在某些實施例中，PBL2區132呈長條形排布在PBL/N-基板結處。FIG. 4 shows a cross-sectional view during a bidirectional TVS with a spatially distributed and individually optimized collector-base and emitter-base junction according to a second embodiment of the present invention. Referring to FIG. 4, the configuration of the TVS element 20 is similar to that of the TVS element 10 shown in FIG. 3 except that the P-body first region 124 and the PBL2 region 132 are made. In the TVS element 10 shown in FIG. 3, a single P-body first region 124 and a single PBL2 region 132 are used together with two separated regions. In the TVS element 20 shown in FIG. 4, the buried P-body junction is composed of a plurality of P-body regions 124 formed at the junction of the N + region 116 and the P-body region 114. The P-bulk first region 124 is more heavily doped than the P-bulk region 114 and serves as an island of doped regions dispersed at the junction of the N + region 116 / P-bulk region 114. In some embodiments, the P-body region 124 is arranged in a strip shape at the junction of the N + region 116 / P-body region 114. At the same time, the PBL2 region is composed of a plurality of PBL2 regions 132 at the junction of the island of the P-type buried layer 108 and the N + substrate 102. The PBL2 region 132 is more heavily doped than the P-type buried layer 108 and serves as a doped region island dispersed at the junction of the PBL / N- substrate. In some embodiments, the PBL2 regions 132 are arranged in a strip shape at the junction of the PBL / N-substrate.
在本發明的實施例中，P-本體一區124和PBL2區132相互隔開分佈。確切地說，在本實施例中，P-本體一區124和PBL2區132相互隔開或交互交替形成。在實際的實施例中，P-本體一區124和PBL2區132可以利用不同的形狀配置，以構成空間分佈的間隔結構。第5圖表示在某些實施例中，第4圖所示的一部分TVS元件20的俯視圖。參見第5圖，TVS元件20包括一個主動區，被溝槽隔離結構130包圍。PBL2區132和P-本體一區124在主動區內作為交替帶。這樣一來，單獨優化的集電極-基極結和發射極-基極結相互隔開，並且穿過TVS元件20的主動區空間分佈。In the embodiment of the present invention, the P-body first region 124 and the PBL2 region 132 are spaced apart from each other. Specifically, in this embodiment, the P-body first region 124 and the PBL2 region 132 are separated from each other or alternately formed alternately. In an actual embodiment, the P-body first region 124 and the PBL2 region 132 may be configured with different shapes to form a spaced-apart space structure. FIG. 5 shows a plan view of a portion of the TVS element 20 shown in FIG. 4 in some embodiments. Referring to FIG. 5, the TVS element 20 includes an active region surrounded by a trench isolation structure 130. The PBL2 region 132 and the P-body-one region 124 act as alternating bands in the active region. In this way, the individually optimized collector-base junction and emitter-base junction are separated from each other and are spatially distributed across the active area of the TVS element 20.
第6圖表示依據本發明的第三實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件30的剖面圖。參見第6圖，TVS元件30除了製成P-本體一區124和PBL2區132之外，其他都與第4圖所示的TVS元件20的配置方式類似。在第6圖所示的TVS元件30中，P-本體一區124和PBL2區132在中心圓裡間隔開，如第7圖所示。第7圖表示在某些實施例中，第6圖所示的一部分TVS元件30的俯視圖。參見第7圖，TVS元件30包括一個主動區，被溝槽隔離結構130包圍著。PBL2區132和P-本體一區124都在主動區內作為中心圓。確切地說，PBL2區132構成一個內圓，被P-本體一區124包圍著，P-本體一區124被第二個PBL2區132包圍著。這樣一來，單獨優化的集電極-基極結和發射極-基極結都隔開，並穿過TVS元件30的主動區空間分佈。Fig. 6 shows a cross-sectional view of a bidirectional TVS element 30 with a spatially distributed and individually optimized collector-base and emitter-base junction according to a third embodiment of the present invention. Referring to FIG. 6, the TVS element 30 is similar to the arrangement of the TVS element 20 shown in FIG. 4 except that the P-body first region 124 and the PBL2 region 132 are made. In the TVS element 30 shown in FIG. 6, the P-body first region 124 and the PBL2 region 132 are spaced in the center circle, as shown in FIG. 7. FIG. 7 shows a plan view of a portion of the TVS element 30 shown in FIG. 6 in some embodiments. Referring to FIG. 7, the TVS element 30 includes an active region surrounded by a trench isolation structure 130. Both the PBL2 region 132 and the P-body-one region 124 serve as center circles in the active region. Specifically, the PBL2 region 132 forms an inner circle and is surrounded by the P-body-one region 124 and the P-body-one region 124 is surrounded by the second PBL2 region 132. In this way, the individually optimized collector-base junction and emitter-base junction are both separated and distributed across the active area of the TVS element 30.
第8圖表示依據本發明的第四實施例，帶有空間分佈和單獨優化的集電極-基極和發射極基極結的雙向TVS元件40的剖面圖。參見第8圖，TVS元件40除了製成P-本體一區124和PBL2區132之外，其他都與第6圖所示的TVS元件30的配置方式相同。在第8圖所示的TVS元件40中，P-本體一區124和PBL2區132在中心圓中隔開，如第9圖所示。第9圖表示在某些實施例中，第8圖所示的一部分TVS元件40的俯視圖。參見第9圖，TVS元件40包括一個主動區，被溝槽隔離結構130包圍著。PBL2區132和P-本體一區124在主動區內作為中心圓。在本實施例中，P-本體一區124構成一個內環，然後這個內環被PBL2區132包圍著。這樣一來，單獨優化的集電極-基極結和發射極-基極結都隔開，並穿過TVS元件40的主動區空間分佈。FIG. 8 shows a cross-sectional view of a bidirectional TVS element 40 with a spatially distributed and individually optimized collector-base and emitter-base junction according to a fourth embodiment of the present invention. Referring to FIG. 8, the TVS element 40 is the same as the TVS element 30 shown in FIG. 6 except that the P-body first region 124 and the PBL2 region 132 are made. In the TVS element 40 shown in FIG. 8, the P-body first region 124 and the PBL2 region 132 are separated in a center circle, as shown in FIG. 9. FIG. 9 shows a plan view of a portion of the TVS element 40 shown in FIG. 8 in some embodiments. Referring to FIG. 9, the TVS element 40 includes an active region surrounded by a trench isolation structure 130. The PBL2 region 132 and the P-body first region 124 serve as center circles in the active region. In this embodiment, the P-body region 124 constitutes an inner ring, and then the inner ring is surrounded by the PBL2 region 132. In this way, the individually optimized collector-base junction and emitter-base junction are both separated and distributed across the active area of the TVS element 40.
第10圖表示依據本發明的第一實施例，帶有單獨優化的集電極-基極結和p-n結的剖面圖。參見第10圖，一個單向TVS 元件(TVS元件50)形成在重摻雜的N+基板102上。一個輕摻雜的N-型外延層(N-外延層104)形成在N+基板102上。N-型掩埋層(NBL)106和P-型掩埋層(PBL)108形成在N-外延層104上。P-型掩埋層108形成在TVS元件50的中心部分或主動區中，同時N-型掩埋層106形成在P-型掩埋層108的外圍附近，作為一個隔離勢壘。在某些實施例中，N-型掩埋層106是利用重N-型摻雜物(例如銻(Sb))製成的，P-型掩埋層108是利用硼(B)製成的。因此，P-型掩埋層108可以形成在比N-型掩埋層106更深的結深處。Fig. 10 shows a cross-sectional view of a collector-base junction and a p-n junction individually optimized according to a first embodiment of the present invention. Referring to FIG. 10, a unidirectional TVS element (TVS element 50) is formed on a heavily doped N + substrate 102. A lightly doped N-type epitaxial layer (N-epitaxial layer 104) is formed on the N + substrate 102. An N-type buried layer (NBL) 106 and a P-type buried layer (PBL) 108 are formed on the N-epitaxial layer 104. A P-type buried layer 108 is formed in the center portion or active area of the TVS element 50, while an N-type buried layer 106 is formed near the periphery of the P-type buried layer 108 as an isolation barrier. In some embodiments, the N-type buried layer 106 is made using a heavy N-type dopant, such as antimony (Sb), and the P-type buried layer 108 is made using boron (B). Therefore, the P-type buried layer 108 may be formed at a deeper junction depth than the N-type buried layer 106.
輕摻雜的P-型外延層(P-型外延層112)形成在N-外延層104、N-型掩埋層106以及P-型掩埋層108上。P-本體區114形成在P-型外延層112上，例如藉由離子注入和驅進。P-本體區114比P-型外延層112更加重摻雜。重摻雜的N+區116形成在P-本體區114中，以完成NPN雙極電晶體。A lightly doped P-type epitaxial layer (P-type epitaxial layer 112) is formed on the N-epitaxial layer 104, the N-type buried layer 106, and the P-type buried layer 108. A P-body region 114 is formed on the P-type epitaxial layer 112, for example, by ion implantation and driving. The P-body region 114 is more heavily doped than the P-type epitaxial layer 112. A heavily doped N + region 116 is formed in the P-body region 114 to complete the NPN bipolar transistor.
這樣一來，TVS元件50製成了一個NPN雙極電晶體，包括一個由N+基板102構成的集電極、一個由P-型掩埋層108、P-型外延層112和P-本體區114 構成的基極以及一個由N+區116構成的發射極。電介質層118形成在半導體結構上方，覆蓋並保護半導體元件。一個開口形成在電介質層118中，一個發射極電極形成在開口中，用於與N+區116歐姆接觸。用於電接觸島N+基板102上的集電極電極，也形成在基板背面。發射極電極和集電極電極通常都由金屬層等導電材料製成。In this way, the TVS element 50 is made into an NPN bipolar transistor, including a collector composed of an N + substrate 102, a P-type buried layer 108, a P-type epitaxial layer 112, and a P-body region 114. And an emitter formed by the N + region 116. A dielectric layer 118 is formed over the semiconductor structure to cover and protect the semiconductor element. An opening is formed in the dielectric layer 118, and an emitter electrode is formed in the opening for ohmic contact with the N + region 116. A collector electrode for electrically contacting the island N + substrate 102 is also formed on the back surface of the substrate. The emitter electrode and the collector electrode are usually made of a conductive material such as a metal layer.
在本說明書中，TVS元件50被溝槽隔離結構111隔開，使得相同的TVS元件50的一個陣列形成在基板上，或者TVS元件50可以帶有其他元件，實現積體電路所需的保護電路。在本實施例中，製備延伸到N-型掩埋層106的溝槽隔離結構111，使TVS元件50隔離，溝槽內襯氧化層109並用多晶矽層110填充。在其他實施例中，可以使用一個氧化物填充的隔離結構。在第10圖中，兩個溝槽隔離結構111表示在TVS元件50的兩邊上。在實際實施例中，溝槽隔離結構111可以是一個單獨的溝槽隔離結構111，包圍著TVS元件50的中心部分或主動區。In this specification, the TVS element 50 is separated by the trench isolation structure 111, so that an array of the same TVS element 50 is formed on the substrate, or the TVS element 50 may be provided with other elements to realize the protection circuit required by the integrated circuit . In this embodiment, a trench isolation structure 111 extending to the N-type buried layer 106 is prepared to isolate the TVS element 50. The trench is lined with an oxide layer 109 and filled with a polycrystalline silicon layer 110. In other embodiments, an oxide-filled isolation structure may be used. In FIG. 10, two trench isolation structures 111 are shown on both sides of the TVS element 50. In an actual embodiment, the trench isolation structure 111 may be a single trench isolation structure 111 that surrounds a central portion or an active area of the TVS element 50.
TVS元件50進一步包括一個N+沉降區128，將N-型掩埋層106連接到重摻雜的P+區126，P+區126形成在半導體結構的表面上。P+區126電連接到發射極電勢，例如藉由電介質層118中的一個接觸開口連接到發射極電極。也就是說，P+區126短接至N+區116，它們兩個都連接到發射極電勢。藉由使用N+沉降區128，集電極-基極結擊穿被提高到半導體結構的表面，在N+沉降區128和P+區126之間的結處。確切地說，N+沉降區128到P+區126的結決定了正向尖峰方向上的擊穿電壓，受保護節點120比參考節點122更加正向偏置，參考節點122在本實施例中是地電勢。在第10圖中，兩個N+沉降區128和P+區126表示在TVS元件50的任一邊上。在實際的實施例中，N+沉降區128和P+區126可以是一個單獨的結構，包圍著TVS元件50的中心部分或主動區。The TVS element 50 further includes an N + sinker region 128 that connects the N-type buried layer 106 to the heavily doped P + region 126, and the P + region 126 is formed on the surface of the semiconductor structure. The P + region 126 is electrically connected to the emitter potential, for example, to the emitter electrode through a contact opening in the dielectric layer 118. That is, the P + region 126 is shorted to the N + region 116, and both of them are connected to the emitter potential. By using the N + sinker region 128, the collector-base junction breakdown is improved to the surface of the semiconductor structure, at the junction between the N + sinker region 128 and the P + region 126. Specifically, the junction of the N + subsidence region 128 to the P + region 126 determines the breakdown voltage in the forward spike direction. The protected node 120 is more forward biased than the reference node 122, which is the ground in this embodiment. Potential. In FIG. 10, two N + settling regions 128 and P + regions 126 are shown on either side of the TVS element 50. In an actual embodiment, the N + subsidence region 128 and the P + region 126 may be a separate structure, which surrounds the central portion or the active region of the TVS element 50.
在TVS元件50中，N+沉降區128形成在TVS元件50的外圍，額外的溝槽隔離結構130用於隔開N+沉降區128和TVS元件50的主動區，TVS元件50的主動區由N+區116限定。溝槽隔離結構130用於終止從N+沉降區128/P+區126結橫向注入到TVS元件50的發射極-基極區內。在本實施例中，溝槽隔離結構130是帶有電介質側壁的多晶矽填充溝槽。在其他實施例中，溝槽隔離結構130可以是氧化物填充溝槽。另外，在本實施例中，額外的N-型掩埋層區域形成在溝槽隔離結構130下方。在本實施例中，N-型掩埋層106穿過P-型掩埋層108水平延伸。然而在另一個實施例中，水平隔離可以藉由增大N+沉降區128和N+區116之間的距離來完成，代替使用溝槽隔離。另外，溝槽隔離結構130和形成在下方的N-型掩埋層區域，都可以利用一個單獨的溝槽隔離結構130製成，單獨的溝槽隔離結構130包圍著TVS元件50主動區的內部。In the TVS element 50, an N + subsidence region 128 is formed on the periphery of the TVS element 50. An additional trench isolation structure 130 is used to separate the N + subsidence region 128 from the active region of the TVS element 50. The active region of the TVS element 50 is an N + region. 116 limited. The trench isolation structure 130 is used to terminate lateral injection from the N + sinker region 128 / P + region 126 junction into the emitter-base region of the TVS element 50. In this embodiment, the trench isolation structure 130 is a polycrystalline silicon filled trench with a dielectric sidewall. In other embodiments, the trench isolation structure 130 may be an oxide-filled trench. In addition, in this embodiment, an additional N-type buried layer region is formed under the trench isolation structure 130. In the present embodiment, the N-type buried layer 106 extends horizontally through the P-type buried layer 108. However, in another embodiment, horizontal isolation may be accomplished by increasing the distance between the N + sinker region 128 and the N + region 116, instead of using trench isolation. In addition, both the trench isolation structure 130 and the N-type buried layer region formed below can be made by using a single trench isolation structure 130, which surrounds the inside of the active area of the TVS element 50.
另外，在TVS元件50中，掩埋P-本體結由P-本體一區124構成，P-本體一區124形成在P-本體區114中，並且在P+區126和N+沉降區128的結處。P-本體一區124比P-本體區114更加重摻雜，但是比P+區126次重摻雜。在某些實施例中，P-本體一區124由P-型摻雜物的注入形成，在結深處，然後退火。在單向TVS元件50中，P+/P-本體一區和N+沉降區128構成PN結二極體。在運行過程中，當受保護節點120比參考節點122(地電勢)更加負偏置時，這等效於參考節點122比受保護節點120更加正向偏置，N+沉降區128到P-本體一區124的掩埋結在反向尖峰方向上決定了閉鎖模式下的擊穿電壓。In addition, in the TVS element 50, the buried P-body junction is composed of the P-body region 124, the P-body region 124 is formed in the P-body region 114, and at the junction of the P + region 126 and the N + settlement region 128 . P-body region 124 is more heavily doped than P-body region 114, but 126 times more heavily doped than P + region. In some embodiments, the P-body region 124 is formed by implantation of a P-type dopant, deep in the junction, and then annealed. In the unidirectional TVS element 50, the P + / P-body first region and the N + sinking region 128 constitute a PN junction diode. During operation, when the protected node 120 is more negatively biased than the reference node 122 (ground potential), this is equivalent to the reference node 122 being more positively biased than the protected node 120, and the N + subsidence region 128 to P- ontology The buried junction of a region 124 determines the breakdown voltage in the blocking mode in the reverse spike direction.
在TVS元件50中，擊穿電壓由集電極-基極結決定——也就是說，N+基板102和P-型掩埋層108之間的距離以及基板和P-型掩埋層108的摻雜濃度。在本實施例中，TVS元件50包括一個P-型摻雜區132，形成在P-型掩埋層108和N+基板102的結處。在一個實施例中，P-型摻雜區132作為一個P-型掩埋層區域，表示為PBL2區132。PBL2區132比P-型掩埋層108更加重摻雜，並且穿過溝槽隔離結構111之間的整個主動區。在本實施例中，PBL2區132形成在比P-型掩埋層108更深的結深處。提供帶有增大P-型摻雜的PBL2區132，集電極-基極結的雪崩擊穿屬性得到了提高，降低了正向尖峰方向上TVS元件50的擊穿電壓。In the TVS element 50, the breakdown voltage is determined by the collector-base junction--that is, the distance between the N + substrate 102 and the P-type buried layer 108 and the doping concentration of the substrate and the P-type buried layer 108. . In this embodiment, the TVS element 50 includes a P-type doped region 132 formed at the junction of the P-type buried layer 108 and the N + substrate 102. In one embodiment, the P-type doped region 132 serves as a P-type buried layer region, and is designated as a PBL2 region 132. The PBL2 region 132 is more heavily doped than the P-type buried layer 108 and passes through the entire active region between the trench isolation structures 111. In this embodiment, the PBL2 region 132 is formed at a deeper junction depth than the P-type buried layer 108. By providing the PBL2 region 132 with an increased P-type doping, the avalanche breakdown property of the collector-base junction is improved, and the breakdown voltage of the TVS element 50 in the forward spike direction is reduced.
這樣一來，TVS元件50包括一個NPN雙極電晶體和一個PN結二極體，帶有單獨優化的雙極電晶體的集電極－基極結以及PN結二極體的p-n結。更確切地說，TVS元件50包括PBL2區132，優化電晶體的集電極-基極結，包括P-本體一區124，優化PN結二極體的p-n結。因此，TVS元件50構成一個NPN雙極電晶體和一個PN結二極體的等效電路對於正向和負向尖峰瞬變電壓，它們都是單獨優化的。In this way, the TVS element 50 includes an NPN bipolar transistor and a PN junction diode, a collector-base junction with a separately optimized bipolar transistor, and a p-n junction of the PN junction diode. More specifically, the TVS element 50 includes a PBL2 region 132, which optimizes the collector-base junction of the transistor, including a P-body-region 124, and optimizes the p-n junction of the PN junction diode. Therefore, the TVS element 50 constitutes an NPN bipolar transistor and an equivalent circuit of a PN junction diode, which are individually optimized for positive and negative spike transient voltages.
第10a圖表示第10圖所示的TVS元件50的等效電路。參見第10a圖，TVS元件50可以看作是一個NPN雙極電晶體Q1和一個PN結二極體D1並聯。NPN雙極電晶體Q1的基極，藉由P-型外延層112和P-本體區114電阻耦合到P+區126以及發射極電極，發射極電極連接到地電勢。二極體D1的陽極由P-本體一區124和P+區126構成，P+區126連接到發射極電極，發射極電極連接到地電勢。二極體D1的陰極由N+沉降區128構成，並且藉由N-型掩埋層106和N+基板102連接到受保護的節點。NPN雙極電晶體Q1具有其集電極-基極結，被PBL2區132優化，PBL2區132和N+基板102結決定了TVS元件50在正向尖峰方向上的擊穿電壓——也就是說受保護節點對於參考節點或地來說更加正向。與此同時，由P-本體一區124和N+沉降區128形成的p-n結決定了TVS元件50在反向尖峰方向上的TVS元件50的擊穿電壓——也就是說，受保護節點比參考節點或地更加負向。因此，TVS元件50用作雙極電晶體和PN結二極體的並聯，帶有單獨優化的擊穿電壓性能設計，以便單獨提高正向和反向尖峰性能。Fig. 10a shows an equivalent circuit of the TVS element 50 shown in Fig. 10. Referring to FIG. 10a, the TVS element 50 can be regarded as an NPN bipolar transistor Q1 and a PN junction diode D1 connected in parallel. The base of the NPN bipolar transistor Q1 is resistively coupled to the P + region 126 and the emitter electrode through the P-type epitaxial layer 112 and the P-body region 114, and the emitter electrode is connected to the ground potential. The anode of the diode D1 is composed of a P-body first region 124 and a P + region 126. The P + region 126 is connected to the emitter electrode, and the emitter electrode is connected to the ground potential. The cathode of the diode D1 is composed of an N + sink region 128 and is connected to a protected node through an N-type buried layer 106 and an N + substrate 102. The NPN bipolar transistor Q1 has its collector-base junction, which is optimized by the PBL2 region 132. The PBL2 region 132 and the N + substrate 102 junction determine the breakdown voltage of the TVS element 50 in the forward spike direction--that is, it is affected by The protection node is more positive for the reference node or ground. At the same time, the pn junction formed by the P-body first region 124 and the N + sinking region 128 determines the breakdown voltage of the TVS element 50 in the reverse spike direction of the TVS element 50-that is, the protected node is better than the reference The node or ground is more negative. Therefore, the TVS element 50 is used as a parallel connection of a bipolar transistor and a PN junction diode with an individually optimized breakdown voltage performance design in order to individually improve forward and reverse spike performance.
第11圖表示依據本發明的第二實施例，帶有單獨優化的集電極-基極結和p-n結的單向TVS元件60的剖面圖。參見第11圖，TVS元件60除了製成N-型掩埋層106和溝槽隔離結構之外，其他的配置方式與第10圖所示的TVS元件50的配置方式相同。在第10圖所示的TVS元件50中，N-型掩埋層106僅部分延伸穿過P-型掩埋層108。在第11圖所示的TVS元件60中，N-型掩埋層106和溝槽隔離結構130延伸穿過P-型掩埋層108和PBL2區132，使得TVS元件60的雙極電晶體的主動區完全隔離。這樣一來，雙極電晶體主動區就形成在溝槽隔離結構130和N-型掩埋層部分106A之間。N-型掩埋層部分106A使NPN雙極電晶體的主動區與PN結二極體完全隔離，PN結二極體形成在溝槽隔離結構111和130之間。即使PBL和PBL2的一部分位於溝槽隔離結構111和130之間的PN結二極體區域中，溝槽隔離結構111和130之間的PBL和PBL2也是虛擬區域，不會對TVS元件60的元件運行有貢獻。FIG. 11 shows a cross-sectional view of a unidirectional TVS element 60 with individually optimized collector-base junctions and p-n junctions according to a second embodiment of the present invention. Referring to FIG. 11, the TVS element 60 is configured in the same manner as the TVS element 50 shown in FIG. 10 except that the N-type buried layer 106 and the trench isolation structure are made. In the TVS element 50 shown in FIG. 10, the N-type buried layer 106 extends only partially through the P-type buried layer 108. In the TVS element 60 shown in FIG. 11, the N-type buried layer 106 and the trench isolation structure 130 extend through the P-type buried layer 108 and the PBL2 region 132, so that the active region of the bipolar transistor of the TVS element 60 Completely isolated. In this way, the bipolar transistor active region is formed between the trench isolation structure 130 and the N-type buried layer portion 106A. The N-type buried layer portion 106A completely isolates the active region of the NPN bipolar transistor from the PN junction diode, and the PN junction diode is formed between the trench isolation structures 111 and 130. Even if a part of the PBL and PBL2 is located in the PN junction diode region between the trench isolation structures 111 and 130, the PBL and PBL2 between the trench isolation structures 111 and 130 are virtual regions and will not affect the components of the TVS element 60. Contributing to operation.
第12圖表示在某些實施例中，第11圖所示的一部分TVS元件60的俯視圖。參見第12圖，TVS元件60包括一個電晶體主動區，被溝槽隔離結構130包圍著。PBL2區132形成在電晶體主動區中並覆蓋這電晶體主動區。TVS元件60進一步包括一個二極體主動區，形成在溝槽隔離結構130和111之間，被溝槽隔離結構111包圍著。P-本體一區124形成在二極體主動區中，並覆蓋二極體主動區。這樣一來，單獨優化的集電極-基極結和p-n結都形成在TVS元件60各自的主動區中，以便單獨優化雙極電晶體和PN結二極體。FIG. 12 shows a top view of a portion of the TVS element 60 shown in FIG. 11 in some embodiments. Referring to FIG. 12, the TVS element 60 includes a transistor active region surrounded by a trench isolation structure 130. The PBL2 region 132 is formed in and covers the transistor active region. The TVS element 60 further includes a diode active region formed between the trench isolation structures 130 and 111 and surrounded by the trench isolation structure 111. The P-body first region 124 is formed in the diode active region and covers the diode active region. In this way, individually optimized collector-base junctions and p-n junctions are formed in the respective active regions of the TVS element 60 in order to individually optimize the bipolar transistor and the PN junction diode.
第13圖表示依據本發明的第五實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件200的剖面圖。第13圖表示沒有使用P-型外延層112的第3圖所示的TVS元件10的結構。參見第13圖，雙向TVS元件(TVS元件200）形成在重摻雜的N+基板102上。輕摻雜的N-型外延層(N-外延層104)形成在N+基板102上。P-型掩埋層(PBL)108形成在N-外延層104上。P-型掩埋層108形成在TVS元件200的中心部分或主動區中。P-本體區114形成在P-型掩埋層108上方的N-型外延層104中。重摻雜的N+區116形成在P-本體區114中，以完成NPN雙極電晶體。FIG. 13 shows a cross-sectional view of a bidirectional TVS element 200 with a spatially distributed and individually optimized collector-base and emitter-base junction according to a fifth embodiment of the present invention. FIG. 13 shows the structure of the TVS element 10 shown in FIG. 3 without using the P-type epitaxial layer 112. Referring to FIG. 13, a bidirectional TVS element (TVS element 200) is formed on a heavily doped N + substrate 102. A lightly doped N-type epitaxial layer (N-epitaxial layer 104) is formed on the N + substrate 102. A P-type buried layer (PBL) 108 is formed on the N-epitaxial layer 104. The P-type buried layer 108 is formed in a central portion or an active region of the TVS element 200. A P-body region 114 is formed in the N-type epitaxial layer 104 above the P-type buried layer 108. A heavily doped N + region 116 is formed in the P-body region 114 to complete the NPN bipolar transistor.
這樣一來，TVS元件200配置成一個NPN雙極電晶體，包括一個由N+基板102形成的集電極，一個由P-型掩埋層108和P-本體區114形成的基極以及一個由N+區116形成的發射極。電介質層118形成在半導體結構上方，以覆蓋和保護半導體元件。一個開口形成在電介質層118中，一個發射極電極形成在開口中，以便於N+區116形成歐姆接觸。集電極電極用於與N+基板102形成電接觸，集電極電極也形成在基板背面。集電極電極和發射極電極通常都由金屬層等導電材料製成。In this way, the TVS element 200 is configured as an NPN bipolar transistor, including a collector formed by the N + substrate 102, a base formed by the P-type buried layer 108 and the P-body region 114, and an N + region 116 formed emitter. A dielectric layer 118 is formed over the semiconductor structure to cover and protect the semiconductor elements. An opening is formed in the dielectric layer 118, and an emitter electrode is formed in the opening so that the N + region 116 forms an ohmic contact. The collector electrode is used to make electrical contact with the N + substrate 102, and the collector electrode is also formed on the back surface of the substrate. The collector electrode and the emitter electrode are usually made of a conductive material such as a metal layer.
在本說明書中，TVS元件200被溝槽隔離結構111隔開。在本實施例中，溝槽延伸到N+基板102，以隔開TVS元件200，並且溝槽內襯氧化層109，用多晶矽層110填充。在其他實施例中，可以使用一個氧化物填充溝槽隔離結構。在第13圖中，兩個溝槽隔離結構111表示在TVS元件200的任一邊上。在實際的實施例中，溝槽隔離結構111可以是一個單獨的溝槽隔離結構111，包圍著TVS元件200的中心部分或主動區。In this specification, the TVS elements 200 are separated by a trench isolation structure 111. In this embodiment, the trench extends to the N + substrate 102 to separate the TVS element 200, and the trench is lined with an oxide layer 109 and filled with a polycrystalline silicon layer 110. In other embodiments, a trench isolation structure may be filled with an oxide. In FIG. 13, two trench isolation structures 111 are shown on either side of the TVS element 200. In an actual embodiment, the trench isolation structure 111 may be a single trench isolation structure 111 that surrounds a central portion or an active area of the TVS element 200.
在TVS元件200中，掩埋P-本體結由P-本體一區124構成，P-本體一區124形成在N+區116和P-本體區114之間的結處。P-本體一區124比P-本體區114更加重摻雜，並且作為摻雜區的島在N+/P-本體結處。TVS元件200進一步包括一個P-型摻雜區132，形成在P-型掩埋層108和N+基板102之間的結處。在一個實施例中，P-型掩埋層132作為P-型掩埋層區域，用PBL2區132表示。PBL2區132比P-型掩埋層108更加重摻雜，並且作為摻雜區的島在P-型掩埋層108和N+基板102結處。P-本體一區124和PBL2區132是空間分佈的。由於兩個優化區域的空間分佈，因此TVS元件200構成兩個並聯的NPN雙極電晶體的等效電路，對於正向和負向尖峰瞬變電壓來說，兩個雙極電晶體都是單獨優化的。In the TVS element 200, the buried P-body junction is composed of a P-body region 124, and the P-body region 124 is formed at the junction between the N + region 116 and the P-body region 114. The P-body region 124 is more heavily doped than the P-body region 114, and the island as a doped region is at the N + / P-body junction. The TVS device 200 further includes a P-type doped region 132 formed at a junction between the P-type buried layer 108 and the N + substrate 102. In one embodiment, the P-type buried layer 132 is used as a P-type buried layer region, and is represented by a PBL2 region 132. The PBL2 region 132 is more heavily doped than the P-type buried layer 108, and the island as a doped region is at the junction of the P-type buried layer 108 and the N + substrate 102. The P-body area 124 and PBL2 area 132 are spatially distributed. Due to the spatial distribution of the two optimized regions, the TVS element 200 constitutes an equivalent circuit of two parallel NPN bipolar transistors. For positive and negative spike transient voltages, both bipolar transistors are separate optimized.
在本實施例中，所示的TVS元件200由一個單獨的P-本體一區124和一個單獨的PBL2區132構成。在其他實施例中，TVS元件200可以利用多個相間的P-本體一區124和PBL2區132構成，其製備方式與第4圖至第9圖所示的配置方式相同。In this embodiment, the TVS element 200 shown is composed of a single P-body one region 124 and a single PBL2 region 132. In other embodiments, the TVS element 200 may be composed of a plurality of interphase P-body first regions 124 and PBL2 regions 132, and the preparation method thereof is the same as that shown in FIGS. 4 to 9.
第14圖表示依據本發明的第六實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件210的剖面圖。參見第14圖，TVS元件210除了製成P-型掩埋層108和P-本體區114之外，其他的配置方式都與第13圖所示的TVS元件200的配置方式相同。在第13圖所示的TVS元件200中，形成分開的P-型掩埋層108和P-本體區114。在第14圖所示的TVS元件210中，利用全面P-型層115，代替分開的PBL和P-本體層。全面P-型層115可以是一個全面的摻雜區，形成在N-外延層104的整個表面上。TVS元件210的剩餘結構可以按照第13圖所示的相同的方式製備。FIG. 14 shows a cross-sectional view of a bidirectional TVS element 210 with a spatially distributed and individually optimized collector-base and emitter-base junction according to a sixth embodiment of the present invention. Referring to FIG. 14, the TVS element 210 is the same as the TVS element 200 shown in FIG. 13 except that the P-type buried layer 108 and the P-body region 114 are made. In the TVS element 200 shown in FIG. 13, a separate P-type buried layer 108 and a P-body region 114 are formed. In the TVS element 210 shown in FIG. 14, a full P-type layer 115 is used instead of the separate PBL and P-body layers. The full P-type layer 115 may be a full doped region formed on the entire surface of the N-epitaxial layer 104. The remaining structure of the TVS element 210 can be prepared in the same manner as shown in FIG. 13.
第15圖表示依據本發明的第三實施例，帶有單獨優化的集電極-基極結和p-n結的單向TVS元件220的剖面圖。第15圖表示沒有使用P-型外延層112，第10圖所示的TVS元件50的結構。參見第15圖，一個單向TVS元件(TVS元件220)形成在一個重摻雜的N+基板102上。一個輕摻雜的N-型外延層(N-外延層104)形成在N+基板102上。一個P-本體區114形成在P-型掩埋層108上方的N-外延層104中。一個重摻雜的N+區116形成在P-本體區114中，以完成NPN雙極電晶體。FIG. 15 shows a cross-sectional view of a unidirectional TVS element 220 with individually optimized collector-base junction and p-n junction according to a third embodiment of the present invention. FIG. 15 shows the structure of the TVS element 50 shown in FIG. 10 without using the P-type epitaxial layer 112. Referring to FIG. 15, a unidirectional TVS element (TVS element 220) is formed on a heavily doped N + substrate 102. A lightly doped N-type epitaxial layer (N-epitaxial layer 104) is formed on the N + substrate 102. A P-body region 114 is formed in the N-epitaxial layer 104 above the P-type buried layer 108. A heavily doped N + region 116 is formed in the P-body region 114 to complete the NPN bipolar transistor.
這樣一來，TVS元件220就製備成一個NPN雙極電晶體，包括一個由N+基板102構成的集電極，一個由P-型掩埋層108和P-本體區114構成的基極以及一個由N+區116構成的發射極。電介質層118形成在半導體結構上方，以便覆蓋和保護半導體元件。一個開口形成在電介質層118中，一個發射極電極形成在開口中，以便於N+區116形成歐姆接觸。集電極電極用於與N+基板102形成電接觸，集電極電極也形成在基板背面。發射極電極和集電極電極通常都由金屬層等導電材料製成。In this way, the TVS element 220 is prepared as an NPN bipolar transistor, including a collector composed of an N + substrate 102, a base composed of a P-type buried layer 108 and a P-body region 114, and an N + The region 116 constitutes an emitter. A dielectric layer 118 is formed over the semiconductor structure to cover and protect the semiconductor elements. An opening is formed in the dielectric layer 118, and an emitter electrode is formed in the opening so that the N + region 116 forms an ohmic contact. The collector electrode is used to make electrical contact with the N + substrate 102, and the collector electrode is also formed on the back surface of the substrate. The emitter electrode and the collector electrode are usually made of a conductive material such as a metal layer.
在本說明書中，TVS元件220與溝槽隔離結構隔開。在本實施例中，溝槽隔離結構延伸到N+基板102，以隔開TVS元件220，並且溝槽內襯氧化層109，用多晶矽層110填充。在其他實施例中，可以使用一個氧化物填充溝槽隔離結構。在第15圖中，兩個溝槽隔離結構111表示在TVS元件220的任一邊上。在實際的實施例中，溝槽隔離結構111可以是一個單獨的溝槽隔離結構111，包圍著TVS元件220的中心部分或主動區。In this specification, the TVS element 220 is separated from the trench isolation structure. In this embodiment, the trench isolation structure extends to the N + substrate 102 to separate the TVS element 220, and the trench is lined with an oxide layer 109 and filled with a polycrystalline silicon layer 110. In other embodiments, a trench isolation structure may be filled with an oxide. In FIG. 15, two trench isolation structures 111 are shown on either side of the TVS element 220. In an actual embodiment, the trench isolation structure 111 may be a single trench isolation structure 111 that surrounds a central portion or an active area of the TVS element 220.
TVS元件220進一步包括一個重摻雜的P+區126，形成在半導體結構的表面上，並且電連接到發射極電勢，例如藉由電介質層118中的一個接觸開口，連接到發射極電極。在TVS元件220中，利用額外的溝槽隔離結構130，使P+區126與TVS元件220的主動區隔離，TVS元件220的主動區由N+區116限定。另外，在TVS元件200中，掩埋P-本體結由P-本體一區124構成，P-本體一區124形成在P-本體區114中，並且在P+區126和P-本體區114的結處。P-本體一區124比P-本體區114更加重摻雜。這樣一來，NPN雙極電晶體主動區就形成在溝槽隔離結構130和PN結二極體之間，PN結二極體形成在隔離結構111和130之間。PN結二極體形成在P-型區(包括P+區126、P-本體一區124、P-本體區114以及P-掩埋層108)和N+基板102之間的結處。The TVS element 220 further includes a heavily doped P + region 126 formed on the surface of the semiconductor structure and electrically connected to the emitter potential, such as through a contact opening in the dielectric layer 118, to the emitter electrode. In the TVS element 220, an additional trench isolation structure 130 is used to isolate the P + region 126 from the active region of the TVS element 220, and the active region of the TVS element 220 is defined by the N + region 116. In addition, in the TVS element 200, the buried P-body junction is composed of a P-body region 124, the P-body region 124 is formed in the P-body region 114, and the junction between the P + region 126 and the P-body region 114 Office. The P-body region 124 is more heavily doped than the P-body region 114. In this way, the active region of the NPN bipolar transistor is formed between the trench isolation structure 130 and the PN junction diode, and the PN junction diode is formed between the isolation structures 111 and 130. The PN junction diode is formed at a junction between the P-type region (including the P + region 126, the P-body region 124, the P-body region 114, and the P-buried layer 108) and the N + substrate 102.
TVS元件220進一步包括一個P-型摻雜區132，形成在P-型掩埋層108和N+基板102之間的結處。在一個實施例中，P-型摻雜區132作為P-型掩埋層區，用PBL2區132表示。在本實施例中，TVS元件220包括一個P-型摻雜區132，形成在P-型掩埋層108和N+基板102之間的結處。在一個實施例中，P-型摻雜區132作為P-型掩埋層區，用PBL2區132表示。PBL2區132比P-型掩埋層108更加重摻雜，並穿過溝槽隔離結構111之間的整個主動區形成。在本實施例中，PBL2區132形成在比P-型掩埋層108更深的結深處。溝槽隔離結構130延伸穿過PBL2區132的層，使PBL2區132的層與溝槽隔離結構111和130之間的有源二極體區域隔離。這樣一來，TVS元件220包括PBL2區132，優化雙極電晶體的集電極-基極結，並且TVS元件220包括P-本體一區124，以優化PN結二極體的p-n結。The TVS element 220 further includes a P-type doped region 132 formed at a junction between the P-type buried layer 108 and the N + substrate 102. In one embodiment, the P-type doped region 132 serves as a P-type buried layer region, and is represented by the PBL2 region 132. In this embodiment, the TVS element 220 includes a P-type doped region 132 formed at a junction between the P-type buried layer 108 and the N + substrate 102. In one embodiment, the P-type doped region 132 serves as a P-type buried layer region, and is represented by the PBL2 region 132. The PBL2 region 132 is more heavily doped than the P-type buried layer 108 and is formed through the entire active region between the trench isolation structures 111. In this embodiment, the PBL2 region 132 is formed at a deeper junction depth than the P-type buried layer 108. The trench isolation structure 130 extends through the layer of the PBL2 region 132 to isolate the layer of the PBL2 region 132 from the active diode region between the trench isolation structures 111 and 130. In this way, the TVS element 220 includes a PBL2 region 132 to optimize the collector-base junction of the bipolar transistor, and the TVS element 220 includes a P-body one region 124 to optimize the p-n junction of the PN junction diode.
第16圖表示依據本發明的第四實施例，帶有單獨優化的集電極-基極結和p-n結的單向TVS元件230的剖面圖。參見第16圖，TVS元件230除了製成P-型掩埋層108和P-本體區114之外，其配置方式都與第15圖所示的TVS元件220的配置方式相同。在第15圖所示的TVS元件220中，形成單獨的P-型掩埋層108和P-本體區114。在第16圖所示的TVS元件230中，利用全面P-型層115，代替單獨的PBL和P-本體層。全面P-型層115形成在N-外延層104的整個表面上。TVS元件230的剩餘部分可以按照第15圖所示的相同的配置方式製備。FIG. 16 shows a cross-sectional view of a unidirectional TVS element 230 with individually optimized collector-base junctions and p-n junctions according to a fourth embodiment of the present invention. Referring to FIG. 16, the TVS element 230 is configured in the same manner as the TVS element 220 shown in FIG. 15 except that the P-type buried layer 108 and the P-body region 114 are made. In the TVS element 220 shown in FIG. 15, a separate P-type buried layer 108 and a P-body region 114 are formed. In the TVS element 230 shown in FIG. 16, a full P-type layer 115 is used instead of the separate PBL and P-body layers. A full P-type layer 115 is formed on the entire surface of the N-epitaxial layer 104. The rest of the TVS element 230 can be prepared in the same configuration as shown in FIG. 15.
在本發明的實施例中，單向或雙向TVS元件的擊穿電壓，都可以藉由調節摻雜基極區的摻雜水平來調節——P-本體區或P-本體一區或P-掩埋層或PBL2區。藉由降低基極摻雜區的摻雜水平，TVS元件的擊穿電壓增大。在某些實施例中，可以增大P-型外延層(如果有的話)的厚度，從而增大擊穿電壓。In the embodiments of the present invention, the breakdown voltage of the unidirectional or bidirectional TVS element can be adjusted by adjusting the doping level of the doped base region—P-body region or P-body region or P- Buried layer or PBL2 area. By reducing the doping level of the base doped region, the breakdown voltage of the TVS element increases. In some embodiments, the thickness of the P-type epitaxial layer, if any, can be increased, thereby increasing the breakdown voltage.
雖然為了表述清楚，以上內容對實施例進行了詳細介紹，但是本發明並不局限於上述細節。實施本發明還有許多可選方案。文中的實施例僅用於解釋說明，不用於局限。Although the embodiments have been described in detail in the above for clarity, the present invention is not limited to the above details. There are many alternatives for implementing the invention. The examples in the text are only used for explanation and are not used for limitation.
1‧‧‧單向TVS保護元件(TVS元件)1‧‧‧One-way TVS protection element (TVS element)
2、6‧‧‧受保護的節點2, 6‧‧‧ protected nodes
5‧‧‧雙向TVS保護元件(TVS元件)5‧‧‧Two-way TVS protection element (TVS element)
10、20、30、40、50、60、200、210、220、230‧‧‧TVS元件10, 20, 30, 40, 50, 60, 200, 210, 220, 230‧‧‧TVS components
102‧‧‧N+基板102‧‧‧N + substrate
104‧‧‧N-外延層104‧‧‧N-Epitaxial Layer
106‧‧‧N-型掩埋層106‧‧‧N-type buried layer
106A‧‧‧N-型掩埋層部分106A‧‧‧N-type buried layer part
108‧‧‧P-型掩埋層108‧‧‧P-type buried layer
109‧‧‧溝槽內襯氧化層109‧‧‧ trench lining oxide layer
110‧‧‧多晶矽層110‧‧‧polycrystalline silicon layer
111、130‧‧‧溝槽隔離結構111, 130‧‧‧Trench isolation structure
112‧‧‧P-型外延層112‧‧‧P-type epitaxial layer
114‧‧‧P-本體區114‧‧‧P-Body area
115‧‧‧全面P-型層115‧‧‧Comprehensive P-type layer
116‧‧‧N+區116‧‧‧N +
118‧‧‧電介質層118‧‧‧Dielectric layer
120‧‧‧受保護節點120‧‧‧ Protected Node
122‧‧‧參考節點122‧‧‧Reference node
124‧‧‧P-本體一區124‧‧‧P-Ontology 1
126‧‧‧P+區126‧‧‧P +
128‧‧‧N+沉降區128‧‧‧N + subsidence area
132‧‧‧P-型摻雜區(PBL2區)132‧‧‧P-type doped region (PBL2 region)
Q1、Q2‧‧‧NPN電晶體Q1, Q2‧‧‧NPN transistors
Q2A、Q2B‧‧‧NPN雙極電晶體Q2A, Q2B‧‧‧NPN Bipolar Transistor
D1、D2‧‧‧PN結二極體D1, D2‧‧‧PN junction diodes
以下的詳細說明及圖式提出了本發明的各個實施例。The following detailed description and drawings set forth various embodiments of the invention.
第1圖表示在本發明的實施例中，單向TVS保護元件的電路圖。FIG. 1 shows a circuit diagram of a unidirectional TVS protection element in an embodiment of the present invention.
第2圖表示在本發明的實施例中，雙向TVS保護元件的電路圖。FIG. 2 shows a circuit diagram of a bidirectional TVS protection element in the embodiment of the present invention.
第3圖表示依據本發明的第一實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。Figure 3 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a first embodiment of the invention.
第3a圖表示第3圖所示的TVS元件的等效電路。Fig. 3a shows an equivalent circuit of the TVS element shown in Fig. 3.
第4圖表示依據本發明的第二實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。Figure 4 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a second embodiment of the invention.
第5圖表示在某些實施例中，第4圖所示的一部分TVS元件的俯視圖。FIG. 5 shows a plan view of a portion of the TVS element shown in FIG. 4 in some embodiments.
第6圖表示依據本發明的第三實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。FIG. 6 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a third embodiment of the present invention.
第7圖表示在某些實施例中，第6圖所示的一部分TVS元件的俯視圖。FIG. 7 shows a top view of a portion of the TVS element shown in FIG. 6 in some embodiments.
第8圖表示依據本發明的第四實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。FIG. 8 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a fourth embodiment of the present invention.
第9圖表示在某些實施例中，第8圖所示的一部分TVS元件的俯視圖。FIG. 9 shows a top view of a portion of the TVS element shown in FIG. 8 in some embodiments.
第10圖 ，表示依據本發明的第一實施例，帶有單獨優化的集電極-基極和p-n結的單向TVS元件的剖面圖。FIG. 10 is a cross-sectional view of a unidirectional TVS element with individually optimized collector-base and p-n junctions according to a first embodiment of the present invention.
第10a圖表示第10圖所示的TVS元件50的等效電路。Fig. 10a shows an equivalent circuit of the TVS element 50 shown in Fig. 10.
第11圖表示表示依據本發明的第二實施例，帶有單獨優化的集電極-基極和p-n結的單向TVS元件的剖面圖。FIG. 11 is a cross-sectional view showing a unidirectional TVS element with a separately optimized collector-base and p-n junction according to a second embodiment of the present invention.
第12圖表示在某些實施例中，第11圖所示的一部分TVS元件的俯視圖。FIG. 12 shows a top view of a portion of the TVS element shown in FIG. 11 in some embodiments.
第13圖表示依據本發明的第五實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。Fig. 13 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a fifth embodiment of the present invention.
第14圖表示依據本發明的第六實施例，帶有空間分佈和單獨優化的集電極-基極和發射極-基極結的雙向TVS元件的剖面圖。Fig. 14 shows a cross-sectional view of a bidirectional TVS element with a spatially distributed and individually optimized collector-base and emitter-base junction according to a sixth embodiment of the present invention.
第15圖表示依據本發明的第三實施例，帶有單獨優化的集電極-基極和p-n結的單向TVS元件的剖面圖。Fig. 15 shows a cross-sectional view of a unidirectional TVS element with individually optimized collector-base and p-n junctions according to a third embodiment of the present invention.
第16圖表示依據本發明的第四實施例，帶有單獨優化的集電極-基極和p-n結的單向TVS元件的剖面圖。Fig. 16 shows a cross-sectional view of a unidirectional TVS element with individually optimized collector-base and p-n junctions according to a fourth embodiment of the present invention.
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