TW201918892A - Method of operating SSD in modern standby mode or connected standby mode and related SSD - Google Patents

Abstract

An SSD includes a volatile memory block and a non-volatile memory block. When a system implemented with the SSD is required to enter a modern standby mode or a connected standby mode, data stored in the volatile memory block is written into the non-volatile memory block for performing write-cache buffer flushing before cutting off the power supplied to the volatile memory block. When receiving a wake-up signal associated with standby timeout refresh, the SSD performs data refresh on the non-volatile memory block in a DRAM-less mode during which no power is supplied to the volatile memory block.

Description

Method of operating solid state hard disk in modern standby mode or wired standby mode and related solid state hard disk

The invention relates to a method for operating a solid state hard disk in a modern standby mode or a wired standby mode, and a related solid state hard disk, in particular to operating a solid state hard disk in a modern standby mode or a wired standby mode to simulate no dynamic random storage. Take the memory mode architecture method and related solid state hard disk.

A solid state disk (SSD) is a computer storage device consisting of a memory with a control chip. Compared with traditional hard disk drives (HDDs), solid state drives have the advantages of fast access speed, low power consumption, low noise, vibration resistance, and low heat, which not only make data more securely stored, but also Continuous operation time can be extended when applied to battery powered devices.

Solid-state hard disks generally use PCIe, SATA interface or NVMe interface, and memory can be configured with low-power dynamic random access memory (LPDRAM) or non-dynamic random access memory (DRAM- Less) architecture. Low-voltage double data rate 3 dynamic random access memory (DDR3L DRAM) As a cache for the SATA interface or NVMe interface.

When operating in modern standby mode or connected standby mode, the system will wake up periodically (about 30 seconds), and after updating the data, it will enter standby again to maintain the low power state. Each time you enter the modern standby mode or the connected standby mode, the solid state drive must enter the power state below DevSlp (SATA interface) or PS4 (NVMe interface). Compared to LPDRAM, which can retain data under low power consumption, DDR3L DRAM will be powered off when entering PS4 power state, so write-cache buffer flushing must be performed to store The data stored in DDR3L DRAM is stored in reverse NAND flash. However, such frequent cleaning and writing operations are very harmful to the life of the solid state hard disk. Taking a 256 GB solid state hard disk as an example, the size of the dynamic random access memory is about 200 MB, and the waiting time is 16 hours per day. As of 375GB, staying in standby for more than six and a half months will exceed the 72TBW writes proposed by the JEDEC Association. At this time, the SSD will be at risk of data corruption.

Therefore, there is a need for a method and a related solid state hard disk capable of operating a solid state hard disk in a modern standby mode or a wired standby mode to balance the high performance and low write capacity of the dynamic random access memory.

The present invention provides a method of operating a solid state hard disk in a modern standby mode or a connected standby mode. The solid state hard disk includes a volatile memory block and a non-volatile memory block. The method includes: when it is determined that a system applying the solid state hard disk needs to enter the modern standby mode or the wired standby mode, the volatile memory block writes memory data into the non-volatile memory block to perform a write The cache buffer clear operation, when the system operates in the modern standby mode or the wired standby mode, power supply to the volatile memory block is stopped; and when one of the standby timeout updates is received When the first wake-up signal is received, the solid-state hard disk updates the non-volatile memory block in a non-dynamic random access memory mode, wherein the volatile memory in the non-dynamic random access memory mode The block is not powered.

1 is a functional block diagram of a solid state hard disk 100 in an embodiment of the present invention. The solid state hard disk 100 can be applied to any computer system including a volatile memory block 10, a non-volatile memory block 20, and a control unit 30. The volatile memory block 10 can be implemented by a low-voltage double data rate 3 dynamic random access memory (DDR3L DRAM) or by other low-voltage dynamic random access memories. Body components are implemented. The non-volatile memory block 20 can be implemented by inverse NAND flash or by other types of flash memory. The control unit 30 accepts messages from the system and controls the operation of the components in the solid state drive 100 accordingly.

FIG. 2 is a flow chart of the operation of the solid state hard disk 100 in the embodiment of the present invention, which includes the following steps:

Step 210: The control unit 30 determines whether the system needs to enter the modern standby mode or the wired standby mode; if yes, step 220 is performed; if not, step 210 is performed.

Step 220: The control unit 30 controls the volatile memory block 10 to write the memory data into the non-volatile memory block 20 to perform the write cache buffer clearing operation; and step 230 is performed.

Step 230: When the system operates in the modern standby mode or the wired standby mode, power supply to the volatile memory block 10 is stopped; step 240 is performed.

Step 240: The control unit 30 determines whether a wake-up signal is received; if yes, step 250 is performed; if not, step 240 is performed.

Step 250: The control unit 30 determines that the wake-up signal is related to the standby timeout update or is related to the entry S0 mode; if it is related to the standby timeout update, step 260 is performed; if it is related to the entry S0 mode, step 270 is performed.

Step 260: Perform data update on the non-volatile memory block 20 in a DRAM-less mode; perform step 230.

Step 270: The power is supplied to the volatile memory block 10, and the memory data of the non-volatile memory block 20 is written back to the volatile memory block 10; step 280 is performed.

Step 280: The system enters the S0 mode; and step 210 is performed.

As is well known in the relevant fields, the WINDOWS operating system supports the Advanced Configuration and Power Interface (ACPI). The definitions of the modes S1~S5 in the power supply options are as follows:

S0 mode: All components are operating normally.

S1 mode: The central processing unit (CPU) stops working.

S2 mode: The CPU is turned off.

S3 mode: Accessories other than memory (including fans) stop working.

S4 mode: Write the memory data to the hard disk and all the accessories stop working.

S5 mode: Turn off all components.

The S4 mode is usually the system's default sleep mode. Since the data in the memory has been completely stored in the hard disk, the memory can be read directly from the hard disk after waking up, because there is no need to execute a bunch of applications like booting. Program, so the speed is much faster than normal boot.

The wired standby mode or the modern standby mode is a new power management system for the WINDOWS operating system. When the system enters the sleep state, the application is suspended (suspend), but it will still be connected to the network. In other words, the application on the Metro UI will continue to update and receive new information, allowing users to instantly update specific data or applications (such as emails and message notifications) on the device. On the other hand, other applications that are not executed on the screen will temporarily stop and store their state, which means that they do not consume CPU power for effective power management purposes. In other words, when the system is operating in wired standby mode or modern standby mode, it behaves like a smart phone. Although the screen device is turned off or hibernated, other applications will maintain and remotely with low power. Link to let the information not be missed or delayed.

In step 210, the control unit 30 determines whether the system to which the solid state hard disk 100 is applied needs to enter the modern standby mode or the wired standby mode. The command to enter the modern standby mode or the wired standby mode can be issued by the user, or the system automatically issues relevant instructions after being idle for more than a predetermined period of time. However, the conditions in which the system using the solid state hard disk 100 enters the modern standby mode or the wired standby mode does not limit the scope of the present invention.

When the system applying the solid state hard disk 100 needs to enter the modern standby mode or the wired standby mode, the control unit 30 controls the volatile memory block 10 to write the memory data to the non-volatile memory block 20 in step 220. Execute the write cache buffer to clear the operation. Next, when the system is operating in the modern standby mode or the wired standby mode in step 230, the solid state hard disk 100 stops supplying power to the volatile memory block 10 to reduce system power consumption.

At step 240, control unit 30 determines if a wake-up signal has been received. As mentioned earlier, when the system enters the modern standby mode or the connected standby mode, it will still be connected to the network. The application on the Metro UI will continue to update and receive new information, so it needs to be at regular intervals. To perform a standby overtime update to ensure data integrity. In addition, the system may also trigger an event returning to the normal S0 mode due to an instruction issued by the user. Accordingly, the present invention can determine in step 250 that the wake-up signal is related to a standby timeout update or to an entry S0 mode.

If it is determined in step 250 that the wake-up signal is related to the standby timeout update, the present invention performs step 260 to perform data update on the non-volatile memory block 20 in the DRAM-less mode, but the volatile memory block 10 remains No power supply. In other words, the present invention does not increase the amount of data written by the volatile memory block 10 when performing the standby timeout update.

If it is determined in step 250 that the wake-up signal is related to entering the S0 mode, the present invention performs step 270 to supply power to the volatile memory block 10, and writes the non-volatile memory block 20 memory data back to the volatile memory region. Block 10. In this way, when the system enters the S0 mode in step 280, the solid state hard disk 100 can quickly provide data to return to the previous working state.

In the present invention, the manner of entering the DRAM-less mode in step 260 can be implemented by means of firmware or another combination of software. In the embodiment of the firmware binding software, the system may add a notification in the Set Feature Command to inform the solid state hard disk 100 that the standby timeout update is to be performed in the DRAM-less mode, the solid state hard disk 100 The body is also modified to recognize the new notifications in the configuration command. In an embodiment of the firmware, the solid state drive 100 can set a flag associated with the DRAM-less mode in the control unit 30: when the system enters the modern standby mode or the wired standby mode, the control unit 30 Raising the flag, indicating that the non-volatile memory block 20 is updated in the DRAM-less mode when the standby timeout update is performed; when the system triggers the event of restoring the S0 mode, the control unit 30 The reset flag indicates that the volatile memory block 10 is updated with data.

In summary, the present invention provides a method and related solid state hard disk capable of operating a solid state hard disk in a modern standby mode or a wired standby mode. When the system operates in the modern standby mode or the wired standby mode, the solid state hard disk of the present invention performs standby overtime update in the DRAM-less mode, thereby reducing the amount of writing of volatile memory blocks. When the system needs to return to the normal mode, the solid state hard disk of the present invention performs data update in the volatile memory block to improve access efficiency. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ volatile memory blocks

20‧‧‧Non-volatile memory blocks

30‧‧‧Control unit

100‧‧‧ Solid State Drive

210~280‧‧‧Steps

1 is a functional block diagram of a solid state hard disk in an embodiment of the present invention. FIG. 2 is a flow chart of the operation of the solid state hard disk in the embodiment of the present invention.

Claims (7)

A method of operating a solid state disk (SSD) in a modern standby mode or a wired standby mode, the solid state hard disk including a volatile memory block and a non-volatile memory block. The method includes: when it is determined that a system applying the solid state hard disk needs to enter the modern standby mode or the wired standby mode, the volatile memory block writes memory data into the non-volatile memory block to execute a Writing to the cache buffer to clear the operation; when the system operates in the modern standby mode or the wired standby mode, powering off the volatile memory block; and receiving an update related to the standby timeout When the first wake-up signal is received, the solid state hard disk performs data update on the non-volatile memory block in a DRAM-less mode, wherein the non-dynamic random access memory mode The volatile memory block is not powered. The method of claim 1, further comprising: when receiving a second wake-up signal related to entering one of the S0 modes, the solid state hard disk supplies power to the volatile memory block, and the non-volatile memory is The body block memory data is written back to the volatile memory block. The method of claim 2, further comprising: the solid state hard disk setting a flag associated with the no-dynamic random access memory mode; when the system enters the modern standby mode or the connection is standby In the mode, the solid state hard disk raises the flag; and when the system triggers an event to resume the S0 mode, the solid state hard disk clears the flag. The method of claim 1, further comprising: the system adding a notification in a set configuration command to notify the solid state hard disk to be executed in the no-dynamic random access memory mode Standby timeout update. The method of claim 1, further comprising: implementing the volatile memory using a low-voltage double data rate 3 dynamic random access memory (DDR3L DRAM) Block; and use the inverse NAND flash to implement the non-volatile memory block. A solid state hard disk comprising: a volatile memory block; a non-volatile memory block; and a control unit for: when determining that one of the solid state drives is required to enter a modern standby mode or In a connected standby mode, controlling the volatile memory block to write memory data into the non-volatile memory block to perform a write cache buffer clearing operation; when the system is in the modern standby mode or Stopping power supply to the volatile memory block when operating in the wired standby mode; and controlling the solid state hard disk in a no-dynamic random access memory when receiving one of the first wake-up signals related to the standby timeout update Data updating of the non-volatile memory block in the body mode, wherein the volatile memory block is not powered in the non-dynamic random access memory mode; and when receiving the relevant entry into a S0 mode Controlling the solid state hard disk to the volatile memory block when the second wake-up signal is received, and controlling the non-volatile memory block to write the memory data back to the volatile memory Piece. The solid state hard disk of claim 6, wherein: the volatile memory block is a low-voltage double data rate 3 dynamic random access memory (DDR3L DRAM) The implementation is performed; and the non-volatile memory block is implemented by inverse NAND flash.