TW201916596A - Adjustable signal equalization device and adjustment method thereof - Google Patents

Abstract

An adjustable signal equalization device includes an equalizer circuitry, an analog-to-digital converter (ADC), a calculation circuitry, and a comparator circuitry. The equalizer circuitry has a transfer function, and processes an input signal based on the transfer function to generate an output signal. The ADC generates a digital signal according to the output signal. The calculation circuitry performs an accumulation according to the first digital signal to generate a first accumulated value and a second accumulated value, and generates a first detection signal and a second detection signal according to the first accumulated value and the second accumulated value. The comparator circuitry compares the first detection signal with the second detection signal to output a control signal to the equalizer circuit if the first detection signal is different from the second detection signal, in order adjust the transfer function.

Description

 Adjustable signal equalization device and adjustment method thereof  

This case is related to an equalizer, and in particular to an adjustable signal equalization device and an adaptive adjustment method thereof.

Equalizers are commonly used in data transfer interfaces to compensate for channel attenuation and reduce inter-symbol interference (ISI). In some techniques, the equalizer can adjust its transfer function by a detection mechanism implemented by the analog circuit. However, in these techniques, the detection mechanism is susceptible to variations in process, voltage, or temperature that cause errors in the transfer function of the equalizer.

Alternatively, in other techniques, the equalizer may adjust its transfer function by detecting the edge of the signal. However, in these techniques, as the circuit operates faster or the form of the signal becomes more complex, the higher the circuit required for this detection mechanism, the more difficult it is to implement.

In order to solve the above problems, an aspect of the present invention is to provide an adjustable signal equalization device including an equalizer circuit system, an analog to digital converter, a calculation circuit system, and a comparison circuit system. The equalizer circuitry has a transfer function and is used to process the input signal based on the transfer function to produce an output signal. The analog to digital converter is configured to generate a first digital signal according to the output signal. The calculating circuit system is configured to generate a first accumulated value and a second accumulated value according to the first digital signal, and generate the first detecting signal and the second detecting signal according to the first accumulated value and the second accumulated value . Comparing the first detection signal and the second detection signal, and outputting a control signal to the equalizer circuit when the first detection signal is different from the second detection signal, Adjust the transfer function.

In some embodiments, the computing circuitry includes a first accumulation circuit, a delay circuit, and a second accumulation circuit. The first accumulating circuit is configured to generate the first accumulated value according to the first digital signal. The delay circuit is configured to delay the first digital signal to generate a second digital signal. The second accumulating circuit is configured to generate the second accumulated value according to the second digital signal.

In some embodiments, the computing circuit system further includes a first frequency down circuit and a second frequency down circuit. The first frequency down circuit is configured to downsample the first digital signal to generate a third digital signal, wherein the first accumulating circuit is configured to accumulate the third digital signal to generate the first accumulated value. The second frequency reduction circuit is configured to downsample the second digital signal to generate a fourth digital signal, wherein the second accumulation circuit is configured to accumulate the fourth digital signal to generate the second accumulated value.

In some embodiments, the computing circuit system further includes a first operational circuit and a second operational circuit. The first operation circuit is configured to add the first accumulated value and the second accumulated value to generate the first detection signal. The second operation circuit is configured to subtract the first accumulated value and the second accumulated value to generate the second detection signal.

In some embodiments, the fast Fourier transform of the first digital signal satisfies the following equation (1):

Where k=0,1,...,N-1,N is a positive number and is the number of sampling points, W _N is the N-th unit root, wherein the first accumulated value is equivalent to multiple odd-numbered lines in the above formula (1) The sum of the factors, and the second accumulated value corresponds to the sum of the plurality of even-numbered sub-factors in the above formula (1).

In some embodiments, the first detection signal satisfies the following equation in the frequency domain:

In some embodiments, the second detection signal satisfies the following equation in the frequency domain:

In some embodiments, the comparison circuit is configured to determine an absolute value of the first detection signal to determine a first energy of the first detection signal, and determine an absolute value of the second detection signal to determine the And a second energy of the second detecting signal, to output the control signal according to the comparison result of the first energy and the second energy.

In some embodiments, the adjustable signal equalization device further includes an amplifier. The amplifier is configured to amplify the output signal, wherein the analog to digital converter is further configured to generate the first digital signal according to the amplified output signal.

An aspect of the present invention is to provide an adjustment method for adjusting a transfer function of an equalizer circuit system, the adjustment method comprising the following operation: converting an output of the equalizer circuit system by an analog to digital converter Outputting a signal to a first digit signal; generating, by a computing circuit system, the first accumulated value and the second accumulated value according to the first digital signal, and according to the first accumulated value and the second accumulated value Generating a first detection signal and a second detection signal; and comparing the first detection signal and the second detection signal by a comparison circuit system, and the first detection signal is different from the second A control signal is output to the equalizer circuitry when the signal is detected to adjust the transfer function.

In some embodiments, generating the first detection signal and the second detection signal includes: generating, by the first accumulation circuit of the calculation circuit system, the first accumulated value according to the first digital signal; And delaying the first digital signal by the delay circuit of the computing circuit to generate a second digital signal; and generating, by the second accumulating circuit of the computing circuit, the second digital signal to generate the second Accumulated value.

In some embodiments, generating the first detection signal and the second detection signal further comprises: downsampling the first digital signal by a first frequency reduction circuit of the computing circuit to generate a third digit a signal, wherein the first accumulating circuit is configured to accumulate the third digit signal to generate the first accumulated value; and the second down-converting circuit of the computing circuit system downsamples the second digit signal to generate a first a fourth digit signal, wherein the second accumulation circuit is configured to accumulate the fourth digit signal to generate the second accumulated value.

In some embodiments, generating the first detection signal and the second detection signal further comprises: adding, by the first operation circuit of the computing circuit system, the first accumulated value and the second accumulated value to Generating the first detection signal; and subtracting the first accumulated value and the second accumulated value by a second operation circuit of the computing circuit to generate the second detection signal.

In some embodiments, the fast Fourier transform of the first digital signal satisfies the following equation (1):

Where k=0,1,...,N-1,N is a positive number and is the number of sampling points, W _N is the N-th unit root, wherein the first accumulated value is equivalent to multiple odd-numbered lines in the above formula (1) The sum of the factors, and the second accumulated value corresponds to the sum of the plurality of even-numbered sub-factors in the above formula (1).

In some embodiments, the first detection signal satisfies the following equation in the frequency domain:

In some embodiments, the second detection signal satisfies the following equation in the frequency domain:

In summary, the adjustable signal equalization device and the adjustment method provided by the present invention can be implemented by simple calculation and digital circuit to reduce the required specifications of the circuit and reduce the influence of variation.

100‧‧‧Adjustable signal equalization device

120‧‧‧ Equalizer circuit system

130‧‧‧ Analog to Digital Converter

140‧‧‧Computational Circuit System

150‧‧‧Comparative Circuit System

VIN‧‧‧ input signal

VC‧‧‧ control signal

VO, VO1‧‧‧ output signal

VD‧‧‧ digital signal

VD1~VD3‧‧‧ digital signal

125‧‧‧Amplifier

A, B‧‧‧ detection signals

141, 142‧‧‧down frequency circuit

143, 144‧‧‧ accumulator circuit

145, 146‧‧‧ arithmetic circuits

147‧‧‧Delay circuit

A1, B1‧‧‧ cumulative value

VIN+, VIN-‧‧‧Differential input signal

VO+, VO-‧‧‧Differential output signal

M1~M4‧‧‧O crystal

RS‧‧‧ adjustable resistor

CS‧‧‧ adjustable capacitor

RL1, RL2‧‧‧ load resistor

VBIAS‧‧‧ bias

300‧‧‧Adjustment method

S310~S330‧‧‧ operation

The schematic diagram of the present invention is as follows: FIG. 1 is a schematic diagram of an adjustable signal equalization device according to some embodiments of the present invention; FIG. 2A is a first image intermediateizer according to some embodiments of the present disclosure. Circuit diagram of the circuit system; FIG. 2B is a schematic diagram showing changes of the transfer function of the circuitizer of the sizing device of FIG. 2A according to some embodiments of the present invention; and FIG. 3 is a schematic diagram of an adjustment method according to some embodiments of the present disclosure. flow chart.

"Coupling" or "connecting" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or two or more The components operate or act on each other.

As used herein, the term "circuitry" refers to a single system that includes one or more circuits. The term "circuitry" generally refers to an object that is connected in a manner by one or more transistors and/or one or more active and passive components to process a signal.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of an adjustable signal equalization device 100 according to some embodiments of the present disclosure. In some embodiments, the adjustable signal equalization device 100 can be applied to a system of a sequencer/deserializer (SerDes), but the present invention is not limited thereto.

In some embodiments, the tunable signal equalization device 100 includes an equalizer circuitry 120, an analog to digital converter 130, a computing circuitry 140, and a comparison circuitry 150. The equalizer circuit system 120 is configured to adjust its internal transfer function according to the control signal VC, and process the input signal VIN based on the transfer function to generate an output signal VO. The input signal VIN can be a data or signal transmitted from a channel (not shown) by a transmitter circuit (not shown). In general, the frequency response of a channel is a low-pass function. In other words, the high frequency component of the input signal VIN will be attenuated by the channel. In some embodiments, to compensate for this attenuation, the transfer function of the equalizer circuitry 120 is set to a high pass function (as shown in Figure 2B below). In some embodiments, the transfer function referred to herein is substantially the frequency response between the input and output of the equalizer circuitry 120.

The analog to digital converter 130 is coupled to the equalizer circuit system 120 to generate a digital signal VD based on the output signal VO. In some embodiments, as shown in FIG. 1, the adjustable signal equalization device 100 further includes an amplifier 125. The amplifier 125 is used to amplify the output signal VO to generate the output signal VO1, and the analog to digital converter 130 is used to convert the output signal VO1 to the digital signal VD. In some embodiments, the amplifier 125 can be implemented by a variable gain amplifier, wherein the gain of the amplifier 125 can be adjusted according to analog to the specifications of the digital converter 130 (eg, the input voltage range).

The computing circuitry 140 is coupled to the analog to digital converter 130 to receive the digital signal VD. The calculation circuit system 140 is configured to accumulate based on the digital signal VD to generate the detection signal A and the detection signal B.

In some embodiments, the computing circuit system 140 includes a plurality of frequency down circuits 141 - 142 , a plurality of accumulation circuits 143 - 144 , a plurality of arithmetic circuits 145 - 146 , and a delay circuit 147 .

The down-conversion circuit 141 is configured to down-sample the digital signal VD to generate a digital signal VD1. For example, the down-conversion circuit 141 is configured to reduce the sample rate of the digital signal VD by two times to generate the digital signal VD1. The accumulation circuit 143 is coupled to the down conversion circuit 141 to receive the digital signal VD1. The accumulation circuit 143 accumulates the digital signal VD1 to generate an accumulated value A1.

The delay circuit 147 is coupled to the analog to digital converter 130 to receive the digital signal VD. The delay circuit 147 is configured to delay the digital signal VD for a predetermined time to generate the digital signal VD2. In some embodiments, the delay circuit 147 can be implemented by an integrator or one or more inverters coupled in series, but the present invention is not limited thereto. The down-conversion circuit 142 is configured to downsample the digital signal VD2 to generate a digital signal VD3. For example, the down-conversion circuit 142 is configured to reduce the sampling rate of the digital signal VD2 by two times to generate the digital signal VD3. The accumulation circuit 144 is coupled to the down conversion circuit 142 to receive the digital signal VD3. The accumulation circuit 144 accumulates the digital signal VD3 to generate an accumulated value B1. In some embodiments, the accumulating circuit 143 and the accumulating circuit 144 may be implemented by logic circuits such as a register and/or an adder, but the present invention is not limited thereto.

The operation circuit 145 is configured to add the accumulated value A1 and the accumulated value B1 to generate the detection signal A. The operation circuit 146 is configured to subtract the accumulated value A1 and the accumulated value B1 to generate the detection signal B. In some embodiments, the arithmetic circuit 145 and the arithmetic circuit 146 can be implemented by an adder.

The design concept of the calculation circuit system 140 in the above embodiment will be explained below in the frequency domain concept. If the fast signal Fourier transform is used for the digital signal VD, the following equation can be derived, where N is a positive number and is the number of sampling points, and k represents the kth sampling point (that is, corresponding to the sine wave with the kth frequency), W _N is N times unit root:

In the above formula, when k=0, the following formula (1) can be obtained:

According to the formula (1), in the frequency domain, if each digital signal VD is accumulated, the signal component of the digital signal VD at the direct current (DC) frequency can be equivalently obtained.

Or, when k=N/2, X(k) can be expressed as:

In the frequency domain, if the difference between two consecutive digital signal VDs is added, the above equation (2) can be obtained equivalently. Compared with the above formula (1), the equation (2) shows the signal component of the digital signal VD at a high frequency.

In the above equations (1) and (2), factors that can be divided into even-numbered terms (ie, x(0), x(2), ..., etc.) and factors of odd-order terms (ie, x(1) ), x(3), ..., etc.). In some embodiments, the accumulated value A1 obtained by processing the input signal VD through the down-converting circuit 141 and the accumulating circuit 143 is equivalent to the sum of the even-numbered sub-factors. In other words, in the frequency domain, the accumulated value A1 is equivalent to x(0)+x(2)+x(4)+....

Similarly, in some embodiments, the accumulated value B1 obtained by processing the input signal VD through the delay circuit 147, the down-conversion circuit 142, and the accumulation circuit 144 is equivalent to the sum of the odd-order factor. In other words, in the frequency domain, the accumulated value B1 is equivalent to x(1)+x(3)+x(5)+....

Accordingly, in the frequency domain, the detection signal A obtained by adding the cumulative value A1 and the integrated value B1 is equivalent to the above formula (1), and the Detect obtained by subtracting the cumulative value A1 and the cumulative value B1 The test signal B corresponds to the above formula (2). The detection signal A is associated with the low frequency component of the digital signal VD (ie, the DC frequency), and the detection signal B is associated with the high frequency component of the digital signal VD. In this way, by comparing the energy of the detection signal A and the detection signal B, it can be known whether the equalizer circuit system 120 has an over equalization or an under equalization.

Continuing to refer to FIG. 1 , the comparison circuit system 150 is coupled to the computing circuit system 140 to receive the detection signal A and the detection signal B. The comparison circuit system 150 is configured to calculate the energy of the detection signal A and the energy of the detection signal B, and further compare the energy of the two to output the control signal VC to adjust the transfer function of the equalizer circuit system 120. In some embodiments, the comparison circuit system 150 can determine the energy of the detection signal A by taking an absolute value of the detection signal A, and determine the energy of the detection signal B by taking an absolute value of the detection signal B, but the case Not limited to this. In some embodiments, comparison circuitry 150 can be implemented by an arithmetic circuit and a comparator to perform the operations described above. Alternatively, in some embodiments, comparison circuitry 150 can be implemented by a digital processing circuit to perform the operations described above. The foregoing embodiment of the comparison circuit system 150 is merely an example, and the present invention is not limited thereto.

For example, when the energy of the detection signal A is greater than the energy of the detection signal B, the energy representing the low frequency signal is greater than the energy of the high frequency signal. Under these conditions, the transfer function of the high equalizer circuit system 120 can be adjusted at a high frequency gain, or the gain of the transfer function of the equalizer circuit system 120 at a low frequency can be reduced to adjust the equalization of the equalizer circuit system 120. strength. Alternatively, when the energy of the detection signal B is greater than the energy of the detection signal A, the energy representing the high frequency signal is greater than the energy of the low frequency signal. Under these conditions, the transfer function of the high equalizer circuit system 120 can be adjusted at a low frequency gain, or the gain of the transfer function of the equalizer circuit system 120 at a high frequency can be reduced to adjust the equalization of the equalizer circuit system 120. strength.

In some embodiments, computing circuitry 140 and comparison circuitry 150 may be implemented by a microcontroller, a digital signal processing circuit, or an application specific integrated circuit (ASIC). The manner of setting the calculation circuit system 140 described above is merely an example, but the present invention is not limited thereto. For example, in some other embodiments, the computing circuit system 140 can directly perform the operations of the foregoing equations (1) and (2) according to the digital signal VD to generate the detection signal A and the detection signal B.

In some embodiments, the adjustable signal equalization device 100 further includes a low pass filter (not shown). The low pass filter is coupled between the comparison circuit system 150 and the equalizer circuit system 120. In some embodiments, the low pass filter can adjust the transfer function of the equalizer circuitry 120 when the control signal VC accumulates above a reference value. As such, the equalizer circuitry 120 can be prevented from being over-adjusted during operation.

In some related technologies, the mechanism for detecting the edge of the signal is often used to determine whether the equalizer is excessively equalized or equalized. In these technologies, as the form of the signal becomes more and more complex (for example, PAM4, PAM8 encoding, etc.) or the operating speed of the circuit increases, the circuit specification requirements for implementing this mechanism will become higher. In this way, the power of the circuit mechanism of the equalizer is too high or the circuit area is too large.

In contrast to the above techniques, the present invention employs the concept of frequency domain to design computing circuitry 140, wherein the operation of computing circuitry 140 can be implemented by simple operations (addition and subtraction operations) and digital circuitry. As such, the circuit specifications of the computing circuitry 140 can be reduced. In addition, by means of digital signal processing, the comparison circuitry 150 can calculate the energy by calculating the absolute value. In this way, the analog power detector can be avoided to calculate energy. Therefore, computing circuitry 140 and comparison circuitry 150 are less affected by process, voltage, or temperature variations.

Referring to FIG. 2A, FIG. 2A is a circuit diagram of the singulator circuit system 120 of FIG. 1 according to some embodiments of the present disclosure. In this example, the input signal VIN in FIG. 1 is a set of differential input signals VIN+ and VIN- and the output signal VO in FIG. 1 is a set of differential output signals VO+ and VO-.

In this example, the equalizer circuit system 120 includes a plurality of transistors M1 M M4, an adjustable resistor RS, a tunable capacitor CS, and a plurality of load resistors RL1 RL RL2. The first end of the transistor M1 is coupled to the load resistor RL1, the second end of the transistor M1 is coupled to the first end of the transistor M3, and the control end of the transistor M1 is configured to receive the input signal VIN+. The first end of the transistor M2 is coupled to the load resistor RL2, the second end of the transistor M2 is coupled to the first end of the transistor M4, and the control end of the transistor M2 is configured to receive the input signal VIN-. The second ends of the transistors M3 and M4 are coupled to ground, and the control terminals of the transistors M3 and M4 are used to receive the bias voltage VBIAS.

The adjustable resistor RS is coupled in parallel with the variable capacitor CS between the second end of the transistor M1 and the second end of the transistor M2. In some embodiments, at least one of the adjustable resistor RS and the variable capacitor CS is set to be controlled by the control signal VC of FIG. For example, in some embodiments, the capacitance of the variable capacitor CS is set to be fixed, and the resistance of the adjustable resistor RS is adjusted by the control signal VC. In some embodiments, the resistance of the adjustable resistor RS is set to be fixed, and the capacitance of the variable capacitor CS is adjusted by the control signal VC. Alternatively, in still other embodiments, the resistance of the adjustable resistor RS and the capacitance of the variable capacitor CS are simultaneously adjusted by one or more control signals VC.

In some embodiments, the adjustable resistance RS can be implemented by a switched resistor array. In some embodiments, the adjustable resistance RS can be implemented by a voltage controlled resistor, wherein the voltage controlled resistor can be implemented by a transistor. In some embodiments, the variable capacitance CS can be implemented by a switched capacitor array. In some embodiments, the variable capacitance CS can be implemented by a voltage controlled capacitor, wherein the voltage control capacitor can be implemented by a transistor. The embodiments of the above various elements are merely examples, and other various applicable embodiments are within the scope of the present disclosure.

Referring to FIGS. 2A and 2B, FIG. 2B is a schematic diagram showing changes in the transfer function of the chemist circuit 120 of FIG. 2A according to some embodiments of the present invention. For ease of understanding, in the example of FIG. 2B, the resistance of the variable resistor RS is set to be adjusted based on the control signal VC, and the capacitance of the variable capacitor CS is set to be fixed. The gain of the transfer function of the equalizer circuit system 120 at the low frequency is related to the variable resistance RS. For example, as the resistance of the variable resistor RS is larger, the gain of the transfer function of the equalizer circuit system 120 at the low frequency is smaller. Alternatively, as the resistance of the variable resistor RS is smaller, the gain of the transfer function of the equalizer circuit system 120 at the low frequency is larger.

Therefore, when the energy of the detection signal A is greater than the energy of the detection signal B, the energy representing the low frequency signal is greater than the energy of the high frequency signal. Under this condition, the comparison circuit system 150 can output a corresponding control signal VC to increase the resistance of the variable resistor RS, thereby making the gain of the transfer function of the equalizer circuit system 120 low at the low frequency.

Alternatively, when the energy of the detection signal B is greater than the energy of the detection signal A, the energy representing the high frequency signal is greater than the energy of the low frequency signal. Under this condition, the comparison circuit system 150 can output a corresponding control signal VC to lower the resistance of the variable resistor RS, thereby increasing the gain of the transfer function of the equalizer circuit system 120 at a low frequency.

The equalizer circuitry 120 of Figure 2A above is merely an example, and other types of equalizer circuitry are also within the scope of this disclosure.

Referring to FIG. 3, FIG. 3 is a flow chart of an adjustment method 300 according to some embodiments of the present disclosure. For ease of explanation, reference is made to FIGS. 1 and 3 together to explain the related operations of the adjustable signal equalization device 100. In some embodiments, the adjustment method 300 includes an operation S310, an operation S320, and an operation S330.

In operation S310, the analog to digital converter 130 converts the output of the equalizer circuit system 120 to the digital signal VD. For example, as shown in FIG. 1, the output signal VO of the equalizer circuitry 120 is converted to a digital signal VD via an analog to digital converter 130.

In operation S320, the computing circuitry 140 processes the digital signal VD to generate the detection signal A and the detection signal B. For example, the calculation circuit system 140 can generate the detection signal A and the detection signal B according to the setting manner of FIG. Alternatively, the computing circuit system 140 can directly process the digital signal VD according to the foregoing equations (1) and (2) to generate the detection signal A and the detection signal B.

In operation S330, the comparison circuit system 150 calculates and compares the energy of the detection signal A and the detection signal B to output a transfer function of the control signal VC adjustment equalizer circuit system 120.

For example, as shown in FIG. 1, the comparison circuit system 150 can calculate the energy of the detection signal A and the energy of the detection signal B by taking absolute values of the detection signal A and the detection signal B, respectively. As previously described, when the energy of the detection signal A is greater than the energy of the detection signal B, the transfer function of the high equalizer circuit system 120 can be adjusted at a high frequency gain, or the transfer function of the equalizer circuit system 120 can be reduced. Gain at low frequencies. Alternatively, when the energy of the detection signal B is greater than the energy of the detection signal A, the transfer function of the high equalizer circuit system 120 can be adjusted at a low frequency gain, or the transfer function of the equalizer circuit system 120 can be lowered at a high frequency. Gain.

The above adjustment method 300 steps are merely examples, and are not limited to be performed in the order in this example. Various operations under the adjustment method 300 may be appropriately added, replaced, omitted, or performed in a different order, without departing from the scope of operation of the embodiments of the present disclosure.

In summary, the adjustable signal equalization device and its adjustment method provided by the present invention can be realized by simple calculation and digital circuit to reduce the required specifications of the circuit and simultaneously reduce the process, voltage, and temperature (PVT) variation. The effect of the function.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the case. Anyone who is familiar with the art can make various changes and refinements without departing from the spirit and scope of the case. Therefore, the scope of protection of this case is attached. The scope defined in the scope of application for patent application shall prevail.

Claims (16)

 An adjustable signal equalization device comprising: a first equalizer circuit circuit having a transfer function for processing an input signal based on the transfer function to generate an output signal; a digital converter for generating a first digital signal according to the output signal; a computing circuit for generating a first accumulated value and a second accumulated value according to the first digital signal, and according to the first And the second detection signal generates a first detection signal and a second detection signal; and a comparison circuit system for comparing the first detection signal and the second detection signal, and When the first detection signal is different from the second detection signal, a control signal is outputted to the equalizer circuit to adjust the transfer function.    The tunable signal equalization device of claim 1, wherein the computing circuit system comprises: a first accumulating circuit for generating the first accumulated value according to the first digital signal; and a delay circuit for Delaying the first digital signal to generate a second digital signal; and a second accumulating circuit for generating the second accumulated value according to the second digital signal.    The tunable signal equalization device of claim 2, wherein the computing circuit system further comprises: a first frequency down circuit for downsampling the first digital signal to generate a third digital signal, wherein the first The accumulating circuit is configured to accumulate the third digit signal to generate the first accumulating value; and a second downconverting circuit is configured to downsample the second digit signal to generate a fourth digit signal, wherein the second accumulating circuit is used The fourth digit signal is accumulated to generate the second accumulated value.    The tunable signal equalization device of claim 2, wherein the computing circuit system further comprises: a first operation circuit, configured to add the first accumulated value and the second accumulated value to generate the first Detector And a second operation circuit for subtracting the first accumulated value and the second accumulated value to generate the second detection signal.   The adjustable signal equalization device according to claim 4, wherein the fast Fourier transform of the first digital signal satisfies the following formula (1): Where k=0,1,...,N-1,N is a positive number and is the number of sampling points, W _N is the N-th unit root, wherein the first accumulated value is equivalent to multiple odd-numbered lines in the above formula (1) The sum of the factors, and the second accumulated value corresponds to the sum of the plurality of even-numbered sub-factors in the above formula (1). The adjustable signal equalization device according to claim 5, wherein the first detection signal satisfies the following formula in the frequency domain: The adjustable signal equalization device according to claim 5, wherein the second detection signal satisfies the following formula in the frequency domain:  The tunable signal equalization device of claim 1, wherein the comparison circuit is configured to determine an absolute value of the first detection signal to determine a first energy of the first detection signal, and to the second The detection signal takes an absolute value to determine a second energy of the second detection signal to output the control signal according to the comparison result of the first energy and the second energy.    The tunable signal equalization device of claim 1, further comprising: an amplifier for amplifying the output signal, wherein the analog to digital converter is further configured to generate the first digital signal according to the amplified output signal .    An adjustment method for adjusting a transfer function of the equalizer circuit system, the method comprising: converting an output signal output by the equalizer circuit system to a first digital signal by an analog to digital converter; Generating a first accumulated value and a second accumulated value according to the first digital signal by a calculating circuit system, and generating a first detecting signal and a first accumulated value according to the first accumulated value and the second accumulated value a second detection signal; and comparing the first detection signal and the second detection signal by a comparison circuit system, and outputting a control signal when the first detection signal is different from the second detection signal The equalizer circuitry adjusts the transfer function.    The method of claim 10, wherein the generating the first detection signal and the second detection signal comprises: generating, by the first accumulation circuit of the calculation circuit system, the accumulation according to the first digital signal a first accumulated value; a delay circuit of the computing circuit system delays the first digital signal to generate a second digital signal; and a second accumulating circuit of the computing circuit system accumulates the second digital signal according to the second digital signal To generate the second accumulated value.    The method of claim 11, wherein the generating the first detection signal and the second detection signal further comprises: downsampling the first digital signal by a first frequency reduction circuit of the computing circuit system to Generating a third digit signal, wherein the first accumulating circuit is configured to accumulate the third digit signal to generate the first accumulating value; and downsampling the second digit signal by using a second downconverting circuit of the computing circuitry And generating a fourth digit signal, wherein the second accumulating circuit is configured to accumulate the fourth digit signal to generate the second accumulated value.    The method of claim 10, wherein the generating the first detection signal and the second detection signal further comprises: adding the first accumulated value and the first by a first operational circuit of the computing circuit system And accumulating the first detection signal; and subtracting the first accumulated value and the second accumulated value by a second operation circuit of the computing circuit to generate the second detection signal.   The adjustment method of claim 13, wherein the fast Fourier transform of the first digital signal satisfies the following formula (1): Where k=0,1,...,N-1,N is a positive number and is the number of sampling points, W _N is the N-th unit root, wherein the first accumulated value is equivalent to multiple odd-numbered lines in the above formula (1) The sum of the factors, and the second accumulated value corresponds to the sum of the plurality of even-numbered sub-factors in the above formula (1). The adjustment method of claim 14, wherein the first detection signal satisfies the following formula in the frequency domain: The adjustment method of claim 14, wherein the second detection signal satisfies the following formula in the frequency domain: