TW201916338A - Spad image sensor and associated fabricating method - Google Patents

Abstract

A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor includes: a substrate having a front surface and a back surface; a trench isolation in the substrate, the trench isolation extending from the front surface of the substrate toward the back surface of the substrate, the trench isolation having a first surface and a second surface opposite to the first surface, the first surface being coplanar with the front surface of the substrate, the second surface being distanced from the back surface of the substrate by a distance greater than 0; wherein the substrate includes: a first layer doped with dopants of a first conductivity type, the first layer extending from the back surface of the substrate toward the trench isolation and laterally surrounding at least a portion of sidewalls of the trench isolation.

Description

Single photon collapse diode image sensor and related manufacturing method

Embodiments of the present invention relate to a single photon collapse diode image sensor and related manufacturing methods.

Digital cameras and optical imaging devices use image sensors. The image sensor converts the optical image into digital data, and the digital data can be expressed as a digital image. An image sensor usually includes a pixel sensor array, which is a unit device for converting an optical image into an electrical signal. Pixel sensors often appear as charge-coupled devices (CCD) or complementary metal-oxide-semiconductor (CMOS) devices. A breakdown photodiode (APD) is a solid-state device that is compatible with traditional CMOS devices. A crash procedure can be triggered when a reverse-biased p-n junction receives additional carriers, such as those generated by incident radiation. For example, in order to detect radiation with low intensity, the p-n junction is biased above its breakdown voltage, thereby allowing a single photo-generated carrier trigger to detect a breakdown current. The image sensor operating in this mode is called a single photon collapsed diode (SPAD) image sensor, or a Geiger mode collapsed photodiode or G-APD.

An embodiment of the present invention relates to a single photon collapse diode (SPAD) image sensor, which includes: a substrate having a front surface and a rear surface; and a trench isolation in the substrate, The trench isolation extends from the front surface of the substrate toward the rear surface of the substrate. The trench isolation has a first surface and a second surface opposite the first surface, and the first surface and the substrate The front surface is coplanar, the second surface is at a distance greater than 0 from the rear surface of the substrate; wherein the substrate includes: a first layer doped with a dopant of a first conductivity type, the first surface A layer extending from the rear surface of the substrate toward the trench isolation and laterally surrounding at least a portion of the sidewall of the trench isolation; a sensing node heavily doped with a second conductivity that is opposite to the first conductivity type Type of dopant, the sensing node is within the substrate and is adjacent to the front surface of the substrate; and a common node heavily doped with the dopant of the first conductivity type, the common node is between the The trench isolates the second surface from the substrate Between the back surface of the board. An embodiment of the present invention relates to a single photon collapse diode (SPAD) image sensor, which includes: a substrate having a front surface and a rear surface, the substrate including: a first layer, which is doped with Doped with a dopant of a first conductivity type, the first layer adjoining the rear surface of the substrate; a second layer doped with a dopant of a second conductivity type opposite to the first conductivity type, The second layer is adjacent to the front surface of the substrate; a third layer is doped with the dopant of the first conductivity type, the third layer is within the first layer and is adjacent to the second layer; A sensing node doped with a dopant of the second conductivity type, the sensing node being within the second layer; and a common node doped with the dopant of the first conductivity type, the The common node is within the first layer and is at a distance greater than 0 from the second layer relative to one of the second directions perpendicular to the front surface of the substrate, and the third layer is relative to the first layer. The first direction is between the sensing node and the common node. An embodiment of the present invention relates to a single photon collapse diode (SPAD) image sensor, which includes: a pixel array arranged in a substrate, the substrate having a front surface and a rear surface, and each The pixel includes: a first layer doped with a dopant of a first conductivity type, the first layer is in the substrate and is adjacent to the rear surface of the substrate; a second layer is doped with the Dopant of the second conductivity type opposite to the first conductivity type, the second layer is within the substrate and is between the front surface of the substrate and the first layer; a third layer is doped There is a dopant of the first conductivity type, the third layer is within the first layer and is adjacent to the second layer; a sensing node is doped with the dopant of the second conductivity type, the sense The measuring node is in the second layer; and a common node is doped with the dopant of the first conductivity type, the common node is in the first layer and opposite to the front surface perpendicular to the substrate A second direction, a first direction, and a distance from the second layer, and the third layer is in the first direction Between the sensing node and the common node; and an isolator between neighboring pixels corresponding to the pixels of the array adjacent to the common node.

The following disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first member formed on or above a second member may include an embodiment in which the first member and the second member are brought into direct contact, and may also include an additional member in which An embodiment formed between the first member and the second member so that the first member and the second member may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity, and does not by itself indicate a relationship between the various embodiments and / or configurations discussed. In addition, for the convenience of description, space-relative terms such as "below", "below", "below", "above", "above", and the like may be used in this article to describe an element or component. The relationship with another element (s) or component is shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein may be interpreted accordingly. Although the numerical ranges and parameters describing the broad scope of this disclosure are approximate, the numerical values set forth in the specific examples are reported as accurately as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective test measurement. Also, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within one acceptable standard error of the mean when considered by a person of ordinary skill. Except in operating / working examples, or unless explicitly specified otherwise, all numerical ranges, amounts, values, and percentages (such as for material quantity, duration, temperature, operating conditions, ratios of amounts, and the like disclosed herein) The numerical ranges, amounts, values, and percentages) should be understood as being modified by the term "about" in all examples. Therefore, unless indicated to the contrary, the numerical parameters set forth in the disclosure and the scope of the appended invention application patents are approximate values that can be changed as needed. At a minimum, each numerical parameter should be understood based on at least the number of significant figures reported and by applying ordinary rounding techniques. A range may be expressed herein as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. SPAD (single photon collapse diode) image sensors can detect incident radiation (e.g., single photon) with very low intensity. The SPAD image sensor includes a plurality of SPAD cells arranged in an array. The SPAD cell includes a pn junction, an arc extinguishing circuit, and a reading circuit. The pn junction operates at a reverse bias well above one of its breakdown voltages. During operation, the photo-generated carriers move to an empty region (ie, a doubling region) of the pn junction and trigger a collapse effect so that a signal current can be detected. An arc extinguishing circuit is used to cut off the collapse effect and reset the SPAD cell. The reading circuit receives and transmits the signal current. An existing planar SPAD image sensor is configured to include a guard ring between a sensing node and a common node. In the case where there is no protection in order to relax the electric field near the sensing node and the common node, an edge collapse may occur before the collapse at the photoelectric detection portion. If the edge collapse occurs first, the electric field strength at the photoelectric detection portion cannot be sufficiently increased, because the increase in voltage only causes current to flow. In particular, if the edge collapse occurs at a voltage lower than one of the breakdown voltages at the photoelectric detection portion, a sufficient multiplication factor cannot be obtained at the photoelectric detection portion, because the photoelectric detection portion cannot be sufficiently increased. The electric field strength does not ensure a sufficiently high photoelectric detection sensitivity, so it cannot fully function as a SPAD. In addition, if an edge collapse has occurred, excessive noise is caused, and this also causes a problem. However, the guard ring consumes a large area and therefore limits the filling factor, a parameter that is a ratio of the area of the characterised photodiode to the total pixel area. Therefore, it is difficult for the existing SPAD image sensor to shrink a pixel area and maintain performance. This disclosure relates to a SPAD image sensor that consumes less area than a conventional SPAD image sensor without sacrificing performance. FIG. 1 is a cross-sectional view of a SPAD image sensor 100 including a CMOS (Complementary Metal Oxide Semiconductor) wafer 103 and an imaging wafer 101 according to a first embodiment of the present disclosure. A schema. The SPAD image sensor 100 includes an array of pixels 101a-101b as shown in FIG. 1 for illustrative purposes. For many cases, the SPAD image sensor 100 may include more than two pixels. The CMOS chip 103 includes a plurality of active devices 105. In some embodiments, the CMOS chip 103 includes an interconnect structure 212 disposed over a substrate 206. In some embodiments, the interconnect structure 212 includes a plurality of metal layers 201 disposed within an inter-dielectric (ILD) layer 203. The active device 105 is placed at least in the substrate 206. The imaging wafer 101 includes an interconnection structure 124 disposed between the interconnection structure 212 of the CMOS wafer 103 and a substrate 109 of the imaging wafer 101. The interconnect structure 124 includes a plurality of metal layers 111 disposed in an ILD layer 128. Each of the pixels 101 a and 101 b includes a SPAD cell placed in the substrate 109. The substrate 109 includes a front surface 100 a facing the interconnection structure 124 and a rear surface 100 b facing away from the interconnection structure 124. A dielectric layer 129 is interposed between the substrate 109 and the interconnection structure 124. Every two adjacent SPAD cells are separated by a trench isolation 117. In some embodiments, the trench isolation 117 may include a main structure 108 extending from the front surface 100a toward the rear surface 100b. The main structure 108 may have an elongated rectangular outline. A first surface of one of the main structures 108 is coplanar with the front surface 100a, and a second surface 108b of one of the main structures 108 is in the substrate 109 and does not contact or overlap the back surface 100b. For many cases, the trench isolation 117 optionally includes an inner spacer 106 and an outer spacer 104. The inner spacer 106 may have an elongated right-angled triangular profile extending along the side wall 108 a of the main structure 108 from the front surface 100 a toward the rear surface 100 b. The long rectangular triangle profile of the inner spacer 106 includes a hypotenuse, a first leg, and a second leg longer than the first leg. The first leg of the inner spacer 106 is coplanar with the front surface 100 a and the second leg of the inner spacer 106 is adjacent to the sidewall 108 a of the trench isolation 117. The second leg of the inner spacer 106 may have the same length as the side wall 108 a of the trench isolation 117. In this way, the inner spacer 106 can completely cover the side wall 108 a of the trench isolation 117 without the side wall 108 a directly contacting the substrate 109. The outer spacer 104 may have an elongated triangular profile extending along a side wall 106 a of the inner spacer 106 from the front surface 100 a toward the rear surface 100 b. The elongated triangular profile of the outer spacer 104 includes a hypotenuse, a first leg, and a second leg longer than the first leg. The first leg of the outer spacer 104 is coplanar with the front surface 100 a and the second leg of the outer spacer 104 is adjacent to the hypotenuse of the inner spacer 106. A length of the second leg of the outer spacer 104 may be shorter than a length of a hypotenuse of the inner spacer 106. In this manner, the outer spacer 104 may cover only a portion of the hypotenuse of the inner spacer 106, and a portion of the hypotenuse of the inner spacer 106 not covered by the outer spacer 104 may directly contact the substrate 109. The trench isolation 117 may be made of a dielectric material such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride or silicon oxynitride), a low-k dielectric, and / or another suitable dielectric. Material) formation. The substrate 109 may include a first layer 114 doped with a dopant of a first conductivity type (eg, p-type). The dopant concentration of one of the first layers 114 of the first conductivity type may be about 1e16 / cm ³ One level. The first layer 114 extends from the rear surface 100 b of the substrate 109 toward the trench isolation 117 and surrounds at least a portion of the adjacent rear surface 100 b of the trench isolation 117. The substrate 109 may further include a second layer 102 in each of the pixels 101 a and 101 b. The second layer 102 may be doped with a dopant of a second conductivity type (eg, n-type), which is opposite to the conductivity type of the first layer 114. One dopant concentration of the second layer 102 may be at about 1e17 / cm ³ To approximately 1e19 / cm ³ One level. The second layer 102 is interposed between the first layer 114 and the front surface 100 a of the substrate 109. Specifically, the second layer 102 is immediately adjacent to the front surface 100 a of the substrate 109 and the trench isolation 117. For many cases, the second layer 102 of the pixel 101a is separated from the second layer 102 of the pixel 101b by trench isolation 117, and the second layer 102 of the pixel 101a is not in contact with the second layer 102 of the pixel 101b. In some embodiments, the second layer 102 may be omitted, that is, replaced by the first layer 114. Each of the pixels 101 a and 101 b further includes a sensing node 110 heavily doped with a dopant of a second conductivity type (eg, n-type), which is the same as the conductivity type of the second layer 102. A dopant concentration of one of the sensing nodes 110 may be heavier than a dopant concentration of the second layer 102. In some embodiments, a ratio of a dopant concentration of the sensing node 110 to a dopant concentration of the second layer 102 may be in a range from about 10 to about 1000. In one embodiment, the dopant concentration of the sensing node 110 may be about 1e20 / cm. ³ One level. The sensing node 110 is formed in the substrate 109 and is immediately adjacent to the front surface 100 a of the substrate 109. In particular, the sensing node 110 is formed in and surrounded by the second layer 102. In other words, the sensing node 110 is separated from the first layer 114 by the second layer 102. Through a contact plug 122, the sensing node 110 can be coupled to the active device 105 of the CMOS chip 103 via the interconnection structure 124 and the ILD layer 203. In some embodiments, the active device 105 may include an active arc extinguishing circuit to stop the collapse effect of the SPAD cell and reset the bias voltage. The active device 105 may also include a read circuit and other control or logic circuits. For example, the active device 105 may include a transistor device having a gate structure 202 and a source / drain region 204. The sensing node 110 can be coupled to a source / drain region 204 of the transistor through a contact plug 208. Each of the pixels 101 a and 101 b may further include a third layer 112 doped with a dopant of a first conductivity type (for example, p-type), the first conductivity type being the same as that of the first layer 114. A dopant concentration of one of the third layers 112 may be greater than a dopant concentration of the first layer 114. In some embodiments, a ratio of a dopant concentration of the third layer 112 to a dopant concentration of the first layer 114 may be in a range from about 1 to about 100. In one embodiment, the dopant concentration of the third layer 112 may be about 1e17 / cm. ³ One level. The third layer 112 is formed in the first layer 114 and is immediately adjacent to the second layer 102. Specifically, the third layer 112 is formed in and surrounded by the first layer 114. In particular, the third layer 112 is separated from the sensing node 110 by the second layer 102. A common node 116 is adjacent to the second surface 108b of each of the trench isolations 117. For many instances, the common node 116 is adjacent to the second surface 108b of each of the trench isolations 117. The common node 116 is heavily doped with a dopant of a first conductivity type (for example, p-type), the first conductivity type being the same as that of the first layer 114 and the third layer 112. The dopant concentration of one of the common nodes 116 may be greater than the dopant concentration of the first layer 114 and the third layer 112. In some embodiments, a ratio of a dopant concentration of the common node 116 to a dopant concentration of the third layer 112 may be in a range from about 10 to about 1000. In one embodiment, the dopant concentration of the common node 116 may be about 1e20 / cm. ³ One level. The common node 116 is formed in and surrounded by the first layer 114. In particular, the common node 116 is separated from the second layer 102 by a distance D1 with respect to a direction perpendicular to one of the directions perpendicular to the front surface or the back surface of the substrate. In some embodiments, the distance D1 may be in a range from about 0.5 um to about 1 um. Through a contact plug 120, the common node 116 can be coupled to the active device 105 of the CMOS chip 103 via the interconnect structure 124 and the ILD layer 203. According to various embodiments of the present disclosure, a desired collapse region 119 around an interface of the third layer 112 and the second layer 102 is depicted in FIG. 1. Because one of the distances between the third layer 112 and the second layer 102 is shorter than the vertical distance D1 between the common node 116 and the second layer 102, an edge crash is more likely than a crash that occurs at the desired crash zone 119. Can't happen. In other words, the vertical distance D1 between the common node 116 and the second layer 102 can replace the protection function of the existing SPAD cell. By adjusting the position of the common node 116 from the front surface 100a of the substrate 109 to a depth inside the substrate 109, a guard ring originally at the front surface 100a and between the sensing node 110 and the common node 116 can be saved. Therefore, the filling factor of this disclosure can be improved. When the crash successfully occurs at the crash zone 119, the holes flow to the sensing node 110 and are collected by the sensing node 110, and the electrons are absorbed by the common node 116. In one embodiment, each of the common node 116 and the contact plug 120 is shared by neighboring SPAD cells. In some embodiments, the imaging wafer 101 and the CMOS wafer 103 are joined together by a hybrid junction (including an inter-metal junction and a dielectric inter-junction). The intermetallic bonding (eg, a diffusion bonding) may be between the top metal layer 126 of one of the plurality of metal layers 111 and the top metal layer 210 of one of the plurality of metal layers 201. The inter-dielectric bonding may directly contact the ILD layer 128 and the ILD layer 203 between the ILD layer 128 and the ILD layer 203. The top metal layers 126 and 210 serve as a pair of pads and may include a redistribution layer (RDL). In some embodiments, the dielectric inter-junction is an inter-oxide junction. In some embodiments, the imaging wafer 101 may also have a plurality of active devices around the array of pixels 101 a to 101 b in the peripheral region of the substrate 109. For example, some or all of the active arc-extinguishing circuit, the reading circuit, and the other control or logic circuits mentioned above may be placed in the substrate 109 of the imaging wafer 101 instead of the CMOS wafer 103. In some embodiments, the SPAD image sensor 100 further includes a high-k dielectric layer 214 and / or an anti-reflective coating (ARC) layer 216 disposed on the rear surface 100b of the substrate 109. To facilitate transmission of incident photons 115 from the back surface 100b to the SPAD cell. The SPAD image sensor 100 may further include a color filter layer 217 above the ARC layer 216. For many cases, the color filter layer 217 contains a plurality of color filters positioned such that the incoming radiation is directed therethrough. A color filter includes a dye-based (or pigment-based) polymer or resin for filtering a specific wavelength band of incoming radiation, the specific wavelength band corresponding to a color spectrum (eg, red, green, and blue). A microlens layer 218 including a plurality of microlenses is formed above the color filter layer 217. Microlenses 218 direct and focus incoming radiation 115 towards SPAD cells. Depending on the refractive index of one of the materials used for the microlens 218 and the distance from a sensor surface, the microlens 218 can be positioned in various configurations and have various shapes. For many cases, from a top view, one center of each of the microlenses 218 overlaps with one center of each of the corresponding SPAD cells. FIG. 2 is a diagram illustrating a cross-sectional view of a SPAD image sensor 200 including a CMOS chip 103 and an imaging chip 301 bonded together according to a second embodiment of the present disclosure. The imaging wafer 301 is the same as the imaging wafer 101 except that the substrate 109 of the imaging wafer 301 further includes a first blocking region 302 and / or a second blocking region 304. The first blocking region 302 may be doped with a dopant of a first conductivity type (for example, p-type), which is the same as the conductivity type of the common node 116. In some embodiments, a ratio of a dopant concentration of the common node 116 to a dopant concentration of one of the first blocking regions 302 may be in a range from about 10 to about 100. For example, the dopant concentration of the first blocking region 302 may be about 1e19 / cm. ³ One level. The first blocking region 302 is within the first layer 114. Specifically, the first blocking region 302 is close to and surrounds a portion of the common node 116 and the trench isolation 117. For many cases, the first blocking region 302 does not extend to the rear surface 100b and the second layer 102. The first blocking region 302 can be used as a guard ring for electric field relaxation to further prevent premature edge collapse of SPAD cells. The second blocking region 304 may be doped with a dopant of a second conductivity type (for example, n-type), which is the same as the conductivity type of the second layer 102. In some embodiments, a ratio of a dopant concentration of the second layer 102 to a dopant concentration of one of the second blocking regions 304 may be in a range from about 10 to about 100. For example, the dopant concentration of the second blocking region 304 may be about 1e16 / cm. ³ To approximately 1e18 / cm ³ One level. The second blocking region 304 is within the first layer 114. In particular, the second blocking region 304 is immediately adjacent to and surrounds a portion of the trench isolation 117. For many cases, the second barrier region 304 is between the first barrier region 302 and the second layer 102. In some embodiments, the second blocking region 304 is immediately adjacent to the first blocking region 302 and the second layer 102. Like the first blocking region 302, the second blocking region 304 can also be used as a guard ring for electric field relaxation to further prevent premature edge collapse of SPAD cells. 3 is a diagram illustrating a cross-sectional view of a SPAD image sensor 300 including a CMOS chip 103 and an imaging chip 401 bonded together according to a third embodiment of the present disclosure. As mentioned above, the common node 116 and the contact plug 120 of the imaging wafer 101 and the imaging wafer 301 are shared by neighboring SPAD cells. An alternative configuration is shown in imaging wafer 401, where common node 116 of imaging wafer 101 and imaging wafer 301 is divided into two common nodes 116a and 116b, and contact plug 120 is divided into two contact plugs 120a and 120b . The contact plugs 120a and 120b are coupled to a common node 116a and a common node 116b, respectively. In particular, the trench isolation 117 may further include an isolator 306 between the common node 116a and the common node 116b. In some embodiments, the isolator 306 extends from the second surface 108 b of the trench isolation 117 toward the rear surface 100 b and separates the first blocking region 302. In some embodiments, the isolator 306 is in contact with the rear surface 100b to further prevent crosstalk between neighboring pixels. As with other parts of the trench isolation 117, the isolator 306 may be made of a dielectric material such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride or silicon oxynitride), a low-k dielectric And / or another suitable dielectric material). For many cases, the first blocking area 302 and / or the second blocking area 304 may be omitted in the SPAD image sensor 300 as appropriate. As mentioned above, the imaging wafer 101 may also have a plurality of active devices around the array of pixels 101 a to 101 b in the peripheral region of the substrate 109. For example, some or all of the active arc-extinguishing circuit, the reading circuit, and the other control or logic circuits mentioned above may be placed in the substrate 109 of the imaging wafer 101 instead of the CMOS wafer 103. For many cases, the active arc extinguishing circuit, reading circuit, other control or logic circuits, and pixels are all integrated in the same substrate and the CMOS chip 103 can be omitted. FIG. 4 is a diagram illustrating a cross-sectional view of a SPAD image sensor 400 including an imaging chip 501 according to a fourth embodiment of the present disclosure. The imaging wafer 501 is the same as the imaging wafer 101 except that the imaging wafer 501 is bonded to a carrier substrate 504 through a buffer layer 502. The buffer layer 502 may include a dielectric material, such as silicon oxide. Alternatively, the buffer layer 502 may optionally include silicon nitride. The carrier substrate 504 may include a silicon material. Alternatively, the carrier substrate 504 may include a glass substrate or other suitable materials. The carrier substrate 504 may be bonded to the buffer layer 502 by molecular force (ie, a technique called direct bonding or optical fusion bonding) or by other bonding techniques known in the art, such as metal diffusion or anodic bonding. The buffer layer 502 provides electrical isolation and protection for various features formed on the front surface 100 a of the substrate 109. The carrier substrate 504 also provides mechanical strength and support for processing the SPAD image sensor 400. In some embodiments, the plurality of active devices 506 and 508 may be integrated in the imaging chip 501. The active device may be formed around an array of pixels 101 a to 101 b in the substrate 109. For example, the active devices 506 and 508 may include active arc extinguishing circuits, reading circuits, and other control or logic circuits. 5 to FIG. 11 are diagrams illustrating fragmentary cross-sectional views of a SPAD image sensor 200 at various stages of manufacturing according to a preferred embodiment of the present disclosure. It should be understood that, for a better understanding of the inventive concept of the present disclosure, FIGS. 5 to 11 have been simplified and may not be drawn to scale. Referring to FIG. 5, a substrate 109 is provided. The substrate 109 includes a first layer 114. The first layer 114 may be doped with a dopant of a first conductivity type and has a thickness of about 1e16 / cm. ³ One-level dopant concentration. The first layer 114 extends from the front surface 100 a to the rear surface 100 b of the substrate 109. The isolation structures 404 are formed in the first layer 114 and each have a rectangular shape, a certain trapezoidal shape, or another suitable shape. Each of the isolation structures 404 has a bottom surface 404a and a sidewall 404b. Referring to FIG. 6, an ion implantation may be performed on the front surface 100 a of the substrate 109 using a second conductivity type dopant (eg, an n-type dopant) opposite to the conductivity type of the first layer 114 to form a second layer. 102. The dopant concentration of the second layer 102 may be about 1e17 / cm ³ To approximately 1e19 / cm ³ One level. The second layer 102 is interposed between the isolation trenches 404. Specifically, the second layer 102 extends from the front surface 100 a of the substrate 109 toward the rear surface 100 b of the substrate 109 and does not exceed the bottom surface 404 a of the isolation structure 404. In other words, the second layer 102 is adjacent to at least a portion of the sidewall 404b of the isolation structure 404. After the second layer 102, the third layer 112 and the sensing node 110 can also be formed by ion implantation. The third layer 112 may be doped with a dopant of a first conductivity type (for example, p-type), which is the same as the conductivity type of the first layer 114. The dopant concentration of the third layer 112 may be heavier than the dopant concentration of the first layer 114. In some embodiments, a ratio of a dopant concentration of the third layer 112 to a dopant concentration of the first layer 114 may be in a range from about 1 to about 100. In one embodiment, the dopant concentration of the third layer 112 may be about 1e17 / cm. ³ One level. The third layer 112 is formed in the first layer 114 and is immediately adjacent to the second layer 102. Specifically, the third layer 112 is formed in and surrounded by the first layer 114. The sensing node 110 may be heavily doped with a dopant of a second conductivity type (for example, n-type), which is the same as the conductivity type of the second layer 102. The dopant concentration of the sensing node 110 may be heavier than the dopant concentration of the second layer 102. In some embodiments, a ratio of a dopant concentration of the sensing node 110 to a dopant concentration of the second layer 102 may be in a range from about 10 to about 1000. In one embodiment, the dopant concentration of the sensing node 110 may be about 1e20 / cm. ³ One level. The sensing node 110 is formed in the substrate 109 and is immediately adjacent to the front surface 100 a of the substrate 109. In particular, the sensing node 110 is formed in and surrounded by the second layer 102. In some embodiments, the first blocking region 302 and the second blocking region 304 may be formed by ion implantation. The first blocking region 302 may be doped with a dopant of a first conductivity type (for example, p-type). In some embodiments, the dopant concentration of the first blocking region 302 may be about 1e19 / cm. ³ One level. The first blocking region 302 is within the first layer 114. In particular, the first blocking region 302 surrounds at least a portion of the groove structure 107. The second blocking region 304 may be doped with a dopant of a second conductivity type (eg, n-type). In some embodiments, the dopant concentration of the second blocking region 304 may be about 1e16 / cm. ³ To approximately 1e18 / cm ³ One level. The second blocking region 304 is within the first layer 114. Specifically, the second blocking region 304 is interposed between the first blocking region 302 and the second layer 102, and the second blocking region 304 surrounds at least a portion of the groove structure 107. It should be noted that the first blocking region 302 and the second blocking region 304 may be omitted as appropriate, like the SPAD image sensor 100 of the first embodiment of the present disclosure. Referring to FIG. 7, an etching process may be performed to obtain the groove structure 107 at the front surface 100 a. Specifically, the groove structure 107 passes through the bottom surface 404 a of the isolation structure 404, and further passes through the second blocking region 304 and extends to the first blocking region 302. For many cases, a portion of the isolation structure 404 may be intentionally retained without being eroded, and the remaining portion may be referred to as the outer spacer 104. The outer spacer 104 may be able to protect the sensing node 110 or other implanted regions in the substrate 109 during subsequent procedures. In some embodiments, the etching process includes a dry etching process. An etching mask (eg, a hard mask, not shown herein) may be formed before performing the etching process to define the size and position of the groove structure 107. The groove structures 107 may be formed to have a rectangular shape, a certain trapezoidal shape, or another suitable shape, respectively. Referring to FIG. 8, a protective layer 702 may be deposited on the front surface 100 a of the substrate to cover the exposed portion of the second layer 102 and the sensing node 110 at the surface 100 a. In some embodiments, the protective layer 702 may be a dielectric material, such as an oxide (for example, silicon oxide), a nitride (for example, silicon nitride or silicon oxynitride), a low-k dielectric, and / Or another suitable dielectric material. In some embodiments, the protective layer 702 may be a hard mask formed of a material selected from the group consisting of a silsesquioxane spin-on-glass (SOG) material and an amorphous carbon material. In some embodiments, an inner spacer 106 may be formed to cover the sidewall of the groove structure 107 as appropriate. Specifically, the inner spacer 106 covers at least a portion of the substrate 109 exposed through the groove structure 107. The inner spacer 106 may be able to further protect the sensing node 110 or other implanted regions in the substrate 109 during subsequent procedures. In this way, the only exposed area of the substrate 109 is the bottom of the groove structure 107. Then, an ion implantation may be performed on the bottom of the groove structure 107 to generate a common node 116. The common node 116 may be heavily doped with a dopant of a first conductivity type (for example, p-type), the first conductivity type being the same as that of the first layer 114 and the third layer 112. The dopant concentration of one of the common nodes 116 may be greater than the dopant concentration of the first layer 114 and the third layer 112. Referring to FIG. 9, a dielectric material 108 such as an oxide (eg, silicon oxide), a nitride (eg, silicon nitride or silicon oxynitride), a low-k dielectric, and / or another suitable dielectric is used. Electrical material) fills the groove structure 107. Then, a chemical mechanical polishing (CMP) may be performed to remove the protective layer 702 and a portion of the inner spacer 106 and the dielectric material 108 to expose the sensing node 110. As shown in FIG. 10, contact plugs 120 and 122 are formed for the heavily doped common node 116 and the sensing node 110. In some embodiments, the contact plugs 120 and 122 may be formed by forming a dielectric layer 129 over the front surface 100 a of the substrate 109. The dielectric layer 129 is subsequently etched to form vias and / or metal trenches. A conductive material is then used to fill the vias and / or metal trenches to form the contact plug 122. In some embodiments, the contact plugs 120 and 122 may be composed of, for example, tungsten, copper, or aluminum copper. An interconnect structure 124 is formed over the substrate 109 to form an imaging wafer 101. In some embodiments, the interconnect structure 124 may be formed by forming an ILD layer 128 (which includes one or more ILD material layers) over the dielectric layer 129. The ILD layer 128 is subsequently etched to form vias and / or metal trenches. A conductive material is then used to fill the vias and / or metal trenches to form a plurality of metal layers 111. In some embodiments, the ILD layer 128 may be deposited by a physical vapor deposition technique (eg, PVD, CVD, etc.). The plurality of metal layers 111 may be formed using a deposition process and / or a plating process (eg, electroplating, electroless plating, etc.). In various embodiments, the plurality of metal layers 111 may be composed of, for example, tungsten, copper, or aluminum-copper. In some embodiments, a top metal layer 126 of one of the plurality of metal layers 111 has an upper surface aligned with an upper surface of the ILD layer 128. As shown in FIG. 11, the imaging wafer 101 is bonded to a CMOS wafer 103. The CMOS wafer 103 includes a substrate 206. An active device 105 is formed in the substrate 206. In various embodiments, the substrate 206 may include any type of semiconductor body (eg, a silicon / CMOS block, SiGe, SOI, etc.) such as a semiconductor wafer or one or more dies on a wafer, and Any other type of semiconductor and / or epitaxial layer formed on and / or otherwise associated with it. In some embodiments, the active device 105 may include a transistor formed by depositing a gate structure 202 over the substrate 206 and forming a source / drain region 204 by implantation or epitaxial growth. An interconnect structure 212 is formed over the substrate 206 to form a CMOS wafer 103. In some embodiments, the interconnect structure 212 may be formed by forming an ILD layer 203 (which includes one or more ILD material layers) over the substrate 206. The ILD layer 203 is subsequently etched to form vias and / or metal trenches. A conductive material is then used to fill the vias and / or metal trenches to form a plurality of metal layers 201. In some embodiments, the ILD layer 203 may be deposited by a physical vapor deposition technique (eg, PVD, CVD, etc.). The metal layer 201 may be formed using a deposition process and / or a plating process (eg, electroplating, electroless plating, etc.). In various embodiments, the plurality of metal layers 201 may be composed of, for example, tungsten, copper, or aluminum-copper. In some embodiments, the top metal layer 210 of the plurality of metal layers 201 has an upper surface aligned with an upper surface of the ILD layer 203. In some embodiments, the bonding process may form a hybrid bond that includes an inter-metal bond and a dielectric inter-bond. The top metal layer 210 and the top metal layer 126 may be directly bonded together. The ILD layer 128 and the ILD layer 203 may be adjacent to each other to define a hybrid inter-dielectric junction. In some embodiments, the dielectric inter-junction is an inter-oxide junction. In some other embodiments, the bonding process may use an intermediate bonding oxide layer (not shown) configured between the ILD layer 128 and the ILD layer 203. Referring again to FIG. 2, a high-k dielectric layer 214 is formed over the rear surface 100 b of the substrate 109. An ARC layer 216 may be formed over the high-k dielectric layer 214. In some embodiments, a high-k dielectric layer 214 and an ARC layer 216 may be deposited using a physical vapor deposition technique. In some embodiments, one of the bonded imaging wafers 101 may be reduced in thickness before the high-k dielectric layer 214 is formed over the rear surface 100 b of the substrate 109. In some embodiments, the substrate 109 can be thinned by etching the rear surface 100b of the substrate 109. In other embodiments, the substrate 109 can be thinned by mechanically polishing the rear surface 100b of the substrate 109. In some embodiments, the substrate 109 can be thinned without exposing the epitaxial layer 108. A color filter 217 may be formed over the rear surface 100b of the substrate 109. In some embodiments, the color filter 217 may be formed by forming a color filter layer and patterning the color filter layer. The color filter layer is formed of a material that allows transmission of radiation (for example, light) having a specific wavelength range while blocking light having wavelengths outside the specified range. Further, in some embodiments, the color filter layer is planarized after formation. A microlens 218 may be formed above the color filter 217. In some embodiments, the microlenses 218 may be formed by depositing a microlens material over a plurality of color filters (eg, by a spin coating method or a deposition process). A microlens template (not shown) having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may include a photoresist material that is exposed using a dispersed exposure dose (for example, for a negative photoresist, more light is exposed at the bottom of the curved surface and exposed at the top of the curved surface Less light), developed and baked to form a circular shape. The microlenses 218 are then formed by selectively etching the microlens material according to the microlens template. Some embodiments of the present disclosure provide a single photon collapse diode (SPAD) image sensor. The SPAD image sensor includes: a substrate having a front surface and a rear surface; and a trench isolation in the substrate, wherein the trench is isolated from the front surface of the substrate toward the rear surface of the substrate Extended, the trench isolation has a first surface and a second surface opposite the first surface, the first surface is coplanar with the front surface of the substrate, and the second surface is with the rear surface of the substrate A distance greater than 0; wherein the substrate includes: a first layer doped with a dopant of a first conductivity type, the first layer extending from the rear surface of the substrate toward the trench isolation and laterally surrounding At least a portion of the sidewall of the trench isolation; a sensing node heavily doped with a dopant of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and adjacent to the substrate The front surface; and a common node heavily doped with the dopant of the first conductivity type, the common node is between the second surface isolated by the trench and the rear surface of the substrate. Some embodiments of the present disclosure provide a single photon collapse diode (SPAD) image sensor. The SPAD image sensor includes a substrate having a front surface and a rear surface. The substrate includes a first layer doped with a dopant of a first conductivity type, and the first layer is adjacent to the substrate. The rear surface; a second layer doped with a dopant of a second conductivity type opposite to the first conductivity type, the second layer adjoining the front surface of the substrate; a third layer, the Doped with the dopant of the first conductivity type, the third layer is within the first layer and is adjacent to the second layer; a sensing node is doped with the dopant of the second conductivity type, The sensing node is in the second layer; and a common node is doped with a dopant of the first conductivity type, and the common node is in the first layer and opposite to the perpendicular to the substrate. A first direction of a second direction of the front surface is separated from the second layer by a distance greater than 0, and the third layer is between the sensing node and the common node with respect to the first direction. Some embodiments of the present disclosure provide a single photon collapse diode (SPAD) image sensor. The SPAD image sensor includes: a pixel array disposed in a substrate, the substrate having a front surface and a rear surface, and each pixel including: a first layer doped with a dopant of a first conductivity type Foreign matter, the first layer is in the substrate and is adjacent to the rear surface of the substrate; a second layer is doped with a dopant of a second conductivity type opposite to the first conductivity type, the first layer Two layers are in the substrate and interposed between the front surface of the substrate and the first layer; a third layer is doped with a dopant of the first conductivity type, and the third layer is in the Within the first layer and adjacent to the second layer; a sensing node doped with a dopant of the second conductivity type, the sensing node is within the second layer; and a common node, which is doped There is a dopant of the first conductivity type, and the common node is within the first layer and is at a distance from the second layer with respect to a first direction that is perpendicular to a second direction perpendicular to the front surface of the substrate. And the third layer is between the sensing node and the common node in the first direction; and an isolator, It is between adjacent common nodes corresponding to adjacent pixels of the pixel array. The features of several embodiments are summarized above, so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other procedures and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of this disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of this disclosure.

100‧‧‧Single Photon Collapse Diode (SPAD) Image Sensor

100a‧‧‧ front surface

100b‧‧‧ rear surface

101‧‧‧ imaging chip

101a‧‧‧ pixels

101b‧‧‧pixels

102‧‧‧Second floor

103‧‧‧ Complementary Metal Oxide Semiconductor (CMOS) Chip

104‧‧‧ Outer spacer

105‧‧‧ Active device

106‧‧‧Inner spacer

106a‧‧‧ sidewall

107‧‧‧ groove structure

108‧‧‧Main Structure / Dielectric Material / Epitaxial Layer

108a‧‧‧ sidewall

108b‧‧‧Second surface

109‧‧‧ substrate

110‧‧‧sensing node

111‧‧‧ metal layer

112‧‧‧Third floor

114‧‧‧First floor

115‧‧‧ incident photon / incoming radiation

116‧‧‧Common node

116a‧‧‧Common node

116b‧‧‧Common node

117‧‧‧Trench Isolation

119‧‧‧ Collapse zone

120‧‧‧contact plug

120a‧‧‧contact plug

120b‧‧‧contact plug

122‧‧‧contact plug

124‧‧‧Interconnection Structure

126‧‧‧Top metal layer

128‧‧‧ Interlayer Dielectric (ILD) layer

129‧‧‧Dielectric layer

200‧‧‧Single photon collapse diode (SPAD) image sensor

201‧‧‧ metal layer

202‧‧‧Gate structure

203‧‧‧Interlayer dielectric (ILD) layer

204‧‧‧Source / Drain Region

206‧‧‧ substrate

208‧‧‧contact plug

210‧‧‧ Top metal layer

212‧‧‧Interconnection Structure

214‧‧‧High-k dielectric layer

216‧‧‧Anti-reflective coating (ARC) layer

217‧‧‧Color filter layer

218‧‧‧Micro lens layer

300‧‧‧Single Photon Collapse Diode (SPAD) Image Sensor

301‧‧‧ imaging chip

302‧‧‧First barrier

304‧‧‧Second Barrier Zone

306‧‧‧Isolator

400‧‧‧Single-photon collapse diode (SPAD) image sensor

401‧‧‧ imaging chip

404‧‧‧Isolation structure / Isolation trench

404a‧‧‧ bottom surface

404b‧‧‧ sidewall

501‧‧‧ imaging chip

502‧‧‧Buffer layer

504‧‧‧ carrier substrate

506‧‧‧active device

508‧‧‧active device

702‧‧‧protective layer

D1‧‧‧distance

The aspect of the disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practice in the industry, various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various components can be arbitrarily increased or decreased. FIG. 1 is a diagram illustrating a cross-sectional view of a SPAD image sensor including a CMOS (Complementary Metal Oxide Semiconductor) wafer and an imaging wafer bonded together according to a first embodiment of the present disclosure. Figure 2 is a diagram illustrating a cross-sectional view of a SPAD image sensor including a CMOS chip and an imaging chip bonded together according to a second embodiment of the disclosure; A schematic diagram of a cross-sectional view of a SPAD image sensor including a CMOS chip and an imaging chip bonded together according to a third embodiment of the disclosure; FIG. 4 is a diagram illustrating a fourth embodiment according to a fourth embodiment of the disclosure; A schematic diagram of a cross-sectional view of a SPAD image sensor including an imaging chip; and FIGS. 5 to 11 show SPAD image sensors at various stages of manufacturing according to a preferred embodiment of the present disclosure. Schematic representation of a fragmentary cross section.

Claims (20)

A single photon collapse diode (SPAD) image sensor includes: a substrate having a front surface and a rear surface; a trench isolation in the substrate, the trench being isolated from the substrate The front surface extends toward the rear surface of the substrate. The trench isolation has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the front surface of the substrate. The second surface is at a distance greater than 0 from the rear surface of the substrate; wherein the substrate includes: a first layer doped with a dopant of a first conductivity type, the first layer being The surface extends towards the trench isolation and laterally surrounds at least a portion of the sidewall of the trench isolation; a sensing node heavily doped with a dopant of a second conductivity type opposite to the first conductivity type, the sensor The measurement node is within the substrate and is adjacent to the front surface of the substrate; and a common node heavily doped with the dopant of the first conductivity type, the common node is interposed between the trench and the second surface And the rear surface of the substrate. The SPAD image sensor according to claim 1, wherein the substrate further comprises: a second layer doped with a dopant of the second conductivity type, the second layer interposed between the front surface of the substrate and the Between the first layers; and a third layer doped with a dopant of the first conductivity type, the third layer being within the first layer and adjacent to the second layer. The SPAD image sensor of claim 2, wherein a distance between the common node and the second layer is in a range from about 0.5 um to about 1 um. The SPAD image sensor of claim 2, wherein a ratio of a dopant concentration of the sensing node to a dopant concentration of the second layer is in a range from about 10 to about 1000. The SPAD image sensor of claim 2, wherein a ratio of a dopant concentration of the third layer to a dopant concentration of the first layer is in a range from about 1 to about 100. The SPAD image sensor of claim 2, wherein a ratio of a dopant concentration of one of the common nodes to a dopant concentration of a third layer is in a range from about 10 to about 1000. The SPAD image sensor of claim 1, wherein the substrate further includes a first blocking area in the first layer, the first blocking area adjoins and surrounds the common node. The SPAD image sensor of claim 7, wherein a ratio of a dopant concentration of one of the common nodes to a dopant concentration of one of the first blocking regions is in a range from about 10 to about 100. The SPAD image sensor of claim 2, wherein the substrate further includes a second blocking region in the first layer, the first blocking region adjoins and surrounds a portion of the trench isolation. The SPAD image sensor of claim 9, wherein a ratio of a dopant concentration of one of the second layers to a dopant concentration of one of the second blocking regions is in a range from about 10 to about 100. A single photon collapse diode (SPAD) image sensor includes: a substrate having a front surface and a rear surface, the substrate comprising: a first layer doped with a dopant of a first conductivity type Debris, the first layer adjoins the rear surface of the substrate; a second layer doped with a dopant of a second conductivity type opposite to the first conductivity type, the second layer adjacent to the substrate The front surface; a third layer doped with a dopant of the first conductivity type, the third layer being within the first layer and adjacent to the second layer; a sensing node doped with The sensing element of the second conductivity type is in the second layer; and a common node is doped with the dopant of the first conductivity type, and the common node is in the first layer. Inside and relative to one of the second directions perpendicular to the front surface of the substrate, the first direction is at a distance greater than 0 from the second layer, and the third layer is between the sensing with respect to the first direction Between the node and the common node. If the SPAD image sensor of claim 11, further comprising a trench isolation extending from the front surface of the substrate toward the rear surface of the substrate, the trench isolation has a first surface and a first surface An opposite second surface, the first surface is coplanar with the front surface of the substrate, and the second surface is at a distance greater than 0 from the rear surface of the substrate. If the SPAD image sensor of claim 12, wherein the trench isolation includes a main structure and an inner spacer, the main structure has a rectangular outline, and the inner spacer has a right-angled triangular outline, and the right-angled triangular outline includes A hypotenuse, a first leg, and a second leg longer than the first leg; wherein: the first leg of the inner spacer is coplanar with the front surface of the substrate, and the second of the inner spacer The legs abut one of the side walls of the main structure. The SPAD image sensor according to claim 13, wherein the trench isolation further includes an outer spacer having a right-angled triangle profile, the right-angled triangle profile includes a hypotenuse, a first leg, and one longer than the first leg A second leg; wherein: the first leg of the outer spacer is coplanar with the front surface of the substrate, and the second leg of the outer spacer is adjacent to the hypotenuse of the inner spacer, and the outer spacer The length of one of the second legs is shorter than the length of the hypotenuse one of the inner spacer. The SPAD image sensor of claim 11, further comprising a first interlayer dielectric (ILD) layer at the front surface of the substrate, the first ILD layer including a plurality of metal layers. The SPAD image sensor of claim 15, further comprising a chip, the chip including a plurality of active devices and a second ILD layer bonded to the first ILD layer. The SPAD image sensor of claim 11, further comprising a lens at the rear surface of the substrate. A single photon collapse diode (SPAD) image sensor includes: a pixel array arranged in a substrate, the substrate having a front surface and a rear surface, and each pixel including: a first layer, It is doped with a dopant of a first conductivity type, the first layer is inside the substrate and is adjacent to the rear surface of the substrate; a second layer is doped with a first material of the opposite type to the first conductivity type. A dopant of two conductivity types, the second layer is within the substrate and interposed between the front surface of the substrate and the first layer; a third layer is doped with the dopants of the first conductivity type Debris, the third layer is in the first layer and is adjacent to the second layer; a sensing node is doped with a dopant of the second conductivity type, and the sensing node is in the second layer And a common node that is doped with a dopant of the first conductivity type, the common node is within the first layer and relative to one of the second directions perpendicular to the front surface of the substrate. A direction is a distance from the second layer, and the third layer is between the sensing node and the first layer in the first direction. Between the common node; and a spacer, which corresponds to the common node between the adjacent neighboring pixels of the pixel arrays. The SPAD image sensor of claim 18, wherein the distance between the common node and the second layer with respect to the first direction is in a range from about 0.5 um to about 1 um. The SPAD image sensor of claim 18, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.