TW201913731A - Method for preparing semiconductor structure - Google Patents

Abstract

The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps: A substrate is provided. A plurality of first core features spaced apart from each other is formed over the substrate. A spacer layer is formed over the first core features, and the spacer layer is formed to cover sidewalls and top surfaces of each first core feature. A plurality of second core features is formed over the substrate, and portions of the spacer layer are exposed through the second core features. A densification treatment is performed on the second core features, and the spacer layer is removed to form a plurality of openings between the first core features and the second core features.

Description

Preparation method of semiconductor structure

This disclosure relates to a method for preparing a semiconductor structure, and more particularly to a method for patterning a semiconductor structure.

In semiconductor manufacturing, lithography is often used to define structures. Typically, the integrated circuit layout is designed and output to one or more photomasks. The integrated circuit layout is then transferred from the mask to the mask layer to form a mask pattern, and from the mask pattern to the target layer. However, with the miniaturization and integration requirements of semiconductor structures such as dynamic random access memory (DRAM), flash memory, static random access memory (SRAM), and ferroelectric (FE) memory, Elements such as semiconductor structures or features have also become finer and more miniaturized. Therefore, with the ever-decreasing size of semiconductor structures and features, there is an increasing demand for techniques for forming the semiconductor structures and features. The above description of the "prior art" is only for providing background technology. It does not recognize that the above description of the "prior technology" reveals the subject of this disclosure, does not constitute the prior technology of this disclosure, and any description of the "prior technology" above Neither shall be part of this case.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The preparation method includes the following steps: providing a substrate; forming a plurality of first core features above the substrate, and the first core features are spaced apart from each other; forming a gap layer above the first core feature, and forming the gap layer Covering the sidewall and top surface of each of the first core features; forming a plurality of second core features above the substrate, and exposing the part of the interstitial layer through the second core features; on the second core features, performing a Densify and remove the gap layer to form a plurality of openings between the first core feature and the second core feature. In some embodiments, the step of forming the plurality of first core features further includes the following steps: forming a first sacrificial layer and a patterned photoresist over the substrate; and etching the first by the patterned photoresist The layer is sacrificed to form the plurality of first core features. In some embodiments, the step of forming the plurality of second core features further includes the steps of: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer to expose and cover each of the first The gap between the sidewall of the core feature and a portion of its top surface. In some embodiments, the method for manufacturing the semiconductor structure further includes forming a mask layer above the top surface of the first core feature. In some embodiments, the step of forming the plurality of second core features further includes the steps of: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer and a portion of the gap layer to expose each The mask layer above the top surface of the first core feature and the gap layer covering the sidewall of the first core feature are exposed. In some embodiments, the step of forming the plurality of second core features further includes the steps of: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer and a portion of the gap layer to expose each The top surface of each of the first core features and the gap layer exposed overlying the sidewall of the first core feature. In some embodiments, the first core feature and the second core feature include a same material. In some embodiments, the densification process is performed while densifying the first core feature and the second core feature. In some embodiments, the densification process includes UV curing or heat treatment. In some embodiments, the heat treatment includes a temperature between about 100 ° C and about 300 ° C. In some embodiments, the gap layer is sandwiched between the second core feature and the substrate. In some embodiments, the first core feature and the second core feature are spaced apart from each other by the opening. In some embodiments, the substrate further includes a hard mask formed on the substrate. In some embodiments, the hard mask includes a multilayer structure. In some embodiments, the multilayer structure includes at least a first mask layer and at least a second mask layer, and the second mask layer is stacked on the first mask layer. In some embodiments, the method of manufacturing the semiconductor structure further includes etching the hard mask through the opening to form a plurality of grooves in the hard mask. In some embodiments, the method for manufacturing the semiconductor structure further includes etching the substrate through the groove to form a plurality of semiconductor structures. In some embodiments, the semiconductor structures are spaced from each other by several gaps. In some embodiments, a width of one of the gaps is substantially equal to a thickness of one of the gap layers. In the embodiment of the present disclosure, the densification process is performed on the second sacrificial layer, so the etching rate of the second core feature is different from the etching rate of the gap layer. As such, the contour of the second core feature is not affected during the removal of the gap layer to form an opening. Therefore, the opening formed between the first core feature and the second core feature is deep enough to have a clear outline. More importantly, when turning into the opening to the substrate, a fine semiconductor structure can be obtained because the opening includes a deep enough depth. In contrast, in a comparison method that does not densify the second core feature, the opening between the first core feature and the second sacrificial layer is not deep enough because the second etch and consumes the second core feature during the removal of the gap layer Sacrifice layer. Therefore, the semiconductor structure formed by turning into the opening to the substrate suffers from insufficient etching problems, and the reliability and performance of the semiconductor element are adversely affected. The technical features and advantages of this disclosure have been outlined quite extensively above, so that the detailed description of this disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application of this disclosure will be described below. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as this disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot be separated from the spirit and scope of this disclosure as defined by the scope of the attached patent application.

The following description of this disclosure is accompanied by the drawings incorporated in and constitutes a part of the description to explain the embodiment of this disclosure, but this disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment. "One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment. In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application. "One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment. In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application. As used herein, the term "feature" refers to a portion of a pattern, such as a line, a gap (partition), a via, a pillar, a trench, a trench, or an edge trench. As used herein, the term "core" refers to a masking feature formed on a vertical level. As used herein, the "target layer" refers to a layer on which a semiconductor structure pattern is to be formed. The target layer may be part of the substrate. The target layer may also be a metal layer, a semiconductor layer, or an insulating layer formed on a substrate. As used herein, the term "patterning" as used in this disclosure describes the operation of forming a predetermined pattern on a surface. The patterning operation includes various steps and processes, and varies according to different embodiments. In some embodiments, a patterning process is used to pattern an existing film or layer. The patterning process includes forming a mask on an existing film or layer, and removing the unmasked film or layer using an etching or other removal process. The mask can be a photoresist or a hard mask. In some embodiments, a patterning process is used to form a patterned layer directly on a surface. The patterning process includes forming a photosensitive film on the surface, performing a lithography process, and performing a development process. The remaining photosensitive film is held and integrated into the semiconductor element. FIG. 1 is a flowchart illustrating a method 10 for fabricating a semiconductor structure according to some embodiments of the present disclosure. The method 10 for preparing a semiconductor structure includes step 102 to provide a substrate. The method 10 for preparing a semiconductor structure further includes a step 104 of forming a plurality of first core features spaced apart from each other above the substrate. The method 10 for manufacturing a semiconductor structure further includes a step 106 of forming a gap layer above the first core feature, and the gap layer covers a sidewall and a top surface of each first core feature. The method 10 for preparing a semiconductor structure further includes a step 108 of forming a plurality of second core features above the substrate. More importantly, part of the interstitial layer is exposed by the second core feature. The method 10 for preparing a semiconductor structure further includes a step 110 of performing a uniform densification process on the second core feature. The method 10 for preparing a semiconductor structure further includes step 112. After the densification process, the gap layer is removed to form a plurality of openings between the first core feature and the second core feature. The method 10 for manufacturing a semiconductor structure will be further described according to one or more embodiments. FIG. 2 to FIG. 10 are schematic diagrams illustrating various manufacturing stages of the manufacturing method 10 of the semiconductor structure according to some embodiments of the present disclosure. Referring to FIG. 2, a substrate 200 is provided according to step 102. The substrate 200 may include silicon (Si), gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon, silicon-germanium (SiGe), silicon carbide (SiC), diamond ( diamond), epitaxy layer, or a combination thereof. In some embodiments of the present disclosure, the target layer 202 is formed over the substrate 200. The target layer 202 may include multiple layers or a single layer. The target layer 202 may be a layer of various IC components, components or structures formed by an IC process. Examples of components, parts, and structures include transistors, capacitors, resistors, diodes, conductive wires, electrodes, bulkheads, trenches, and the like. The target layer 202 may include a material selected based on the type of device to be formed. Examples of the target layer material include, for example, but not limited to, a dielectric material, a semiconductor material, and a conductive material. Still referring to FIG. 2, a hard mask 204 is provided over the target layer 202 and the substrate 200. In some embodiments of the present disclosure, the hard mask 204 includes a multilayer structure. For example, but not limited to, the hard mask 204 may include at least a first mask layer 206a and a second mask layer 206b, and the second mask layer 206b is stacked on the first mask layer 206a. More importantly, the first mask layer 206a and the second mask layer 206b may include different materials or materials with different coefficients in composition. In this way, using a suitable etching chemistry, compared with the first mask layer 206a, The second mask layer 206b can be selectively removed. By way of example and not limitation, the first masking layer 206a may include a silicon oxide (SiO) material, a silicon nitride (SiN) material, or a silicon oxynitride (SiON) material. The second mask layer 206b may include a SiO material, a SiN material, or a SiON material. The second mask layer 206b can be selectively used, so when a suitable etching chemistry is used, the second mask layer 206b can be selectively removed without affecting the first mask layer 206a. Those skilled in the art can easily understand that this disclosure chooses a single-layer hard mask or a double-layer hard mask based on the cost, time, efficacy and process considerations of a given application. Still referring to FIG. 2, above the hard mask 204, a first sacrificial layer 210 is formed. In some embodiments of the present disclosure, the first sacrificial layer 210 may include an organic material, and the organic material may include a photosensitive material or a non-photosensitive material, but the disclosure is not limited thereto. In addition, as shown in FIG. 2, the mask layer 208 may be selectively formed over the first sacrificial layer 210. However, in some embodiments of the present disclosure, the mask layer 208 may be omitted. The mask layer 208 may provide improved etch selectivity and / or anti-reflection for removing the first sacrificial layer 210, and may provide a substantially flat surface on which additional materials may be formed, as follows As described. A patterned photoresist 220 is formed over the mask layer 208 and / or the first sacrificial layer 210, as shown in FIG. 2. The patterned photoresist 220 may include, for example, but not limited to, a wiring formed by a conventional lithography, as is known in the field of semiconductor manufacturing. It should be understood that although three patterned photoresistor 220 lines are shown in FIG. 2 for simplicity of explanation, it is obvious that any number of photoresistor lines may be formed by those skilled in the art when considering the disclosure. Referring to FIG. 3, according to step 104, the first sacrificial layer 210 is etched by the patterned photoresist 220 to form a plurality of first core features 212 over the substrate 200. As shown in FIG. 3, the first core features 212 are spaced from each other. Those skilled in the art can easily understand that the first core feature 212 includes a circuit defined by the patterned photoresist 220. After that, the patterned photoresist 220 is removed. The first core feature 212 includes a line width L1, and the gap between the first core features 212 includes a width W1. Referring to FIG. 4, according to step 106, a gap layer 230 is formed over the first core feature 220. The gap layer 230 is conformally formed to cover or coat the sidewall and top surface of each first core feature 212 as shown in FIG. 4. In some embodiments of the present disclosure, the gap layer 230 includes a thickness T. In some embodiments of the present disclosure, the thickness T of the gap layer 230 is less than 20 nanometers (nm). In some embodiments of the present disclosure, the thickness T of the gap layer 230 is less than 12 nanometers (nm), but the present disclosure is not limited thereto. The gap layer 230 may include a material different from that of the first sacrificial layer 210, but the disclosure is not limited thereto. In some embodiments of the present disclosure, the gap layer 230 may include, for example, but not limited to, silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), a combination thereof, a stacked layer thereof, or the like. Referring to FIG. 5, a second sacrificial layer 240 is formed over the substrate 200. A second sacrificial layer 240 is formed to fill the gap between the first core feature 212 and the gap layer 230. In some embodiments of the present disclosure, the second sacrificial layer 240 may include an organic material, and the organic material may include a photosensitive material or a non-photosensitive material, but the disclosure is not limited thereto. In some embodiments of the present disclosure, the second sacrificial layer 240 includes a different material from the first sacrificial layer 210. In some embodiments of the present disclosure, the first sacrificial layer 210 and the second sacrificial layer 240 include the same material. Referring to FIG. 6, according to step 108, a part of the second sacrificial layer 240 is removed to form a plurality of second core features 242, and a part of the gap layer 230 is exposed. In some embodiments of the present disclosure, part of the second sacrificial layer 240 may be removed by an etch-back process, but the present disclosure is not limited thereto. Therefore, as shown in FIG. 6, the second sacrificial layer 240 is etched back to expose the gap layer 230 on the top surface and the sidewall of the first core feature 212. Therefore, the remaining second sacrificial layer 240 may include a plurality of second core features 242, and the second core feature includes a line width L2. More importantly, the line width L2 of the second core feature 242 is substantially equal to the line width L1 of the first core feature 212. As shown in FIG. 6, when the second core feature 242 covers the gap layer 230, the first core feature 212 is covered by the gap layer 230. In addition, the first core feature 212 and the second core feature 242 are spaced apart from each other by a gap layer 230, and the gap layer 230 includes a thickness T. Referring to FIG. 7, according to step 110, a densification process 250 is then performed on the second core feature 242. In some embodiments of the present disclosure, the densification process 250 includes a surface treatment such as a UV treatment or a chemical treatment. In some embodiments of the present disclosure, the densification process 250 includes a heat treatment, and the heat treatment includes a temperature between about 100 degrees (° C) and about 300 degrees (° C). Accordingly, the densification process 250 alters and densifies at least a portion of each second core feature 242, such as a surface or an upper portion. As shown in Figure 7, at least the upper portion 244 of each second core feature 242 is thus densified. Therefore, the etching rate of the upper portion 244 of the second core feature 242 is sufficiently different from that of the gap layer 230. In addition, as shown in FIG. 7, since the first core feature 212 is covered by the gap layer 230, the etching rate of the first core feature 212 is not substantially affected by the densification process 250. Referring to FIG. 8, according to step 112, after the densification process 250, the gap layer 230 is removed to form a plurality of openings 232 between the first core feature 212 and the second core feature 242. In some embodiments of the present disclosure, as shown in FIG. 8, the hard mask 204 exposes the bottom of the opening 232. As described above, since the etching rate of the upper portion 244 of the second core feature 242 and the etching rate of the gap layer 230 are sufficiently different, the gap layer 230 portion on the top surface and the sidewall of the first core feature 212 can be removed without damage. Or consume the second core feature 242. Therefore, the first core feature 212 and the second core feature 242 are spaced apart from each other by the opening 232, and the opening 232 includes a width W2 that is the same as the thickness T of the gap layer 230. In addition, according to this embodiment, the height of the first core feature 212 is smaller than the height of the second core feature 242. Referring to FIG. 9, the hard mask 204 that is then exposed at the bottom of the opening 232 is etched to form a plurality of grooves 234. As shown in FIG. 9, a groove 234 is formed between the first core feature 212 and the second core feature 242. In some embodiments of the present disclosure, the groove 234 may be formed at least in the second hard mask layer 206b, but the present disclosure is not limited thereto. Referring to FIG. 10, the substrate 200 or the target layer 202 is etched by the grooves 234 to form a plurality of semiconductor structures 260. It is worth noting that the semiconductor structure 260 includes a line width L3, and the line width L3 is substantially equal to the line width L1 of the first core feature 212 and the line width L2 of the second core feature 242. As shown in FIG. 10, the semiconductor structures 260 are spaced apart from each other by the gap 236, and the width W3 of the gap 236 is substantially equal to the thickness T of the gap layer 230. According to the embodiment described above, the densification process 250 is performed on the second core feature 242, so that the etching rate of at least the upper portion 244 of the second core feature 242 and the etching rate of the gap layer 230 are sufficiently different. As such, when the gap layer 230 is removed to form the opening 232, the outline of the second core feature 242 is not affected. Therefore, the opening 232 formed between the first core feature 210 and the second core feature 242 is deep enough to have a clear outline. More importantly, the fine semiconductor structure 260 can be obtained by turning into the hard mask 204 through the opening 232 and then into the substrate 200 or the target layer 202. 11 to 13 are schematic diagrams illustrating other manufacturing stages of a method for manufacturing a semiconductor structure according to other embodiments of the present disclosure. It should be understood that for clarity and simplicity, similar features in FIGS. 2 to 10 and 11 to 13 are identified by the same reference numerals. In addition, similar elements in FIGS. 2 to 10 and 11 to 13 may include similar materials, and these details are omitted for brevity. As shown in FIG. 11, in some embodiments of the present disclosure, steps 102 to 106 are performed, and as shown in FIG. 11, a gap layer 230 is formed over the substrate 200. As described above, the gap layer 230 covers the sidewalls and top surfaces of the plurality of first core features 212. Since the components obtained by performing steps 102 to 106 are similar to those described above, these details are omitted for brevity, and therefore only the differences are provided. Next, a second sacrificial layer 240 is formed over the substrate 200. Subsequently, according to step 108, a part of the second sacrificial layer 240 is removed to form a plurality of second core features 242, and a part of the gap layer 230 is exposed. As described above, part of the second sacrificial layer 240 may be removed by an etch-back process, but the disclosure is not limited thereto. In some embodiments of the present disclosure, the second sacrificial layer 240 is etched back to expose the gap layer 230 on the top surface and the sidewall of the first core feature 212. More importantly, as shown in FIG. 11, the second sacrificial layer 240 and the gap layer 230 above the top surface of the first core feature 212 are further removed to expose a mask above the top surface of the first core feature 212. Layer 208. Therefore, according to step 108, the remaining second sacrificial layer 240 may include a plurality of second core features 242. As shown in FIG. 11, the first core feature 212 and the second core feature 242 are spaced apart from each other by the gap layer 230, and the gap layer 230 includes a thickness T. Referring to FIG. 12, according to step 110, a densification process 250 is then performed on the second core feature 242. As described above, in some embodiments, the densification process 250 may include a surface treatment, such as a UV treatment or a chemical treatment. In some embodiments, the densification process 250 may include a heat treatment. As shown in FIG. 12, at least the upper portion 244 of each of the second core features 242 is densified, so the etching rate of the upper portion 244 of the second core feature 242 is sufficiently different from the etching rate of the gap layer 230. In some embodiments, as shown in FIG. 12, since the first core feature 212 is covered by the gap layer 230, the etching rate of the first core feature 212 is not substantially affected by the densification process 250. As shown in FIG. 13, step 112 may be performed to remove the gap layer 230, and a plurality of openings 232 are formed between the first core feature 212 and the second core feature 242 as described above. As shown in FIG. 13, the hard mask 204 is exposed at the bottom of the opening 232. In addition, the gap layer 230 is sandwiched between the substrate 200 and the second core feature 242. As described above, the opening 232 may be transferred into the hard mask 204 and then into the substrate 200 or the target layer 202. In addition, according to this embodiment, the height of the first core feature 212 is substantially equal to the height of the second core feature 242. As described above, the densification process 250 is performed on the second core feature 242, so the etching rate of at least the upper portion 244 of the second core feature 242 and the etching rate of the gap layer 230 are sufficiently different. As such, the contour of the second core feature 242 is not affected during the removal of the gap layer 230 to form the opening 232. As described above, the opening 232 formed between the first core feature 210 and the second core feature 242 is deep enough to have a clear outline. More importantly, by turning into the hard mask 204 through the opening 232 and then into the substrate 200 or the target layer 202, a fine semiconductor structure can be obtained. 14 to 16 are schematic diagrams illustrating various manufacturing stages of the method for manufacturing the semiconductor structure according to some embodiments of the present disclosure. It should be understood that for clarity and simplicity, similar features in FIGS. 2 to 10 and 14 to 16 are identified by the same reference numerals. In addition, similar elements in FIGS. 2 to 10 and 14 to 16 may include similar materials, so these details are omitted for brevity. As shown in FIG. 14, in some embodiments of the present disclosure, steps 102 to 106 are performed, and a gap layer 230 is formed over the substrate 200. As described above, the gap layer 230 covers the side walls and the top surfaces of the plurality of first core features 212. Because the components obtained by performing steps 102 to 106 are similar to the above, some details are omitted for brevity, and only the differences are explained in detail. Next, a second sacrificial layer 240 is formed over the substrate 200. Subsequently, in step 108, a portion of the second sacrificial layer 240 is removed to form a plurality of second core features 242 and a portion of the gap layer 230 is exposed. As mentioned above, part of the second sacrificial layer 240 can be removed by an etch-back process, but the disclosure is not limited thereto. In some embodiments of the present disclosure, the second sacrificial layer 240 is etched back to expose the gap layer 230 on the top surface and the sidewall of the first core feature 212. More importantly, as shown in FIG. 14, layers such as the gap layer 230 and the mask layer 208 above the top surface of the first core feature 212 are further removed to expose the top surface of the first core feature 212. Therefore, in step 108, the remaining second sacrificial layer 240 may include a plurality of second core features 242. As shown in FIG. 14, the first core feature 212 and the second core feature 242 are spaced apart from each other by a gap layer 230, and the gap layer 230 includes a thickness T. Referring to FIG. 15, in step 110, a densification process 250 is subsequently performed on the first core feature 212 and the second core feature 242 simultaneously. As described above, the densification process 250 may include, for example, a UV process or a chemical process in some embodiments disclosed herein. The densification process 250 may include a heat treatment. According to this embodiment, since the top surface of the first core feature 212 is exposed, at least the upper portion 214 of each first core feature 212 and the upper portion 244 of each second core feature 242 are densified. In some embodiments, the first core feature 212 and the second core feature 242 may include the same material, and the etching rate of the upper portion 214 of the first core feature 212 and the etching rate of the upper portion 244 of the second core feature 242 are dense. The etching rate of the gap layer 230 of the chemical treatment 250 is different. However, it should be understood that the first core feature 212 and the second core feature 242 may include different materials, but the etching rates of the upper portions 214, 244 of the first and second core features 212, 242 may still be modified to be densified. The etching rate of the gap layer 230 of the process 250 is different. As shown in FIG. 16, in step 112, a plurality of openings 232 are formed between the first core feature 212 and the second core feature 242. The hard mask 204 exposes the bottom of the opening 232. In addition, the gap layer 230 is sandwiched between the substrate 200 and the second core feature 242. In addition, the opening 232 may be transferred to the hard mask 204 and then to the substrate 200 or the target layer 202. In addition, according to this embodiment, the height of the first core feature 212 is substantially equal to the height of the second core feature 242. In the embodiment of the present disclosure, the densification process 250 is performed on the second sacrificial layer 240, so the etching rate of at least the upper portion 244 of the second core feature 242 is sufficiently different from the etching rate of the gap layer 230. As such, the contour of the second core feature 242 is not affected during the removal of the gap layer 230 to form the opening 232. Therefore, the opening 232 formed between the first core feature 212 and the second core feature 242 is deep enough to have a clear outline. More importantly, the fine semiconductor structure 260 can be obtained by turning into the hard mask 204 through the opening 232 and then into the substrate 200 or the target layer 202. In contrast, in a comparison method that does not densify the second core feature, the opening between the first core feature and the second sacrificial layer is not deep enough because the second etch and consumes the second core feature during the removal of the gap layer Sacrifice layer. Therefore, the semiconductor structure formed by turning into the opening to the substrate suffers from insufficient etching problems, and the reliability and performance of the semiconductor element are adversely affected. An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes the steps of: providing a substrate. A plurality of first core features are formed above the substrate, and the first core features are spaced from each other. A gap layer is formed above the first core feature, and the gap layer is formed to cover a sidewall and a top surface of each of the first core features. A plurality of second core features are formed above the substrate, and the portion of the gap layer is exposed by the second core features. On the second core feature, a uniform densification process is performed, and the gap layer is removed to form a plurality of openings between the first core feature and the second core feature. Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced with other processes or combinations thereof. Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods and steps described in the description. Those skilled in the art can understand from the disclosure of this disclosure that according to this disclosure, they can use existing, or future developmental processes, machinery, manufacturing, materials that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Composition, means, method, or step. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10‧‧‧Preparation method

102-112‧‧‧step

200‧‧‧ substrate

202‧‧‧Target

204‧‧‧hard mask

206a‧‧‧First mask layer

206b‧‧‧Second mask layer

208‧‧‧Mask layer

210‧‧‧First sacrificial layer

212‧‧‧The first core feature

214‧‧‧upper

220‧‧‧patterned photoresist

230‧‧‧ Interstitial layer

232‧‧‧ opening

234‧‧‧Groove

236‧‧‧Gap

242‧‧‧Second Core Features

244‧‧‧upper

250‧‧‧ Densification

260‧‧‧Semiconductor Structure

L1, L2, L3‧‧‧ Line width

T‧‧‧thickness

W1, W2, W3‧‧‧Width

When referring to the drawings combined with the embodiments and the scope of the patent application, the disclosure in this application can be understood more fully. The same component symbols in the drawings refer to the same components. FIG. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. FIG. 2 to FIG. 10 are schematic diagrams illustrating various manufacturing stages of the method for manufacturing the semiconductor structure according to some embodiments of the present disclosure. FIG. 11 to FIG. 13 are schematic diagrams according to other embodiments of the present disclosure, illustrating a method for preparing the semiconductor structure. FIG. 14 to FIG. 16 are schematic diagrams illustrating other methods for preparing the semiconductor structure according to other embodiments of the present disclosure.

Claims (19)

A method for preparing a semiconductor pattern includes: providing a substrate; forming a plurality of first core features above the substrate, and the first core features being spaced apart from each other; forming a gap layer above the first core feature, the gap layer Covering the sidewall and top surface of each of the first core features; forming a plurality of second core features above the substrate, wherein the part of the gap layer is exposed by the second core features; on the second core feature, Performing a consistent densification process; and after the densification process, removing the gap layer to form a plurality of openings between the first core feature and the second core feature. The method according to claim 1, wherein forming the plurality of first core features further comprises: forming a first sacrificial layer and a patterned photoresist on the substrate; and etching the patterned photoresist through the patterned photoresist. A first sacrificial layer to form the plurality of first core features. The method according to claim 1, wherein forming the plurality of second core features further comprises: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer to expose and cover each of the first A sidewall of a core feature and a portion of its top surface is the gap layer. The manufacturing method as claimed in claim 1, further comprising forming a mask layer over a top surface of the first core feature. According to the manufacturing method of claim 4, forming the plurality of second core features further includes: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer and a portion of the gap layer to expose each The mask layer above the top surface of the first core feature and the gap layer covering the sidewall of the first core feature are exposed. The method according to claim 1, wherein forming the plurality of second core features further comprises: forming a second sacrificial layer over the substrate; and removing a portion of the second sacrificial layer and a portion of the gap layer to expose A top surface of each of the first core features and the gap layer covering a sidewall of the first core feature are exposed. The method according to claim 6, wherein the first core feature and the second core feature include a same material. The method according to claim 7, wherein the densification process is performed while densifying the first core feature and the second core feature. The method according to claim 1, wherein the densification treatment includes UV curing or heat treatment. The method according to claim 9, wherein the heat treatment comprises a temperature between about 100 ° C and about 300 ° C. The method of claim 1, wherein the gap layer is sandwiched between the second core feature and the substrate. The method according to claim 1, wherein the first core feature and the second core feature are spaced apart from each other by the opening. The method according to claim 1, wherein the substrate further comprises a hard mask formed on the substrate. The method of claim 13, wherein the hard mask comprises a multilayer structure. The method according to claim 14, wherein the multilayer structure includes at least a first mask layer and at least a second mask layer, and the second mask layer is stacked on the first mask layer. The method according to claim 13, further comprising etching the hard mask through the opening to form a plurality of grooves in the hard mask. The method of claim 16, further comprising etching the substrate through the groove to form a plurality of semiconductor structures. The method according to claim 13, wherein the semiconductor structures are spaced from each other by a plurality of gaps. The method according to claim 18, wherein a width of one of the gaps is substantially equal to a thickness of one of the gap layers.