TW201913421A - method for analyzing failure patterns of wafers - Google Patents

Abstract

A method for analyzing failure patterns of wafers, executed by a processor, includes the operations of: providing a target wafer containing a failure pattern of defected dies and to-be-selected wafers containing known failure patterns of defected dies, and obtaining defected die raw data of the target wafer and the to-be-selected wafers; performing data mining; and determining similarity between a target pattern of the target wafer and each of base patterns of a group of to-be-compared wafers according to a ranking result of the angle differences from data mining. Data mining includes two screening steps for determining a target pattern of the target wafer and base patterns of the to-be-selected wafers of a group of to-be-compared wafers (pattern match rate ≥ 0.5); constructing feature vectors of the target pattern of the target wafer and feature vectors of the base patterns of the group of to-be-compared wafers; and determining angle differences between the feature vectors of the target pattern of the target wafer and the feature vectors of each of the base patterns of the group of to-be-compared wafers.

Description

Wafer failure pattern analysis method

The present invention relates to an analytical method, and more particularly to a wafer failure pattern analysis method.

For semiconductor technology, continuous reduction of the size of the integrated circuit structure, improvement of speed, performance, density and cost reduction are important development goals. For example, even if the size of the integrated circuit structure is reduced or how it is developed, the electronic characteristics of the semiconductor device must be maintained or improved at least to meet the market requirements for electronic products. If the layers of the integrated circuit structure and the associated semiconductor components are defective or damaged, the electrical performance of the semiconductor structure will be affected, thereby causing one or more defective dies on the wafer. The chip probe (CP) is used to electrically detect the wafer on the wafer before the assembly, in order to distinguish the electrically defective wafer.

In the conventional method, a plurality of wafer failure patterns are selected from a large database and manually matched to find a failure pattern similar to a target pattern of a target wafer, which is inefficient. Extremely time consuming.

The invention relates to a wafer failure pattern analysis method, which can greatly reduce the comparison time of a target wafer and a database to be selected (a failure pattern with a known defect wafer), and more efficiently and accurately The sorting method determines the wafer to be selected similar to the target pattern of the target wafer.

According to an embodiment, a wafer failure pattern analysis method is provided, and the method is performed by a processor, the method comprising: providing a target wafer having a failure pattern of one of the defective wafers, and providing the Knowing a plurality of to-be-selected wafers of the failure pattern of the defective wafer, and obtaining the defective die raw data of the target wafer and the to-be-selected wafers; Data mining; determining the pattern similarity between the target pattern of the target wafer and each of the reference patterns in the group of wafers to be compared according to a ranking result of the angle differences (similarity). Among them, the steps of data exploration include:

The failure pattern of the target wafer is classifying with the failure patterns of the to-be-selected wafers, and is known from the defective wafers of the target wafer and from the to-be-selected wafers. Corresponding cluster failure points are respectively selected in the defective wafers to respectively generate a target pattern of the target wafer and a reference pattern of the to-be-selected wafers (base patterns of the to-be-selected Wafers);

Determining a pattern match rate of the data information message between the target pattern of the target wafer and the reference patterns of the respective wafers to be selected, and screening out the pattern matching ratio of the selected wafers to be less than 0.5 One or more wafers, and the remaining wafers to be selected generate a group of wafers to be compared;

Establishing feature vectors of the target pattern of the target wafer, and establishing feature vectors of the reference patterns in the group of the wafer to be compared;

Determining an angle difference between a feature vector of a target pattern of the target wafer and the feature vectors of the reference patterns in the group of wafers to be aligned;

Sort the angle differences.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

According to an embodiment of the present disclosure, a method for analyzing a failure patterns of wafers is proposed, and the method is performed by a processor. By the method proposed in the embodiment, the comparison time of the target wafer and the database to be selected (the failure pattern of the wafer with known defects) can be greatly reduced, and the ordering manner can be determined more quickly, efficiently and accurately. A wafer to be selected similar to the target pattern of the target wafer (ie, the pattern of the failure pattern is clustered) can solve the problem that the target wafer of the conventional analysis method and the large number of wafers to be selected in the database are difficult to compare. It is a very time consuming problem to compare with labor. Therefore, the method proposed in the embodiment can quickly and accurately obtain related information that needs to be adjusted and modified in the semiconductor process of the target wafer, and improve the yield.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings to describe related manufacturing methods. The process details of the related embodiments are as described in the following examples. However, the disclosure is not limited to the details and details of the process, and the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. The content of the embodiments may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. In the embodiments, the same or similar reference numerals are used to designate the same or similar parts. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the ordinal numbers used in the specification and/or claims (e.g., the terms "first", "second", ..., etc.) are used to modify the elements of the claim, which are not intended to be Any previous ordinal does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to make one request element with a certain name the same as the other. Named request elements can make a clear distinction.

Please also refer to Figure 1-3. 1 is a flow chart showing a method for analyzing failure patterns of wafers according to an embodiment of the present disclosure. Figure 2 is a schematic view showing the XY coordinates of the defective wafer. FIG. 3 is a flow chart showing a method of data exploration steps in an embodiment of the present disclosure.

As shown in FIG. 1, first, as in step S1, a target wafer having a failure pattern of defected dies is provided, and a failure pattern having a wafer having a known defect is provided ( The known failure patterns of defected dies are a plurality of to-be-selected wafers, and the defective die raw data of the target wafer and the to-be-selected wafers are obtained. Then, in step S2, data mining is performed; then, in step S3, according to the sorting result of the data exploration (for example, in an embodiment, according to a sorting result of the angle difference between the feature vectors obtained after the data mining), A pattern similarity between the target pattern of the target wafer and each of the reference patterns in the group of wafers to be compared is determined.

According to an embodiment, in step S1, the defective wafer raw data of the target wafer and the to-be-selected wafer is obtained, for example, including: target wafer and wafer identification of the to-be-selected wafers (wafer-idendifications, ID (ID includes, for example, the size of the wafer, the wafer properties of the wafer and related processes, etc.), and the corresponding XY coordinate values of the raw data of each defective wafer of the target wafer and the selected wafers ( XY coordinate values).

According to an embodiment, the data exploration (step S2) comprises, for example, the following steps S21 to S26.

As shown in step S21, the target wafer is unifying with the defective wafer raw data of the to-be-selected wafers. For example, a failure pattern of the defective wafer of the target wafer and a radius-theta coordinate value of the failure pattern of the known defective wafer of the candidate wafer are determined (step S210). In an example, the step of unifying the defective wafer raw data includes, for example, combining the to-be-selected wafers corresponding to the target wafer size; and confirming the XY coordinates of the target wafer and the centers of the to-be-selected wafers. And converting the XY coordinate values of the defective wafer raw data from the target wafer and the to-be-selected wafers to obtain a failure pattern of the defective wafer of the target wafer and a known defective wafer of the wafer to be selected The radius-angle coordinate value corresponding to the failure pattern.

Referring to Figure 2, there is shown a schematic diagram of the XY coordinates of defective wafer dots A-C and A'-C'. Where the defective wafer point AC and the point A'-C' have different XY coordinates in the figure, but after coordinate conversion, for example, converting the XY coordinate value of each defective wafer point into a polar coordinate (ie radius-angle coordinate value), it can be found The distance from the center O to the point AC and the point A'-C' is associated, for example OA = OA', OB = OB', OC = OC'. Thus, the completion of the data conversion of the radius-angle coordinate values facilitates the determination of the pattern match rate of the two failed pattern alignments in the subsequent steps (as described in step S23).

Step S22, classifying the failure pattern of the target wafer and the failure pattern of the to-be-selected wafers, for example, from the defective wafer of the target wafer and from the known defective wafers of the to-be-selected wafers. Corresponding clustered failed points are respectively selected to respectively generate a target pattern of the target wafer and a base pattern of the to-be -selected wafers).

In an embodiment, the classification is, for example, a defect-based clustering algorithm (Density-Based Spatial Clustering of Applications with Noise (DBSCAN), algorithm) for the defective wafer of the target wafer and all the candidates to be selected. The known defective wafer of the wafer is subjected to clustering, and the non-clustered failed points of the defected dies of the target wafer and the filter removal are removed by filtering. A non-clustered failure point in the known defective wafer of the wafer to be selected (step S220). For example, in one example, the cluster failure points selected by the DBSCAN algorithm are labeled as, for example, "0", while the non-clustered failed points are not selected. Make a mark (ie is removed). Thus step S22 can be considered as the first screening step in the method of one embodiment.

Then, in step S23, a pattern match rate of data information between the target pattern of the target wafer and the reference pattern of each wafer to be selected is determined, and the selected crystals are selected. A one or more of the wafers to be selected having a pattern matching ratio of less than 0.5 (step S230) generates a group of to-be-compared wafers as residual. Therefore, the group of wafers to be aligned is composed of the wafer to be selected with a pattern matching ratio of 0.5 or more. Therefore, step S23/step S230 can be regarded as the second screening step in the method of an embodiment.

According to an example, the data data message determining the pattern matching rate includes: a target wafer and a wafer identification (ID) of the to-be-selected wafers, a target wafer, and the foregoing defective wafer original of the to-be-selected wafers. The XY coordinate value of the defected die raw data and the corresponding transformation data of radius-theta coordinate values.

Step S24 is performed to establish a feature vectors of the target pattern and a feature vectors of the base patterns in the group of the wafers to be compared. In an example, the step of establishing a feature vector includes, for example:

(i) calculating feature values of the target pattern of the target wafer, and calculating feature values of the reference patterns in the group of wafers to be compared; and (ii) target patterns relative to the target wafer The calculated feature values are normalizing the corresponding feature values of the reference patterns in the group of wafers to be aligned, respectively.

Then, in step S25, for example, the feature values normalized by the reference pattern are subjected to operation analysis to determine the feature vector of the target pattern of the target wafer and the reference pattern of the pair of wafers to be compared. The angle differences between the feature vectors. This angle difference also represents the degree of coincidence between the reference pattern and the target pattern, and thus may also be referred to as a match theta. Then, step S26 is performed to rank the angle differences. The sorting method is, for example, sequentially arranged to the maximum value by the minimum value of the angle difference, and is arranged from the first bit, the second bit, ... to the last bit respectively.

In an example, the difference between the plurality of feature vectors that can be applied, and the feature vectors (the reference patterns are compared to the target pattern) is described later. Please also refer to Figures 1, 3 and Table 1 and Table 2.

In one example, the "pattern points" of one of the target patterns (located on the target wafer) and the reference patterns (wafers in the group of wafers to be aligned) are established. Different feature vectors can be roughly divided into three feature groups (ie first to third feature groups) according to their properties. Please refer to Table 1 and Table 2. The generation of the relevant feature vectors of the three feature groups and the brief description of the contents are also listed in Table 1. But of course, the disclosure is not limited to the feature vectors selected in the three feature groups here. In addition, the "pattern point" mentioned in the text refers to the grouping failure point of the target pattern after the second screening step (step S23 / step S230), and the pattern match rate is greater than 0.5. The clustering failure points marked in the respective reference patterns in the wafer group are compared.

In an example, the feature vector established with respect to the "pattern point" of the target pattern (located on the target wafer) and the reference patterns (wafers located in the group of wafers to be aligned) includes, for example, :

a first feature group whose feature vector is related to a radius distribution and a theta distribution, and a radius-theta coordinate corresponding to the pattern points (radius-theta coordinate) Values) and decided. For example, in an application example, the first feature group may include: a radius center, a radius range, a theta range, and a ratio of a radius range to an angle range (a ratio of the Radius range to the theta range) (in Table 1 and Table 2, "proportion _r2t"), the standard deviation of the angle (theta standard deviation) (in Table 1 and Table 2, "angle _std") and the standard deviation of the radius (radius standard deviation) (in Table 1 and Table 2, indicated by "radius_std"), the average radius of the pattern points, etc.;

A second feature group to determine a linear or non-linear distribution of the pattern points. For example, in an application example, the second feature group may include:

The P value of the X points of the pattern points is expressed by the Pearson correlation coefficient (in Table 1 and Table 2, the coefficient _x2y);

One of the pattern points has a radius value relative to a Pearson correlation coefficient at the point counts at the radius value (in Table 1 and Table 2, the coefficient _r2c) (This coefficient can be used to help determine if the pattern points are arc-shaped);

The atta value of the pattern points is expressed relative to the Pearson correlation coefficient of the point counts at the theta value (in Table 1 and Table 2, the coefficient _t2c). (This coefficient can be used to help determine if the pattern points are fan-shaped);

A ratio of a theta count at a maximum radius to a minimum of a minimum radius (a ratio of a theta count at a minimum radius) (Table 1 and Table 2 "Angle_range_r") (this coefficient can be used to assist in determining the size and width of the fan-shaped distribution of the pattern points);

a Pearson correlation coefficient of a plurality of angle values of the plurality of pattern points to a plurality of angle values (indicated by "coefficient _r2t" in Table 1 and Table 2);

The third feature group is related to the density of the pattern points, and is determined by the X-Y coordinate values corresponding to the pattern points. For example, in an application example, the second group of features may include: the pattern points divided by the value of the pattern across area (in Table 1 and Table 2, indicated by "Point_density"). The pattern distribution area can be obtained, for example, by multiplying the X value range of the pattern points by the Y value range, as shown in FIG. 4 (which shows a schematic diagram of a pattern point and a pattern distribution area on a wafer).

Step S240 in Fig. 3 simply lists the feature vectors as exemplified above. However, the above description is for illustrative purposes only, and the disclosure is not limited to the step S240 to simply list the feature vectors as in the above examples.

Table I

In the following, one of the analysis examples is proposed according to the above steps, including listing the relevant values such as the above steps (ex: pattern matching rate, feature vector), etc., which are listed in Table 2 to illustrate a wafer failure pattern analysis method of the application embodiment. An ordering of the pattern similarity between the target pattern of the target wafer and each of the reference patterns in the group of wafers to be aligned may be generated.

Table II

(Continued from Table 2)

(Continued from Table 2)

Referring to FIG. 1 again, in an embodiment disclosed, the step S3 of determining the similarity of the pattern may include the following steps:

Step S31: visualizing the target pattern of the target wafer and the reference patterns in the group of wafers to be aligned;

Step S32: automatically analyzing the target pattern of the target wafer and the group of the wafer to be compared according to a ranking result of the angle differences of the one of the angles between the feature vectors Pattern similarity between the reference patterns; and

Step S33: Conclude whether any one or more similar patterns are similar to the target pattern of the target wafer among the reference patterns of the group to be compared.

In another embodiment, the image may be visualized (ex: presented on a display screen) according to the sorting result of one of the angles between the feature vectors from the minimum value to the maximum value (target wafer) Corresponding reference pattern in the group of wafers to be aligned (ex: sequentially arranged from the first order of the analysis sorting result, the number of presentations is, for example, 10 wafers, or more or less, actual comparison The pattern similarity between the target pattern and the reference pattern can be observed or automatically analyzed by the human eye to infer whether one or more similar patterns are similar to the target pattern of the target wafer. According to the embodiment, even if the reference pattern presented by the method steps of classification, analysis, and the like proposed in the embodiment is manually observed, the similarity can be quickly and accurately found according to the pattern similarity ordering manner. One or several sheets are to be compared to the wafer, so the method of the embodiment can still reduce the number of manually observed wafers to an extremely low level compared to the conventional alignment method.

After the step of inferring a similar pattern similar to the target pattern of the target wafer from the reference pattern of the group of wafers to be compared, the correlation of the semiconductor wafer of the target wafer that needs to be adjusted and modified can be quickly and accurately obtained. Message, plan to improve countermeasures, and thus improve process yield. Furthermore, depending on the actual situation, it is determined whether the target pattern of the target wafer is added to the data base containing the wafers to be selected, and becomes one of the future wafers to be compared.

The disclosure also performs correlation simulation analysis according to the analysis method proposed in the above embodiment, and lists the results of six sets of simulation analysis as follows.

FIG. 5 is a diagram showing a first set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. The labeled cluster failure point in the defect wafer of the target wafer in Fig. 5 is located in the edge region at about 7 o'clock. According to the simulation analysis results, 11 similar patterns are found from the database. Similar to the target pattern of the target wafer, although the cluster failure points of the 11 wafers appear in different clock positions, the distribution of the cluster failure points is related to the target wafer. A similar feature. In addition, taking the target wafer of FIG. 5 as an example, the "SYCNL 18" indicated by the target wafer in the figure is, for example, the wafer ID, and the consecutive number "5" represents, for example, the cluster analysis flag generated by the DBSCAN algorithm. Code, the last digit "0" represents the angle difference between the feature vector of the target pattern of the target wafer and the feature vectors of the reference pattern to be compared to the wafer (since this is the target wafer, features The angle difference between the vectors is 0). Similarly, similar pattern 1 is taken as an example, the labeled "STYYN 14" is the wafer ID, the consecutive number "1" is the cluster analysis identification code, and the last number "0.51" represents the target pattern of the target wafer. The difference between the feature vector and the feature vectors of the reference pattern of the wafer is 0.51. The remaining patterns exemplified in Figures 5-10, the numbers indicated above are also as described above, and are not described herein.

FIG. 6 is a diagram showing a second set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. The clustering failure point indicated in the defective wafer of the target wafer in Fig. 6 is a half-moon shape distribution. According to the simulation analysis results, a total of five similar patterns are found from the database. The target pattern of the target wafer is similar, and the distribution of the cluster failure points of the five similar patterns exhibits very similar characteristics to the target wafer.

FIG. 7 is a diagram showing a third set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. In Figure 7, the labeled cluster failure points in the defective wafer of the target wafer are presented in a staggered cross-strip distribution. According to the results of the simulation analysis, a total of five similar patterns are found from the database. The target pattern of the target wafer is similar, and the distribution of the cluster failure points of the four patterns of similar patterns 1-4 exhibits very similar characteristics to the target wafer.

FIG. 8 is a diagram showing a fourth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. In Figure 8, the labeled cluster failure points in the defective wafer of the target wafer are in a single stripe distribution. According to the results of the simulation analysis, a total of five similar patterns and targets are found from the database. The target pattern of the wafer is similar, and the distribution of the cluster failure points of the four patterns of similar patterns 1-4 exhibits very similar characteristics to the target wafer.

FIG. 9 is a diagram showing a fifth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. In Figure 9, the labeled cluster failure point in the defective wafer of the target wafer is a fan shape distribution. According to the simulation analysis results, five similar patterns and target wafers are found from the database. The target patterns are similar, and the distribution of the cluster failure points of the three patterns of similar patterns 1-3 exhibits very similar characteristics to the target wafer.

FIG. 10 is a diagram showing a sixth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. The labeled cluster failure point in the defective wafer of the target wafer in Fig. 10 is a block shape distribution from the center to the edge. According to the simulation analysis results, five similar patterns are found from the database ( Similar patterns) are similar to the target pattern of the target wafer, in which the distribution of the cluster failure points of the four patterns of similar patterns 1-4 exhibits very similar characteristics to the target wafer.

Therefore, according to the above, the analysis method proposed in the embodiment of the present disclosure mainly performs two screening steps first, wherein (1) the first screening step - the selected wafer and the target wafer are subjected to cluster analysis, and the non-filter is filtered out. The clustering defect points are left, and the clustering defect points are left (ie, the clustering analysis and labeling in the foregoing step S22); (2) the second screening step is a comparison between the wafer to be selected and the target wafer, and the comparison is performed. A portion of the wafer to be selected (ie, the pattern matching ratio <0.5 in the foregoing step S23) is filtered out. After the second screening step, a group of wafers to be aligned is generated (the pattern matching ratio of the wafer to be aligned is ≥0.5), and the wafers to be aligned in the group have the first time. A well-marked base pattern (consisting of clustering defect points). Thereafter, the base pattern of each wafer in the group of wafers to be aligned generated after the second screening step, and the target pattern of the target wafer are subjected to the first Sub-screening), the construction of various feature vectors is performed. Then, comparing the vector angle difference between the reference pattern of the wafer to be compared with the target pattern of the target wafer, and sorting according to the comparison result to compare the wafers to be compared in the group of wafers to be compared The reference pattern finds a pattern similar to the target pattern.

The method according to the above embodiment has many advantages, such as: (1) The method step utilizes a highly reliable DBSCAN clustering algorithm to classify defective wafers, such as cluster analysis and labeling cluster failure points; 2) It is possible to use 12 feature vectors (such as Table 1) to clearly and effectively describe the pattern characteristics, so the low algorithm complexity; (3) the pattern overlap ratio is calculated when the pattern is analyzed to add the angle Position factor considerations, and the pattern similarity of the wafers to be selected can be sorted, so the analysis results have high accuracy/stability (High Accuracy/Robustness); (4) Alignment and ordering through efficient pattern calculation In this way, the comparison time between the target wafer and the database to be selected (the failure pattern of the wafer with known defects) can be greatly reduced; (5) and the high automation extent, which greatly reduces the time of manual operation. . In summary, the method of the embodiment can determine the candidate wafer to be selected similarly to the target wafer pattern in a faster, efficient and accurate manner, and solve the huge number of target wafers and databases in the traditional analysis method. The wafer to be selected is difficult to compare with the manual and is very time consuming. Therefore, the method proposed in the embodiment can quickly and accurately obtain related information that needs to be adjusted and modified in the semiconductor process of the target wafer, and improve the yield.

Other embodiments, such as other step details or other feature vector factors, may also be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or varied. Therefore, the contents and steps shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, it is to be understood by those skilled in the art that the embodiments are not limited to the illustrated embodiments, and the requirements and/or manufacturing steps according to the actual application may be made without departing from the spirit of the disclosure. Adjustment.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S1-S3, S21-S26, S210-S240, S31-S33‧‧‧ steps

FIG. 1 is a flow chart showing a method for analyzing a wafer failure pattern according to an embodiment of the present disclosure. Figure 2 is a schematic view showing the XY coordinates of the defective wafer. FIG. 3 is a flow chart showing a method for data exploration steps in an embodiment of the present disclosure. FIG. 4 is a schematic view showing a pattern dot and a pattern distribution area on a wafer. FIG. 5 is a diagram showing a first set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. FIG. 6 is a diagram showing a second set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. FIG. 7 is a diagram showing a third set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. FIG. 8 is a diagram showing a fourth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. FIG. 9 is a diagram showing a fifth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment. FIG. 10 is a diagram showing a sixth set of simulation analysis results produced by a wafer failure pattern analysis method according to an embodiment.

Claims (16)

A wafer failure pattern analysis method, and the method is performed by a processor, the method comprising: providing a target wafer having a failure pattern of defected dies, And providing a plurality of to-be-selected wafers having known failure patterns of defected dies, and obtaining the target wafer and the defective wafers of the to-be-selected wafers Defected die raw data; performing data mining, including: classifying the failure pattern of the target wafer and the failure patterns of the to-be-selected wafers, and Selecting corresponding clustered failed points in the defective wafers of the target wafer and in the known defective wafers of the to-be-selected wafers to respectively generate a target pattern of the target wafer (target pattern of the target wafer) and the base patterns of the to-be-selected wafers; determining the target of the target wafer a pattern match rate of data information between the pattern and the reference patterns of the plurality of to-be-selected wafers, and screening the pattern to be selected to have a pattern matching ratio of less than 0.5 One or more of the remaining wafers to be selected to generate a group of to-be-compared wafers as remained; the target of the target wafer is established Feature vectors of the target pattern of the target wafer and feature vectors of the base patterns of the group of to-be And determining an angle difference between the feature vector of the target pattern of the target wafer and the feature vectors of each of the reference patterns of the pair of wafers to be aligned; Sorting the angle differences; and determining a target pattern of the target wafer and each of the groups of the wafers to be compared according to the ranking results of the angle differences The pattern similarity between the reference patterns. The method of claim 1, wherein the step of selecting the clustering failure points in the defective wafers of the target wafer and the known defective wafers of the candidate wafers is And removing non-clustered failure points in the defective wafers of the target wafer, and removing non-clustered failure points in the known defective wafers of the to-be-selected wafers. The method of claim 1, wherein the failure pattern of the target wafer and the failure patterns of the to-be-selected wafers are classified by a density-based clustering algorithm of noise The DBSCAN algorithm performs clustering analysis on the defective wafers of the target wafer and the known defective wafers of the selected wafers. The method of claim 3, wherein the DBSCAN algorithm clusters the selected ones of the defective wafers of the target wafer and the known defective wafers of the selected wafers The failure point is labeled as "0", and the non-clustered failed points in the defective wafers of the target wafer and the known defective wafers of the candidate wafers (non-clustered failed points) ) is not marked. The method of claim 1, wherein the step of performing the foregoing data exploration comprises: prior to categorizing the failure pattern of the target wafer and the failure patterns of the to-be-selected wafers: Unifying the target wafer and the defective wafer raw data of the to-be-selected wafers, wherein at least the failure pattern of the defective wafers of the target wafer and the known wafers to be selected are known The radius-theta coordinate values of the failure patterns of the defective wafers. The method of claim 5, wherein the step of unifying the defective wafer raw data includes: combining the to-be-selected wafers corresponding to the target wafer size; confirming the target wafer and the XY coordinate values of the centers of the wafer to be selected; and converting XY coordinate values of the raw data of the defective wafers from the target wafer and the to-be-selected wafers to obtain the The failure pattern of the defective wafers of the target wafer and the radius-angle coordinate values of the failure patterns of the defective wafers of the to-be-selected wafers. The method of claim 5, wherein the data data message determining the pattern matching rate comprises: a wafer-idendifications (ID) of the target wafer and the to-be-selected wafers; The XY coordinate values of the target wafer and the aforementioned defective wafer raw data of the to-be-selected wafers; and the data conversion of the radius-theta coordinate values. The method of claim 1, wherein the step of establishing the feature vector comprises: calculating feature values of the target pattern of the target wafer, and calculating a group of the wafer to be compared The feature values of the reference patterns; and the feature values of the target pattern relative to the target wafer are respectively normalized for the feature values of the reference patterns in the group of the wafers to be compared Normalizing. The method of claim 1, wherein the feature vectors established with respect to the target pattern and the pattern points of one of the reference patterns comprise: a first feature group (first Feature group), which is related to the radius distribution and the angular distribution, and is determined by the radius-angle coordinate values corresponding to the pattern points. The method of claim 9, wherein the first group of features comprises: a radius center, a radius range, an angle range, a ratio of the radius range to the angle range, an angular standard deviation, and a standard deviation of the radius. The method of claim 9, wherein the feature vectors established by the target pattern and the pattern points of one of the reference patterns further comprise: a second feature group ) to determine the linear or non-linear distribution of the pattern points. The method of claim 11, wherein the second group of features comprises: a Pearson correlation coefficient of the X values of the pattern points relative to the Y value; a radius of the pattern points a Pearson correlation coefficient of a value relative to a point counts at the radius value; an angle value of the pattern points relative to a number of pattern points at the angle value (point counts at the theta value) a Pearson correlation coefficient; a ratio of a theta count at a maximum radius to a minimum of a minimum radius; and The Pearson correlation coefficient of a plurality of angular values of a pattern point to a plurality of angle values. The method of claim 9, wherein the feature vectors established by the target pattern and the pattern points of one of the reference patterns further comprise: a third feature group ), related to the density of the pattern points, and determined by the XY coordinate values corresponding to the pattern points. The method of claim 13, wherein the third group of features comprises: dividing the pattern points by a value of a pattern across area. The method of claim 1, wherein the step of determining the similarity of the pattern comprises: visualizing the target pattern of the target wafer and the reference patterns in the group of the wafers to be compared ( Visualizing; automatically analyzing the target pattern of the target wafer and the reference patterns in the group of the wafers to be aligned according to the sorting result of the one of the angle differences from the minimum value to the maximum value Pattern similarity; and inferring whether any one or more similar patterns are present in the reference patterns of the group of wafers to be aligned, similar to the target pattern of the target wafer. The method of claim 15, further comprising: adding the target wafer to a data including the to-be-selected wafers after inferring whether there is any one or more of the foregoing similar patterns In the data base.