TW201911803A - Self-adaptive delayer and data and clock recovery circuit which assure to complete the accurate sampling when data comes so as to have advantage of accomplishing the accurate sampling and the cost saving - Google Patents

Abstract

A data and clock recovery circuit having self-adaptive delay adjustment function comprises a clock signal generator, a self-adaptive delayer and a data sampler. The clock signal generator generates a plurality of clock signals in equally spaced phase differences. The self-adaptive delayer comprises a delay compensation module and a control module. The delay compensation module adjusts the delay time based upon a control signal in order to change a sampled point of the delayed data stream. The control module generates the control signal based upon the sampling edge of the clock signal and the sampled point of the delayed data stream so that the sampled point of the delayed data stream matches a signal establish time or a signal retaining time. The data sampler performs sampling for the delayed data stream matching the sampling condition based upon multiple clock signals so as to recover data within the data stream.

Description

Adaptive delayer and data and clock recovery circuit

The invention relates to a circuit, in particular to a data and clock recovery circuit with an adaptive delay adjustment technique.

The existing delay adjustment technology is an OTP (One Time Programmable (OTP) adjustment. Because of the need to observe the phase relationship between the data and the clock, it is necessary to manually adjust the delay according to the experimental result, resulting in additional cost, and the test adjustment is time consuming and laborious. Develop dynamic delay adjustment technology under the consideration of cost, but the future research direction.

Accordingly, it is an object of the present invention to provide a data and clock recovery circuit that adaptively adjusts latency and reduces cost.

Thus, the data and clock recovery circuit of the present invention comprises a clock signal generator, an adaptive delay device and a data sampler.

The clock signal generator receives input data having clock cycle information and performs clock reconstruction processing to generate a plurality of clock signals in equal interval phase differences.

The adaptive delay device includes a delay compensation module and a control module.

The delay compensation module receives the input data and delays the input data according to a delay time to generate a delay data, and receives a control signal, and adjusts the delay time according to the control signal to change the delayed data stream. A sampled point.

The control module is electrically connected to the delay compensation module and the clock signal generator to receive the delay data from the delay compensation module and one of the plurality of clock signals from the clock signal generator, the control mode The group generates the control signal according to the sampling edge of the clock signal and the sampled point of the delay data, so that the sampled point of the delayed data conforms to a sampling condition, and the sampling condition is a signal establishment time and a signal holding time. At least one of them.

The data sampler is electrically connected to the delay compensation module and the clock signal generator to receive the delay data from the delay compensation module and the plurality of clock signals from the clock signal generator, and according to the plurality of clock signals The delay data that meets the sampling conditions is sampled to recover the data in the data stream.

The utility model has the advantages of: using the adaptive delay adjustment technology to automatically determine whether the rising edge of the clock signal used for sampling is front or back, correspondingly increasing or decreasing the delay of the sampled data, thereby ensuring the data. Proper sampling can be done on arrival, taking into account the advantages of accurate sampling and cost savings.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 1, an embodiment of the data and clock recovery circuit of the present invention includes a clock signal generator 1, an adaptive delay device 2, and a data sampler 3.

The clock signal generator 1 receives an input data having clock cycle information, and performs clock reconstruction processing to generate a plurality of clock signals clk_1 to clk_n which are equally spaced phase differences.

The adaptive delay device 2 is used to compensate the phase delay of the input data through the clock signal generator 1, and the adaptive delay device 2 includes a delay compensation module 4 and a control module 5.

The delay compensation module 4 receives the input data and delays the input data according to a delay time to generate a delay data data_d, and receives a control signal, and adjusts the delay time according to the control signal to change the delay data. One of the points taken. As shown in FIG. 2, the delay compensation module 4 includes a plurality of delay lines D1 D D4 and a data selector mux.

The plurality of delay lines D1 D D4 are used to delay the phase of the input data according to a plurality of different delay times to generate output data of a plurality of different delay phases, each delay line having a first end and a second end. The first ends of the plurality of delay lines are electrically connected together to receive the input data, and the second ends of the plurality of delay lines respectively output a plurality of output data. In this embodiment, four delay lines are used, which are the first delay line D1, the second delay line D2, the third delay line D3, and the fourth delay line D4, respectively. The delay time for the input data is delay1, delay1+. Δt, delay1+2Δt, delay1+3Δt, wherein the initial preset path through which the input data passes is the first delay line D1 of the shortest delay time delay1, but is not limited thereto, and other delay lines may be selected as Enter the initial preset path through which the data passes.

The data selector mux receives the control signal, and electrically connects the output ends of the plurality of delay lines D1 D D4 to respectively receive the plurality of output data, and selects one of the plurality of output data as the delay according to the control signal data. In the present embodiment, the control signal of the data selector mux is a four-bit logical b<3:0>.

The control module 5 is electrically connected to the delay compensation module 4 and the clock signal generator 1 to receive the delay data from the delay compensation module 4 and the plurality of clock signals from the clock signal generator 1 First, the control module 5 generates the control signal according to the sampling edge of the clock signal clk_n-1 (the rising edge of the logical transition state) and the sampled point of the delay data, so that the sampled point of the delayed data matches A sampling condition, the sampling condition being at least one of a signal set up time and a signal hold time. Among them, the definition of the signal establishment time, the level of the sampled data has been maintained for a while before the rising edge of the clock comes. The definition of the hold time, when the rising edge of the clock comes, the level of the sampled data remains for a while. The control module 5 includes a clock delay unit 51, a determination unit 52, and a logic unit 53.

The clock delay unit 51 is electrically connected to the clock signal generator 1 to receive one of the plurality of clock signals clk_n-1, and delays the clock signal clk_n-1 to generate a delayed clock signal clk_n-1_d. The phase difference Td between the clock signal clk_n-1 and the delayed clock signal clk_n-1_d is proportional to the phase delay of the input data passing through the clock signal generator 1. It is further explained that the clock signal clk_n-1 is delayed by the clock delay unit 51 to ensure that the sampled data has sufficient signal setup time or hold time, so that the clock signal clk_n-1 can obtain an ideal one. Sampling location. The set value of the phase difference Td is inversely proportional to the data transmission rate, and it is also affected by the process, voltage, and temperature (referred to as: PVT). In high-speed applications, the setting should be as small as possible while satisfying the application.

The determining unit 52 receives the delay data, and electrically connects the clock delay unit 51 to receive the delayed clock signal clk_n-1_d, and according to the clock transition time point of the delayed clock signal clk_n-1_d and the data transition state of the delay data data_d At a time point, a logic output indicating whether the delayed data conforms to the sampling condition is generated.

The determining unit 52 includes a first data delay unit du1, a second data delay unit du2, a first sampling unit su1, a second sampling unit su2, and a third sampling unit su3.

The first data delay unit du1 receives the delay data, and delays the delay data by one unit time 1×Δt, and the unit time Δt is proportional to the signal establishment time.

The second data delay unit du2 receives the delay data, and delays the delay data by two unit time 2×Δt.

The first sampling unit su1 receives the delay data, and is electrically connected to the clock delay unit 51 to receive the delayed clock signal clk_n-1_d, and samples the delayed data according to the delayed clock signal clk_n-1_d to generate a first logic signal a1. .

The second sampling unit su2 is electrically connected to the clock delay unit 51 and the first data delay unit du1 to receive the delayed clock signal clk_n-1_d and the delay data delayed by one unit time Δt, and according to the delayed clock signal clk_n-1_d Sampling is performed to generate a second logic signal a2.

The third sampling unit su3 is electrically connected to the clock delay unit 51 and the second data delay unit du2 to receive the delayed clock signal clk_n-1_d and the delay data of the delay of two unit time 2Δt, and according to the delayed clock signal clk_n- 1_d performs sampling to generate a third logic signal a3.

The logic unit 53 is electrically connected to the determining unit 52 to receive the logic output, and accordingly generates the control signal b<3:0>, the control signal b<3:0> indicating selection of one of the plurality of delay lines So that the delayed data passing through the selected delay line meets the signal setup time/hold time requirement, wherein the control signal b<3:0> is logically changed from the first to third logic signals (a3a2a1), For example, when (a3a2a1)=000, b<3:0>=0001; when (a3a2a1)=001, b<3:0>=0010; when (a3a2a1)=011, b<3:0>=0100 When (a3a2a1)=111, b<3:0>=1000.

As shown in FIG. 3, in the delay adjustment timing diagram of the above embodiment, the rising edge of the clock signal clk_n-1 has a problem that the holding time is insufficient relative to the position of the delay data data_d, and there may be an erroneous sampling to increase the error. Rate, while the delayed clock signal clk_n-1_d is sampled to the high potential of the delay data data_d (logic 1), the first logic signal a1 goes high (logic 1), and the second and third logic signals a2, a3 remain low (logic 0), causing the logic unit 53 to generate the control signal b<3:0> to select the second delay line D2, that is, (a3a2a1)=[001], b<3:0>=[0010], the second delay line The delay time of the input data of D2 is delay1+Δt (equal to the delay data DATA of the first preset data_d backward Δt) as the data signal data_real to be sampled, and is output to the data sampler 3 to achieve accurate sampling. 4 is a timing chart of delay adjustment 2Δt, at which time (a3a2a1)=[011], b<3:0>=[0100]. Fig. 5 is a timing chart of delay adjustment 3?t, at which time (a3a2a1) = [111], b < 3: 0 > = [1000]. Wherein, when the delay data data_d satisfies the setup/hold time, then (a3a2a1)=[000], b<3:0>=[0001].

The data sampler 3 is electrically connected to the delay compensation module 4 and the clock signal generator 1 to receive the delay data from the delay compensation module 4 and the plurality of clock signals clk_1~clk_n from the clock signal generator 1. And sampling the delayed data that meets the sampling condition according to the plurality of clock signals to recover the data in the data.

As shown in FIG. 6, the data and clock recovery circuit of the present invention performs a delay adjustment method, and the delay adjustment method includes the following steps:

(A) The control module 5 generates a control signal indicating the initial preset delay path, and selects the output of the first delay line D1 having the shortest delay as the delay data.

(B) The control module 5 determines whether the setup time/hold time (setup/hold time) of the delay data is sufficient, and if not, proceeds to step (C), and if so, proceeds to step (D).

(C) The control module 5 controls the data selector mux to select the output of the delay line that meets the setup time/hold time.

(D) The control module 5 controls the data selector mux to output the delayed data to the data sampler 3 for accurate sampling.

In summary, as the processing frequency of the wafer applied in the display field is higher and higher, the signal setup time and the hold time are shorter and shorter, and the data and the clock signal used for sampling are processed under the conditions of process, voltage and temperature variation. The delay mismatch will affect the final display effect. The above embodiment uses the adaptive delay adjustment technique to automatically determine whether the rising edge of the clock signal used for sampling is front or back to increase the delay of the sampled data. By subtracting, it is ensured that the correct sampling can be completed when the data arrives, and the advantages of accurate sampling and cost saving are taken into consideration, so that the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧clock signal generator

2‧‧‧Adaptive delay

3‧‧‧ data sampler

4‧‧‧Delay compensation module

D1~D4‧‧‧first to fourth delay lines

Mux‧‧‧data selector

5‧‧‧Control Module

51‧‧‧clock delay unit

52‧‧‧judging unit

53‧‧‧Logical unit

Du1‧‧‧First data delay unit

Du2‧‧‧second data delay unit

Su1‧‧‧first sampling unit

Su2‧‧‧Second sampling unit

Su3‧‧‧ third sampling unit

A‧‧‧Steps for initial preset delay path

B‧‧‧Steps of judgment

C‧‧‧Steps for selecting the delay line

D‧‧‧Steps for accurate sampling

Clk_1~clk_n‧‧‧clock signal

Clk_n-1_d‧‧‧delay clock signal

Data_d‧‧‧delay data

Data_real‧‧‧data signal

A1‧‧‧first logic signal

A2‧‧‧second logic signal

A3‧‧‧ third logic signal

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a circuit diagram of one embodiment of the data and clock recovery circuit of the present invention; FIG. 3 is a first delay adjustment timing diagram of the embodiment; FIG. 4 is a second delay adjustment timing diagram of the embodiment; FIG. 5 is a third delay adjustment timing diagram of the embodiment; And FIG. 6 is a flow chart of a delay adjustment method of the embodiment.

Claims (10)

A data and clock recovery circuit includes: a clock signal generator that receives input data having clock cycle information and performs clock reconstruction processing to generate a plurality of clock signals having equal interval phase differences; an adaptive delay The device includes a delay compensation module, receives the input data and delays the input data according to a delay time to generate a delay data, and receives a control signal, and adjusts the delay time according to the control signal to change a sampled point of the delayed data stream; a control module electrically connecting the delay compensation module and the clock signal generator to receive the delay data from the delay compensation module and the slave from the clock signal generator One of the plurality of clock signals, the control module generates the control signal according to the sampling edge of the clock signal and the sampled point of the delay data, so that the sampled point of the delayed data conforms to a sampling condition, The sampling condition is at least one of a signal establishment time and a signal retention time; a data sampler electrically connecting the delay compensation a module and the clock signal generator for receiving the delay data from the delay compensation module and the plurality of clock signals from the clock signal generator, and delaying the sampling condition according to the plurality of clock signals The data is sampled to recover the data in the data stream. The data and clock recovery circuit of claim 1, wherein the delay compensation module comprises: a plurality of delay lines for respectively delaying a phase of the input data according to a plurality of different delay times to generate a plurality of different Deferred phase output data, each delay line has a first end and a second end, the first ends of the plurality of delay lines are electrically connected together to receive the input data, and the second ends of the plurality of delay lines are respectively Outputting a plurality of output data; a data selector receiving the control signal and electrically connecting the output ends of the plurality of delay lines to respectively receive the plurality of output data, and selecting one of the plurality of output data according to the control signal One is used as the delay data. The data and clock recovery circuit of claim 1, wherein the control module comprises: a clock delay unit electrically connected to the clock signal generator to receive one of the plurality of clock signals, and the clock The signal is delayed to generate a delayed clock signal; a determining unit receives the delayed data and electrically connects the clock delay unit to receive the delayed clock signal, and according to the transition time point of the delayed clock signal and the delay data transition time Pointing to generate a logic output indicating that the transition time point is leading or falling; a logic unit electrically connecting the determining unit to receive the logic output and generating the control signal accordingly. The data and clock recovery circuit of claim 3, wherein the determining unit comprises: a first data delay unit, receiving the delay data, and delaying the delay data by one unit time; a second data delay unit, Receiving the delay data, and delaying the delay data by two unit time; a first sampling unit receiving the delay data, and electrically connecting the clock delay unit to receive the delayed clock signal, and delaying the delay according to the delayed clock signal Data sampling, generating a first logic signal; a second sampling unit electrically connecting the clock delay unit and the first data delay unit to receive the delayed clock signal and the delay data delayed by one unit time, and according to the delay The clock signal is sampled to generate a second logic signal; a third sampling unit is electrically connected to the clock delay unit and the second data delay unit to receive the delayed clock signal and the delay data of the delay of two unit time, and Sampling is performed based on the delayed clock signal to generate a third logic signal. The data and clock recovery circuit of claim 4, wherein the unit time is proportional to the signal establishment time. The data and clock recovery circuit of claim 3, wherein the phase difference between the clock signal and the delayed clock signal is proportional to a phase delay of the input data through the clock signal generator. An adaptive delay device includes: a delay compensation module, receives input data having clock cycle information and delays the input data according to a delay time to generate a delay data, and receives a control signal, and according to the Controlling the signal to adjust the delay time to change a sampled point of the delayed data stream; a control module receiving a clock signal and electrically connecting the delay compensation module to receive the delayed data from the delay compensation module The control module generates the control signal according to the sampling edge of the clock signal and the sampled point of the delay data, so that the sampled point of the delayed data conforms to a sampling condition, and the sampling condition is a signal establishment time and A signal holds at least one of the times. The adaptive delay device of claim 7, wherein the delay compensation module comprises: a plurality of delay lines for respectively delaying a phase of the input data according to a plurality of different delay times to generate a plurality of different delay phases Output data, each delay line has a first end and a second end, the first ends of the plurality of delay lines are electrically connected together to receive the input data, and the second ends of the plurality of delay lines are respectively outputted Output data; a data selector receiving the control signal and electrically connecting the outputs of the plurality of delay lines to respectively receive the plurality of output data, and selecting one of the plurality of output data according to the control signal as The delay data. The adaptive delay device of claim 7, wherein the control module comprises: a clock delay unit that receives the clock signal and delays the clock signal to generate a delayed clock signal; a determining unit that receives the delay Data, and electrically connected to the clock delay unit to receive the delayed clock signal, and generate a logic output according to the transition time point of the delayed clock signal and the delay data transition time point; a logic unit, electrically connecting the determination a unit to receive the logic output and generate the control signal accordingly. The adaptive delay device of claim 9, wherein the determining unit comprises: a first data delay unit, receiving the delay data, and delaying the delay data by one unit time; and a second data delay unit receiving the Delaying the data, and delaying the delayed data by two unit time; a first sampling unit receiving the delayed data, and electrically connecting the clock delay unit to receive the delayed clock signal, and sampling the delayed data according to the delayed clock signal Generating a first logic signal; a second sampling unit electrically connecting the clock delay unit and the first data delay unit to receive the delayed clock signal and the delay data delayed by one unit time, and according to the delayed clock signal Sampling to generate a second logic signal; a third sampling unit electrically connecting the clock delay unit and the second data delay unit to receive the delayed clock signal and the delay data of the delay of two unit time, and according to the The delayed clock signal is sampled to generate a third logic signal.