TW201911515A - Semiconductor package and method of fabricating semiconductor package - Google Patents

Semiconductor package and method of fabricating semiconductor package Download PDF

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Publication number
TW201911515A
TW201911515A TW107125864A TW107125864A TW201911515A TW 201911515 A TW201911515 A TW 201911515A TW 107125864 A TW107125864 A TW 107125864A TW 107125864 A TW107125864 A TW 107125864A TW 201911515 A TW201911515 A TW 201911515A
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TW
Taiwan
Prior art keywords
redistribution
layer
redistribution layer
pattern
hole portion
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Application number
TW107125864A
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Chinese (zh)
Other versions
TWI694570B (en
Inventor
余振華
余俊輝
余國寵
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台灣積體電路製造股份有限公司
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Priority claimed from US15/662,279 external-priority patent/US10157864B1/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201911515A publication Critical patent/TW201911515A/en
Application granted granted Critical
Publication of TWI694570B publication Critical patent/TWI694570B/en

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Abstract

A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Description

半導體封裝及製作半導體封裝的方法Semiconductor package and method for manufacturing semiconductor package

封裝技術涉及用於包封積體電路（integrated circuit，IC）和/或半導體裝置的包封材料以及作為半導體裝置與封裝之間的介面的重佈線層。細間距節距重佈線層的形成允許製作高積體封裝。Packaging technology involves an encapsulation material for encapsulating integrated circuits (ICs) and / or semiconductor devices, and a redistribution layer as an interface between the semiconductor device and the package. The formation of a fine-pitch pitch redistribution layer allows the fabrication of high volume packages.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第二特徵的上方或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所討論的各個實施例和/或配置之間的關係。The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which the first feature An embodiment in which additional features may be formed between a feature and a second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. Such reuse is for brevity and clarity and does not in itself represent the relationship between the various embodiments and / or configurations discussed.

此外，為易於說明，本文中可能使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。除附圖中所繪示的取向以外，所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同取向。設備可被另外取向（旋轉90度或處於其他取向），且本文所使用的空間相對性描述語可同樣相應地作出解釋。In addition, for ease of explanation, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used herein to explain an element shown in the figure. The relationship of a feature or feature to another (other) element or feature. In addition to the orientations depicted in the drawings, the terms of spatial relativity are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或在基底上形成的測試接墊（test pad），以使得能夠對三維封裝或三維積體電路進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率（yield）並降低成本。This disclosure may also include other features and processes. For example, a test structure may be included to illustrate verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of three-dimensional packages or three-dimensional integrated circuits, probes and / or probe cards ( probe card). Verification tests can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good die to improve yield and reduce costs.

圖1A到圖1G是根據一些實施例示意性地示出根據製作半導體封裝的方法來形成重佈線層的製程的各個階段。參照圖1A，提供具有多個接觸件104的基底102。在一些實施例中，在基底102的上方形成覆蓋接觸件104的第一介電層110。在一些實施例中，基底102是其中具有多個半導體晶片的半導體晶圓。在某些實施例中，基底102是包括在模塑化合物中模塑的多個晶粒的重構晶圓（reconstituted wafer）。在一些實施例中，舉例來說，基底102可以是單晶體（monocrystalline）半導體基底，例如矽基底、絕緣體上矽（silicon-on-insulator，SOI）基底或絕緣體上鍺（germanium-on-insulator，GOI）基底。根據所述實施例，所述半導體基底可包括其他導電層、摻雜區或其他半導體元件，例如電晶體、二極體等。所述實施例旨在用於說明目的，而非旨在限定本公開的範圍。1A to 1G are schematic diagrams illustrating various stages of a process of forming a redistribution layer according to a method of fabricating a semiconductor package according to some embodiments. Referring to FIG. 1A, a substrate 102 having a plurality of contacts 104 is provided. In some embodiments, a first dielectric layer 110 is formed over the substrate 102 to cover the contacts 104. In some embodiments, the substrate 102 is a semiconductor wafer having a plurality of semiconductor wafers therein. In some embodiments, the substrate 102 is a reconstituted wafer including a plurality of dies die molded in a molding compound. In some embodiments, for example, the substrate 102 may be a monocrystalline semiconductor substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. ) Substrate. According to the embodiment, the semiconductor substrate may include other conductive layers, doped regions, or other semiconductor elements, such as transistors, diodes, and the like. The described embodiments are intended for illustrative purposes and are not intended to limit the scope of the present disclosure.

參照圖1A，在一些實施例中，第一介電層110可透過例如旋轉塗佈製程等塗佈製程、層壓製程或包括化學氣相沉積（chemical vapor deposition，CVD）製程的沉積製程來形成。在某些實施例中，第一介電層110可以是感光性材料層。在一些實施例中，第一介電層110的材料可包括聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）、聚苯並噁唑（polybenzooxazole，PBO）或任何合適的感光性聚合物材料或其他光阻材料。在某些實施例中，第一介電層110可包括有機聚合物材料層。在替代實施例中，第一介電層110可包括無機介電材料層。Referring to FIG. 1A, in some embodiments, the first dielectric layer 110 may be formed through a coating process such as a spin coating process, a lamination process, or a deposition process including a chemical vapor deposition (CVD) process. . In some embodiments, the first dielectric layer 110 may be a photosensitive material layer. In some embodiments, the material of the first dielectric layer 110 may include polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any suitable photosensitive polymer. Materials or other photoresist materials. In some embodiments, the first dielectric layer 110 may include a layer of an organic polymer material. In an alternative embodiment, the first dielectric layer 110 may include a layer of an inorganic dielectric material.

參照圖1B，在一些實施例中，將第一介電層110圖案化成具有開口的經圖案化的第一介電層110a。在一些實施例中，經圖案化的第一介電層110a的開口包括通孔開口VS1，且通孔開口VS1中的一些暴露出基底102的接觸件104。在某些實施例中，第一介電層110透過執行微影及蝕刻製程而被圖案化。在某些實施例中，第一介電層110透過曝光及顯影製程而被部分地移除。在某些實施例中，第一介電層110透過執行雷射燒蝕（laser ablation）製程而被部分地移除或圖案化。Referring to FIG. 1B, in some embodiments, the first dielectric layer 110 is patterned into a patterned first dielectric layer 110 a having an opening. In some embodiments, the openings of the patterned first dielectric layer 110 a include through-hole openings VS1, and some of the through-hole openings VS1 expose the contacts 104 of the substrate 102. In some embodiments, the first dielectric layer 110 is patterned by performing a lithography and etching process. In some embodiments, the first dielectric layer 110 is partially removed through an exposure and development process. In some embodiments, the first dielectric layer 110 is partially removed or patterned by performing a laser ablation process.

參照圖1C，在一些實施例中，形成具有溝渠圖案的第二介電層120。在某些實施例中，第二介電層120的形成及圖案化可類似於經圖案化的第一介電層110a的形成及圖案化且在此不再重複細節。在一些實施例中，第二介電層120的材料可包括聚醯亞胺、BCB、PBO或任何合適的感光性聚合物材料或其他光阻材料。在某些實施例中，第二介電層120可包括有機聚合物材料層。在替代實施例中，第二介電層120可包括無機介電材料層。在一些實施例中，第二介電層120的材料不同於第一介電層110的材料，且第二介電層120與經圖案化的第一介電層110a構成堆疊的介電層。在一些實施例中，第一介電層110及第二介電層120由相同的材料形成。在一些實施例中，具有溝渠圖案的第二介電層120包括多個溝渠開口TS1。在一些實施例中，如在圖1C所示剖視圖中所看到的，不直接位於通孔開口VS1上方的部分溝渠開口TS1暴露出下伏的經圖案化的第一介電層110a。在一些實施例中，不直接位於通孔開口VS1上方的部分溝渠開口TS1（作為佈線線）可窄於比直接位於通孔開口VS1上方的其他溝渠開口TS1。在一些實施例中，溝渠開口TS1中的一些的位置與通孔開口VS1中的一些的位置垂直地對齊。在某些實施例中，溝渠開口TS1中的一些的位置與通孔開口VS1中的一些的位置垂直地重疊。在一些實施例中，溝渠開口TS1中的一些通向通孔開口VS1（即，與通孔開口VS1進行接合），且接合的溝渠開口TS1及通孔開口VS1構成雙鑲嵌開口DS1。在一些實施例中，雙鑲嵌開口DS1中的一些暴露出基底102的接觸件104。Referring to FIG. 1C, in some embodiments, a second dielectric layer 120 having a trench pattern is formed. In some embodiments, the formation and patterning of the second dielectric layer 120 may be similar to the formation and patterning of the patterned first dielectric layer 110a and details are not repeated here. In some embodiments, the material of the second dielectric layer 120 may include polyimide, BCB, PBO, or any suitable photosensitive polymer material or other photoresist material. In some embodiments, the second dielectric layer 120 may include a layer of an organic polymer material. In alternative embodiments, the second dielectric layer 120 may include a layer of an inorganic dielectric material. In some embodiments, the material of the second dielectric layer 120 is different from the material of the first dielectric layer 110, and the second dielectric layer 120 and the patterned first dielectric layer 110a constitute a stacked dielectric layer. In some embodiments, the first dielectric layer 110 and the second dielectric layer 120 are formed of the same material. In some embodiments, the second dielectric layer 120 having a trench pattern includes a plurality of trench openings TS1. In some embodiments, as seen in the cross-sectional view shown in FIG. 1C, a portion of the trench opening TS1 that is not directly above the via opening VS1 exposes the underlying patterned first dielectric layer 110 a. In some embodiments, part of the trench opening TS1 that is not directly above the via opening VS1 (as a wiring line) may be narrower than other trench openings TS1 that are directly above the via opening VS1. In some embodiments, the positions of some of the trench openings TS1 are vertically aligned with the positions of some of the through-hole openings VS1. In some embodiments, the positions of some of the trench openings TS1 vertically overlap the positions of some of the through-hole openings VS1. In some embodiments, some of the trench openings TS1 lead to the through-hole opening VS1 (ie, are joined with the through-hole opening VS1), and the joined trench opening TS1 and the through-hole opening VS1 constitute a dual damascene opening DS1. In some embodiments, some of the dual damascene openings DS1 expose the contacts 104 of the substrate 102.

在一些實施例中，在圖1B及圖1C中，通孔開口VS1在水平方向x（與厚度方向z垂直）上形成有深度d1及底部大小k1。在一些實施例中，直接位於通孔開口VS1上方的溝渠開口TS1在水平方向x上形成有深度d2及底部大小k2。在一些實施例中，溝渠開口TS1、通孔開口VS1及雙鑲嵌開口DS1中的一些具有傾斜的側壁。在一些實施例中，溝渠開口TS1、通孔開口VS1及雙鑲嵌開口DS1中的一些具有實質上垂直的側壁。在一些實施例中，通孔開口VS1的底部大小k1小於溝渠開口TS1的底部大小k2。在一些實施例中，通孔開口VS1的底部大小k1小於或約為10微米。在一些實施例中，深度d1實質上等於或小於深度d2。在某些實施例中，通孔開口VS1形成有實質上相同的大小和/或相同的形狀。在某些實施例中，溝渠開口TS1形成為呈一種或多種形狀且呈一種或多種大小。In some embodiments, in FIGS. 1B and 1C, the through-hole opening VS1 is formed with a depth d1 and a bottom size k1 in the horizontal direction x (vertical to the thickness direction z). In some embodiments, the trench opening TS1 located directly above the through hole opening VS1 is formed with a depth d2 and a bottom size k2 in the horizontal direction x. In some embodiments, some of the trench opening TS1, the through-hole opening VS1, and the dual damascene opening DS1 have inclined sidewalls. In some embodiments, some of the trench opening TS1, the through-hole opening VS1, and the dual damascene opening DS1 have substantially vertical sidewalls. In some embodiments, the bottom size k1 of the via opening VS1 is smaller than the bottom size k2 of the trench opening TS1. In some embodiments, the bottom size k1 of the through hole opening VS1 is less than or about 10 microns. In some embodiments, the depth d1 is substantially equal to or less than the depth d2. In some embodiments, the through-hole openings VS1 are formed with substantially the same size and / or the same shape. In some embodiments, the trench opening TS1 is formed in one or more shapes and in one or more sizes.

在替代實施例中，有可能形成其中形成有通孔開口及溝渠開口的單個介電層。In alternative embodiments, it is possible to form a single dielectric layer in which a via opening and a trench opening are formed.

參照圖1D，在一些實施例中，在經圖案化的第一介電層110a及第二介電層120的疊堆的上方形成第一晶種金屬層125。在某些實施例中，第一晶種金屬層125被形成為與經圖案化的第一介電層110a及第二介電層120的疊堆的外形共形。即，第一晶種金屬層125共形地覆蓋溝渠開口TS1及雙鑲嵌開口DS1，從而均勻地覆蓋溝渠開口TS1及雙鑲嵌開口DS1的側壁及底表面且覆蓋第二介電層120的頂表面120a。在某些實施例中，第一晶種金屬層125是透過化學氣相沉積（CVD）、物理氣相沉積（physical vapor deposition，PVD）、原子層沉積（atomic layer deposition，ALD）、高密度電漿CVD（high density plasma CVD，HDPCVD）或其組合而形成。在某些實施例中，第一晶種金屬層125是透過依序沉積或濺射鈦層及銅層（圖中未示出）而形成。在一個實施例中，第一晶種金屬層125覆蓋且接觸接觸件104被暴露出的表面（即，通孔開口VS1的底表面）。在某些實施例中，對於不直接位於通孔開口VS1上方的溝渠開口TS1，第一晶種金屬層125被形成為共形地覆蓋溝渠開口TS1的側壁及底表面。Referring to FIG. 1D, in some embodiments, a first seed metal layer 125 is formed over a stack of the patterned first dielectric layer 110 a and the second dielectric layer 120. In some embodiments, the first seed metal layer 125 is formed to conform to the outer shape of the patterned stack of the first dielectric layer 110 a and the second dielectric layer 120. That is, the first seed metal layer 125 conformally covers the trench opening TS1 and the dual damascene opening DS1, thereby uniformly covering the sidewall and bottom surfaces of the trench opening TS1 and the dual damascene opening DS1, and covers the top surface of the second dielectric layer 120. 120a. In some embodiments, the first seed metal layer 125 is through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density electrical It is formed by high density plasma CVD (HDPCVD) or a combination thereof. In some embodiments, the first seed metal layer 125 is formed by sequentially depositing or sputtering a titanium layer and a copper layer (not shown). In one embodiment, the first seed metal layer 125 covers and contacts the exposed surface of the contact 104 (ie, the bottom surface of the through-hole opening VS1). In some embodiments, for the trench opening TS1 that is not directly above the via opening VS1, the first seed metal layer 125 is formed to conformally cover the sidewall and bottom surface of the trench opening TS1.

參照圖1E，在第一晶種金屬層125上形成第一金屬層130且第一金屬層130填滿位於經圖案化的第一介電層110a上方的雙鑲嵌開口DS1及溝渠開口TS1。在一些實施例中，第一金屬層130的形成包括透過電鍍在第一晶種金屬層125上形成銅層或銅合金層（圖中未示出）來填充雙鑲嵌開口DS1並填滿不直接位於通孔開口VS1上方的溝渠開口TS1。在一些實施例中，第一金屬層130是透過CVD製程、電化學鍍覆（electrochemical plating，ECP）製程或者甚至是濺射製程而形成。然而，應理解，本公開的範圍不限於上文所公開的材料及說明。Referring to FIG. 1E, a first metal layer 130 is formed on the first seed metal layer 125 and the first metal layer 130 fills the dual damascene opening DS1 and the trench opening TS1 located above the patterned first dielectric layer 110 a. In some embodiments, the formation of the first metal layer 130 includes forming a copper layer or a copper alloy layer (not shown in the figure) on the first seed metal layer 125 through electroplating to fill the dual damascene opening DS1 and fill indirectly. The trench opening TS1 is located above the through-hole opening VS1. In some embodiments, the first metal layer 130 is formed through a CVD process, an electrochemical plating (ECP) process, or even a sputtering process. It should be understood, however, that the scope of the present disclosure is not limited to the materials and descriptions disclosed above.

在一些實施例中，由於在將金屬層填充到開口中之前形成共形晶種層，因此確保對後來形成的金屬層的更好的黏附（adhesion）。In some embodiments, since the conformal seed layer is formed before the metal layer is filled into the opening, better adhesion to a later formed metal layer is ensured.

參照圖1F，執行平坦化製程以部分地移除位於第二介電層120的頂表面120a上方的第一金屬層130以及第一晶種金屬層125。在一些實施例中，位於第二介電層120的頂表面120a上方的第一金屬層130連同第一晶種金屬層125一起被移除，直到第二介電層120的頂表面120a被暴露出，以形成第一晶種金屬圖案126及第一金屬重佈線圖案135。在一些實施例中，第一金屬重佈線圖案135包括填充在溝渠開口TS1內的佈線重佈線圖案132及填充在雙鑲嵌開口DS1內的雙鑲嵌重佈線圖案131。在一些實施例中，平坦化製程可包括化學機械拋光（chemical-mechanical polishing，CMP）製程、機械研磨製程、飛切製程（fly-cutting）或回蝕製程。在一些實施例中，平坦化製程可包括CMP製程。在某些實施例中，在平坦化之後，完成在封裝結構100內的第一重佈線層（RDL1）的形成。Referring to FIG. 1F, a planarization process is performed to partially remove the first metal layer 130 and the first seed metal layer 125 located on the top surface 120 a of the second dielectric layer 120. In some embodiments, the first metal layer 130 located above the top surface 120a of the second dielectric layer 120 is removed together with the first seed metal layer 125 until the top surface 120a of the second dielectric layer 120 is exposed. To form a first seed metal pattern 126 and a first metal redistribution pattern 135. In some embodiments, the first metal redistribution pattern 135 includes a wiring redistribution pattern 132 filled in the trench opening TS1 and a dual damascene redistribution pattern 131 filled in the dual damascene opening DS1. In some embodiments, the planarization process may include a chemical-mechanical polishing (CMP) process, a mechanical polishing process, a fly-cutting process, or an etch-back process. In some embodiments, the planarization process may include a CMP process. In some embodiments, after the planarization, the formation of the first redistribution layer (RDL1) within the package structure 100 is completed.

在替代實施例中，基底102是其中沒有形成接觸件的晶圓載體或玻璃載體，且重佈線層是暫時形成在載體上且將在後續階段與載體分離。In an alternative embodiment, the substrate 102 is a wafer carrier or a glass carrier in which no contacts are formed, and the rewiring layer is temporarily formed on the carrier and will be separated from the carrier at a later stage.

在一些實施例中，在平坦化之後，在圖1F中，保留在雙鑲嵌開口DS1內的第一晶種金屬層125及第一金屬層130成為第一晶種金屬圖案126及雙鑲嵌重佈線圖案131，而保留在溝渠開口TS1內的第一晶種金屬層125及第一金屬層130成為第一晶種金屬圖案126及佈線重佈線圖案132。在一些實施例中，第一晶種金屬圖案126位於雙鑲嵌開口DS1內，夾置在雙鑲嵌重佈線圖案131與雙鑲嵌開口DS1之間，且共形地覆蓋雙鑲嵌重佈線圖案131的側壁及底表面（也覆蓋雙鑲嵌開口DS1的側壁及底表面）。在一些實施例中，位於雙鑲嵌開口DS1內的第一晶種金屬圖案126是均勻地及共形地覆蓋雙鑲嵌重佈線圖案131的側壁及底表面的一體件（integral piece），且上述多個第一晶種金屬圖案126是從相同的層（第一晶種金屬層125）獲得。In some embodiments, after planarization, in FIG. 1F, the first seed metal layer 125 and the first metal layer 130 remaining in the dual damascene opening DS1 become the first seed metal pattern 126 and the dual damascene redistribution. Pattern 131, and the first seed metal layer 125 and the first metal layer 130 remaining in the trench opening TS1 become the first seed metal pattern 126 and the wiring redistribution pattern 132. In some embodiments, the first seed metal pattern 126 is located within the dual damascene opening DS1, is sandwiched between the dual damascene redistribution pattern 131 and the dual damascene opening DS1, and conformally covers the sidewall of the dual damascene redistribution pattern 131 And bottom surface (also covers the side wall and bottom surface of the dual mosaic opening DS1). In some embodiments, the first seed metal pattern 126 located in the dual damascene opening DS1 is an integral piece that uniformly and conformally covers the side wall and the bottom surface of the dual damascene redistribution pattern 131. The first seed metal patterns 126 are obtained from the same layer (first seed metal layer 125).

在一些實施例中，如圖1F所示，位於雙鑲嵌開口DS1內的雙鑲嵌重佈線圖案131包括通孔部分133（位於通孔開口VS1內）及佈線部分134（位於溝渠開口TS1內）。位於雙鑲嵌開口DS1內的第一晶種金屬圖案126共形地覆蓋雙鑲嵌重佈線圖案131的佈線部分134的側壁以及通孔部分133的側壁及底表面。在一些實施例中，第二介電層120的頂表面120a與雙鑲嵌重佈線圖案131的頂表面131a以及佈線重佈線圖案132的頂表面132a共面且齊平。在一些實施例中，透過雙鑲嵌製程，已形成的第一重佈線層RDL1為隨後形成的上方膜層提供良好的平面性。與半加性製程（semi-additive process）相比，在以上實施例中所述的製造製程製作有利於包括金屬雙鑲嵌圖案的封裝結構，具有較低成本及較低傳輸損耗，且此類結構可適用於高密度應用或高頻應用。In some embodiments, as shown in FIG. 1F, the dual damascene redistribution pattern 131 located in the dual damascene opening DS1 includes a via portion 133 (located in the via opening VS1) and a wiring portion 134 (located in the trench opening TS1). The first seed metal pattern 126 located in the dual damascene opening DS1 conformally covers the sidewall of the wiring portion 134 of the dual damascene redistribution pattern 131 and the sidewall and bottom surface of the through-hole portion 133. In some embodiments, the top surface 120a of the second dielectric layer 120 is coplanar and flush with the top surface 131a of the dual damascene redistribution pattern 131 and the top surface 132a of the wiring redistribution pattern 132. In some embodiments, through the dual damascene process, the first redistribution layer RDL1 that has been formed provides good planarity for the subsequent upper film layer. Compared with the semi-additive process, the manufacturing process described in the above embodiments facilitates the packaging structure including the metal dual damascene pattern, which has lower cost and lower transmission loss, and such a structure Suitable for high density applications or high frequency applications.

在一些實施例中，第一重佈線層RDL1包括至少經圖案化的第一介電層110a及第二介電層120、第一晶種金屬圖案126以及第一金屬重佈線圖案135。第一重佈線層RDL1與基底102的接觸件104電連接。在替代實施例中，第一重佈線層RDL1可包括多於一個介電圖案及包括跡線或連接線的各種類型的重佈線圖案。在示例性實施例中，第一重佈線層RDL1的重佈線圖案的佈局可形成用於晶圓級封裝或晶圓級晶片尺寸封裝的扇入型（fan-in）佈線。在替代實施例中，第一重佈線層RDL1的重佈線圖案的佈局可形成用於晶圓級封裝技術或者用於整合扇出型（integrated fan-out，InFO）封裝或疊層封裝（package-on-package，PoP）結構的扇出型佈線。In some embodiments, the first redistribution layer RDL1 includes at least a patterned first and second dielectric layers 110a and 120, a first seed metal pattern 126, and a first metal redistribution pattern 135. The first redistribution layer RDL1 is electrically connected to the contact 104 of the substrate 102. In alternative embodiments, the first redistribution layer RDL1 may include more than one dielectric pattern and various types of redistribution patterns including traces or connection lines. In an exemplary embodiment, the layout of the redistribution pattern of the first redistribution layer RDL1 may form a fan-in wiring for a wafer level package or a wafer level wafer size package. In alternative embodiments, the layout of the redistribution pattern of the first redistribution layer RDL1 may be formed for wafer-level packaging technology or for integrated fan-out (InFO) packaging or package-package (package- Fan-out wiring with on-package (PoP) structure.

在某些實施例中，透過鑲嵌開口的形成，改善金屬層至雙鑲嵌開口中的填充能力，且透過在雙鑲嵌開口與雙鑲嵌重佈線圖案之間形成晶種金屬圖案，提供雙鑲嵌開口與雙鑲嵌重佈線圖案之間的更好的黏附。另外，由於填充到接合的溝渠開口及通孔開口中的金屬層是一體件，因此可實現更好的機械強度。此外，共形晶種金屬層有助於降低電阻，且雙鑲嵌重佈線圖案改善重佈線層的可靠性及電性質。在一些實施例中，包括一個或多個雙鑲嵌重佈線圖案及覆蓋雙鑲嵌重佈線圖案的側壁及底表面的晶種金屬圖案的重佈線層被視為含雙鑲嵌的重佈線層。In some embodiments, the filling ability of the metal layer to the dual-mosaic opening is improved through the formation of the mosaic-inlaid opening, and the dual-mosaic opening and Better adhesion between dual damascene redistribution patterns. In addition, since the metal layers filled in the trench openings and through-hole openings that are joined are integral pieces, better mechanical strength can be achieved. In addition, the conformal seed metal layer helps reduce resistance, and the dual damascene redistribution pattern improves the reliability and electrical properties of the redistribution layer. In some embodiments, a redistribution layer including one or more dual-damascene redistribution patterns and a seed metal pattern covering sidewalls and bottom surfaces of the dual-damascene redistribution pattern is considered to be a dual-damascene redistribution layer.

參照圖1G，在封裝結構100的第一重佈線層RDL1上形成第二重佈線層RDL2。第二重佈線層RDL2的形成可採用與在圖1A到圖1F中所述相同或實質上相似的製程步驟且使用與在以上實施例中所述相同或相似的材料。在一些實施例中，第二重佈線層RDL2設置在第一重佈線層RDL1上且與第一重佈線層RDL1電連接。在一些實施例中，第二重佈線層RDL2包括至少介電層140、第二金屬重佈線圖案165及夾置在介電層140與第二金屬重佈線圖案165之間的第二晶種金屬圖案156。在一些實施例中，介電層140可以是單個介電層或者兩個或更多個介電層的堆疊結構。在一些實施例中，第二金屬重佈線圖案165包括位於雙鑲嵌開口DS2（接合的通孔開口VS2及溝渠開口TS2）內的雙鑲嵌重佈線圖案161及位於溝渠開口TS2內的佈線重佈線圖案162。在一些實施例中，夾置在雙鑲嵌重佈線圖案161與雙鑲嵌開口DS2之間的第二晶種金屬圖案156共形地覆蓋雙鑲嵌開口DS2的側壁及底表面。在某些實施例中，夾置在溝渠開口TS2與佈線重佈線圖案162之間的第二晶種金屬圖案156共形地覆蓋溝渠開口TS2的側壁及底表面。Referring to FIG. 1G, a second redistribution layer RDL2 is formed on the first redistribution layer RDL1 of the package structure 100. The second redistribution layer RDL2 may be formed using the same or substantially similar process steps as described in FIGS. 1A to 1F and using the same or similar materials as described in the above embodiments. In some embodiments, the second redistribution layer RDL2 is disposed on the first redistribution layer RDL1 and is electrically connected to the first redistribution layer RDL1. In some embodiments, the second redistribution layer RDL2 includes at least a dielectric layer 140, a second metal redistribution pattern 165, and a second seed metal sandwiched between the dielectric layer 140 and the second metal redistribution pattern 165. Pattern 156. In some embodiments, the dielectric layer 140 may be a single dielectric layer or a stacked structure of two or more dielectric layers. In some embodiments, the second metal redistribution pattern 165 includes a dual damascene redistribution pattern 161 located in the dual damascene opening DS2 (joined via opening VS2 and trench opening TS2) and a wiring redistribution pattern located in the trench opening TS2 162. In some embodiments, the second seed metal pattern 156 sandwiched between the dual damascene redistribution pattern 161 and the dual damascene opening DS2 conformally covers the sidewall and bottom surface of the dual damascene opening DS2. In some embodiments, the second seed metal pattern 156 sandwiched between the trench opening TS2 and the wiring redistribution pattern 162 conformally covers the sidewall and bottom surface of the trench opening TS2.

在一些實施例中，如圖1G所示，位於雙鑲嵌開口DS2內的雙鑲嵌重佈線圖案161包括通孔部分163（位於通孔開口VS2內）及佈線部分164（位於溝渠開口TS2內）。在一些實施例中，堆疊的介電層140的頂表面140a與雙鑲嵌重佈線圖案161的頂表面161a及佈線重佈線圖案162的頂表面162a共面且齊平。In some embodiments, as shown in FIG. 1G, the dual damascene redistribution pattern 161 located in the dual damascene opening DS2 includes a via portion 163 (located in the via opening VS2) and a wiring portion 164 (located in the trench opening TS2). In some embodiments, the top surface 140a of the stacked dielectric layer 140 is coplanar and flush with the top surface 161a of the dual damascene redistribution pattern 161 and the top surface 162a of the redistribution pattern 162.

在圖1G中，第二重佈線層RDL2中的雙鑲嵌重佈線圖案161的通孔部分163的位置與第一重佈線層RDL1中的雙鑲嵌重佈線圖案131的通孔部分133的位置垂直地（沿厚度方向z）對齊。即，通孔開口VS2或通孔部分163的位置與通孔開口VS1或通孔部分133的位置垂直地對齊。在某些實施例中，通孔部分163的位置與通孔部分133的位置垂直地重疊。在一些實施例中，第二重佈線層RDL2的雙鑲嵌重佈線圖案161及第二晶種金屬圖案156直接設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案131上。在一些實施例中，位於第二重佈線層RDL2的雙鑲嵌重佈線圖案161下方的第二晶種金屬圖案156直接接觸第一重佈線層RDL1的雙鑲嵌重佈線圖案131。在一些實施例中，第二重佈線層RDL2的通孔部分163分別堆疊在第一重佈線層RDL1的通孔部分133的正上方。在一些實施例中，通孔部分163在水平方向x上的底部大小小於或約為10微米。In FIG. 1G, the position of the via portion 163 of the dual damascene redistribution pattern 161 in the second redistribution layer RDL2 is perpendicular to the position of the via portion 133 of the dual damascene redistribution pattern 131 in the first redistribution layer RDL1. (In thickness direction z). That is, the position of the through-hole opening VS2 or the through-hole portion 163 is vertically aligned with the position of the through-hole opening VS1 or the through-hole portion 133. In some embodiments, the position of the through-hole portion 163 vertically overlaps the position of the through-hole portion 133. In some embodiments, the dual damascene redistribution pattern 161 and the second seed metal pattern 156 of the second redistribution layer RDL2 are directly disposed on the dual damascene redistribution pattern 131 of the first redistribution layer RDL1. In some embodiments, the second seed metal pattern 156 under the dual damascene redistribution pattern 161 of the second redistribution layer RDL2 directly contacts the dual damascene redistribution pattern 131 of the first redistribution layer RDL1. In some embodiments, the via portions 163 of the second redistribution layer RDL2 are stacked directly above the via portions 133 of the first redistribution layer RDL1, respectively. In some embodiments, the bottom size of the through-hole portion 163 in the horizontal direction x is less than or about 10 microns.

在一些實施例中，通孔開口VS2的底部大小（在方向x上）小於或至多約等於雙鑲嵌重佈線圖案131的下伏佈線部分134的頂部大小（在方向x上）。在一些實施例中，雙鑲嵌重佈線圖案161（通孔部分163和/或佈線部分164）中的一些及佈線重佈線圖案162中的一些具有傾斜的側壁。在一些實施例中，雙鑲嵌重佈線圖案161（通孔部分163和/或佈線部分164）中的一些及佈線重佈線圖案162中的一些具有實質上垂直的側壁。在一些實施例中，通孔開口VS1的底部大小實質上相同於通孔開口VS2的底部大小。在一些實施例中，通孔開口VS1的底部大小不同於通孔開口VS2的底部大小。在一些實施例中，提供多個重佈線層之間的通孔重疊及通孔堆疊對齊。In some embodiments, the bottom size (in direction x) of the via opening VS2 is less than or at most approximately equal to the top size (in direction x) of the underlying wiring portion 134 of the dual damascene redistribution pattern 131. In some embodiments, some of the dual damascene redistribution patterns 161 (through-hole portion 163 and / or wiring portion 164) and some of the redistribution patterns 162 have inclined sidewalls. In some embodiments, some of the dual damascene redistribution patterns 161 (via portions 163 and / or wiring portions 164) and some of the redistribution patterns 162 have substantially vertical sidewalls. In some embodiments, the bottom size of the via opening VS1 is substantially the same as the bottom size of the via opening VS2. In some embodiments, the bottom size of the through hole opening VS1 is different from the bottom size of the through hole opening VS2. In some embodiments, via overlap and via stack alignment between multiple redistribution layers is provided.

在圖1G中，在第一重佈線層或第二重佈線層中示出多於一個雙鑲嵌重佈線圖案。在一些實施例中，一個或多個通孔部分被包括在雙鑲嵌重佈線圖案中，且佈線部分中的一些可與雙鑲嵌重佈線圖案連接。然而，重佈線層的佈局或雙鑲嵌重佈線圖案的排列不受本文所述的實施例限制。In FIG. 1G, more than one dual damascene redistribution pattern is shown in the first redistribution layer or the second redistribution layer. In some embodiments, one or more via portions are included in the dual damascene redistribution pattern, and some of the wiring portions may be connected to the dual damascene redistribution pattern. However, the layout of the redistribution layer or the arrangement of the dual damascene redistribution pattern is not limited by the embodiments described herein.

在某些實施例中，在上述製程步驟之後，形成至少一個或多個重佈線層。應理解，可執行進一步的製造製程步驟或封裝製程步驟以完成封裝結構，且上述製程步驟與晶圓級封裝技術相容。In some embodiments, after the above process steps, at least one or more redistribution layers are formed. It should be understood that further manufacturing process steps or packaging process steps may be performed to complete the packaging structure, and the above process steps are compatible with wafer-level packaging technology.

在某些實施例中，當金屬雙鑲嵌結構具有覆蓋其側壁及底表面的共形金屬晶種層時，會在單層式或多層式重佈線層中實現金屬鑲嵌結構與周圍介電材料之間的更好的黏附。對於多層式重佈線層，不同重佈線層中的雙鑲嵌結構的通孔部分直接堆疊在彼此（each other）或互相（one another）的上方。In some embodiments, when the metal dual damascene structure has a conformal metal seed layer covering its sidewalls and bottom surface, the metal damascene structure and the surrounding dielectric material are realized in a single-layer or multi-layer redistribution layer. Better adhesion in between. For the multilayer redistribution layer, the via portions of the dual damascene structure in different redistribution layers are directly stacked on top of each other or one another.

圖2是根據一些實施例示意性地示出具有一個或多個重佈線層的半導體封裝。在一些實施例中，圖2所示的結構可採用在圖1A到圖1G中所述的製程形成，且在形成第二重佈線層RDL2之後，透過沉積、塗佈或層壓在封裝結構100（圖1G）的上方形成保護層，然後透過微影製程或雷射處理將所述保護層圖案化以形成暴露出位元在下方的部分第二重佈線層RDL2的開口。隨後，將多個導電球附著到第二重佈線層RDL2，且封裝結構100（圖1G）可經歷切割製程而被切割成多個封裝200。參照圖2，封裝200包括晶粒或晶片202、第一重佈線層RDL1、第二重佈線層RDL2及導電球260。在一些實施例中，第一重佈線層RDL1設置在晶片202上且與晶片202的接觸件204電連接及實體連接。在一些實施例中，第二重佈線層RDL2設置在第一重佈線層RDL1上且與第一重佈線層RDL1電連接。在一些實施例中，保護層250位於第二重佈線層RDL2上且覆蓋第二重佈線層RDL2，且保護層250具有暴露出下伏第二重佈線層RDL2的開口。在一些實施例中，一些導電球260位於被暴露出的第二重佈線層RDL2上並在所述開口內，且與第二重佈線層RDL2電連接及實體連接。保護層250的形成是可選的，且在其他實施例中，可省去保護層250。FIG. 2 is a schematic illustration of a semiconductor package having one or more redistribution layers, according to some embodiments. In some embodiments, the structure shown in FIG. 2 may be formed using the process described in FIGS. 1A to 1G, and after the second redistribution layer RDL2 is formed, it is deposited, coated or laminated on the packaging structure 100. (FIG. 1G) A protective layer is formed on the top, and then the protective layer is patterned through a lithography process or a laser process to form an opening that exposes a portion of the second redistribution layer RDL2 with the bits below. Subsequently, a plurality of conductive balls are attached to the second redistribution layer RDL2, and the package structure 100 (FIG. 1G) may be cut into a plurality of packages 200 through a dicing process. 2, the package 200 includes a die or a wafer 202, a first redistribution layer RDL1, a second redistribution layer RDL2, and a conductive ball 260. In some embodiments, the first redistribution layer RDL1 is disposed on the wafer 202 and is electrically and physically connected to the contacts 204 of the wafer 202. In some embodiments, the second redistribution layer RDL2 is disposed on the first redistribution layer RDL1 and is electrically connected to the first redistribution layer RDL1. In some embodiments, the protective layer 250 is located on the second redistribution layer RDL2 and covers the second redistribution layer RDL2, and the protective layer 250 has an opening exposing the underlying second redistribution layer RDL2. In some embodiments, some conductive balls 260 are located on the exposed second redistribution layer RDL2 and within the opening, and are electrically and physically connected to the second redistribution layer RDL2. The formation of the protective layer 250 is optional, and in other embodiments, the protective layer 250 may be omitted.

在圖2中，第一重佈線層RDL1包括一個或多個雙鑲嵌重佈線圖案DP1，且第二重佈線層RDL2包括一個或多個雙鑲嵌重佈線圖案DP2。在一些實施例中，第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2堆疊且設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1的正上方。在某些實施例中，雙鑲嵌重佈線圖案DP2的通孔部分VP2的位置與雙鑲嵌重佈線圖案DP1的通孔部分VP1的位置重疊且垂直地對齊。即，通孔部分VP2到基底表面的平面上的正交投影與通孔部分VP1到基底表面的平面上的正交投影重疊。如在圖2的上部分中所看到的，如果考慮到通孔開口VS1的底部大小實質上等於或大於通孔開口VS2的底部大小，則通孔部分VP1在基底表面202a上的正交投影（示出為點線）與通孔部分VP2在基底表面202a上的正交投影（示出為虛線）彼此重疊且同心地排列在圓形接觸件204的跨度（span）內。In FIG. 2, the first redistribution layer RDL1 includes one or more dual damascene redistribution patterns DP1, and the second redistribution layer RDL2 includes one or more dual damascene redistribution patterns DP2. In some embodiments, the dual damascene redistribution pattern DP2 of the second redistribution layer RDL2 is stacked and disposed directly above the dual damascene redistribution pattern DP1 of the first redistribution layer RDL1. In some embodiments, the position of the via portion VP2 of the dual damascene redistribution pattern DP2 and the position of the via portion VP1 of the dual damascene redistribution pattern DP1 overlap and are vertically aligned. That is, the orthogonal projection of the through-hole portion VP2 onto the plane of the substrate surface and the orthogonal projection of the through-hole portion VP1 onto the plane of the substrate surface overlap. As seen in the upper part of FIG. 2, if considering that the bottom size of the via opening VS1 is substantially equal to or larger than the bottom size of the via opening VS2, the orthogonal projection of the via portion VP1 on the substrate surface 202a (Shown as a dotted line) and an orthogonal projection (shown as a dashed line) of the through-hole portion VP2 on the base surface 202 a overlap each other and are arranged concentrically within a span of the circular contact 204.

在圖2中，第一重佈線層RDL1及第二重佈線層RDL2是形成在晶片202的主動表面上的前側重佈線層。圖2中的結構可以是晶圓級晶片尺寸封裝（wafer level chip scale package，WLCSP）結構，且所述晶片及重佈線層具有實質上相同的大小規格。In FIG. 2, the first redistribution layer RDL1 and the second redistribution layer RDL2 are front-side redistribution layers formed on the active surface of the wafer 202. The structure in FIG. 2 may be a wafer level chip scale package (WLCSP) structure, and the wafer and the redistribution layer have substantially the same size specifications.

圖3A到圖3D是根據一些實施例示意性地示出根據製作半導體封裝的方法來形成另一個重佈線層的製程的各個階段。參照圖3A，提供具有形成在基底302上的至少第一重佈線層RDL1的封裝結構。在一些實施例中，第一重佈線層RDL1與基底302的接觸件304電連接。在一些實施例中，圖3A中的封裝結構可採用在圖1A到圖1F中所述的製程形成。在一些實施例中，在第一重佈線層RDL1上形成具有通孔開口VS3的第三介電層310且在第三介電層310的上方形成第三晶種金屬層315，從而共形地覆蓋第三介電層310及通孔開口VS3。3A to 3D are schematic diagrams illustrating various stages of a process of forming another redistribution layer according to a method of fabricating a semiconductor package according to some embodiments. 3A, a package structure having at least a first redistribution layer RDL1 formed on a substrate 302 is provided. In some embodiments, the first redistribution layer RDL1 is electrically connected to the contacts 304 of the substrate 302. In some embodiments, the package structure in FIG. 3A may be formed using the process described in FIGS. 1A to 1F. In some embodiments, a third dielectric layer 310 having a through hole opening VS3 is formed on the first redistribution layer RDL1 and a third seed metal layer 315 is formed above the third dielectric layer 310, thereby conformally Covers the third dielectric layer 310 and the via opening VS3.

然後，如在圖3B中所看到的，在一些實施例中，在第三晶種金屬層315上形成界定溝渠開口TS3的光阻圖案320。溝渠開口TS3中的一些與通孔開口VS3進行接合以形成開口DS3。在一些實施例中，光阻圖案320是透過層壓或旋轉塗佈以形成光阻層（圖中未示出）而形成，然後透過微影製程或雷射製程進行圖案化。在某些實施例中，在第三晶種金屬層315上形成第三金屬層330，第三金屬層330包括填充在溝渠開口TS3中的佈線重佈線圖案332及填充在開口DS3中的重佈線圖案331。在一些實施例中，第三金屬層330的形成包括透過電鍍在晶種金屬層315上形成銅層或銅合金層（圖中未示出）以填充開口DS3且填滿溝渠開口TS3。在一些實施例中，第三金屬層330是透過CVD製程、ECP製程或者甚至是濺射製程而形成。然而，應理解，本公開的範圍不限於上文所公開的材料及說明。Then, as seen in FIG. 3B, in some embodiments, a photoresist pattern 320 defining a trench opening TS3 is formed on the third seed metal layer 315. Some of the trench openings TS3 are joined with the through-hole opening VS3 to form the opening DS3. In some embodiments, the photoresist pattern 320 is formed by lamination or spin coating to form a photoresist layer (not shown in the figure), and then patterned by a lithography process or a laser process. In some embodiments, a third metal layer 330 is formed on the third seed metal layer 315. The third metal layer 330 includes a wiring redistribution pattern 332 filled in the trench opening TS3 and a redistribution filled in the opening DS3. Pattern 331. In some embodiments, the formation of the third metal layer 330 includes forming a copper layer or a copper alloy layer (not shown) on the seed metal layer 315 through electroplating to fill the opening DS3 and fill the trench opening TS3. In some embodiments, the third metal layer 330 is formed through a CVD process, an ECP process, or even a sputtering process. It should be understood, however, that the scope of the present disclosure is not limited to the materials and descriptions disclosed above.

在一些實施例中，在圖3B及圖3C中，移除光阻圖案320。在一些實施例中，在光阻圖案320的移除期間，將光阻圖案320下方的第三晶種金屬層315連同光阻圖案320一起移除，以在佈線重佈線圖案332及重佈線圖案331的下方形成第三晶種金屬圖案316。在替代實施例中，透過剝離製程移除光阻圖案320，然後透過蝕刻製程部分地移除第三晶種金屬層315。參照圖3C，第三晶種金屬圖案316夾置在第三介電層310與佈線重佈線圖案332的底表面之間及在第三介電層310與重佈線圖案331的底表面之間。在一些實施例中，第三晶種金屬圖案316覆蓋重佈線圖案331的佈線部分的底表面且覆蓋重佈線圖案331的通孔部分的側壁及底表面。即，第三晶種金屬圖案316不覆蓋佈線重佈線圖案332的側表面及重佈線圖案331的側表面。In some embodiments, in FIGS. 3B and 3C, the photoresist pattern 320 is removed. In some embodiments, during the removal of the photoresist pattern 320, the third seed metal layer 315 under the photoresist pattern 320 is removed together with the photoresist pattern 320 to re-route the pattern 332 and the redistribution pattern. A third seed metal pattern 316 is formed below 331. In an alternative embodiment, the photoresist pattern 320 is removed through a lift-off process, and then the third seed metal layer 315 is partially removed through an etch process. Referring to FIG. 3C, the third seed metal pattern 316 is interposed between the third dielectric layer 310 and the bottom surface of the wiring redistribution pattern 332 and between the third dielectric layer 310 and the bottom surface of the redistribution pattern 331. In some embodiments, the third seed metal pattern 316 covers the bottom surface of the wiring portion of the redistribution pattern 331 and covers the sidewall and the bottom surface of the through-hole portion of the redistribution pattern 331. That is, the third seed metal pattern 316 does not cover the side surface of the wiring redistribution pattern 332 and the side surface of the redistribution pattern 331.

在一些實施例中，在圖3D中，在第一重佈線層RDL1上形成第四介電層340。在一些實施例中，第四介電層340可透過層壓或塗佈而形成以覆蓋佈線重佈線圖案332及重佈線圖案331，然後被部分地移除或蝕刻以暴露出重佈線圖案331的頂表面331a及佈線重佈線圖案332的頂表面332a。完成在第一重佈線層RDL1上的第三重佈線層RDL3的形成。In some embodiments, in FIG. 3D, a fourth dielectric layer 340 is formed on the first redistribution layer RDL1. In some embodiments, the fourth dielectric layer 340 may be formed by laminating or coating to cover the wiring redistribution pattern 332 and the redistribution pattern 331, and then partially removed or etched to expose the redistribution pattern 331. The top surface 331a and the top surface 332a of the wiring redistribution pattern 332. The formation of the third redistribution layer RDL3 on the first redistribution layer RDL1 is completed.

圖3D’是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝的剖視圖。在圖3D’中，第四介電層340’覆蓋佈線重佈線圖案332，但暴露出重佈線圖案331的部分。在一些實施例中，第四介電層340’可透過層壓或塗佈而形成以完全覆蓋佈線重佈線圖案332及重佈線圖案331，然後被部分地移除或蝕刻以暴露出重佈線圖案331的所述部分的頂表面331a。FIG. 3D 'is a cross-sectional view schematically showing a semiconductor package having a plurality of redistribution layers according to some embodiments. In FIG. 3D ', the fourth dielectric layer 340' covers the wiring redistribution pattern 332, but a portion of the redistribution pattern 331 is exposed. In some embodiments, the fourth dielectric layer 340 'may be formed by laminating or coating to completely cover the wiring redistribution pattern 332 and the redistribution pattern 331, and then partially removed or etched to expose the redistribution pattern. The top surface 331a of the portion of 331.

在一些實施例中，第三重佈線層RDL3可以是具有小尺寸的線及間隔（L/S）的超高密度重佈線層（ultra-high density redistribution layer）。在某些實施例中，第三重佈線層RDL3具有約為或小於2微米/2微米的L/S尺寸。在示例性實施例中，第三重佈線層RDL3是透過半加性製程而形成，從而具有與含雙鑲嵌的重佈線層（例如，第一重佈線層RDL1或第二重佈線層RDL2）的L/S尺寸相比更小的L/S尺寸。在一些實施例中，第三重佈線層RDL3形成在一個或多個含雙鑲嵌的重佈線層上，且這些堆疊的重佈線結構可被視為混合型（hybrid type）重佈線結構。In some embodiments, the third redistribution layer RDL3 may be an ultra-high density redistribution layer with small-sized lines and spaces (L / S). In some embodiments, the third redistribution layer RDL3 has an L / S size of about or less than 2 microns / 2 microns. In an exemplary embodiment, the third redistribution layer RDL3 is formed through a semi-additive process, so that the third redistribution layer RDL3 has a double redistribution layer (eg, the first redistribution layer RDL1 or the second redistribution layer RDL2). L / S size compared to smaller L / S size. In some embodiments, the third redistribution layer RDL3 is formed on one or more redistribution layers with dual damascene, and these stacked redistribution structures can be regarded as a hybrid type redistribution structure.

圖4是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。參照圖4，整合扇出型（InFO）封裝400包括並排排列且包封在模塑化合物430內的第一晶粒410及第二晶粒420。在一些實施例中，至少第一重佈線層RDL1及第二重佈線層RDL2位於模塑化合物430上及第一晶粒410及第二晶粒420的上方。另外，多個導電元件440位於第二重佈線層RDL2上且連接到第二重佈線層RDL2。在圖4中，第一重佈線層RDL1包括一個或多個雙鑲嵌重佈線圖案DP1，且第二重佈線層RDL2包括一個或多個雙鑲嵌重佈線圖案DP2。第二重佈線層RDL2的形成類似於在圖1A到圖1F中所述的第一重佈線層RDL1的形成。在一些實施例中，第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2堆疊且設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1的正上方。在某些實施例中，通孔部分VP2到晶粒表面的平面上的正交投影與通孔部分VP1到同一平面上的正交投影完全重疊。FIG. 4 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. Referring to FIG. 4, an integrated fan-out (InFO) package 400 includes a first die 410 and a second die 420 arranged side by side and enclosed within a molding compound 430. In some embodiments, at least the first redistribution layer RDL1 and the second redistribution layer RDL2 are located on the molding compound 430 and above the first die 410 and the second die 420. In addition, a plurality of conductive elements 440 are located on and connected to the second redistribution layer RDL2. In FIG. 4, the first redistribution layer RDL1 includes one or more dual damascene redistribution patterns DP1, and the second redistribution layer RDL2 includes one or more dual damascene redistribution patterns DP2. The formation of the second redistribution layer RDL2 is similar to the formation of the first redistribution layer RDL1 described in FIGS. 1A to 1F. In some embodiments, the dual damascene redistribution pattern DP2 of the second redistribution layer RDL2 is stacked and disposed directly above the dual damascene redistribution pattern DP1 of the first redistribution layer RDL1. In some embodiments, the orthogonal projection of the via portion VP2 onto the plane of the die surface and the orthogonal projection of the via portion VP1 onto the same plane completely overlap.

在一些實施例中，第一重佈線層RDL1與第一晶粒410及第二晶粒420電連接，且第二重佈線層RDL2也透過第一重佈線層RDL1與第一晶粒410及第二晶粒420電連接。第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1中的一些直接與第一晶粒410的第一接觸件412及第二晶粒420的第二接觸件422連接。在某些實施例中，第一晶粒410包括系統晶片（system-on-a-chip，SoC）晶粒或應用專用積體電路（application specific integrated circuit，ASIC）晶片。在某些實施例中，第二晶粒420包括記憶體晶片或高頻寬記憶體晶片。在圖4中，第一重佈線層RDL1及第二重佈線層RDL2是前側重佈線層。在一些實施例中，保護層450位於第二重佈線層RDL2上且覆蓋所述第二重佈線層RDL2，保護層450具有暴露出下伏第二重佈線層RDL2的開口。在一些實施例中，導電元件440位於被暴露出的第二重佈線層RDL2上並位在所述開口內，且與第二重佈線層RDL2電連接及實體連接。在一些實施例中，導電元件440是凸塊、受控塌陷晶粒連接（controlled collapse chip connection，C4）凸塊或球柵陣列（ball grid array，BGA）球。保護層450的形成是可選的，且在其他實施例中，可省去保護層450。In some embodiments, the first redistribution layer RDL1 is electrically connected to the first die 410 and the second die 420, and the second redistribution layer RDL2 is also connected to the first die 410 and the first die 410 through the first redistribution layer RDL1. The two dies 420 are electrically connected. Some of the dual damascene redistribution patterns DP1 of the first redistribution layer RDL1 are directly connected to the first contacts 412 of the first die 410 and the second contacts 422 of the second die 420. In some embodiments, the first die 410 includes a system-on-a-chip (SoC) die or an application specific integrated circuit (ASIC) die. In some embodiments, the second die 420 includes a memory chip or a high-bandwidth memory chip. In FIG. 4, the first redistribution layer RDL1 and the second redistribution layer RDL2 are front-side redistribution layers. In some embodiments, the protection layer 450 is located on the second redistribution layer RDL2 and covers the second redistribution layer RDL2. The protective layer 450 has an opening exposing the underlying second redistribution layer RDL2. In some embodiments, the conductive element 440 is located on the exposed second redistribution layer RDL2 and is located in the opening, and is electrically and physically connected to the second redistribution layer RDL2. In some embodiments, the conductive element 440 is a bump, a controlled collapse chip connection (C4) bump, or a ball grid array (BGA) ball. The formation of the protective layer 450 is optional, and in other embodiments, the protective layer 450 may be omitted.

圖5是根據一些實施例示意性地示出具有各種重佈線層的半導體封裝。參照圖5，整合扇出型（InFO）封裝500包括包封在模塑化合物530內的至少一個晶粒510及多於一個的層間穿孔（through interlayer via，TIV）520。在一些實施例中，至少第一重佈線層RDL1、第二重佈線層RDL2及第三重佈線層RDL3依序堆疊在且位於模塑化合物530上，並位在晶粒510及層間穿孔 520的上方。另外，多個導電元件540位於第三重佈線層RDL3上且連接到第三重佈線層RDL3。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2可採用在圖1A到圖1G中所述的製程形成。第三重佈線層RDL3的形成類似於採用在圖3A到圖3D中所述的製程的第三重佈線層RDL3的形成。在圖5中，第一重佈線層RDL1、第二重佈線層RDL2及第三重佈線層RDL3分別包括一個或多個雙鑲嵌重佈線圖案DP1、DP2、DP3。在一些實施例中，第三重佈線層RDL3的雙鑲嵌重佈線圖案DP3相應地堆疊且設置在第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2的正上方，而第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2相應地堆疊且設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1的正上方。在某些實施例中，對應的雙鑲嵌重佈線圖案DP1、DP2、DP3的通孔部分VP1、VP2、VP3的正交投影在同一平面（晶粒頂表面510a）上彼此完全重疊。在一些實施例中，前保護層FP覆蓋第三重佈線層RDL3且具有開口暴露出下伏第三重佈線層RDL3的部分。前保護層FP的形成是可選的，且在其他實施例中，可省去前保護層FP。在一些實施例中，導電元件540中的一些位於被暴露出的第三重佈線層RDL3上並位在所述開口內，且與第三重佈線層RDL3電連接及實體連接。在一些實施例中，導電元件540是凸塊、受控塌陷晶粒連接（C4）凸塊或球柵陣列（BGA）球。FIG. 5 is a semiconductor package having various redistribution layers, according to some embodiments. Referring to FIG. 5, an integrated fan-out (InFO) package 500 includes at least one die 510 and more than one through interlayer via (TIV) 520 encapsulated within a molding compound 530. In some embodiments, at least the first redistribution layer RDL1, the second redistribution layer RDL2, and the third redistribution layer RDL3 are sequentially stacked and located on the molding compound 530, and are located on the die 510 and the interlayer via 520 Up. In addition, a plurality of conductive elements 540 are located on and connected to the third redistribution layer RDL3. In some embodiments, the first redistribution layer RDL1 and the second redistribution layer RDL2 may be formed by the processes described in FIGS. 1A to 1G. The formation of the third redistribution layer RDL3 is similar to the formation of the third redistribution layer RDL3 using the process described in FIGS. 3A to 3D. In FIG. 5, the first redistribution layer RDL1, the second redistribution layer RDL2, and the third redistribution layer RDL3 respectively include one or more dual damascene redistribution patterns DP1, DP2, and DP3. In some embodiments, the dual damascene redistribution pattern DP3 of the third redistribution layer RDL3 is correspondingly stacked and disposed directly above the dual damascene redistribution pattern DP2 of the second redistribution layer RDL2, and the The dual damascene redistribution pattern DP2 is stacked accordingly and is disposed directly above the dual damascene redistribution pattern DP1 of the first redistribution layer RDL1. In some embodiments, the orthogonal projections of the through-hole portions VP1, VP2, and VP3 of the corresponding dual damascene redistribution patterns DP1, DP2, and DP3 completely overlap each other on the same plane (top surface 510a). In some embodiments, the front protective layer FP covers the third redistribution layer RDL3 and has a portion that exposes the underlying third redistribution layer RDL3. The formation of the front protective layer FP is optional, and in other embodiments, the front protective layer FP may be omitted. In some embodiments, some of the conductive elements 540 are located on the exposed third redistribution layer RDL3 and are located in the opening, and are electrically and physically connected to the third redistribution layer RDL3. In some embodiments, the conductive element 540 is a bump, a controlled collapsed grain connection (C4) bump, or a ball grid array (BGA) ball.

在一些實施例中，在圖5中，第一重佈線層RDL1與晶粒510電連接，且第二重佈線層RDL2及第三重佈線層RDL3透過第一重佈線層RDL1與晶粒510電連接。第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1中的一些分別直接與晶粒510的接觸件512及層間穿孔 520連接。在某些實施例中，晶粒510包括ASIC晶片、類比晶片、感測器晶片、無線及射頻晶片、電壓調節器晶片或記憶體晶片。在一些實施例中，整合扇出型封裝500還包括具有與層間穿孔520電連接的佈線線（routing lines）552及穿孔（through vias）554的背側重佈線結構550。在一些實施例中，背保護層BP位於背側重佈線結構550的上方且覆蓋背側重佈線結構550，且背保護層BP具有暴露出部分佈線線552及部分穿孔554的開口。這種背保護層BP的形成是可選的，且在其他實施例中，可省去背保護層BP。在某些實施例中，背側重佈線結構550有利於與另一個晶粒或子封裝的進一步連接，從而形成疊層封裝（PoP）結構。In some embodiments, in FIG. 5, the first redistribution layer RDL1 is electrically connected to the die 510, and the second redistribution layer RDL2 and the third redistribution layer RDL3 are electrically connected to the die 510 through the first redistribution layer RDL1. connection. Some of the dual damascene redistribution patterns DP1 of the first redistribution layer RDL1 are directly connected to the contacts 512 and the interlayer vias 520 of the die 510, respectively. In some embodiments, the die 510 includes an ASIC chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. In some embodiments, the integrated fan-out package 500 further includes a backside heavy wiring structure 550 having routing lines 552 and through vias 554 electrically connected to the inter-layer vias 520. In some embodiments, the back protection layer BP is located above the back-side redistribution structure 550 and covers the back-side redistribution structure 550, and the back protection layer BP has an opening exposing part of the wiring line 552 and part of the through-hole 554. The formation of such a back protective layer BP is optional, and in other embodiments, the back protective layer BP may be omitted. In some embodiments, the back-side redistribution structure 550 facilitates further connection with another die or sub-package to form a package-on-package (PoP) structure.

在圖5中，第一重佈線層RDL1、第二重佈線層RDL2及第三重佈線層RDL3是前側重佈線層，且與晶粒510及層間穿孔 520電連接。在一些實施例中，佈線重佈線圖案也形成在前側重佈線層的混合結構內，且根據產品的佈局設計，不同重佈線層中的佈線重佈線圖案的位置不一定是垂直對齊的。在示例性實施例中，第三重佈線層RDL3具有與含雙鑲嵌的重佈線層（例如，第一重佈線層RDL1或第二重佈線層RDL2）的L/S尺寸相比更小的L/S尺寸。由於第一重佈線層RDL1及第二重佈線層RDL2為隨後形成的高密度第三重佈線層RDL3提供良好的平面性，因此混合型前側重佈線層提供電連接的良好的可靠性及電性質。In FIG. 5, the first redistribution layer RDL1, the second redistribution layer RDL2, and the third redistribution layer RDL3 are front-side redistribution layers, and are electrically connected to the die 510 and the interlayer via 520. In some embodiments, the wiring redistribution pattern is also formed in the mixed structure of the front redistribution layer, and according to the layout design of the product, the positions of the redistribution pattern in different redistribution layers are not necessarily vertically aligned. In an exemplary embodiment, the third redistribution layer RDL3 has a smaller L / S size compared to the L / S size of the redistribution layer including the dual damascene (eg, the first redistribution layer RDL1 or the second redistribution layer RDL2). / S size. Since the first redistribution layer RDL1 and the second redistribution layer RDL2 provide good planarity for the subsequent high-density third redistribution layer RDL3, the hybrid front-side redistribution layer provides good reliability and electrical properties of the electrical connection. .

圖6是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。參照圖6，整合扇出型封裝600包括包封在模塑化合物630內的至少一個晶粒610及多於一個的層間穿孔（TIV）620。在一些實施例中，封裝600的形成可採用先重佈線層（redistribution layer first，RDL-first）製程，包括在放置晶粒610之前在載體上形成至少第一重佈線層RDL1及第二重佈線層RDL2。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2位於模塑化合物630下方（位於模塑化合物630的底表面上）及晶粒610及層間穿孔 620的下方。第一重佈線層RDL1與層間穿孔 620電連接且透過佈線線652及層間穿孔 620與背側重佈線結構650電連接。另外，多個導電元件640位於第二重佈線層RDL2上且連接到第二重佈線層RDL2。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2中的兩者或至少一者可採用在圖1A到圖1F中所述的製程形成。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2中的至多一者是採用在圖3A到圖3D中所述的製程形成。在圖6中，第一重佈線層RDL1及第二重佈線層RDL2分別包括一個或多個雙鑲嵌重佈線圖案DP1、DP2。在一些實施例中，第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2相應地堆疊且設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案DP1的正上方。在某些實施例中，對應雙鑲嵌重佈線圖案DP1、DP2的通孔部分VP1、VP2的正交投影在同一平面上彼此完全重疊。即，第一重佈線層RDL1與第二重佈線層RDL2彼此電連接。FIG. 6 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. Referring to FIG. 6, the integrated fan-out package 600 includes at least one die 610 and more than one interlayer via (TIV) 620 encapsulated within a molding compound 630. In some embodiments, the formation of the package 600 may use a redistribution layer first (RDL-first) process, which includes forming at least a first redistribution layer RDL1 and a second redistribution on a carrier before the die 610 is placed. Layer RDL2. In some embodiments, the first redistribution layer RDL1 and the second redistribution layer RDL2 are located under the molding compound 630 (on the bottom surface of the molding compound 630) and under the die 610 and the interlayer via 620. The first redistribution layer RDL1 is electrically connected to the interlayer via 620 and is electrically connected to the backside redistribution structure 650 through the wiring line 652 and the interlayer via 620. In addition, a plurality of conductive elements 640 are located on the second redistribution layer RDL2 and are connected to the second redistribution layer RDL2. In some embodiments, both or at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 may be formed using a process described in FIGS. 1A to 1F. In some embodiments, at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 is formed using a process described in FIGS. 3A to 3D. In FIG. 6, the first redistribution layer RDL1 and the second redistribution layer RDL2 respectively include one or more dual damascene redistribution patterns DP1 and DP2. In some embodiments, the dual damascene redistribution pattern DP2 of the second redistribution layer RDL2 is correspondingly stacked and disposed directly above the dual damascene redistribution pattern DP1 of the first redistribution layer RDL1. In some embodiments, the orthogonal projections of the through-hole portions VP1 and VP2 corresponding to the dual damascene redistribution patterns DP1 and DP2 completely overlap each other on the same plane. That is, the first redistribution layer RDL1 and the second redistribution layer RDL2 are electrically connected to each other.

在一些實施例中，在圖6中，第一重佈線層RDL1透過位於晶粒610與第一重佈線層RDL1之間的凸塊615與晶粒610電連接，且第二重佈線層RDL2與導電元件640電連接。在一些實施例中，前保護層FP覆蓋第二重佈線層RDL2並具有暴露出部分第二重佈線層RDL2的開口。前保護層FP的形成是可選的，且在其他實施例中，可省去前保護層FP。在一些實施例中，凸塊615是微凸塊，且底部填充膠618進一步包括在晶粒610與第一重佈線層RDL1之間及凸塊615之間。在一些實施例中，導電元件640中的一些位於被暴露出的第二重佈線層RDL2上並位在前保護層FP的開口內，且與第二重佈線層RDL2電連接及實體連接。在一些實施例中，導電元件640是受控塌陷晶粒連接（C4）凸塊或球柵陣列（BGA）球。第二重佈線層RDL2的雙鑲嵌重佈線圖案DP2中的一些直接與導電元件640連接。在一些實施例中，背側重佈線結構650有利於與另一個晶粒或子封裝的進一步連接以形成疊層封裝（PoP）結構。在一些實施例中，背保護層BP位於背側重佈線結構650的上方且覆蓋背側重佈線結構650，且背保護層BP具有暴露出部分佈線線652的開口。這種背保護層BP的形成是可選的，且在其他實施例中，可省去背保護層BP。In some embodiments, in FIG. 6, the first redistribution layer RDL1 is electrically connected to the die 610 through the bump 615 located between the die 610 and the first redistribution layer RDL1, and the second redistribution layer RDL2 is The conductive element 640 is electrically connected. In some embodiments, the front protective layer FP covers the second redistribution layer RDL2 and has an opening exposing a part of the second redistribution layer RDL2. The formation of the front protective layer FP is optional, and in other embodiments, the front protective layer FP may be omitted. In some embodiments, the bump 615 is a micro-bump, and the underfill 618 is further included between the die 610 and the first redistribution layer RDL1 and between the bump 615. In some embodiments, some of the conductive elements 640 are located on the exposed second redistribution layer RDL2 and are located in the openings of the front protective layer FP, and are electrically and physically connected to the second redistribution layer RDL2. In some embodiments, the conductive element 640 is a controlled collapsed grain connection (C4) bump or a ball grid array (BGA) ball. Some of the dual damascene redistribution patterns DP2 of the second redistribution layer RDL2 are directly connected to the conductive element 640. In some embodiments, the back-side redistribution structure 650 facilitates further connection with another die or sub-package to form a package-on-package (PoP) structure. In some embodiments, the back protection layer BP is located above the back-side redistribution structure 650 and covers the back-side redistribution structure 650, and the back protection layer BP has an opening exposing a part of the wiring lines 652. The formation of such a back protective layer BP is optional, and in other embodiments, the back protective layer BP may be omitted.

參照圖7，在一些實施例中，封裝700包括安裝在電路板層壓板（circuit board laminate）760上的子封裝70。子封裝70類似於在圖6中所述的封裝600，但沒有導電元件。在一些實施例中，子封裝70具有第一重佈線層RDL1及第二重佈線層RDL2。在一些實施例中，第二重佈線層RDL2與嵌置在電路板層壓板760內的導電插塞762實體連接及電連接。另外，導電元件780設置在電路板層壓板760下方且與導電插塞762連接。在一些實施例中，電路板層壓板760是印刷電路板，且導電元件780是球柵陣列（BGA）球。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2中的兩者或至少一者可採用在圖1A到圖1F中所述的製程形成。在一些實施例中，第一重佈線層RDL1及第二重佈線層RDL2中的至多一者是採用在圖3A到圖3D中所述的製程形成。在圖7中，在一些實施例中，第二重佈線層RDL2的雙鑲嵌重佈線圖案相應地堆疊且設置在第一重佈線層RDL1的雙鑲嵌重佈線圖案的正上方。Referring to FIG. 7, in some embodiments, the package 700 includes a sub-package 70 mounted on a circuit board laminate 760. The sub-package 70 is similar to the package 600 described in FIG. 6 but without conductive elements. In some embodiments, the sub-package 70 has a first redistribution layer RDL1 and a second redistribution layer RDL2. In some embodiments, the second redistribution layer RDL2 is physically and electrically connected to the conductive plug 762 embedded in the circuit board laminate 760. In addition, a conductive element 780 is disposed below the circuit board laminate 760 and is connected to the conductive plug 762. In some embodiments, the circuit board laminate 760 is a printed circuit board and the conductive element 780 is a ball grid array (BGA) ball. In some embodiments, both or at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 may be formed using a process described in FIGS. 1A to 1F. In some embodiments, at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 is formed using a process described in FIGS. 3A to 3D. In FIG. 7, in some embodiments, the dual damascene redistribution pattern of the second redistribution layer RDL2 is correspondingly stacked and disposed directly above the dual damascene redistribution pattern of the first redistribution layer RDL1.

圖8是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。參照圖8，封裝800包括電路基底880、中介層860、以及包封在模塑化合物830內的第一晶粒810及第二晶粒820。在一些實施例中，經包封的第一晶粒810及第二晶粒820位於中介層860上，且內連結構850位於模塑化合物830與中介層860之間。在一些實施例中，封裝800包括第一重佈線層RDL1及第二重佈線層RDL2位於中介層860的下側上以及與第二重佈線層RDL2連接且位於電路基底880與第二重佈線層RDL2之間的導電元件870。凸塊815及凸塊825分別位於第一晶粒810與內連結構850之間及第二晶粒820與內連結構850之間，第一晶粒810及第二晶粒820透過凸塊815及凸塊825與內連結構850電連接。在某些實施例中，中介層860包括穿透過中介層860的中介層穿孔865。在某些實施例中，第一晶粒810及第二晶粒820透過位於它們之間的凸塊815、凸塊825、內連結構850及中介層穿孔865與第一重佈線層RDL1及第二重佈線層RDL2電連接。另外，導電球890進一步連接到電路基底880上。FIG. 8 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. Referring to FIG. 8, the package 800 includes a circuit substrate 880, an interposer 860, and a first die 810 and a second die 820 encapsulated in a molding compound 830. In some embodiments, the encapsulated first die 810 and the second die 820 are located on the interposer 860, and the interconnect structure 850 is located between the molding compound 830 and the interposer 860. In some embodiments, the package 800 includes a first redistribution layer RDL1 and a second redistribution layer RDL2 on the lower side of the interposer 860 and is connected to the second redistribution layer RDL2 and is located on the circuit substrate 880 and the second redistribution layer Conductive element 870 between RDL2. The bumps 815 and 825 are respectively located between the first die 810 and the interconnect structure 850 and between the second die 820 and the interconnect structure 850. The first die 810 and the second die 820 pass through the bump 815. The bump 825 is electrically connected to the interconnect structure 850. In some embodiments, the interposer 860 includes an interposer via 865 passing through the interposer 860. In some embodiments, the first die 810 and the second die 820 pass through the bump 815, the bump 825, the interconnect structure 850, and the interposer via 865 and the first redistribution layer RDL1 and The double wiring layer RDL2 is electrically connected. In addition, the conductive ball 890 is further connected to the circuit substrate 880.

在一些實施例中，圖8中的第一重佈線層RDL1及第二重佈線層RDL2中的兩者或至少一者可採用在圖1A到圖1F中所述的製程形成。在一些實施例中，第一重佈線層RDL1的雙鑲嵌重佈線圖案相應地堆疊且設置在第二重佈線層RDL2的雙鑲嵌重佈線圖案的正上方。在某些實施例中，第一重佈線層RDL1的雙鑲嵌重佈線圖案中的一些直接與中介層穿孔865連接。在某些實施例中，第一晶粒810包括SoC晶粒或ASIC晶片。在某些實施例中，第二晶粒820包括記憶體晶片或高頻寬記憶體晶片。在一些實施例中，導電元件870是凸塊或受控塌陷晶粒連接（C4）凸塊。在一些實施例中，電路基底880是有機柔性基底或印刷電路板，而導電球890是球柵陣列（BGA）球。在某些實施例中，封裝800可透過基底上晶圓上晶片（chip on wafer on substrate，CoWoS）封裝製程而形成。In some embodiments, two or at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 in FIG. 8 may be formed using the processes described in FIGS. 1A to 1F. In some embodiments, the dual damascene redistribution pattern of the first redistribution layer RDL1 is correspondingly stacked and disposed directly above the dual damascene redistribution pattern of the second redistribution layer RDL2. In some embodiments, some of the dual damascene redistribution patterns of the first redistribution layer RDL1 are directly connected to the interposer vias 865. In some embodiments, the first die 810 includes a SoC die or an ASIC wafer. In some embodiments, the second die 820 includes a memory chip or a high-bandwidth memory chip. In some embodiments, the conductive element 870 is a bump or a controlled collapsed grain connection (C4) bump. In some embodiments, the circuit substrate 880 is an organic flexible substrate or a printed circuit board, and the conductive ball 890 is a ball grid array (BGA) ball. In some embodiments, the package 800 may be formed through a chip on wafer on substrate (CoWoS) packaging process.

參照圖9，在一些實施例中，封裝900類似於在圖8中所述的封裝800，其具有內連結構950，但沒有中介層860及中介層穿孔865。在一些實施例中，封裝900具有第一重佈線層RDL1及第二重佈線層RDL2。類似地，第一重佈線層RDL1及第二重佈線層RDL2中的兩者或至少一者可採用在圖1A到圖1F中所述的製程形成。在一些實施例中，第一重佈線層RDL1的雙鑲嵌重佈線圖案相應地堆疊且設置在第二重佈線層RDL2的雙鑲嵌重佈線圖案的正上方。Referring to FIG. 9, in some embodiments, the package 900 is similar to the package 800 described in FIG. 8, which has an interconnect structure 950 but without an interposer 860 and an interposer via 865. In some embodiments, the package 900 has a first redistribution layer RDL1 and a second redistribution layer RDL2. Similarly, both or at least one of the first redistribution layer RDL1 and the second redistribution layer RDL2 may be formed using a process described in FIGS. 1A to 1F. In some embodiments, the dual damascene redistribution pattern of the first redistribution layer RDL1 is correspondingly stacked and disposed directly above the dual damascene redistribution pattern of the second redistribution layer RDL2.

在以上實施例中所展示及闡述的重佈線層可適用於各種類型的封裝，且重佈線層的佈局及設計可基於產品的電要求進行修改。The redistribution layer shown and explained in the above embodiments can be applied to various types of packages, and the layout and design of the redistribution layer can be modified based on the electrical requirements of the product.

根據本公開的一些實施例，公開了一種半導體封裝。所述半導體封裝包括第一晶粒、第一重佈線層及第二重佈線層。所述第一重佈線層設置在所述第一晶粒的上方且與所述第一晶粒電連接。所述第一重佈線層包括第一雙鑲嵌重佈線圖案及第一晶種金屬圖案。所述第一雙鑲嵌重佈線圖案包括第一通孔部分及直接位於所述第一通孔部分上的第一佈線部分。所述第一晶種金屬圖案覆蓋所述第一佈線部分的側壁且覆蓋所述第一通孔部分的側壁及底表面。所述第二重佈線層設置在所述第一重佈線層上及所述第一晶粒的上方且與所述第一重佈線層及所述第一晶粒電連接。所述第二重佈線層包括第二雙鑲嵌重佈線圖案及第二晶種金屬圖案。所述第二雙鑲嵌重佈線圖案包括第二通孔部分及直接位於所述第二通孔部分上的第二佈線部分。所述第二晶種金屬圖案覆蓋所述第二佈線部分的側壁且覆蓋所述第二通孔部分的側壁及底表面。所述第二通孔部分的位置與第一通孔部分的位置對齊。According to some embodiments of the present disclosure, a semiconductor package is disclosed. The semiconductor package includes a first die, a first redistribution layer, and a second redistribution layer. The first redistribution layer is disposed above the first die and is electrically connected to the first die. The first redistribution layer includes a first dual damascene redistribution pattern and a first seed metal pattern. The first dual damascene redistribution pattern includes a first through-hole portion and a first wiring portion directly on the first through-hole portion. The first seed metal pattern covers a sidewall of the first wiring portion and covers a sidewall and a bottom surface of the first through-hole portion. The second redistribution layer is disposed on the first redistribution layer and above the first die and is electrically connected to the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern and a second seed metal pattern. The second dual damascene redistribution pattern includes a second through-hole portion and a second wiring portion directly on the second through-hole portion. The second seed metal pattern covers a sidewall of the second wiring portion and covers a sidewall and a bottom surface of the second through-hole portion. The position of the second through-hole portion is aligned with the position of the first through-hole portion.

根據本公開的一些實施例，一種半導體封裝包括至少一個晶粒、第一重佈線層、第二重佈線層及第三重佈線層。所述第一重佈線層設置在所述至少一個晶粒的上方且與所述至少一個晶粒電連接。所述第一重佈線層包括第一雙鑲嵌重佈線圖案及第一晶種金屬圖案，且所述第一雙鑲嵌重佈線圖案包括第一通孔部分及直接位於所述第一通孔部分上的第一佈線部分。所述第一晶種金屬圖案覆蓋所述第一佈線部分的側壁且覆蓋所述第一通孔部分的側壁及底表面。所述第二重佈線層設置在所述第一重佈線層上及所述至少一個晶粒的上方且與所述第一重佈線層及所述至少一個晶粒電連接。所述第二重佈線層包括第二雙鑲嵌重佈線圖案及第二晶種金屬圖案，且所述第二雙鑲嵌重佈線圖案包括第二通孔部分及直接位於所述第二通孔部分上的第二佈線部分。所述第二晶種金屬圖案覆蓋所述第二佈線部分的側壁且覆蓋所述第二通孔部分的側壁及底表面。所述第三重佈線層設置在所述第二重佈線層上及所述至少一個晶粒的上方且與所述第一重佈線層及所述第二重佈線層以及所述至少一個晶粒電連接。所述第三重佈線層包括第三雙鑲嵌重佈線圖案及第三晶種金屬圖案，且所述第三雙鑲嵌重佈線圖案包括第三通孔部分及第三佈線部分。所述第三晶種金屬圖案覆蓋所述第三佈線部分的底表面且覆蓋所述第三通孔部分的側壁及底表面。所述第一通孔部分、所述第二通孔部分及所述第三通孔部分垂直地堆疊在彼此的上方且垂直地彼此對齊。According to some embodiments of the present disclosure, a semiconductor package includes at least one die, a first redistribution layer, a second redistribution layer, and a third redistribution layer. The first redistribution layer is disposed above the at least one die and is electrically connected to the at least one die. The first redistribution layer includes a first dual-damascene redistribution pattern and a first seed metal pattern, and the first dual-damascene redistribution pattern includes a first through-hole portion and is located directly on the first through-hole portion. The first wiring section. The first seed metal pattern covers a sidewall of the first wiring portion and covers a sidewall and a bottom surface of the first through-hole portion. The second redistribution layer is disposed on the first redistribution layer and above the at least one die and is electrically connected to the first redistribution layer and the at least one die. The second redistribution layer includes a second dual-mosaic redistribution pattern and a second seed metal pattern, and the second dual-mosaic redistribution pattern includes a second through-hole portion and is located directly on the second through-hole portion. Second wiring section. The second seed metal pattern covers a sidewall of the second wiring portion and covers a sidewall and a bottom surface of the second through-hole portion. The third redistribution layer is disposed on the second redistribution layer and above the at least one die and is in contact with the first redistribution layer and the second redistribution layer and the at least one die. Electrical connection. The third rewiring layer includes a third dual damascene redistribution pattern and a third seed metal pattern, and the third dual damascene redistribution pattern includes a third through-hole portion and a third wiring portion. The third seed metal pattern covers a bottom surface of the third wiring portion and covers a side wall and a bottom surface of the third through-hole portion. The first through-hole portion, the second through-hole portion, and the third through-hole portion are vertically stacked above each other and vertically aligned with each other.

根據本公開的替代實施例，一種製作半導體封裝的方法包括至少以下步驟。提供基底。在所述基底的上方形成具有多個第一通孔開口的第一介電層。在所述第一介電層上形成具有多個第一溝渠開口的第二介電層。至少一個第一溝渠開口與所述多個第一通孔開口中的一個進行接合以在所述第一介電層及所述第二介電層中形成第一雙鑲嵌開口。在所述第二介電層的上方形成第一晶種金屬層，且所述第一晶種金屬層覆蓋所述第一雙鑲嵌開口。在所述第一晶種金屬層上形成填滿所述第一雙鑲嵌開口的第一金屬層。形成在所述第一雙鑲嵌開口中具有第一雙鑲嵌重佈線圖案的第一重佈線層。在所述第二介電層上形成具有多個第二通孔開口的第三介電層。所述第二通孔開口的位置相應地與所述第一通孔開口的位置對齊。在所述第三介電層上形成具有多個第二溝渠開口的第四介電層。至少一個第二溝渠開口與所述多個第二通孔開口中的一個進行接合以在所述第三介電層及所述第四介電層中形成第二雙鑲嵌開口。在所述第四介電層的上方形成第二晶種金屬層且所述第二晶種金屬層覆蓋所述第二雙鑲嵌開口。在所述第二晶種金屬層上形成填滿所述第二雙鑲嵌開口的第二金屬層。形成在所述第二雙鑲嵌開口中具有第二雙鑲嵌重佈線圖案的第二重佈線層。According to an alternative embodiment of the present disclosure, a method of manufacturing a semiconductor package includes at least the following steps. Provide a substrate. A first dielectric layer having a plurality of first through-hole openings is formed over the substrate. A second dielectric layer having a plurality of first trench openings is formed on the first dielectric layer. At least one first trench opening is joined with one of the plurality of first through-hole openings to form a first dual damascene opening in the first dielectric layer and the second dielectric layer. A first seed metal layer is formed over the second dielectric layer, and the first seed metal layer covers the first dual damascene opening. A first metal layer is formed on the first seed metal layer to fill the first double damascene opening. A first redistribution layer having a first double-damascene redistribution pattern is formed in the first double-damascene opening. A third dielectric layer having a plurality of second through-hole openings is formed on the second dielectric layer. The position of the second through-hole opening is correspondingly aligned with the position of the first through-hole opening. A fourth dielectric layer having a plurality of second trench openings is formed on the third dielectric layer. At least one second trench opening is bonded to one of the plurality of second through-hole openings to form a second dual damascene opening in the third dielectric layer and the fourth dielectric layer. A second seed metal layer is formed over the fourth dielectric layer, and the second seed metal layer covers the second dual damascene opening. A second metal layer is formed on the second seed metal layer to fill the second double damascene opening. A second redistribution layer having a second double damascene redistribution pattern is formed in the second double damascene opening.

雖然本發明實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明實施例的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the embodiments of the present invention are disclosed as above, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the embodiments of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

70‧‧‧子封裝70‧‧‧ sub package

100‧‧‧封裝結構100‧‧‧ package structure

102、302‧‧‧基底102, 302‧‧‧ substrate

104、204、304、512‧‧‧接觸件104, 204, 304, 512‧‧‧ contact

110‧‧‧第一介電層110‧‧‧first dielectric layer

110a‧‧‧經圖案化的第一介電層110a‧‧‧ patterned first dielectric layer

120‧‧‧第二介電層120‧‧‧Second dielectric layer

120a、131a、132a、140a、161a、162a、331a、332a‧‧‧頂表面120a, 131a, 132a, 140a, 161a, 162a, 331a, 332a‧‧‧ Top surface

125‧‧‧第一晶種金屬層125‧‧‧ first seed metal layer

126‧‧‧第一晶種金屬圖案126‧‧‧The first seed metal pattern

130‧‧‧第一金屬層130‧‧‧first metal layer

131、161‧‧‧雙鑲嵌重佈線圖案131, 161‧‧‧Double Mosaic Redistribution Pattern

132、162、332‧‧‧佈線重佈線圖案132, 162, 332 ‧‧‧ wiring redistribution pattern

133、163‧‧‧通孔部分133, 163‧‧‧through hole part

134、164‧‧‧佈線部分134、164‧‧‧Wiring section

135‧‧‧第一金屬重佈線圖案135‧‧‧The first metal redistribution pattern

140‧‧‧介電層140‧‧‧ Dielectric layer

156‧‧‧第二晶種金屬圖案156‧‧‧Second seed metal pattern

165‧‧‧第二金屬重佈線圖案165‧‧‧Second metal redistribution pattern

200、700、800、900‧‧‧封裝200, 700, 800, 900‧‧‧ package

202‧‧‧晶粒或晶片202‧‧‧ Die or Chip

202a‧‧‧基底表面202a‧‧‧ substrate surface

250、450‧‧‧保護層250, 450‧‧‧ protective layer

260、890、990‧‧‧導電球260, 890, 990‧‧‧ conductive ball

310‧‧‧第三介電層310‧‧‧Third dielectric layer

315‧‧‧第三晶種金屬層315‧‧‧ Third seed metal layer

316‧‧‧第三晶種金屬圖案316‧‧‧ Third seed metal pattern

320‧‧‧光阻圖案320‧‧‧Photoresist pattern

330‧‧‧第三金屬層330‧‧‧ Third metal layer

331‧‧‧重佈線圖案331‧‧‧ Redistribution pattern

340、340’‧‧‧第四介電層340, 340’‧‧‧ Fourth dielectric layer

400、500、600‧‧‧‧‧‧整合扇出型封裝400, 500, 600‧‧‧‧‧‧‧ Integrated Fan-Out Package

410、810、910‧‧‧第一晶粒410, 810, 910‧‧‧ first die

412‧‧‧第一接觸件412‧‧‧First contact

420、820、920‧‧‧第二晶粒420, 820, 920‧‧‧Second die

422‧‧‧第二接觸件422‧‧‧Second contact

430、530、630、830、930‧‧‧模塑化合物430, 530, 630, 830, 930 ‧ ‧ ‧ molding compounds

440、540、640、780、870、970‧‧‧導電元件440, 540, 640, 780, 870, 970‧‧‧ conductive elements

510、610、710‧‧‧晶粒510, 610, 710‧‧‧

510a‧‧‧晶粒頂表面510a‧‧‧ top surface of grain

520、620‧‧‧層間穿孔520、620‧‧‧‧Perforation between layers

550、650‧‧‧背側重佈線結構550, 650‧‧‧back side wiring structure

552、652‧‧‧佈線線552, 652‧‧‧ wiring

554‧‧‧穿孔554‧‧‧perforation

615、815、825、915、925‧‧‧凸塊615, 815, 825, 915, 925‧‧‧ bumps

618‧‧‧底部填充膠618‧‧‧ underfill

760‧‧‧電路板層壓板760‧‧‧Circuit board laminate

762‧‧‧導電插塞762‧‧‧Conductive plug

850、950‧‧‧內連結構850, 950‧‧‧ interconnected structure

860‧‧‧中介層860‧‧‧Intermediary

865‧‧‧中介層穿孔865‧‧‧ interposer perforation

880、980‧‧‧電路基底880, 980‧‧‧Circuit base

BP‧‧‧背保護層BP‧‧‧back protective layer

d1、d2‧‧‧深度d1, d2‧‧‧ depth

DP1、DP2、DP3‧‧‧雙鑲嵌重佈線圖案DP1, DP2, DP3 ‧‧‧ Dual Mosaic Redistribution Pattern

DS1、DS2‧‧‧雙鑲嵌開口DS1, DS2‧‧‧‧Double mosaic opening

DS3‧‧‧開口DS3‧‧‧ opening

FP‧‧‧前保護層FP‧‧‧ Front Cover

k1、k2‧‧‧底部大小k1, k2‧‧‧ bottom size

RDL1‧‧‧第一重佈線層RDL1‧‧‧First Redistribution Layer

RDL2‧‧‧第二重佈線層RDL2‧‧‧Second Redistribution Layer

RDL3‧‧‧第三重佈線層RDL3‧‧‧Third wiring layer

TS1、TS2、TS3‧‧‧溝渠開口Trench openings TS1, TS2, TS3

VP1、VP2、VP3‧‧‧通孔部分VP1, VP2, VP3 ‧‧‧ through hole part

VS1、VS2、VS3‧‧‧通孔開口VS1, VS2, VS3‧‧‧through hole opening

x‧‧‧水平方向x‧‧‧ horizontal direction

z‧‧‧厚度方向z‧‧‧ thickness direction

根據以下的詳細說明並配合所附圖式以了解本發明實施例。應注意的是，根據本產業的一般作業，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A到圖1G是根據一些實施例示意性地示出根據製作半導體封裝的方法來形成重佈線層的製程的各個階段。 圖2是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖3A到圖3D是根據一些實施例示意性地示出根據製作半導體封裝的方法來形成另一個重佈線層的製程的各個階段。 圖3D’是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝的剖視圖。 圖4是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖5是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖6是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖7是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖8是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。 圖9是根據一些實施例示意性地示出具有多個重佈線層的半導體封裝。To understand the embodiments of the present invention according to the following detailed description and the accompanying drawings. It should be noted that according to the general operations of the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. 1A to 1G are schematic diagrams illustrating various stages of a process of forming a redistribution layer according to a method of fabricating a semiconductor package according to some embodiments. FIG. 2 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. 3A to 3D are schematic diagrams illustrating various stages of a process of forming another redistribution layer according to a method of fabricating a semiconductor package according to some embodiments. FIG. 3D 'is a cross-sectional view schematically showing a semiconductor package having a plurality of redistribution layers according to some embodiments. FIG. 4 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. FIG. 5 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. FIG. 6 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. FIG. 7 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. FIG. 8 is a semiconductor package having a plurality of redistribution layers, according to some embodiments. FIG. 9 is a semiconductor package having a plurality of rewiring layers, according to some embodiments.

Claims (20)

一種半導體封裝，包括： 第一晶粒； 第一重佈線層，設置在所述第一晶粒的上方且與所述第一晶粒電連接，其中所述第一重佈線層包括第一雙鑲嵌重佈線圖案及第一晶種金屬圖案，所述第一雙鑲嵌重佈線圖案包括第一通孔部分及直接位於所述第一通孔部分上的第一佈線部分，且所述第一晶種金屬圖案覆蓋所述第一佈線部分的側壁且覆蓋所述第一通孔部分的側壁及底表面；以及 第二重佈線層，設置在所述第一重佈線層上及所述第一晶粒的上方且與所述第一重佈線層及所述第一晶粒電連接，其中所述第二重佈線層包括第二雙鑲嵌重佈線圖案及第二晶種金屬圖案，所述第二雙鑲嵌重佈線圖案包括第二通孔部分及直接位於所述第二通孔部分上的第二佈線部分，且所述第二晶種金屬圖案覆蓋所述第二佈線部分的側壁且覆蓋所述第二通孔部分的側壁及底表面， 其中所述第二通孔部分的位置與所述第一通孔部分的位置對齊。A semiconductor package includes: a first die; a first redistribution layer disposed above the first die and electrically connected to the first die, wherein the first redistribution layer includes a first double A damascene redistribution pattern and a first seed metal pattern, the first dual damascene redistribution pattern includes a first through-hole portion and a first wiring portion directly on the first through-hole portion, and the first crystal A metal pattern covering a sidewall of the first wiring portion and covering a sidewall and a bottom surface of the first through-hole portion; and a second redistribution layer disposed on the first redistribution layer and the first crystal And is electrically connected to the first redistribution layer and the first die, wherein the second redistribution layer includes a second dual damascene redistribution pattern and a second seed metal pattern, and the second The dual damascene redistribution pattern includes a second through-hole portion and a second wiring portion directly on the second through-hole portion, and the second seed metal pattern covers a sidewall of the second wiring portion and covers the second wiring portion. Side wall and bottom surface of the second through hole portion Wherein the position of the second through hole portion is aligned with the position of the first through hole portion. 如申請專利範圍第1項所述的半導體封裝，其中所述第二雙鑲嵌重佈線圖案直接位於所述第一雙鑲嵌重佈線圖案上，且所述第二晶種金屬圖案接觸所述第一重佈線層的所述第一雙鑲嵌重佈線圖案。The semiconductor package according to item 1 of the scope of patent application, wherein the second dual damascene redistribution pattern is directly located on the first dual damascene redistribution pattern, and the second seed metal pattern contacts the first The first dual damascene redistribution pattern of a redistribution layer. 如申請專利範圍第1項所述的半導體封裝，其中所述第二通孔部分的正交投影與所述第一通孔部分的正交投影完全重疊。The semiconductor package according to item 1 of the scope of patent application, wherein the orthogonal projection of the second through-hole portion and the orthogonal projection of the first through-hole portion completely overlap. 如申請專利範圍第1項所述的半導體封裝，其中所述第一通孔部分的底部大小大於所述第二通孔部分的底部大小，且所述第一通孔部分的正交投影與所述第二通孔部分的正交投影以同心方式彼此重疊。The semiconductor package according to item 1 of the patent application scope, wherein a bottom size of the first via portion is larger than a bottom size of the second via portion, and an orthogonal projection of the first via portion and the The orthogonal projections of the second through-hole portions overlap each other in a concentric manner. 如申請專利範圍第1項所述的半導體封裝，更包括包封所述第一晶粒的模塑化合物，其中所述第一重佈線層及所述第二重佈線層位於所述模塑化合物的第一側上。The semiconductor package according to item 1 of the scope of patent application, further comprising a molding compound that encapsulates the first die, wherein the first redistribution layer and the second redistribution layer are located in the molding compound. On the first side. 如申請專利範圍第5項所述的半導體封裝，更包括位於所述模塑化合物中的多個層間穿孔及位於所述模塑化合物第二側上的背側重佈線結構，所述第二側與所述第一側相對，其中所述多個層間穿孔穿透過所述模塑化合物且與所述背側重佈線結構連接。The semiconductor package according to item 5 of the scope of patent application, further comprising a plurality of interlayer vias located in the molding compound and a backside heavy wiring structure on a second side of the molding compound, the second side and The first side is opposite, wherein the plurality of interlayer vias penetrate the molding compound and are connected to the backside redistribution structure. 如申請專利範圍第5項所述的半導體封裝，更包括包封在所述模塑化合物中的第二晶粒及位於所述模塑化合物與所述第一重佈線層之間及所述模塑化合物與所述第二重佈線層之間的內連結構。The semiconductor package according to item 5 of the scope of patent application, further comprising a second die encapsulated in the molding compound and located between the molding compound and the first redistribution layer and the mold An interconnect structure between the plastic compound and the second redistribution layer. 如申請專利範圍第7項所述的半導體封裝，更包括中介層及位於所述中介層中的多個中介層穿孔，其中所述中介層及所述多個中介層穿孔位於所述內連結構與所述第一重佈線層之間及所述內連結構與所述第二重佈線層之間。The semiconductor package according to item 7 of the scope of patent application, further comprising an interposer and a plurality of interposer perforations located in the interposer, wherein the interposer and the plurality of interposer perforations are located in the interconnect structure. With the first redistribution layer and between the interconnect structure and the second redistribution layer. 如申請專利範圍第1項所述的半導體封裝，更包括位於所述第二重佈線層上的第三重佈線層，其中所述第三重佈線層包括第三雙鑲嵌重佈線圖案，所述第三雙鑲嵌重佈線圖案具有第三通孔部分，且所述第三通孔部分的位置與所述第一通孔部分的所述位置及所述第二通孔部分的所述位置對齊。The semiconductor package according to item 1 of the scope of patent application, further comprising a third redistribution layer on the second redistribution layer, wherein the third redistribution layer includes a third dual damascene redistribution pattern, and The third dual damascene redistribution pattern has a third through-hole portion, and a position of the third through-hole portion is aligned with the position of the first through-hole portion and the position of the second through-hole portion. 一種半導體封裝，包括： 至少一個晶粒； 第一重佈線層，設置在所述至少一個晶粒的上方且與所述至少一個晶粒電連接，其中所述第一重佈線層包括第一雙鑲嵌重佈線圖案及第一晶種金屬圖案，所述第一雙鑲嵌重佈線圖案包括第一通孔部分及直接位於所述第一通孔部分上的第一佈線部分，且所述第一晶種金屬圖案覆蓋所述第一佈線部分的側壁且覆蓋所述第一通孔部分的側壁及底表面； 第二重佈線層，設置在所述第一重佈線層上及所述至少一個晶粒的上方且與所述第一重佈線層及所述至少一個晶粒電連接，其中所述第二重佈線層包括第二雙鑲嵌重佈線圖案及第二晶種金屬圖案，所述第二雙鑲嵌重佈線圖案包括第二通孔部分及直接位於所述第二通孔部分上的第二佈線部分，且所述第二晶種金屬圖案覆蓋所述第二佈線部分的側壁且覆蓋所述第二通孔部分的側壁及底表面；以及 第三重佈線層，設置在所述第二重佈線層上及所述至少一個晶粒的上方且與所述第一重佈線層及所述第二重佈線層以及所述至少一個晶粒電連接，其中所述第三重佈線層包括第三雙鑲嵌重佈線圖案及第三晶種金屬圖案，所述第三雙鑲嵌重佈線圖案包括第三通孔部分及第三佈線部分，且所述第三晶種金屬圖案覆蓋所述第三佈線部分的底表面且覆蓋所述第三通孔部分的側壁及底表面， 其中所述第一通孔部分、所述第二通孔部分及所述第三通孔部分垂直地堆疊在彼此的上方且垂直地彼此對齊。A semiconductor package includes: at least one die; a first redistribution layer disposed above the at least one die and electrically connected to the at least one die, wherein the first redistribution layer includes a first double A damascene redistribution pattern and a first seed metal pattern, the first dual damascene redistribution pattern includes a first through-hole portion and a first wiring portion directly on the first through-hole portion, and the first crystal A metal pattern covers a sidewall of the first wiring portion and covers a sidewall and a bottom surface of the first through-hole portion; a second redistribution layer disposed on the first redistribution layer and the at least one die And is electrically connected to the first redistribution layer and the at least one die, wherein the second redistribution layer includes a second dual damascene redistribution pattern and a second seed metal pattern, and the second dual The damascene redistribution pattern includes a second through-hole portion and a second wiring portion directly on the second through-hole portion, and the second seed metal pattern covers a sidewall of the second wiring portion and covers the first Two through hole A side wall and a bottom surface; and a third redistribution layer, which is disposed on the second redistribution layer and above the at least one die and is in communication with the first redistribution layer and the second redistribution layer and The at least one die is electrically connected, wherein the third redistribution layer includes a third dual damascene redistribution pattern and a third seed metal pattern, and the third dual damascene redistribution pattern includes a third through-hole portion and a third Three wiring portions, and the third seed metal pattern covers a bottom surface of the third wiring portion and covers a sidewall and a bottom surface of the third through-hole portion, wherein the first through-hole portion, the first through-hole portion, The two through-hole portions and the third through-hole portion are vertically stacked above each other and vertically aligned with each other. 如申請專利範圍第10項所述的半導體封裝，其中所述第二通孔部分的正交投影與所述第一通孔部分的正交投影重疊，且所述第三通孔部分的正交投影與所述第二通孔部分的所述正交投影重疊。The semiconductor package according to claim 10, wherein the orthogonal projection of the second through-hole portion overlaps with the orthogonal projection of the first through-hole portion, and the orthogonality of the third through-hole portion is orthogonal. The projection overlaps the orthogonal projection of the second through-hole portion. 如申請專利範圍第10項所述的半導體封裝，其中所述第一通孔部分的底部大小實質上等於所述第二通孔部分的底部大小，且所述第一通孔部分的正交投影與所述第二通孔部分的正交投影以同心方式彼此重疊。The semiconductor package according to claim 10, wherein a bottom size of the first through-hole portion is substantially equal to a bottom size of the second through-hole portion, and an orthogonal projection of the first through-hole portion An orthogonal projection with the second through-hole portion overlaps each other in a concentric manner. 如申請專利範圍第10項所述的半導體封裝，更包括包封所述至少一個晶粒的模塑化合物，其中所述第一重佈線層及所述第二重佈線層位於所述模塑化合物的第一側上。The semiconductor package according to claim 10, further comprising a molding compound that encapsulates the at least one die, wherein the first redistribution layer and the second redistribution layer are located in the molding compound. On the first side. 如申請專利範圍第13項所述的半導體封裝，更包括位於所述模塑化合物中的多個層間穿孔及位於所述模塑化合物第二側上的背側重佈線結構，所述第二側與所述第一側相對，其中所述多個層間穿孔穿透過所述模塑化合物且與所述背側重佈線結構連接。The semiconductor package according to item 13 of the scope of patent application, further comprising a plurality of interlayer vias located in the molding compound and a backside heavy wiring structure on a second side of the molding compound, the second side and the The first side is opposite, wherein the plurality of interlayer vias penetrate the molding compound and are connected to the backside redistribution structure. 一種半導體封裝的製造方法，包括： 提供基底； 在所述基底的上方形成具有多個第一通孔開口的第一介電層； 在所述第一介電層上形成具有多個第一溝渠開口的第二介電層，其中所述多個第一溝渠開口中的至少一個第一溝渠開口與所述多個第一通孔開口的一個第一通孔開口進行接合以在所述第一介電層及所述第二介電層中形成第一雙鑲嵌開口； 在所述第二介電層的上方形成覆蓋所述第一雙鑲嵌開口的第一晶種金屬層； 在所述第一晶種金屬層上形成填滿所述第一雙鑲嵌開口的第一金屬層； 形成在所述第一雙鑲嵌開口中具有第一雙鑲嵌重佈線圖案的第一重佈線層； 在所述第二介電層上形成具有多個第二通孔開口的第三介電層，其中所述多個第二通孔開口的位置與所述多個第一通孔開口的位置對應地對齊； 在所述第三介電層上形成具有多個第二溝渠開口的第四介電層，其中所述多個第二溝渠開口中的至少一個第二溝渠開口與所述多個第二通孔開口的一個第二通孔開口進行接合以在所述第三介電層及所述第四介電層中形成第二雙鑲嵌開口； 在所述第四介電層的上方形成覆蓋所述第二雙鑲嵌開口的第二晶種金屬層； 在所述第二晶種金屬層上形成填滿所述第二雙鑲嵌開口的第二金屬層；以及 形成在所述第二雙鑲嵌開口中具有第二雙鑲嵌重佈線圖案的第二重佈線層。A method for manufacturing a semiconductor package includes: providing a substrate; forming a first dielectric layer having a plurality of first through-hole openings over the substrate; and forming a plurality of first trenches on the first dielectric layer An opened second dielectric layer, wherein at least one first trench opening in the plurality of first trench openings is joined with one first through-hole opening of the plurality of first through-hole openings in the first Forming a first double damascene opening in the dielectric layer and the second dielectric layer; forming a first seed metal layer over the second dielectric layer to cover the first double damascene opening; in the first Forming a first metal layer on the seed metal layer to fill the first double damascene opening; forming a first redistribution layer having a first double damascene redistribution pattern in the first double damascene opening; and Forming a third dielectric layer having a plurality of second through-hole openings on the second dielectric layer, wherein the positions of the plurality of second through-hole openings are aligned corresponding to the positions of the plurality of first through-hole openings; Forming a plurality of second trenches on the third dielectric layer An opened fourth dielectric layer, wherein at least one second trench opening of the plurality of second trench openings is joined with one second through-hole opening of the plurality of second through-hole openings in the third Forming a second double damascene opening in the dielectric layer and the fourth dielectric layer; forming a second seed metal layer over the fourth dielectric layer to cover the second double damascene opening; in the first A second seed metal layer is formed on the second seed metal layer to fill the second double damascene opening; and a second redistribution layer having a second double damascene redistribution pattern is formed in the second double damascene opening. 如申請專利範圍第15項所述的方法，其中形成在所述第一雙鑲嵌開口中具有第一雙鑲嵌重佈線圖案的第一重佈線層包括：執行第一平坦化工藝以移除位於所述第一雙鑲嵌開口外的所述第一金屬層及所述第一晶種金屬層，從而形成夾置在所述第一雙鑲嵌開口與填滿所述第一雙鑲嵌開口的所述第一重佈線圖案之間的第一晶種金屬圖案。The method of claim 15, wherein forming a first redistribution layer having a first double damascene redistribution pattern in the first double damascene opening comprises: performing a first planarization process to remove The first metal layer and the first seed metal layer outside the first double mosaic opening, thereby forming the first double mosaic opening and the first double mosaic opening filling the first double mosaic opening The first seed metal pattern between the double wiring patterns. 如申請專利範圍第15項所述的方法，其中形成在所述第二雙鑲嵌開口中具有第二雙鑲嵌重佈線圖案的第二重佈線層包括：執行第二平坦化工藝以移除位於所述第二雙鑲嵌開口外的所述第二金屬層及所述第二晶種金屬層，從而形成夾置在所述第二雙鑲嵌開口與填滿所述第二雙鑲嵌開口的所述第二重佈線圖案之間的第二晶種金屬圖案。The method of claim 15, wherein forming a second redistribution layer having a second double damascene redistribution pattern in the second double damascene opening includes performing a second planarization process to remove the second redistribution pattern. The second metal layer and the second seed metal layer outside the second double-mosaic opening form a first sandwiched between the second double-mosaic opening and the first double-mosaic opening. A second seed metal pattern between the double wiring patterns. 如申請專利範圍第16項所述的方法，更包括形成多個層間穿孔且在所述第二重佈線層的上方設置至少一個晶粒，其中所述多個層間穿孔及所述至少一個晶粒與所述第一重佈線層及所述第二重佈線層電連接。The method according to item 16 of the scope of patent application, further comprising forming a plurality of interlayer vias and setting at least one die above the second redistribution layer, wherein the plurality of interlayer vias and the at least one die It is electrically connected to the first redistribution layer and the second redistribution layer. 如申請專利範圍第18項所述的方法，更包括形成包封所述至少一個晶粒及所述多個層間穿孔的模塑化合物。The method of claim 18, further comprising forming a molding compound that encapsulates the at least one die and the plurality of interlayer perforations. 如申請專利範圍第18項所述的方法，更包括在所述第一重佈線層的上方設置多個導電元件。The method according to item 18 of the scope of patent application, further comprising disposing a plurality of conductive elements above the first redistribution layer.
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