TW201901680A - Flash memory storage apparatus - Google Patents

Abstract

A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes includes a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.

Description

Flash memory storage device

The present invention relates to a memory storage device, and more particularly to a flash memory storage device.

With the evolution of electronic technology, electronic devices have become a necessary tool in people's lives. In order to provide long-lasting and large-scale data storage functions, non-volatile memory has become an important data storage medium. Also, in today's electronic products, flash memory is one of the more popular non-volatile memories. The operation modes of the flash memory storage device mainly include an active mode, a normal standby mode, and a deep power down mode.

In the prior art, the flash memory storage device needs to receive an instruction to enter the deep power saving mode. The dynamic operation of the flash memory storage device entering the deep power saving mode is stopped, and the advantage is that the current consumed is very low, but the flash memory storage device that wakes up into the deep power saving mode usually takes a considerable amount of time. time. The time spent is usually used to restore the circuit settings inside the flash memory storage device.

On the other hand, although the flash memory storage device in the normal standby mode consumes a higher current, its wake-up time is shorter. The current consumed by the flash memory storage device in normal standby mode is typically due to the fact that in this mode, the voltage generator circuit still needs to operate to provide a high voltage to the word line decoder circuit. Therefore, the current consumed by the flash memory storage device in the normal standby mode cannot be effectively reduced.

The present invention provides a flash memory storage device that operates in a low standby current mode with a small standby current and a short wake-up time.

The flash memory storage device of the present invention has a variety of modes of operation. The flash memory storage device includes a memory control circuit and a memory cell array. The memory control circuit is used to control the operation of the flash memory storage device in one of a plurality of operating modes. The mode of operation includes a low standby current mode. The memory cell array is coupled to the memory control circuit. A memory cell array is used to store data. The information includes read-only memory data. The memory control circuit controls the flash memory storage device to enter a low standby current mode according to the first command. The memory control circuit wakes up the flash memory storage device from the low standby current mode according to the second command. When the flash memory storage device operates in the low standby current mode, read-only memory data (ROM data) is held.

The flash memory storage device of the present invention has a variety of modes of operation. The flash memory storage device includes a memory control circuit and a memory cell array. The memory control circuit is used to control the operation of the flash memory storage device in one of a plurality of operating modes. The mode of operation includes a low standby current mode. The memory cell array is coupled to the memory control circuit. A memory cell array is used to store data. The information includes read-only memory data. The memory control circuit controls the flash memory storage device to enter a low standby current mode according to the first command. The memory control circuit wakes up the flash memory storage device from the low standby current mode according to the second command. The operation modes include a normal standby mode and a deep power saving mode. The flash memory storage device operates in the low standby current mode, the normal standby mode, and the deep power saving mode, respectively having a first current, a second current, and a third current. The first current is less than the second current and greater than the third current.

Based on the above, in an exemplary embodiment of the invention, the flash memory storage device controls entry into or exit of the low standby current mode in accordance with the instructions. And the read-only memory data is maintained while the flash memory storage device is operating in the low standby current mode. Therefore, when the flash memory storage device operates in the low standby current mode, its standby current is small and the wake-up time is short.

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the invention. Referring to FIG. 1 , the flash memory storage device 100 of the present embodiment includes a memory control circuit 110 and a memory cell array 120 . The memory cell array 120 is coupled to the memory control circuit 110. The memory control circuit 110 is configured to control the flash memory storage device 100 to operate in one of a plurality of operating modes. The memory cell array 120 is used to store data. In the embodiment, the operation modes of the flash memory storage device 100 include a low standby current mode, a normal standby mode, and a deep power saving mode.

In the present embodiment, the memory control circuit 110 controls the flash memory storage device 100 to operate the deep power saving mode to further reduce the standby current when the memory control circuit 110 operates in the normal standby mode. In the deep power saving mode, the manner of reducing the standby current is, for example, turning off various operations of the flash memory storage device 100 in the normal standby mode, or blocking by a power blocking scheme. A power source required for operation of each component in the flash memory storage device 100. In this embodiment, the memory control circuit 110 controls the flash memory storage device 100 to enter the deep power saving mode according to the deep power saving command, and controls the flash memory storage device 100 to leave the deep power saving mode according to the wake-up command. Enter normal standby mode.

Therefore, in the present embodiment, the flash memory storage device 100 operates in a normal standby mode (second current) greater than a current operating in a deep power saving mode (third current). In the present embodiment, the time (second wake-up time) at which the flash memory storage device 100 is woken up from the normal standby mode is shorter than the time (third wake-up time) that is awakened from the deep power saving mode. In this embodiment, the operation mode of the flash memory storage device 100 further includes a low standby current mode. The standby current (first current) of the low standby current mode is less than the second current and greater than the third current. The wake-up time (first wake-up time) of the low standby current mode is longer than the second wake-up time and shorter than the third wake-up time. A number of embodiments are set forth below to illustrate the low standby current mode of the present invention.

In this embodiment, the circuit architecture of the memory controller circuit 110 and the memory cell array 120 can be implemented by any suitable circuit in the art, and the invention is not limited thereto. The detailed steps and implementations thereof may be adequately taught, suggested, and implemented by the ordinary knowledge in the art, and therefore will not be described again.

2 is a schematic diagram showing a word line decoder circuit and a voltage generator circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation signals of the embodiment of FIG. 2. Referring to FIG. 1 to FIG. 3 , the flash memory storage device 100 of FIG. 1 further includes a voltage generator circuit 200 and a word line decoder circuit 300 . In the present embodiment, the word line decoder circuit 300 is coupled to one or more word lines WL of the flash memory storage device 100. The voltage generator circuit 200 is coupled to the word line decoder circuit 300. The voltage generator circuit 200 is operative to provide a high voltage to the word line decoder circuit 300 via the node HV as a power source required for operation. In Figure 3, the signal labeled HV refers to the voltage signal at node HV.

Specifically, in the present embodiment, the voltage generator circuit 200 includes a clock generator 210, a charge pump 220, a reference voltage generator 230, and a voltage regulator 240. The reference voltage generator 230 is coupled to the first voltage VP via the first transistor switch Q1, and the voltage regulator 240 is coupled to the second voltage VSS via the second transistor switch Q2. The clock generator 210 includes a third transistor switch (not shown). The node HV is coupled to the second voltage VSS via the fourth transistor switch Q4. In this embodiment, the clock generator 210 is configured to generate a clock signal to the charge bar 220. The charge beam 220 generates a voltage signal according to the clock signal, and outputs a voltage signal to the voltage regulator 240. The reference voltage generator 230 is configured to generate a reference voltage signal and output a reference voltage signal to the voltage regulator 240. The voltage regulator 240 generates the high voltage according to the reference voltage signal and the voltage signal, and outputs the high voltage to the word line decoder circuit 300.

In this embodiment, the memory control circuit 110 controls the flash memory storage device 100 to enter the low standby current mode according to the first command CMD1. The memory control circuit 110 wakes up the flash memory storage device 100 according to the second command CMD2, and enters the normal standby mode from the low standby current mode. In this embodiment, when the flash memory storage device 100 enters the low standby current mode, the control signal Vctrl is pulled high to a high level. When the flash memory storage device 100 leaves the low standby current mode, the control signal Vctrl is lowered to a low level. In the low standby current mode, the high level control signal Vctrl does not turn on the first transistor switch Q1, the second transistor switch Q2, and the third transistor switch in the clock generator 210. Therefore, the power source required for the voltage generator circuit 200 to operate, such as the first voltage VP and the second voltage VSS, is blocked from being supplied to the circuit elements therein, thereby the clock generator 210, the charge bar 220, and the reference voltage. Generator 230 and voltage regulator 240 cease operation. In addition, in the low standby current mode, the fourth transistor switch Q4 is turned on according to the control signal Vctrl, so the voltage of the node HV is pulled down to the second voltage VSS to further reduce the power consumption of the word line decoder circuit. Therefore, in the present embodiment, the flash memory storage device 100 operates in a low standby current mode (first current) less than a current operating in a normal standby mode (second current). In Figure 2, marked as The signal is the inverted signal of the control signal Vctrl.

In this embodiment, the data stored in the memory cell array 120 includes read-only memory data, such as programmable read-only memory data (PROM data). When the flash memory storage device 100 is operating in the low standby current mode, the read only memory data is held, for example, in a volatile memory. Therefore, when the flash memory storage device 100 is awake from the low standby current mode to the normal standby mode or the normal operation mode, the read-only memory data does not need to be reloaded into the volatile memory, so the wake-up time tLSTB is short. In the present embodiment, in the deep power saving mode, the read-only memory data is not retained. Therefore, when the flash memory storage device 100 is woken up, its read-only memory data needs to be reloaded into the volatile memory so that its wake-up time is long. Therefore, in the present embodiment, the time (the first wake-up time) at which the flash memory storage device 100 is woken up from the low standby current mode is shorter than the time (the third wake-up time) that is awakened from the deep power saving mode.

In the present embodiment, the circuit architectures of the voltage generator circuit 200 and the word line decoder circuit 300 can be implemented by any suitable circuit in the art, and the invention is not limited thereto. The detailed steps and implementations thereof may be adequately taught, suggested, and implemented by the ordinary knowledge in the art, and therefore will not be described again.

4 is a schematic diagram showing a word line decoder circuit and a voltage generator circuit according to another embodiment of the present invention. FIG. 5 is a schematic diagram showing the operation signals of the embodiment of FIG. 4. Referring to FIG. 2 to FIG. 5, the word line decoder circuit and the voltage generator circuit of this embodiment are similar to the embodiment of FIG. 2, but the main difference between the two is, for example, that the node HV is not coupled to the via transistor switch. The second voltage VSS. In the present embodiment, in the low standby current mode, the voltage of the node HV is floated, and thus pulled down to the second voltage VSS at a slower speed. In addition, the operation method of the memory storage device of the embodiment of the present invention can be sufficiently taught, suggested, and implemented by the description of the embodiment of FIG. 1 to FIG. 3, and therefore will not be described again.

In summary, in an exemplary embodiment of the invention, the operating mode of the flash memory storage device includes a low standby current mode. The flash memory storage device operates in a low standby current mode with a standby current that is smaller than a standby current operating in a normal standby mode. The flash memory storage device returns to the normal standby mode according to the instruction to enter the low standby current mode or leave the low standby current mode. The flash memory storage device is awakened from a low standby current mode for a shorter time than a deep power save mode.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Flash memory storage device

110‧‧‧Memory Control Circuit

120‧‧‧Memory cell array

200‧‧‧Voltage generator circuit

210‧‧‧ clock generator

220‧‧‧ Charge Lei

230‧‧‧reference voltage generator

240‧‧‧Voltage regulator

300‧‧‧word line decoder circuit

WL‧‧‧ character line

HV‧‧‧ node, node voltage signal

Q1, Q2, Q4‧‧‧ transistor switch

VP‧‧‧First voltage

VSS‧‧‧second voltage

Vctrl‧‧‧ control signal

‧‧‧Inverted signal of control signal

CMD1‧‧‧ first instruction

CMD2‧‧‧ second instruction

tLSTB‧‧‧Wake time

FIG. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing a word line decoder circuit and a voltage generator circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation signals of the embodiment of FIG. 2. 4 is a schematic diagram showing a word line decoder circuit and a voltage generator circuit according to another embodiment of the present invention. FIG. 5 is a schematic diagram showing the operation signals of the embodiment of FIG. 4.

Claims (10)

A flash memory storage device having a plurality of operation modes, and the flash memory storage device includes: a memory control circuit for controlling operation of the flash memory storage device in one of the operation modes, wherein The operating modes include a low standby current mode, and a memory cell array coupled to the memory control circuit for storing data, the data including read-only memory data, wherein the memory control circuit is based on a The first command controls the flash memory storage device to enter the low standby current mode, and wakes up the flash memory storage device from the low standby current mode according to the second instruction, wherein the flash memory storage device operates at the low The read-only memory data is held in the standby current mode. The flash memory storage device of claim 1, wherein the operation modes include a normal standby mode and a deep power saving mode, and the flash memory storage device operates in the low standby current mode, The normal standby mode and the deep power saving mode respectively have a first current, a second current, and a third current, wherein the first current is less than the second current and greater than the third current. The flash memory storage device of claim 1, wherein the operation modes include a normal standby mode and a deep power saving mode, and the flash memory storage device is from the low standby current mode, The normal standby mode and the deep power saving mode are respectively required to wake up, a second wake-up time, and a third wake-up time, wherein the first wake-up time is longer than the second wake-up time and shorter than the third wake-up time time. The flash memory storage device of claim 1, further comprising: a word line decoder circuit coupled to the plurality of word lines of the flash memory storage device; and a voltage generator a circuit coupled to the word line decoder circuit for providing a high voltage to the word line decoder circuit via a node, wherein the plurality of transistors in the voltage generator circuit are in the low standby current mode The switch is not conductive according to a control signal. The flash memory storage device of claim 4, wherein the voltage generator circuit comprises a clock generator, a reference voltage generator, and a voltage regulator, and the reference voltage generator is first The transistor switch is coupled to a first voltage, the voltage regulator is coupled to a second voltage via a second transistor switch, and the clock generator includes a third transistor switch, wherein the low standby current In the mode, the first transistor switch, the second transistor switch, and the third transistor switch are not turned on according to the control signal. The flash memory storage device of claim 5, wherein the node is coupled to the second voltage via a fourth transistor switch, and in the low standby current mode, the fourth transistor switch is The control signal is turned on to pull the voltage of the node to the second voltage. The flash memory storage device of claim 4, wherein the node is floated in the low standby current mode. A flash memory storage device having a plurality of operation modes, and the flash memory storage device includes: a memory control circuit for controlling operation of the flash memory storage device in one of the operation modes, wherein The operating modes include a low standby current mode, and a memory cell array coupled to the memory control circuit for storing data, the data including read-only memory data, wherein the memory control circuit is based on a The first command controls the flash memory storage device to enter the low standby current mode, and wakes up the flash memory storage device from the low standby current mode according to the second instruction, wherein the operation modes include a normal standby mode and a a deep power saving mode, wherein the flash memory storage device operates in the low standby current mode, the normal standby mode, and the deep power saving mode respectively have a first current, a second current, and a third current, wherein the current The first current is less than the second current and greater than the third current. The flash memory storage device of claim 8, further comprising: a word line decoder circuit coupled to the plurality of word lines of the flash memory storage device; and a voltage generator a circuit coupled to the word line decoder circuit for providing a high voltage to the word line decoder circuit via a node, wherein the plurality of transistors in the voltage generator circuit are in the low standby current mode The switch is not conductive according to a control signal. The flash memory storage device of claim 9, wherein the voltage generator circuit comprises a clock generator, a reference voltage generator, and a voltage regulator, and the reference voltage generator is first The transistor switch is coupled to a first voltage, the voltage regulator is coupled to a second voltage via a second transistor switch, and the clock generator includes a third transistor switch, wherein the low standby current In the mode, the first transistor switch, the second transistor switch, and the third transistor switch are not turned on according to the control signal.