TW201841339A - Integrated circuit having contact jumper and semiconductor device - Google Patents

Abstract

An integrated circuit and a semiconductor device are disclosed. The integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Description

Integrated circuit and semiconductor device with contact window jumper

The inventive concept relates to an integrated circuit, and more particularly to a standard unit, a standard cell library including a standard unit, an integrated circuit, and a computer implementation method for designing an integrated circuit and A computing system. [Cross-reference to related applications]

This application claims the Korean Patent Application No. 10-2017-0017676 filed on February 8, 2017 in the Korea Intellectual Property Office and the Korean Patent Application filed in the Korea Intellectual Property Office on June 28, 2017. The benefit of the present application is incorporated herein by reference in its entirety.

The design of the integrated circuit can be based on standard cells. Specifically, the layout of the integrated circuit can be generated by arranging standard cells (standard cell "configuration") defining the integrated circuit and routing the standard cells. As the design rules of the semiconductor process become smaller, the layout of the layout such as the pattern size can be made smaller to satisfy the design rule. In particular, in an example of an integrated circuit including fins such as finFETs, the pitch of the fins may have to be reduced, resulting in a smaller footprint in the active area in the standard cell. Therefore, the "height" of the standard cell (the size of the standard cell in the layout) is reduced.

According to one aspect of the inventive concept, an integrated circuit includes a first active region and a second active region, a first gate line, and a first contact window jumper. The first active region and the second active region respectively extend in the first direction; the first gate line extends longitudinally across the first active region and the second active region in a second direction substantially perpendicular to the first direction; A contact window jumper includes a first conductive pattern and a second conductive pattern, the first conductive pattern crossing the first gate line above the first active region, and the second conductive pattern is above the first gate line in the second direction The upper portion extends longitudinally and is connected to the first conductive pattern.

According to another aspect of the inventive concept, an integrated circuit includes a first active region and a second active region, a first gate line and a second gate line, and a first contact window jumper. The first active region and the second active region respectively extend in the first direction; the first gate line and the second gate line are separated from each other in the first direction, and each of the first gate line and the second gate line One extends longitudinally across the first active region and the second active region in a second direction substantially perpendicular to the first direction; the first contact window jumper includes a first conductive pattern and a second conductive pattern, the first conductive The pattern intersects the first gate line and the second gate line over the first active region, and the second conductive pattern is between the first gate line and the second gate line as shown in a plan view of the integrated circuit The second direction extends longitudinally and is connected to the first conductive pattern.

According to another aspect of the inventive concept, an integrated circuit includes a first active region and a second active region, a first gate line and a second gate line, a contact window jumper, a first through hole, and a second Through hole and first metal layer. The first active region and the second active region each extend in the first direction and are spaced apart in a second direction substantially perpendicular to the first direction, such that the first active region and the second active region are interposed There is an intermediate region in the second direction; the first gate line and the second gate line are separated from each other in the first direction, and each of the first gate line and the second gate line is in the second direction The upper longitudinal extension extends across the first active region and the second active region and the intermediate region; the contact window jumper comprises a first conductive pattern and a second conductive pattern, the first conductive pattern being above the first active region and the first gate line Crossing, the second conductive pattern extends longitudinally in the second direction over the first gate line and is connected to the first conductive pattern; the first via and the second via are between the first active region and the second active region The intermediate regions are aligned with each other in the first direction, wherein the first via is disposed on the second conductive pattern, and the second via is located above the second gate; the first metal layer includes the first metal pattern, the second metal Pattern and multiple third metals a first metal pattern extending in a first direction above the first active region, a second metal pattern extending in a first direction over the second active region, the plurality of third metal patterns being in the middle region The two directions extend and are respectively disposed on the first through hole and the second through hole.

According to another aspect of the inventive concept, a semiconductor device includes a substrate, a plurality of gate lines, a contact window, a via, and a first metallization layer. The substrate has a first active region, a second active region, and an intermediate region, each of the first active region and the second active region extending in a first direction and spaced apart in a second direction substantially perpendicular to the first direction, The intermediate region is interposed between the first active region and the second active region in the second direction; the plurality of gate lines are separated from each other in the first direction, and each of the plurality of gate lines is in the first Longitudinally extending across the first active region and the second active region and the intermediate region in two directions; the layer of contact windows being on the substrate and having a plurality of upper surfaces that are substantially coplanar at a level above the substrate, The contact window comprises a contact window jumper comprising a first conductive pattern and a second conductive pattern, the first conductive pattern extending in the first direction and above the first active area of the substrate Upwardly intersecting at least one of the plurality of gate lines, the second conductive pattern extending longitudinally from the first conductive pattern in a second direction over at least a portion of the intermediate portion of the substrate; a layer of vias in the one On the contact window, each of the through holes extends on an upper surface of a corresponding one of the contact windows, and the one of the through holes includes a top surface disposed above the substrate and aligned with each other in the first direction a plurality of via holes; a first metallization layer on the one via hole, wherein only one metal track of the first metallization layer extends over the first active region, and only the first metallization layer A metal path extends over the second active region, and each of the two metal paths extends across the plurality of gate lines in a first direction.

FIG. 1 illustrates a first standard unit SC1 and a second standard unit SC2 having different heights.

Referring to Fig. 1, the first standard cell SC1 has a first height H, the second standard cell SC2 has a second height H', and the second height H' is smaller than the first height H. Therefore, the term "height" refers to the size of the standard cell to be laid out, that is, the size in the layout of the standard cell, or the size seen in the plan view of the cell in the integrated circuit. The first height H and the second height H' may be determined according to the number of tracks (hereinafter referred to as "number of paths") above the first standard cell SC1 and the second standard cell SC2, respectively. Here, the paths are wires that are extended in the first direction (for example, the X direction) and arranged in parallel with each other, and may correspond to a metal line pattern of, for example, a metal layer of the semiconductor device. The metal pattern of the metal layer can constitute a so-called metallization layer.

Each of the first standard unit SC1 and the second standard unit SC2 may include a first power source region PWR1 and a second power source region PWR2, a first active region AR1 and a second active region AR2, and an intermediate region MR. The supply voltage and the ground voltage are applied to the first power supply region PWR1 and the second power supply region PWR2, respectively. The first height H of the first standard cell SC1 may correspond to the sum of the respective heights H1 to H5 of the above-described regions of the first cell SC1 (ie, H = H1 + H2 + H3 + H4 + H5) (more on this later) The second height H' of the second standard cell SC2 may correspond to the sum of the respective heights H1' to H5' of the above-mentioned regions of the second standard cell SC2 (ie, H'=H1'+ H2'+ H3'+ H4'+ H5').

Active fins AF extending in the first direction and parallel to each other are disposed in the first active area AR1 and in the second active area AR2, and a plurality of dummy fins DF extending in the first direction and parallel to each other are disposed in the middle In the area MR. Recent developments in semiconductor process technology have led to a gradual reduction in fin pitch. Therefore, with respect to the size of the standard cell arranged in the layout of the integrated circuit, the height of the first active region AR1 is gradually decreased, for example, from H2 to H2', and the height of the second active region AR2 is gradually decreased, for example, from H4 to H4. '. That is to say, it is now possible to realize a standard cell having a relatively small height, such as the second standard cell SC2, when designing the layout of the integrated circuit.

When a standard cell having a larger height is reduced to a standard cell having a smaller height, for example, when the second standard cell SC2 is implemented instead of the first standard cell SC1, the metal pitch is reduced as compared with the pitch of the fins. The reduction in the pitch of the metal paths is relatively small. For example, the two paths MTa and MTb may be arranged above the first active area AR1 of the first standard unit SC1. On the other hand, if the same two paths MTa and MTb are arranged above the first active area AR1 of the second standard unit SC2, the lower path MTb of the two paths MTa and MTb may be in the first active area AR1. outer. Here, the term "lower" may refer to a path closer to the origin of the X-Y coordinate system, where the origin is at the "bottom" of the standard cell and the Y-axis extends along the height of the cell. Therefore, the lower path MTb affects the position of a contact or via disposed in the intermediate region MR of the second standard cell SC2, that is, a metal pattern (for example, by a routing process) The resulting metal pattern has less freedom of design.

2A illustrates a layout of an example of an integrated circuit 10 in accordance with the teachings of the present invention.

Referring to FIG. 2A, the integrated circuit 10 may include a first active region AR1 and a second active region AR2, a plurality of gate lines GL, a first contact window jumper CJ1, and a via V0. Here, the term "contact window jumper" refers to a conductor that connects any two points or any two terminals of the integrated circuit 10 with a relatively short length, and may be simply referred to as a "jumper". The integrated circuit library 10 can be used to design the integrated circuit 10, and the first active area AR1 and the second active area AR2, the plurality of gate lines GL and the first contact window jumper CJ1 can be part of a standard unit ( For example, it corresponds to the second standard cell SC2) in FIG.

The first active area AR1 and the second active area AR2 may extend in a first direction (eg, may extend in a first direction corresponding to the X direction in the drawing) and may be arranged in parallel with each other. The first active region AR1 and the second active region AR2 may be spaced apart from each other along a second direction (eg, the Y direction) substantially perpendicular to the first direction, and may be of different conductivity types. The first active area AR1 and the second active area AR2 may be referred to as a diffusion area. An area between the first active area AR1 and the second active area AR2 in the second direction may be defined as an intermediate area MR. The intermediate region MR may be referred to as a dummy region or a middle of line (MOL) region. Active fins extending in the first direction (eg, active fin AF of the second standard cell SC2 in FIG. 1) may be disposed in the first active area AR1 and in the second active area AR2, and extend in the first direction The dummy fins (for example, the dummy fins DF of the second standard cell SC2 in FIG. 1) may be disposed in the intermediate region MR.

The plurality of gate lines GL may include a first gate line GL1 and a second gate line GL2. Each of the gate lines GL may extend in the second direction and may intersect the first active area AR1 and the second active area AR2. In addition, the gate lines GL may be spaced apart from each other at a fixed interval in the first direction. In this case, the plurality of gate lines GL may correspond to gates of the semiconductor device. Hereinafter, the first contact window jumper CJ1 above the first gate line GL1 will be explained in detail. However, the inventive concept is not limited thereto, and the first contact window jumper CJ1 may be disposed over any conductive trace to implement a skip device. Moreover, the term "upper" refers to the vertical orientation in which the integrated circuit 10 is implemented, that is, the orientation corresponds to the Z direction in the drawing that is perpendicular to the X direction and the Y direction. Thus, when one element is "above" another element, the elements are shown as overlapping in the layout.

The first contact window jumper CJ1 may include a first conductive pattern PT1 and a second conductive pattern PT2 connected to each other. The first conductive pattern PT1 may extend in the first direction, and the second conductive pattern PT2 may extend in the second direction. Specifically, the first conductive pattern PT1 may cross the first gate line GL1 over the first active area AR1, and the second conductive pattern PT2 may extend in the second direction above the first gate line GL1 and may be connected To the first conductive pattern PT1. In this manner, the first contact window jumper CJ1 can have a T-shape, and the first contact jumper CJ1 can therefore be referred to as a T-shaped jumper. It is noted that in the foregoing and in the following description, and as will be apparent from the context, the term "extension" generally refers to the longitudinal direction of the element or feature or the direction along the length, particularly when the element or the The feature is when the line component or line feature is present.

If the second conductive pattern PT2 is disposed between the first gate line GL1 and the second gate line GL2, so that the first contact window jumper CJ1 has an L shape, then is disposed on the second gate line GL2. The upper gate contact may interfere with the first contact jumper CJ1. Therefore, the shape and position of the gate contact window, the via hole, and the metal pattern to be subsequently disposed in the intermediate region MR may thus be complicated, and thus it may be necessary to increase the height of the intermediate region MR in the second direction. Therefore, although the fin pitch is reduced, it may be difficult to keep the height of the standard cell to a minimum.

However, according to the present example, since the second conductive pattern PT2 is disposed above the first gate line GL1 and the first contact window jumper CJ1 has a T-shape, the first contact window jumper CJ1 and subsequently are disposed in the second The interference between the gate contact windows on the gate line GL2 can thus be reduced. Therefore, the shape of the gate contact window, the via hole, and the metal pattern can be simply formed in the intermediate region MR, that is, the gate contact window, the via hole, and the metal pattern can be easily arranged, and the gate contact window can be The via holes and the metal patterns are aligned with each other. Therefore, the height of the intermediate portion MR in the second direction can be prevented from increasing. Therefore, as the fin pitch is reduced, the height of the standard cell can also be reduced, and the overall size of the integrated circuit 10 including the standard cell can also be reduced.

The first conductive pattern PT1 may electrically connect the regions on both sides of the first gate line GL1 in the first active region AR1. Therefore, the first gate line GL1 can be a dummy gate line, that is, a skipped gate line, which is not a true gate line. However, the position of the first contact window jumper CJ1 according to the present example is not limited to the area above the first active area AR1 and above the intermediate area MR. Hereinafter, a modified example of the first contact window jumper CJ1 will be explained with reference to FIG. 2B.

Fig. 2B illustrates the layout of the integrated circuit 10' according to another example.

Referring to FIG. 2B, the integrated circuit 10' may include a first active area AR1 and a second active area AR2, a plurality of gate lines GL, and a first contact window jumper CJ1a. The first contact window jumper CJ1a may include a first conductive pattern PT1a and a second conductive pattern PT2a connected to each other. The first conductive pattern PT1a may extend in a first direction (eg, the X direction), and the second conductive pattern PT2a may extend in a second direction (eg, a Y direction). Specifically, the first conductive pattern PT1a may cross the first gate line GL1 over the second active area AR2, and the second conductive pattern PT2a may extend in the second direction above the first gate line GL1 and may be connected To the first conductive pattern PT1a. In this way, the first contact window jumper CJ1a may have an inverted T shape. The first conductive pattern PT1a of the first contact window jumper CJ1a may electrically connect the regions on both sides of the first gate line GL1 in the second active region AR2. Therefore, the first gate line GL1 can be a dummy gate line.

Referring back to FIG. 2A, the via hole V0 may be disposed on the second conductive pattern PT2 of the first contact window jumper CJ1a. In an example, the via hole V0 may be disposed on the second conductive pattern PT2 in the intermediate region MR. Therefore, a routing interconnection line to be subsequently disposed on the via hole V0, for example, a first metal layer (for example, the metal layer M1 in FIG. 21B), may be disposed above the intermediate region MR instead of being arranged Above the first active area AR1. However, the position of the via hole V0 is not limited to the intermediate region MR, and in some examples, depending on the length of the second conductive pattern PT2, the via hole V0 may be disposed on the second conductive pattern PT2 in the first active region AR1 or The second conductive pattern PT2 in the second active region AR2.

In an example, the first contact window jumper CJ1 can be formed using a single mask. For example, the first contact window jumper CJ1 can be formed using a mask for forming an active contact window (eg, a source/drain contact window). As another example, the first contact window jumper CJ1 can be formed using a mask for forming a gate contact window. Hereinafter, an example in which a single cover curtain is used to form the first contact window jumper CJ1 will be explained with reference to FIG.

Figure 3 is a cross-sectional view taken along the line X1a-X1a' and the line X1b-X1b' in Figure 2A.

Referring to Fig. 3, integrated circuit 10 may be an example of an integrated circuit device (i.e., a semiconductor device) fabricated in accordance with the layout of Fig. 2A. In the present example, the first conductive pattern PT1 and the second conductive pattern PT2 of the first contact window jumper CJ1 may be implemented as the first contact window CA. The first contact window CA may also be referred to as an active contact window.

The substrate SUB can be a semiconductor substrate, and for example, the semiconductor substrate can include germanium, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, germanium or gallium arsenide. . The substrate SUB may include a first active area AR1 and a second active area AR2 and an intermediate area MR. For example, shallow trench isolation (STI) may be disposed in the substrate SUB to separate the intermediate region MR from the first active region AR1 and the second active region AR2.

The plurality of gate insulating films GI and the plurality of gate lines GL may extend in the second direction (for example, the Y direction) on the substrate SUB. The plurality of gate insulating films GI may include a hafnium oxide film, a high dielectric constant (k) film, or a combination thereof. The plurality of gate lines GL may include a metal material such as tungsten (W), tantalum (Ta), cobalt (Co), or copper (Cu), a nitride thereof, a germanide thereof, and a doped polysilicon, and examples thereof In other words, it can be formed using a deposition process. The upper surface and the two side wall surfaces of each of the gate lines GL are covered by the insulating spacers SP. The insulating spacer SP may extend parallel to the gate line GL in the second direction. The insulating spacer SP may include a tantalum nitride film, a SiOCN film, a SiCN film, or a combination thereof. The gate insulating film GI, the gate line GL, and the insulating spacer SP may constitute the gate structure GS.

The first contact window CA may be formed on the substrate SUB on which the gate structure GS is formed. The first contact window CA may intersect the first gate line GL1 in the first active area AR1 and may be disposed above the first gate line GL1 in the intermediate area MR. The first contact window CA may comprise any material having electrical conductivity, such as tungsten. The via hole V0 may be disposed in the intermediate region MR on the first contact window CA disposed above the first gate line GL1.

Fig. 4 is a view showing the layout of the integrated circuit 10a according to an example, and Fig. 5 is a cross-sectional view taken along the line X2a-X2a' and the line X2b-X2b' in Fig. 4.

Referring to FIGS. 4 and 5, the first conductive pattern PT1 of the first contact window jumper CJ1 can be implemented as the first contact window CA, and the second conductive pattern PT2 of the first contact window jumper CJ1 can be implemented as The second contact window CB. Therefore, the first contact window jumper CJ1 can be formed using the first mask for the first contact window CA and the second mask for the second contact window CB.

In an example, the first contact window CA may correspond to an active contact window such as a source/drain contact window, and the second contact window CB may correspond to a gate contact window. In this case, the first contact window CA and the second contact window CB may overlap each other in some areas. The upper surface level of the first contact window CA and the upper surface level of the second contact window CB may be substantially equal to each other. The lower surface level of the first contact window CA may be equal to the upper surface level of the substrate SUB, and the lower surface level of the second contact window CB may be lower than the upper surface level of the gate structure GS, and thus, the second contact The window CB can be connected to the first gate line GL1.

Fig. 6 is a view showing the layout of the integrated circuit 10b according to an example, and Fig. 7 is a cross-sectional view taken along the line X3a-X3a' and the line X3b-X3b' in Fig. 6.

Referring to FIGS. 6 and 7, the integrated circuit 10b is similar to the integrated circuit 10a illustrated in FIG. 4, but further includes a trench germanium TS. The trench germanium TS may be disposed between two adjacent gate lines GL in the first active region AR1, respectively. The trench telluride TS may extend in a second direction (eg, the Y direction), and the length of the trench germanide TS in the second direction may be substantially equal to the length of the first active region AR1 in the second direction. Each of the trench germanium TS may include a conductive material such as tungsten (W), cobalt (Co), or copper (Cu).

In an example, the height of the trench germanium TS in the third direction (eg, the Z direction) may be greater than the height of the gate structure GS in the third direction. The first contact window CA may be disposed on the trench germanium TS. Therefore, the first contact window CA may not be connected to the gate structure GS.

8 is a cross-sectional view taken along line X4a-X4a' and section line X4b-X4b' in FIG. 8, and FIG. 10 is a cross-sectional view taken along line X4a-X4a' and line X4b-X4b' in FIG. A perspective view of the integrated circuit 10c.

Referring to FIGS. 8 through 10, the integrated circuit 10c is similar to the integrated circuit 10 illustrated in FIG. 2A, but further includes a first contact window CA as compared with the integrated circuit 10 of FIG. 2A. The first contact windows CA may be disposed between two adjacent gate lines GL in the first active region AR1, respectively. The first contact window CA may extend in a second direction (eg, the Y direction), and the length of the first contact window CA in the second direction may be substantially equal to the length of the first active region AR1 in the second direction. The height of the first contact window CA in the third direction (for example, the Z direction) may be greater than the height of the gate structure GS in the third direction. An interlayer dielectric layer ILD may be disposed over the gate structure GS. The interlayer dielectric layer ILD may comprise an insulating material such as an oxide, a nitride or an oxynitride.

In addition, the first conductive pattern PT1 and the second conductive pattern PT2 of the first contact window jumper CJ1 may be implemented as the third contact window CM. For example, the third contact window CM may correspond to a merged contact window and may merge the first contact windows CA separated from each other. The third contact window CM may be disposed above the first contact window CA and above the interlayer dielectric layer ILD. Therefore, the distance from the substrate SUB to the lower surface of the third contact window CM may be greater than the height of the gate structure GS in the third direction, thereby ensuring the third contact window CM and the gate structure GS (specifically, the gate line GL ) The space between the insulation. The through hole V0 may be arranged on the third contact window CM in the intermediate region MR.

Fig. 11 is a view showing the layout of the integrated circuit 10d according to an example, and Fig. 12 is a cross-sectional view taken along the line X5a-X5a' and the line X5b-X5b' in Fig. 11.

Referring to FIGS. 11 and 12, the integrated circuit 10d is similar to the example of the integrated circuit 10c illustrated in FIG. 8, but further includes a trench germanium TS. A plurality of trenched germanium TSs may be disposed between two adjacent gate lines GL in the first active region AR1, respectively. The trench telluride TS may extend in a second direction (eg, the Y direction), and the length of the trench germanide TS in the second direction may be substantially equal to the length of the first active region AR1 in the second direction. Additionally, in the second direction, the first contact window CA may be shorter than the trench telluride TS.

FIG. 13 illustrates the layout of the integrated circuit 20 in accordance with an example.

Referring to Fig. 13, the integrated circuit 20 is similar to the example of the integrated circuit 10 of Fig. 2A, but further includes a second contact window jumper CJ2. The second contact window jumper CJ2 may extend in a first direction (eg, the X direction) and intersect the first gate line GL1 over the second active area AR2. In this case, the second contact window jumper CJ2 is spaced apart from the first contact window jumper CJ1. The first contact window jumper CJ1 and the second contact window jumper CJ2 can be implemented in any form and using any of the respective techniques described above with reference to Figures 2A-12.

In one example, three masks can be used to implement the first contact window jumper CJ1 and the second contact window jumper CJ2. For example, the first contact window jumper CJ1 may be formed by the first contact window CA and the third contact window CM, and the second contact window jumper CJ2 may be formed by the second contact window CB. In one example, two masks can be used to implement the first contact window jumper CJ1 and the second contact window jumper CJ2. For example, the first contact window jumper CJ1 may be formed by the first contact window CA, and the second contact window jumper CJ2 may be formed by the second contact window CB. In one example, the first contact window jumper CJ1 and the second contact window jumper CJ2 can be implemented using a single mask. For example, the first contact window jumper CJ1 and the second contact jumper CJ2 may be formed by the first contact window CA.

FIG. 14 illustrates the layout of the integrated circuit 30 in accordance with an example.

Referring to Fig. 14, the integrated circuit 30 is similar to the example of the integrated circuit 20 of Fig. 13, but in the present example, the length of the first contact window jumper CJ1 in the first direction (e.g., the X direction) is in contact with the second contact. The lengths of the window jumper CJ2' in the first direction (for example, the X direction) are different from each other. The second contact window jumper CJ2' may extend in the first direction and intersect the first gate line GL1 and the second gate line GL2 over the second active area AR2. In this manner, the length of the second contact window jumper CJ2' in the first direction is greater than the length of the second contact window jumper CJ2 of Fig. 13 in the first direction. The inventive concept is not limited thereto, and in some examples, the length of the second contact window jumper CJ2' in the first direction may extend further than in the illustrated example, that is, the second contact window jumper The piece CJ2' can intersect with three or more gate lines GL.

FIG. 15 illustrates the layout of the integrated circuit 40 in accordance with an example.

Referring to Fig. 15, the integrated circuit 40 is similar to the example of the integrated circuit 20 of Fig. 13, but the length of the first contact window jumper CJ1' in the first direction (e.g., the X direction) and the second contact window jumper The lengths of CJ2 in the first direction (for example, the X direction) are different from each other. The first conductive pattern PT1' of the first contact window jumper CJ1' may extend in the first direction and intersect the first gate line GL1 and the second gate line GL2 over the first active area AR1. In this way, the length of the first conductive pattern PT1' of the first contact window jumper CJ1' in the first direction is greater than the first conductive pattern PT1 of the first contact window jumper CJ1 of FIG. 13 in the first direction. length. However, the inventive concept is not limited thereto, and in some examples, the length of the first conductive pattern PT1' of the first contact window jumper CJ1' in the first direction may extend further than in the illustrated example. That is, the first contact window jumper CJ1' may intersect with three or more gate lines GL.

FIG. 16 illustrates the layout of the integrated circuit 50 according to an example.

Referring to FIG. 16, the integrated circuit 50 may include a first active area AR1 and a second active area AR2, a plurality of gate lines GL, and a third contact window jumper CJ3. The third contact window jumper CJ3 may include a first conductive pattern PT1, a second conductive pattern PT2', and a third conductive pattern PT3 connected to each other. The first conductive pattern PT1 and the third conductive pattern PT3 may extend in a first direction (e.g., the X direction), and the second conductive pattern PT2' may extend in a second direction (e.g., a Y direction). Specifically, the first conductive pattern PT1 may cross the first gate line GL1 above the first active area AR1, and the second conductive pattern PT2' may extend in the second direction above the first gate line GL1 and may be connected To the first conductive pattern PT1, the third conductive pattern PT3 may cross the first gate line GL1 over the second active region AR2. In this way, the third contact window jumper CJ3 may have an I-shape or an H-shape.

The first conductive pattern PT1 may electrically connect the regions on both sides of the first gate line GL1 in the first active region AR1. The third conductive pattern PT3 may electrically connect the regions on both sides of the first gate line GL1 in the second active region AR2. In addition, the second conductive pattern PT2' may connect the first conductive pattern PT1 and the third conductive pattern PT3 to each other. Therefore, the first gate line GL1 can be a dummy gate line, that is, a skipped gate line, which is not a true gate line (that is, it does not function in the integrated circuit 50).

In one example, three masks can be used to implement the first conductive pattern PT1, the second conductive pattern PT2', and the third conductive pattern PT3. For example, the first conductive pattern PT1, the second conductive pattern PT2', and the third conductive pattern PT3 may be implemented as a first contact window CA, a second contact window CB, and a third contact window CM, respectively. In one example, the two conductive masks PT1, the second conductive pattern PT2', and the third conductive pattern PT3 may be implemented using two masks. For example, the first conductive pattern PT1, the second conductive pattern PT2', and the third conductive pattern PT3 may be implemented as a first contact window CA and a third contact window CM. In one example, a single mask can be used to implement the first conductive pattern PT1, the second conductive pattern PT2', and the third conductive pattern PT3. For example, the first conductive pattern PT1, the second conductive pattern PT2', and the third conductive pattern PT3 may be implemented as a first contact window CA or a second contact window CB.

FIG. 17 illustrates the layout of an integrated circuit 60 in accordance with an example.

Referring to Fig. 17, the integrated circuit 60 is similar to the example of the integrated circuit 50 of Fig. 16. However, in this example, the third conductive pattern PT3' of the third contact window jumper CJ3' may extend in a first direction (eg, the X direction) and above the second active region AR2 with the first gate line GL1 And the second gate line GL2 intersects. In this way, the length of the third conductive pattern PT3' of the third contact window jumper CJ3' in the first direction is greater than the third conductive pattern PT3 of the third contact window jumper CJ3 of FIG. 16 in the first direction. length. The inventive concept is not limited thereto, and in some examples, the length of the third conductive pattern PT3' of the third contact window jumper CJ3' in the first direction may further extend than in the illustrated example, that is, The third contact window jumper CJ3' may intersect with three or more gate lines GL.

FIG. 18 illustrates the layout of the integrated circuit 70 in accordance with an example.

Referring to Fig. 18, the integrated circuit 70 is similar to the example of the integrated circuit 30 of Fig. 14, but the integrated circuit 70 includes a first active area AR1 and a second active area AR2, a plurality of gate lines GL, and a fourth contact window jump. Wire member CJ4 and second contact window jumper CJ2'. The fourth contact window jumper CJ4 may include a first conductive pattern PT1' and a second conductive pattern PT2'' connected to each other. The first conductive pattern PT1' may extend in a first direction (e.g., the X direction), and the second conductive pattern PT2'' may extend in a second direction (e.g., the Y direction).

Specifically, the first conductive pattern PT1 ′ may cross the first gate line GL1 and the second gate line GL2 above the first active region AR1, and the second conductive pattern PT2 ′′ may be at the first gate line GL1 And the second gate line GL2 extends in the second direction and is connectable to the first conductive pattern PT1'. In this way, the fourth contact window jumper CJ4 can have a T-shape. In the first active region AR1, the first conductive pattern PT1' of the fourth contact jumper CJ4 can electrically connect the region on the left side of the first gate line GL1 and the region on the right side of the second gate line GL2. Therefore, the first gate line GL1 and the second gate line GL2 in the PMOS region may be dummy gate lines, that is, skipped gate lines, which are not true gate lines. In some examples, the first conductive pattern PT1 ′ may intersect with three or more gate lines GL, and in this case, the second conductive pattern PT2 ′′ may be in three or more gate lines GL Any one of the strips extends between the gate lines GL in the second direction.

In addition, the second contact window jumper CJ2' can cross the first gate line GL1 and the second gate line GL2 over the second active area AR2, and can be separated from the fourth contact window jumper CJ4. . In the second active region AR2, the second contact window jumper CJ2' can electrically connect the region on the left side of the first gate line GL1 and the region on the right side of the second gate line GL2. Therefore, the first gate line GL1 and the second gate line GL2 in the NMOS region may be dummy gate lines, that is, skipped gate lines, which are not true gate lines. In some examples, the second contact window jumper CJ2' may intersect three or more gate lines GL.

In addition, the integrated circuit 70 may further include a through hole V0'. The via hole V0' may be disposed on the second conductive pattern PT2'' of the fourth contact window jumper CJ4. In an example, the via hole V0' may be disposed on the second conductive pattern PT2'' in the intermediate region MR. Therefore, a wiring interconnection line to be subsequently disposed on the via hole V0', for example, a first metal layer, may be disposed over the intermediate region MR instead of being disposed above the first active region AR1. However, the position of the via hole V0' is not limited to the intermediate region MR, and in some examples, depending on the length of the second conductive pattern PT2", the via hole V0 is disposed in the second conductive pattern PT2 in the first active region AR1 ''Upper or second conductive pattern PT2'' in the second active area AR2.

FIG. 19 illustrates the layout of an integrated circuit 80 in accordance with an example.

Referring to Fig. 19, the integrated circuit 80 is similar to the example of the integrated circuit 50 of Fig. 16, but the integrated circuit 80 includes a first active area AR1 and a second active area AR2, a plurality of gate lines GL, and a fifth contact window jump. Wire CJ5. The fifth contact window jumper CJ5 may include a first conductive pattern PT1', a second conductive pattern PT2''', and a third conductive pattern PT3' connected to each other. The first conductive pattern PT1' and the third conductive pattern PT3' may extend in a first direction (e.g., the X direction), and the second conductive pattern PT2''' may extend in a second direction (e.g., the Y direction).

Specifically, the first conductive pattern PT1 ′ may cross the first gate line GL1 and the second gate line GL2 above the first active area AR1, and the third conductive pattern PT3 ′ may be above the second active area AR2 The first gate line GL1 and the second gate line GL2 intersect. The second conductive pattern PT2''' may extend in the second direction between the first gate line GL1 and the second gate line GL2, and may be connected to the first conductive pattern PT1' and the third conductive pattern PT3'. In this way, the fifth contact window jumper CJ5 may have an I-shape or an H-shape.

In the first active region AR1, the first conductive pattern PT1' of the fifth contact window jumper CJ5 can electrically connect the region on the left side of the first gate line GL1 and the region on the right side of the second gate line GL2. In the second active region AR2, the third conductive pattern PT3' of the fifth contact window jumper CJ5 can electrically connect the region on the left side of the first gate line GL1 and the region on the right side of the second gate line GL2. Therefore, the first gate line GL1 and the second gate line GL2 may be dummy gate lines, that is, skipped gate lines, which are not true gate lines.

In addition, the integrated circuit 80 may further include a through hole V0'. The via hole V0' may be disposed on the second conductive pattern PT2''' of the fifth contact window jumper CJ5. In an example, the via hole V0' may be disposed on the second conductive pattern PT2''' in the intermediate region MR. Therefore, a wiring interconnection line to be subsequently disposed on the via hole V0', for example, a first metal layer, may be disposed above the intermediate region MR instead of being disposed above the first active region AR1 or above the second active region AR2. However, the position of the via hole V0' is not limited to the intermediate region MR, and in some examples, the via hole V0 is disposed on the second conductive pattern PT2"' in the first active region AR1 or the second active region AR2 Two conductive patterns PT2'''.

FIG. 20A illustrates a symbol of a standard cell SCa according to an example, and FIG. 20B is a circuit diagram of a standard cell SCa of FIG. 20A.

Referring to FIG. 20A, the standard unit SCa may be an AOI22 unit, and may receive the first input signal A0, the second input signal A1, the third input signal B0, and the fourth input signal B1, and output an output signal Y. Referring to FIG. 20B, the standard cell SCa may include first to fourth PMOS transistors PM1 to PM4 and first to fourth NMOS transistors NM1 to NM4.

The first PMOS transistor PM1 may include a gate to which the first input signal A0 is applied, and the second PMOS transistor PM2 may include a gate to which the second input signal A1 is applied. The third PMOS transistor PM3 may include a gate to which the third input signal B0 is applied, and the fourth PMOS transistor PM4 may include a gate to which the fourth input signal B1 is applied. In this case, the drain of the first PMOS transistor PM1, the drain of the second PMOS transistor PM2, the source of the third PMOS transistor PM3, and the source of the fourth PMOS transistor PM4 may be in the PMOS region. The input wiring pattern or the internal wiring pattern IRT is electrically connected. In an example, the internal wiring pattern IRT may be implemented in a horizontal metal pattern (eg, metal pattern M1a in FIG. 21B) that is first in the first active region (eg, active region AR1 in FIG. 21B) The direction (for example, the X direction) extends, and the first PMOS transistor PM1 to the fourth PMOS transistor PM4 are disposed therein.

The first NMOS transistor NM1 may include a gate to which the first input signal A0 is applied, and the second NMOS transistor NM2 may include a gate to which the third input signal B0 is applied. The third NMOS transistor NM3 may include a gate to which the second input signal A1 is applied, and the fourth NMOS transistor NM4 may include a gate to which the fourth input signal B1 is applied. In this case, the drain of the third PMOS transistor PM3, the drain of the fourth PMOS transistor PM4, the drain of the first NMOS transistor NM1, and the drain of the second NMOS transistor NM2 may be connected to the PMOS region. And the output wiring pattern ORT of the NMOS region is electrically connected.

In an example, the output wiring pattern ORT can include a T-shaped contact window jumper disposed above the first active region (eg, contact window jumper 110 in FIG. 21A), a contact window disposed over the second active region And an upper metal pattern (for example, the metal pattern M1b in FIG. 21B) connecting the T-shaped contact window jumper and the contact window. Therefore, only one horizontal metal pattern can be arranged above the first active area. Hereinafter, the layout of the integrated circuit including the standard cell SCa will be explained with reference to FIGS. 21A to 27. Specifically, various examples of the T-shaped contact window jumper for implementing the output wiring pattern ORT of the standard cell SCa will be explained below.

21A illustrates the layout of an integrated circuit 100 in accordance with an example.

Referring to FIG. 21A, the integrated circuit 100 may include a standard cell SCa_1 corresponding to the standard cell SCa in FIG. 20A and FIG. 20B, and the standard cell SCa_1 may include a first active region AR1 and a second active region AR2, and multiple gates. The line GL and a layer of contact windows including the first contact window CA and the second contact window CB. The first contact window CA may be disposed between the first active region AR1 and the gate line GL in the second active region AR2, respectively. The second contact windows CB may be respectively disposed on the gate lines GL in the intermediate region MR. The upper surface of the first contact window CA and the upper surface of the second contact window CB may be substantially coplanar at a level above the substrate.

The standard cell SCa_1 may include a first contact window jumper 110 and a second contact window jumper 120. For example, the first contact window jumper 110 and the second contact window jumper 120 can be implemented by the first contact window CA. The first contact window jumper 110 can include a first portion that intersects the first gate line 130 above the first active region AR1 and a second portion that is in the intermediate region MR at the first gate line 130. The upper portion extends in the second direction (for example, the Y direction). The second contact window jumper 120 may intersect the first gate line 130 above the second active area AR2. For example, the first contact window jumper 110 can correspond to the first contact window jumper CJ1 of FIG. 2A or FIG. 13 and the second contact window jumper 120 can correspond to the second contact window of FIG. Wire CJ2. Other features/patterns described above with reference to Figures 2A and 13 are also applicable to this example.

In an example, the integrated circuit 100 can further include a cut region CT. The cutting region CT may be arranged above the first gate line 130 in the intermediate region MR. Therefore, even if a short circuit occurs between the first contact window jumper 110 and the first gate line 130, the first gate line (ie, the PMOS gate line) above the first active area AR1 can be combined with the second active The second gate line (ie, the NMOS gate line) above the region AR2 is isolated.

Fig. 21B illustrates the layout of the integrated circuit 100' according to an example, the integrated circuit 100' further including the first metal layer M1 as compared with Fig. 21A.

Referring to Fig. 21B, the integrated circuit 100' may further include a first via hole V0 and a first metal layer M1 on the first via hole V0. The first via hole V0 may be a part of the first layer via hole, and the first layer via hole is disposed on the one layer contact window including the first contact window CA and the second contact window CB. The first through holes V0 may be aligned with each other in the intermediate portion MR. For example, the first through holes V0 may be arranged in a straight line in the first direction (for example, the X direction) in the intermediate portion MR.

The first metal layer M1 is disposed on the first layer via and may be referred to as a first metallization layer. The first metal layer M1 may include a first metal pattern M1a, a second metal pattern M1b, and a third metal pattern M1c, the first metal pattern M1a connecting the first via holes V0 disposed in the first active region AR1 to each other, and second The metal pattern M1b connects the first via holes V0 arranged in the second active region AR2 to each other, and the third metal patterns M1c are respectively connected to the first via holes V0 arranged in the intermediate region MR. The first metal layer M1 may further include a power supply voltage pattern VDD and a ground voltage pattern VSS.

According to the present example, only one horizontal metal path, that is, the first metal pattern M1a, may be disposed above the first active area AR1, and only one horizontal metal path may be disposed above the second active area AR2, that is, the second metal pattern M1b . Since the horizontal metal path extending beyond the first active area AR1 does not exist, the second contact window CB and the first through hole V0 disposed in the intermediate area MR may be disposed at aligned positions. In addition, the second contact window CB can be implemented in the same pattern, and the first via hole V0 can also be implemented in the same pattern. Therefore, since the pattern in the integrated circuit 100' is simplified, the process risk can be reduced in the design rule inspection stage and the number of violations of the design rule can be reduced.

Fig. 21C illustrates the layout of the integrated circuit 100'' according to an example, the integrated circuit 100'' further including a second metal layer as compared with Fig. 21B. Figure 22 is a cross-sectional view taken along the line X6a-X6a' and the line X6b-X6b' in Figure 21C.

Referring to FIG. 21C and FIG. 22, the integrated circuit 100'' may further include a second via hole V1 (that is, a second layer via hole on the first metal layer M1) and a second via hole V1 (second layer pass) a second metal layer M2 (ie, a second metallization layer) on the holes). The second via hole V1 may be disposed on the third metal pattern M1c of the first metal layer M1 in the intermediate region MR. The second through holes V1 may be aligned with each other in the intermediate portion MR. For example, the second through holes V1 may be arranged in a straight line in the first direction (for example, the X direction) in the intermediate portion MR.

The second metal layer M2 may include a plurality of metal patterns, that is, a metal pattern M2a to a metal pattern M2e. In an example, the metal pattern M2a to the metal pattern M2e may be the same pattern, that is, may have the same shape and size. For example, the widths of the metal patterns M2a to M2e in the first direction may be equal to each other. In addition, for example, the lengths of the metal pattern M2a to the metal pattern M2e in the second direction (ie, the Y direction) may be equal to each other. For example, the metal pattern M2a, the metal pattern M2b, the metal pattern M2c, and the metal pattern M2e may correspond to the input wiring to which the first input signal A0, the second input signal A1, the third input signal B0, and the fourth input signal B1 are applied. The pattern (ie, the metal input terminal), and the metal pattern M2d may correspond to the output wiring pattern ORT (ie, the metal output terminal) that outputs an output signal Y in FIG. 20B.

23A and 23B show the integrated circuit 100a and the integrated circuit 100b which are other examples of the integrated circuit 100 of Fig. 21A, respectively.

Referring to Fig. 23A, the integrated circuit 100a is similar to the example of the integrated circuit 100 of Fig. 21A. The integrated circuit 100a may include the standard cells SCa_1a, and the first contact windows CA of the standard cells SCa_1a may be disposed between the first active region AR1 and the gate lines GL in the second active region AR2, respectively. The length of some of the first contact windows CA in the second direction (eg, the Y direction) may be less than the length of the first contact window CA of FIG. 21A. In an example, the cutting region CT may be disposed above the first gate line 130 in the intermediate region MR. Referring to Fig. 23B, the integrated circuit 100b is similar to the example of the integrated circuit 100a of Fig. 23A. The integrated circuit 100b may include a standard cell SCa_1b, and the cut region CT' of the standard cell SCa_1b may be disposed above the first gate line 130 in the second active region AR2.

FIG. 24A illustrates a layout of an integrated circuit 200 in accordance with an example.

Referring to FIG. 24A, the integrated circuit 200 may include a standard cell SCa_2 corresponding to the standard cell SCa in FIG. 20A and FIG. 20B. The standard cell SCa_2 may include a first active region AR1 and a second active region AR2, a plurality of gate lines GL, a trench germanium TS, a first contact window CA, and a second contact window CB. The trench germanium TS may be disposed between the first active region AR1 and the gate line GL in the second active region AR2, respectively. The length of the trench germanide TS in the second direction (eg, the Y direction) may be substantially equal to the length of the first active region AR1 and the second active region AR2 in the second direction. The first contact window CA may be disposed on the trench germanium TS in the first active region AR1 and the second active region AR2, respectively. The second contact windows CB may be respectively disposed on the gate lines GL in the intermediate region MR.

The standard cell SCa_2 may include a first contact window jumper 210 and a second contact window jumper 220. For example, the first contact window jumper 210 and the second contact window jumper 220 can be implemented by the first contact window CA. The first contact window jumper 210 can include a first portion that intersects the first gate line 230 in the first active region AR1 and a second portion that is in the intermediate region MR at the first gate line 230. The upper portion extends in the second direction. The second contact window jumper 220 may intersect the first gate line 230 above the second active area AR2. For example, the first contact window jumper 210 may correspond to the first contact window jumper CJ1 of FIG. 6 or FIG. 13 and the second contact window jumper 220 may correspond to the second contact window of FIG. Wire CJ2. Other features/patterns of the examples described above with reference to Figures 6, 7, and 13 are also applicable to this example.

Fig. 24B illustrates the layout of the integrated circuit 200' according to an example, the integrated circuit 200' further including the first metal layer M1 as compared with Fig. 24A. Referring to Fig. 24B, the integrated circuit 200' may further include a first via hole V0 and a first metal layer M1 on the first via hole V0. The implementation mode of the first via hole V0 and the first metal layer M1 may be substantially the same as the mode explained with reference to the example illustrated in FIG. 21B, and thus will not be described in detail.

Fig. 24C illustrates the layout of the integrated circuit 200'' according to an example, the integrated circuit 200'' further including the second metal layer M2 as compared with Fig. 24B. Figure 25 is a cross-sectional view taken along the line X7a-X7a' and the line X7b-X7b' in Figure 24C. Referring to Figures 24C and 25, the integrated circuit 200'' may further include a second via hole V1 and a second metal layer M2 on the second via hole V1. The implementation modes of the second via hole V1 and the second metal layer M2 may be substantially the same as the modes explained with reference to the example illustrated in FIG. 21C, and thus will not be described in detail.

FIG. 26A illustrates the layout of an integrated circuit 300 in accordance with an example.

Referring to FIG. 26A, the integrated circuit 300 may include a standard cell SCa_3 corresponding to the standard cell SCa in FIG. 20A and FIG. 20B, and the standard cell SCa_3 may include a first active region AR1 and a second active region AR2, and multiple gates. Line GL, first contact window CA, second contact window CB, and third contact window CM. The first contact window CA may be disposed between the first active region AR1 and the gate line GL in the second active region AR2, respectively. The second contact windows CB may be respectively disposed on the gate lines GL in the intermediate region MR. The third contact window CM may be disposed on some of the first contact windows CA and some of the second contact windows CB.

The standard cell SCa_3 may include a first contact window jumper 310 and a second contact window jumper 320. For example, the first contact window jumper 310 and the second contact window jumper 320 can be implemented by the third contact window CM. The first contact window jumper 310 can include a first portion that intersects the first gate line 330 in the first active region AR1 and a second portion that is in the intermediate region MR at the first gate line 330. The upper portion extends in the second direction (for example, the Y direction). The second contact window jumper 320 may intersect the first gate line 330 in the second active region AR2. For example, the first contact window jumper 310 may correspond to the first contact window jumper CJ1 of FIG. 8, FIG. 11, or FIG. 13, and the second contact window jumper 320 may correspond to the second of FIG. Contact window jumper CJ2. Other aspects/features of the examples described above with reference to Figures 8 through 13 are also applicable to this example.

Fig. 26B illustrates the layout of the integrated circuit 300' according to an example, the integrated circuit 300' further including the first metal layer M1 as compared with Fig. 26A. Referring to Fig. 26B, the integrated circuit 300' may further include a first via hole V0 and a first metal layer M1 on the first via hole V0. The first through hole V0 may be disposed on the third contact window CM. The implementation mode of the first through hole V0 may be substantially the same as the example illustrated in FIG. 21B, and a repetitive description thereof will be omitted.

Fig. 26C illustrates the layout of the integrated circuit 300'' according to an example, the integrated circuit 300'' further including the second metal layer M2 as compared with Fig. 26B. Figure 27 is a cross-sectional view taken along the line X8a-X8a' and the line X8b-X8b' in Figure 26C. Referring to Figures 26C and 27, the integrated circuit 300'' may further include a second via hole V1 and a second metal layer M2 on the second via hole V1. The implementation modes of the second via hole V1 and the second metal layer M2 may be substantially the same as the modes explained with reference to the example illustrated in FIG. 21C, and thus will not be described in detail.

FIG. 28A shows the notation of the adder ADD, and FIG. 28B is a logic circuit diagram of the adder ADD including the standard cell SCb according to an example.

Referring to FIGS. 28A and 28B, the adder ADD may include a carry-out cell, and the carry output unit may be implemented by the standard cell SCb. The standard unit SCb can receive the first input signal A, the second input signal B, and the third input signal Cin, and can output an output signal Cout. Hereinafter, the layout of the integrated circuit including the standard cell SCb will be explained with reference to FIGS. 29A to 29C. In particular, various examples of contact window jumpers for implementing the output wiring of the standard cell SCb will be described below.

FIG. 29A illustrates a layout of an integrated circuit 400 in accordance with an example.

Referring to FIG. 29A, the integrated circuit 400 may include a standard cell SCb_1 corresponding to the standard cell SCb in FIG. 28B, and the standard cell SCb_1 may include a first active region AR1 and a second active region AR2, and a plurality of gate lines GL, A contact window CA, a second contact window CB, and a third contact window CM. The first contact window CA may be disposed between the first active region AR1 and the gate line GL in the second active region AR2, respectively. The second contact windows CB may be respectively disposed on the gate lines GL in the intermediate region MR. The third contact window CM may be disposed on some of the first contact windows CA and some of the second contact windows CB.

The standard cell SCb_1 may include a contact window jumper 410. For example, the contact window jumper 410 can be implemented by the third contact window CM. The contact window jumper 410 can include a first portion, a second portion, and a third portion, the first portion intersecting the first gate line 420 in the first active region AR1 and the second portion in the intermediate region MR at the first gate The line 420 extends above the second direction (eg, the Y direction), and the third portion intersects the first gate line 420 and is coupled to the second portion in the second active area AR2. For example, contact window jumper 410 can correspond to third contact window jumper CJ3 of FIG. Other aspects/features of the examples described above with reference to Figure 16 are also applicable to this example.

Fig. 29B illustrates the layout of an integrated circuit 400' according to an example, the integrated circuit 400' further including a first metal layer M1 as compared with Fig. 29A.

Referring to Fig. 29B, the integrated circuit 400' may further include a first via hole V0 and a first metal layer M1 on the first via hole V0. The first through hole V0 may be disposed on the third contact window CM. The first through holes V0 may be aligned with each other in the intermediate portion MR. For example, the first through holes V0 may be arranged in a straight line in the first direction (for example, the X direction) in the intermediate portion MR.

The first metal layer M1 may include a first metal pattern M1a', a second metal pattern M1b', and a plurality of third metal patterns M1c', the first metal pattern M1a' being disposed in the first via hole in the first active region AR1 V0 are connected to each other, the second metal pattern M1b' connects the first via holes V0 arranged in the second active region AR2 to each other, and the third metal patterns M1c' are respectively connected to the first via holes V0 arranged in the intermediate region MR . The first metal layer M1 may further include a power supply voltage pattern VDD and a ground voltage pattern VSS.

According to the present example, only one horizontal metal path, that is, the first metal pattern M1a′ may be disposed above the first active area AR1, and only one horizontal metal path may be disposed above the second active area AR2, that is, the second metal pattern. M1b'. Therefore, the number of horizontal metal patterns in the standard cell can be limited to two, that is, two horizontal metal patterns are sufficient. If the integrated circuit 400' does not include the contact window jumper 410, the standard unit would require four horizontal metal patterns. In addition, according to the present example, the horizontal metal path extending beyond the first active area AR1 does not exist. Therefore, the second contact window CB, the third contact window CM, and the first through hole V0 disposed in the intermediate portion MR may be disposed at aligned positions. The second contact window CB can be implemented in the same pattern, and the first via hole V0 can also be implemented in the same pattern.

According to the present example, the widths of the third metal patterns M1c' in the first direction may be equal to each other. Further, the lengths of the third metal patterns M1c' in the second direction may be equal to each other. In this way, the third metal patterns M1c' may be the same pattern and may be aligned with each other. For example, the third metal pattern M1c' may be arranged in a straight line in the first direction.

Fig. 29C illustrates the layout of the integrated circuit 400'' according to an example, the integrated circuit 400'' further including the second metal layer M2 as compared with Fig. 29B.

Referring to Fig. 29C, the integrated circuit 400'' may further include a second via hole V1 and a second metal layer M2 on the second via hole V1. The second through hole V1 may be arranged on the first metal layer M1 in the intermediate region MR. The second through holes V1 may be aligned with each other in the intermediate portion MR. For example, the second through holes V1 may be arranged in a straight line in the first direction (for example, the X direction) in the intermediate portion MR. In addition, the second through holes V1 may be implemented in the same pattern.

The second metal layer M2 may include a plurality of metal patterns, that is, a metal pattern M2a' to a metal pattern M2e'. In an example, the metal pattern M2a' to the metal pattern M2e' may be the same pattern. For example, the widths of the metal pattern M2a' to the metal pattern M2e' in the first direction may be equal to each other. Further, the lengths of the metal pattern M2a' to the metal pattern M2e' in the second direction (i.e., the Y direction) may be equal to each other. In an example, the metal pattern M2a', the metal pattern M2b', the metal pattern M2c', and the metal pattern M2e' may correspond to an input wiring pattern. For example, the first input signal A can be applied to the metal pattern M2a' and the metal pattern M2c', the second input signal B can be applied to the metal pattern M2b', and the third input signal Cin can be applied to the metal pattern M2e. '. In an example, the metal pattern M2d' may correspond to an output wiring pattern. For example, the output signal Cout can be output from the metal pattern M2d'.

The integrated circuit 400'' may further include a third via hole V2 and a third metal layer M3 on the third via hole V2. The third via holes V2 may be disposed on the metal pattern M2a' of the second metal layer M2 and on the metal pattern M2c', respectively. The third metal layer M3 may extend in the first direction and may be disposed on the third via hole V2 such that the metal pattern M2a' and the metal pattern M2c' may be electrically connected to each other.

FIG. 30 illustrates a layout of an integrated circuit 500 in accordance with an example.

Referring to FIG. 30, the integrated circuit 500 may include a first active area AR1 and a second active area AR2, a plurality of gate lines GL, a first contact window jumper 510 to a third contact window jumper 530, and a first pass. Hole V0 and first metal layer M1. In an example, the first contact window jumper 510 to the third contact window jumper 530 can be implemented using a first contact window CA, as depicted in Figures 2A and 3. In an example, the first contact window jumper 510 to the third contact window jumper 530 can be implemented using the first contact window CA and the second contact window CB, as illustrated in FIGS. 4 and 5. In an example, the first contact window jumper 510 to the third contact window jumper 530 can be implemented using trench germanium, first contact window CA, and/or second contact window CB, as shown in FIG. 6 and 7 is drawn. In an example, the first contact window jumper 510 to the third contact window jumper 530 can be implemented using the first contact window CA and the third contact window CM, as illustrated in FIGS. 8-10.

The first contact window jumper 510 can have a T-shape including a first portion and a second portion, the first portion crossing the first gate line 540 above the first active region AR1 and the second portion at the first gate line 540 The upper portion extends in the second direction (eg, the Y direction) and is connected to the first portion. The second contact window jumper 520 can intersect the first gate line 540 above the second active area AR2. Therefore, the first gate line 540 can be a dummy gate line.

The third contact window jumper 530 may have an I-shape including a first portion, a second portion, and a third portion, the first portion crossing the second gate line 550 above the first active region AR1, and the second portion being at the second portion The active region AR2 crosses the second gate line 550, and the third portion extends over the second gate line 550 in the second direction and is connected to the first portion and the second portion. Therefore, the second gate line 550 can be a dummy gate line.

In an example, the first contact windows CA disposed above the first active area AR1 may be aligned with each other along the first line L1. In an example, the second contact windows CB disposed above the intermediate region MR may be aligned with each other along the second line L2. In an example, the first contact windows CA disposed above the second active area AR2 may be aligned with each other along the third line L3.

The first through holes V0 may be disposed on some of the first contact windows CA and some of the second contact windows CB. In an example, the first vias V0 may be formed in a pattern of the same shape. In an example, the first vias V0 disposed above the first active region AR1 may be aligned with each other along the first line L1. In an example, the first through holes V0 disposed above the intermediate region MR may be aligned with each other along the second line L2. In an example, the first via holes V0 disposed above the second active region AR2 may be aligned with each other along the third line L3.

The first metal layer M1 may include a first metal pattern M1a′′ extending in the first direction above the first active region AR1 and a second metal pattern M1b′′ extending in the first direction above the second active region AR2 And a third metal pattern M1c'' extending in the second direction above the intermediate region MR. Therefore, the number of horizontal metal patterns in the standard cell can be limited to two. The first metal pattern M1a'' may connect the first contact windows CA on the first active area AR1 to each other, and the second metal pattern M1b'' may connect the first contact windows CA on the second active area AR2 to each other, and The three metal patterns M1c'' may be respectively connected to the second contact windows CB on the intermediate region MR. In an example, in the third metal patterns M1c'', the third metal patterns M1c'' disposed above the second contact window CB may have the same height in the second direction.

FIG. 31 illustrates a storage medium 1000 in accordance with an example.

Referring to FIG. 31, the storage medium 1000 may store a cell library 1100, a configuration and routing (P&R) program 1200, a static timing analysis (STA) program 1300, and layout data 1400. The storage medium 1000 can be a computer readable storage medium and can include any storage medium that can be read by the computer during use to provide instructions and/or data to the computer. For example, the storage medium 1000 may include a magnetic storage medium or an optical recording medium (eg, a disc, a cassette, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD-R, or a DVD-RW), and is volatile. Or non-volatile memory (such as RAM, ROM or flash memory), non-volatile memory accessible via USB interface, and microelectromechanical system (MEMS). The computer readable storage medium can be embedded in a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and/or wireless link.

The cell library 1100 may be a standard cell library and may include information about a standard cell as a unit constituting the integrated circuit. In an example, the information about the standard unit may include layout information for layout generation. In an example, information about standard cells may include timing information for layout verification or simulation. In particular, the cell library 1100 may include layout information regarding standard cells as described above with reference to FIGS. 1 through 30.

The P&R program 1200 can include instructions for implementing configuration and routing of standard cells by using the cell library 1100. The STA program 1300 may include an instruction for executing a STA, and the STA is an analog method of calculating an expected timing of the digital circuit, and may perform timing analysis on all timing paths of the arranged standard cells and output timing analysis results. The layout data 1400 can include entity information regarding the layout generated by the configuration and routing operations.

As is conventional in the art, the blocks described above that perform one or more functions may be via analog and/or digital circuits (eg, logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits). Physically implemented, passive electronic components, active electronic components, optical components, fixed-line circuits, etc., and selectively driven by firmware and/or software. The circuit can be implemented, for example, in one or more semiconductor wafers, or can be implemented on a substrate support such as a printed circuit board or the like. The circuitry constituting the block may be implemented by a dedicated hardware or processor, such as one or more programmed microprocessors and associated circuitry, or may be implemented by a combination of dedicated hardware and processors. Some functions of the block are performed by the dedicated hardware, while other functions of the block are performed by the processor. Each of the blocks in this example can be physically divided into two or more interacting and discrete blocks without departing from the scope of the inventive concept. Similarly, the blocks in this example can be physically combined into more complex blocks without departing from the scope of the inventive concept.

32 is a flow chart showing a method of fabricating a semiconductor device, according to an example.

Referring to Fig. 32, a method of manufacturing a semiconductor device can be divided into a design of an integrated circuit and a manufacturing process of an integrated circuit. The design of the integrated circuit includes an operation S110 and an operation S130, and the manufacturing process of the integrated circuit includes an operation S150 and an operation S170, and the operation S150 and the operation S170 are operations for manufacturing the semiconductor device according to the integrated circuit based on the layout data, and It can be performed by a semiconductor manufacturing module.

In operation S110, a synthesizing operation is performed. For example, operation S110 can be performed by the processor using a synthesis tool. Specifically, the input data defined by the register transfer level (RTL) of an integrated circuit can be synthesized by using a standard cell library (for example, the standard cell library 1100 in FIG. 31), thereby generating a gate. A gate-level netlist.

In operation S130, standard cells defining an integrated circuit according to the net list are arranged and wired to generate layout data of the integrated circuit. For example, operation S130 can be performed by the processor using the P&R tool. For example, the layout data may be data in a graphic design system (GDS) II format. Specifically, as shown in FIG. 1 to FIG. 30, layout data can be generated by arranging standard cells having a reduced (ie, relatively small) height and including contact window jumpers, thereby The overall size (footprint) of the integrated circuit is minimized. After operation S130, a parasitic component extraction operation, a STA operation, and the like may be further performed.

In operation S150, one or more masks are generated based on the layout data. Specifically, optical proximity correction (OPC) can be performed based on the layout data. OPC means a process of changing the layout by reflecting errors due to optical proximity effects. One or more masks can then be fabricated in accordance with a layout that is altered based on the results of the OPC. In this case, one or more masks can be fabricated by using a layout that reflects the OPC, such as the GDS II in which the OPC is reflected.

In operation S170, one or more masks are used to fabricate a semiconductor device in which an integrated circuit has been implemented. Specifically, various semiconductor processes are performed on a semiconductor substrate (eg, a wafer) by using a plurality of masks to form a semiconductor device in which an integrated circuit has been implemented. For example, a process using a mask can be referred to as a patterning process by a lithography process. A desired pattern can be formed on the semiconductor substrate or on the material layer by a patterning process. The semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, and the like. Moreover, the semiconductor process can include a packaging process for mounting a semiconductor device on a printed circuit board (PCB) and sealing the semiconductor device via a sealing material, and can include a test process for testing the semiconductor device or semiconductor package.

33 is a block diagram of an integrated circuit design system 2000 in accordance with an example.

Referring to FIG. 33, the integrated circuit design system 2000 may include a processor 2100, a memory 2300, an input/output (I/O) device 2500, a storage device 2700, and a bus bar 2900. The integrated circuit design system 2000 can be provided as a dedicated device for designing an integrated circuit of a semiconductor device, but can also be a computer for driving various simulation tools or design tools.

The processor 2100 can be used to execute instructions to implement at least one of various operations for designing an integrated circuit. The processor 2100 can communicate with the memory 2300, the I/O device 2500, and the storage device 2700 via the bus 2900. The processor 2100 can perform an operation of generating layout data of the integrated circuit by driving the P&R module 2310 loaded to the memory 2300. The memory 2300 can store the P&R module 2310. In addition, the memory 2300 can further store a synthesis module, a parasitic component extraction module, and/or a timing analysis module. The P&R module 2310 can be loaded from the storage device 2700 into the memory 2300. The memory 2300 can be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as PRAM, MRAM, ReRAM, FRAM or NOR flash memory.

I/O device 2500 can control user input and user output from a user interface device. For example, I/O device 2500 can include input devices such as a keyboard, mouse, or trackpad to receive input data defining integrated circuits. The storage device 2700 can store various data related to the P&R module 2310. The storage device 2700 can include a memory card (MMC, eMMC, SD, MicroSD, etc.), a solid state drive (SSD), and/or a hard disk drive (HDD).

The present invention has been described with reference to the embodiments thereof, and it is understood that the scope of the present invention may be modified in various forms and details without departing from the spirit and scope of the invention. It is subject to the definition of the scope of the patent application attached.

10, 10', 10a, 10b, 10c, 10d, 20, 30, 40, 50, 60, 70, 80, 100, 100', 100", 100a, 100b, 200, 200', 200", 300 , 300', 300'', 400, 400', 400'', 500‧‧‧ integrated circuits

110, 210, 310, 510‧‧‧ first contact window jumper

120, 220, 320, 520‧‧‧ second contact window jumper

130, 230, 330, 420, 540‧‧‧ first gate line

410‧‧‧Contact window jumper

530‧‧‧3rd contact window jumper

550‧‧‧second gate line

1000‧‧‧Storage media

1100‧‧‧cell library

1200‧‧‧P&R procedure

1300‧‧‧STA procedure

1400‧‧‧ Layout data

2000‧‧‧Integrated Circuit Design System

2100‧‧‧ processor

2300‧‧‧ memory

2310‧‧‧P&R module

2500‧‧‧I/O devices

2700‧‧‧Storage device

2900‧‧ ‧ busbar

A, A0‧‧‧ first input signal

A1, B‧‧‧ second input signal

ADD‧‧‧Adder

AF‧‧‧active fins

AR1‧‧‧First active area

AR2‧‧‧Second active area

B0‧‧‧ third input signal

B1‧‧‧ fourth input signal

CA‧‧‧ first contact window

CB‧‧‧Second contact window

Cin‧‧‧ third input signal

Cout‧‧‧ output signal

CJ1, CJ1', CJ1a‧‧‧ first contact window jumper

CJ2, CJ2', CJ2''‧‧‧ second contact window jumper

CJ3, CJ3'‧‧‧ third contact window jumper

CJ4‧‧‧4th contact window jumper

CJ5‧‧‧5th contact window jumper

CM‧‧ Third contact window

CT, CT’‧‧‧ cutting area

DF‧‧‧Dummy fins

GI‧‧‧gate insulating film

GL‧‧‧ gate line

GL1‧‧‧ first gate line

GL2‧‧‧second gate line

GS‧‧‧ gate structure

H, H1, H2, H3, H4, H5, H', H1', H2', H3', H4', H5'‧‧‧ height

ILD‧‧‧ interlayer dielectric layer

IRT‧‧‧Input wiring pattern, internal wiring pattern

L1‧‧‧ first line

L2‧‧‧ second line

L3‧‧‧ third line

M1‧‧‧ first metal layer

M1a, M1a’, M1a’’‧‧‧ first metal pattern

M1b, M1b', M1b’'‧‧‧ second metal pattern

M1c, M1c’, M1c’’‧‧‧ Third metal pattern

M2‧‧‧ second metal layer

Metal patterns of M2a, M2a', M2b, M2b', M2c, M2c', M2d, M2d', M2e, M2e'‧‧

M3‧‧‧ third metal layer

MR‧‧‧Intermediate area

MTa, MTb‧‧‧ path

NM1‧‧‧First NMOS transistor

NM2‧‧‧Second NMOS transistor

NM3‧‧‧ third NMOS transistor

NM4‧‧‧4th NMOS transistor

ORT‧‧‧ output wiring pattern

PM1‧‧‧First PMOS transistor

PM2‧‧‧Second PMOS transistor

PM3‧‧‧ Third PMOS transistor

PM4‧‧‧fourth PMOS transistor

PT1, PT1', PT1a‧‧‧ first conductive pattern

PT2, PT2', PT2'', PT2''', PT2a‧‧‧ second conductive pattern

PT3, PT3'‧‧‧ third conductive pattern

PWR1‧‧‧First power supply area

PWR2‧‧‧second power supply area

SC1‧‧‧ first standard unit

SC2‧‧‧Second standard unit

SCa, SCa_1, SCa_1a, SCa_1b, SCa_2, SCa_3, SCb, SCb_1‧‧‧ standard units

SP‧‧‧Insulation spacer

SUB‧‧‧Base

TS‧‧‧ trench telluride

V0‧‧‧ first through hole

V0’‧‧‧through hole

V1‧‧‧ second through hole

V2‧‧‧ third through hole

VDD‧‧‧Power supply voltage pattern

VSS‧‧‧ Ground voltage pattern

Y‧‧‧ output signal

X1a-X1a', X1b-X1b', X2a-X2a', X2b-X2b', X3a-X3a', X3b-X3b', X4a-X4a', X4b-X4b', X5a-X5a', X5b-X5b', X6a-X6a', X6b-X6b', X7a-X7a', X7b-X7b', X8a-X8a', X8b-X8b'‧‧‧

In order to make the concept of the present invention more obvious and obvious, the following specific embodiments are described in detail below with reference to the accompanying drawings: FIG. 1 illustrates a first standard unit and a second standard unit having different heights. Fig. 2A is a plan view showing an example of an integrated circuit according to the concept of the present invention. Fig. 2B is a plan view showing another example of the integrated circuit according to the concept of the present invention. Fig. 3 is a cross-sectional view showing portions of the integrated circuit of Fig. 2A taken along a line X1a-X1a' and a line X1b-X1b' in Fig. 2A. Fig. 4 is a plan view showing an example of an integrated circuit according to the concept of the present invention. Figure 5 is a cross-sectional view taken along the line X2a-X2a' and the line X2b-X2b' in Figure 4 . Figure 6 is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Fig. 7 is a cross-sectional view taken along the line X3a-X3a' and the line X3b-X3b' in Fig. 6. Figure 8 is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Figure 9 is a cross-sectional view taken along the line X4a-X4a' and the line X4b-X4b' in Figure 8 . Figure 10 is a perspective view of the integrated circuit of Figure 8. Figure 11 is a plan view showing an example of an integrated circuit according to the concept of the present invention. Figure 12 is a cross-sectional view taken along the line X5a-X5a' and the line X5b-X5b' in Figure 11 . 13, 14, 15, 16, 17, 18, and 19 are plan views of an example of an integrated circuit according to the concept of the present invention. Figure 20A illustrates the notation of an example of a standard unit. Figure 20B is a circuit diagram of the standard cell of Figure 20A. Figure 21A is a plan view showing an example of an integrated circuit according to the concept of the present invention. 21B is a plan view showing an example of an integrated circuit further including a first metal layer as compared with FIG. 21A. 21C is a plan view showing an example of an integrated circuit further including a second metal layer as compared with FIG. 21B. Figure 22 is a cross-sectional view taken along the line X6a-X6a' and the line X6b-X6b' in Figure 21C. Figure 23A is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Figure 23B is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Fig. 24A is a plan view showing an example of an integrated circuit according to the concept of the present invention. Figure 24B is a plan view showing an example of an integrated circuit including a first metal layer in comparison with Figure 24A, in accordance with the teachings of the present invention. Fig. 24C is a plan view showing an example of an integrated circuit according to the concept of the present invention, which further includes a second metal layer as compared with Fig. 24B. Figure 25 is a cross-sectional view taken along the line X7a-X7a' and the line X7b-X7b' in Figure 24C. Figure 26A is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Figure 26B is a plan view showing an example of an integrated circuit according to the concept of the present invention, which further includes a first metal layer as compared with Figure 26A. Figure 26C is a plan view showing an example of an integrated circuit according to the concept of the present invention, which further includes a second metal layer as compared with Figure 26B. Figure 27 is a cross-sectional view taken along the line X8a-X8a' and the line X8b-X8b' in Figure 26C. Figure 28A shows the notation of the adder. Figure 28B is a logic circuit diagram of an adder including standard cells. Figure 29A is a plan view showing an example of an integrated circuit in accordance with the concept of the present invention. Figure 29B is a plan view showing an example of an integrated circuit according to the concept of the present invention, which further includes a first metal layer as compared with Figure 29A. Figure 29C is a plan view showing an example of an integrated circuit according to the concept of the present invention, which further includes a second metal layer as compared with Figure 29B. Figure 30 is a plan view showing an example of an integrated circuit according to the concept of the present invention. 31 is a block diagram of a storage medium that can include integrated circuits in accordance with the teachings of the present invention. 32 is a flow chart showing an example of a method of fabricating a semiconductor device in accordance with the teachings of the present invention. Figure 33 is a block diagram showing an integrated circuit design system for designing an integrated circuit in accordance with the teachings of the present invention.

Claims (25)

An integrated circuit comprising: a first active region and a second active region each extending in a first direction; a first gate line extending longitudinally across a second direction substantially perpendicular to the first direction The first active region and the second active region; and a first contact window jumper comprising a first conductive pattern crossing the first gate line over the first active region and A first conductive line extends longitudinally in the second direction and is connected to the second conductive pattern of the first conductive pattern. The integrated circuit of claim 1, wherein the first active region and the second active region are spaced apart in the second direction, such that the first active region and An intermediate region exists between the second active regions in the second direction, and the second conductive pattern extends over the intermediate region between the first active region and the second active region, And the integrated circuit further includes a through hole disposed on the second conductive pattern at a position above the intermediate portion. The integrated circuit of claim 1, wherein the first contact window jumper further comprises a third conductive pattern, the third conductive pattern being over the second active area and the first The gate lines are crossed and connected to the second conductive pattern. The integrated circuit of claim 3, further comprising at least one second gate line parallel to the first gate line, wherein the third conductive pattern and the first gate line The at least one second gate line intersects. The integrated circuit of claim 1, further comprising a second contact window jumper, the second contact window jumper crossing the first gate line above the second active area And being separated from the first contact window jumper. The integrated circuit of claim 1, further comprising: at least one second gate line parallel to the first gate line; and a second contact window jumper, at the second active The upper portion of the region intersects the first gate line and the at least one second gate line and is spaced apart from the first contact window jumper. The integrated circuit of claim 1, further comprising: at least one second gate line parallel to the first gate line; and a second contact window jumper, at the second active An upper portion of the region intersects with the first gate line and is separated from the first contact window jumper, wherein the first conductive pattern and the first gate line and the at least one second gate Polar line crossing. The integrated circuit of claim 1, further comprising: a first contact window on the first active area; and a first metal pattern on the first side above the first active area Extending upwardly and disposed above the first contact window and electrically connecting the first contact window. The integrated circuit of claim 8, further comprising: a second contact window on the second active area; and a second metal pattern on the first side above the second active area Extending upwardly and disposed above the second contact window and electrically connecting the second contact window, wherein the second metal pattern is disposed in the integrated circuit at a level opposite to the first metal pattern The height is the same level. The integrated circuit of claim 1, wherein the first active region and the second active region are spaced apart in the second direction, such that the first active region and An intermediate region exists between the second active regions in the second direction, and the second conductive pattern extends over the intermediate region between the first active region and the second active region, The integrated circuit further includes: a plurality of second gate lines parallel to the first gate line; a first via hole between the first active region and the second active region a position above the intermediate portion is disposed on the second conductive pattern; a second through hole on the plurality of second gate lines in the intermediate portion; and a metal pattern in the first through hole And the second through hole and extending in the second direction. The integrated circuit of claim 10, wherein the metal patterns on the plurality of second via holes have substantially the same width in the first direction, and the second via holes The metal patterns have substantially the same length in the second direction. The integrated circuit of claim 10, wherein the first through hole and the second through hole are aligned in the first direction. The integrated circuit of claim 10, wherein the first conductive pattern intersects at least one of the second gate lines. The integrated circuit of claim 1, wherein the first conductive pattern comprises a first contact window on the first active region, and the second conductive pattern comprises the first gate line The second contact window. The integrated circuit of claim 1, further comprising a first trench germanide and a second trench germanide, wherein the first trench germanide and the second trench germane are Two sides of the first gate line in the first active region and extending in the second direction, wherein the first conductive pattern includes the first trench germanide and the second trench a first contact window on the trench germanium, and the second conductive pattern includes a second contact window on the first gate line. The integrated circuit of claim 1, further comprising a first contact window and a second contact window, wherein the first contact window and the second contact window are in the first active area Two sides of the first gate line, wherein the first conductive pattern is disposed on the first contact window and the second contact window and electrically the first contact window and the second contact window Connected, and the second conductive pattern is electrically isolated from the first gate line. An integrated circuit comprising: a first active area and a second active area, each extending in a first direction and spaced apart in a second direction substantially perpendicular to the first direction, such that An intermediate region exists between the first active region and the second active region in the second direction; a first gate line and a second gate line are separated from each other in the first direction, the first Each of a gate line and the second gate line extends longitudinally across the first active region and the second active region and the intermediate region in the second direction; a wire member including a first conductive pattern crossing the first gate line above the first active region and extending longitudinally in the second direction over the first gate line and connected to the a second conductive pattern of the first conductive pattern; a first via hole and a second via hole in the first direction between the first active region and the second active region in the first direction Alignment, wherein the first via is disposed in the second conductive a pattern, and the second via is located above the second gate line; and the first metal layer includes a first metal pattern, a second metal pattern, and a plurality of third metal patterns, the first metal pattern Extending in the first direction above the first active region, the second metal pattern extending in the first direction over the second active region, the plurality of third metal patterns being The intermediate portion extends in the second direction and is disposed on the first through hole and the second through hole, respectively. The integrated circuit of claim 17, wherein the contact window jumper further comprises a third conductive pattern, the third conductive pattern being over the second active region and the first gate The line and the second gate line cross and are connected to the second conductive pattern. The integrated circuit of claim 18, wherein the third metal pattern has substantially the same width in the first direction, and the third metal pattern has a second direction in the second direction Substantially the same length. The integrated circuit of claim 18, further comprising: a third through hole respectively disposed on the third metal pattern; and a second metal layer, respectively disposed on the third through hole a fourth metal pattern, each of the fourth metal patterns extending longitudinally in the second direction, wherein the fourth metal pattern has substantially the same width in the first direction, and The fourth metal pattern has substantially the same length in the second direction. A semiconductor device comprising: a substrate having a first active region, a second active region, and an intermediate region, each of the first active region and the second active region extending in a first direction and substantially perpendicular to the Separating in a second direction of the first direction, the intermediate region being interposed between the first active region and the second active region in the second direction; a gate line, in the Separating from each other in a direction, each of the gate lines extending longitudinally across the first active region and the second active region and the intermediate region in the second direction; a layer of contact windows, On the substrate, and having a substantially coplanar upper surface at a level above the substrate, the one layer contact window comprising a contact window jumper, the contact window jumper comprising a first conductive a pattern and a second conductive pattern extending in the first direction and at least in the first direction and the gate line above the first active region of the substrate One crossed, said a second conductive pattern extending longitudinally from the first conductive pattern in the second direction over at least a portion of the intermediate portion of the substrate; a first layer of vias on the layer of contact windows Each of the through holes extends over an upper surface of a corresponding one of the contact windows, and the first layer through hole includes a top surface disposed over the intermediate portion of the substrate and at the a plurality of vias aligned with each other in a direction; and a first metallization layer on the first via via, wherein only one of the first metallization layers extends over the first active region And only one of the first metallization layers extends over the second active region, and each of the metal paths extends across the gate line in the first direction. The semiconductor device of claim 21, wherein the first metallization layer comprises a first metal pattern, a second metal pattern, and a third metal pattern, the first metal pattern being in the substrate The first active area extends longitudinally in the first direction and constitutes the metal path extending above the first active area, and the second metal pattern is above the second active area at the first Longitudinally extending in a direction and constituting the metal path extending over the second active region, each of the third metal patterns being longitudinally above the intermediate region of the substrate in the second direction And extending and disposed on one of the plurality of through holes. The semiconductor device of claim 21, wherein the second conductive pattern of the contact window jumper extends longitudinally above one of the gate lines in the second direction, and A first one of the plurality of via holes is disposed on the second conductive pattern so as to be disposed on the one of the gate lines at a position above the intermediate portion of the substrate. The semiconductor device of claim 22, further comprising a second layer via hole on the first metallization layer, wherein the via holes of the second layer are respectively disposed on the third metal pattern. The semiconductor device of claim 24, further comprising a second metallization layer on the second via hole, and comprising a plurality of discrete metals respectively disposed on the via holes of the second layer pattern.