TW201839952A - Micro-led display assembly - Google Patents

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a micro-LED display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

Description

 Micro-lighting diode display assembly  

The present invention relates to semiconductor structures, and more particularly to a micro-light-emitting diode display assembly and a method of fabricating the same.

The inorganic light-emitting diode (ILED) is a light-emitting diode made of a semiconductor material. The use of ILEDs has the potential to produce a variety of different colors, including red, green, yellow and blue. Operationally, the ILED will illuminate when a forward bias is applied to the P-N junction of the semiconductor material.

LED devices for display systems require high pixel placement densities on large surfaces. However, traditional LEDs manufacturing methods are a challenge to meet production requirements, especially for larger display sizes. Furthermore, the cost of next-generation displays will be higher due to poor wafer area utilization. With regard to this latter, the use of a single die for large LED displays and image sensor arrays will leave a large amount of unused space around the edge of the wafer in a portion of the field area.

In one aspect of the invention, the structure includes: an interposer; and a plurality of micro-light emitting diode arrays each including a plurality of through-connecting pixels of the plurality of micro-light emitting diode arrays to the interposer hole.

In one aspect of the invention, a structure includes: an interposer comprising a plurality of through holes; a plurality of micro-light emitting diode arrays each comprising each pixel connected to a plurality of micro-light emitting diode arrays a plurality of through holes; and a back-end of the line interposer including a wiring scheme that connects the through holes of each pixel to the through holes of the interposer.

In one aspect of the invention, a method includes: forming a plurality of through holes connected to a pixel of a micro light emitting diode array in a substrate; and a plurality of micro light emitting through a through hole aligned with the connection of the interposer The pixels of each of the diode arrays are connected to a single interposer.

10‧‧‧ pixels

12‧‧‧ electrodes

14a‧‧‧Subpixels

14b‧‧‧Subpixels

14c‧‧‧Subpixel

14d‧‧‧Subpixel

16‧‧‧Nami Line

20‧‧‧Microluminescent diode assembly

22‧‧‧Substrate

24‧‧‧through through hole

24a‧‧‧through through hole

26‧‧‧Metal pad

26a‧‧‧Metal pad

28‧‧‧ Coverage

30‧‧‧ Conductive terminal layer (Fig. 2) / interposer (Fig. 4, 5)

35‧‧‧BEOL wiring

45‧‧‧Microcolumn interconnection

50‧‧‧through through hole

55‧‧‧Welded connection

100a‧‧‧nGaN

100b‧‧‧InGaN

100c‧‧‧pGaN

100d‧‧‧Terminal layer

100e‧‧‧phosphorus layer

100f‧‧‧ color filter

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described by way of non-limiting examples of illustrative embodiments of the invention and reference to the plurality of drawings.

Figure 1 shows a pixel design in accordance with aspects of the present invention.

2 shows a cross section of a microluminescent diode assembly and corresponding fabrication process in accordance with an aspect of the present invention.

Figure 3 shows another structure and corresponding manufacturing procedure in accordance with aspects of the present invention.

4 shows a cross section of a micro-light emitting diode display assembly in accordance with aspects of the present invention.

Figure 5 shows a perspective view of a micro-light emitting diode display assembly in accordance with aspects of the present invention.

Figure 6 shows a flow chart of a manufacturing process in accordance with aspects of the present invention.

The present invention relates to semiconductor structures, and more particularly to a micro-light-emitting diode display assembly and a method of fabricating the same. More particularly, the present invention relates to a micro-light emitting diode display assembly consisting of a plurality of small micro-light emitting diode arrays placed in a larger array using through-via via technology. That is, the micro-light emitting diode display assembly uses a plurality of small crystal grains in an array to replace one large array. Microluminescent diode display assemblies can be used with, for example, 2.5D and 3D technologies.

In a specific embodiment, each of the small micro-light emitting diode arrays includes through silicon via (TSV) technology for mounting on a substrate to form a larger display assembly. In a specific embodiment, the TSVs are connected to each individual micro-light emitting diode (eg, a pixel). The TSV micro-light emitting diode array device can be connected using a germanium or glass interposer, or directly to a pixel driver. In a particular embodiment, the 矽 interposer allows for direct integration of the pixel drive circuitry; however, the glass interposer will require a separate pixel driver. In a particular embodiment, a plurality of small micro-light emitting diode arrays provide high density wiring to each TSV/micro-light emitting diode connection.

Advantageously, the micro-light emitting diode display assembly provides improved (e.g., high) yield for large display sizes compared to using a single, larger pixel array. This is due to the fact that multiple small grains can be assembled to collectively form a larger array of LEDs; rather than a single large die. More specifically, if a failure is found on a single large die, the entire die will need to be discarded; however, as disclosed herein, if a single failure is found on a smaller die, only a single smaller one will have to be discarded. Grain. This will significantly reduce costs and improve revenue, because in the case of pixel failure, discarding smaller grains is more cost effective than discarding larger grains.

In addition, more efficient use of space on the wafer can significantly reduce manufacturing costs. For example, using smaller dies makes it possible to more efficiently utilize unused space around the edge of the wafer. In addition, the micro-light-emitting diode display assembly described herein improves reliability by using an interposer, which acts as a stress buffer between the circuit board and the micro-emitting diode die.

The microluminescent diode display assembly of the present invention can be fabricated in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures having dimensions on the order of microns and nanometers. The method (i.e., technique) for fabricating the micro-light emitting diode display assembly of the present invention has been employed from integrated circuit (IC) technology. For example, a micro-light emitting diode display assembly is built on a wafer and implemented in a thin film of material patterned by an optical lithography process on top of the wafer. In particular, the fabrication of a wafer pad structure uses three basic components: (i) deposition of a thin film of material on the substrate, (ii) application of a patterned photomask to the top of the film by optical lithography, and (iii) The film is selectively etched to the reticle.

Figure 1 shows a single pixel in a micro-light emitting diode assembly for use in accordance with aspects of the present invention. It will be understood by those skilled in the art that Figure 1 (and other figures described herein) may also represent a layout pattern for any reproducible design (e.g., memory cell array, etc.). In Figure 1, pixel 10 includes a contact plate or electrode 12 having four sub-pixels 14a-14d. In a particular embodiment, for example, the contact plate or electrode 12 can be a nanowire contact and reflector plate composed of an opaque material such as a metal to maximize light emission from the sub-pixels 14a-14d.

In a particular embodiment, pixel 10 has a size of 6.35 [mu]m x 6.35 [mu]m and sub-pixels 14a-14d have a size of 3.175 [mu]m x 3.175 [mu]m; however other sizes are contemplated herein. As will be understood by those skilled in the art, a plurality of these pixels 10 can be formed on a single micro-light emitting diode assembly in accordance with aspects of the present invention. For example, the micro-light emitting diode assembly implemented herein can comprise 1000 pixels multiplied by 1000 pixels; however, other pixel numbers can be considered herein depending on the technology or tool of assembly.

Still referring to FIG. 1, in an illustrative example, subpixels 14a-14d include RGB pixel designs for use in inorganic light emitting diodes (ILEDs). In a particular embodiment, each of the sub-pixels 14a-14d can have a different number of nanowires 16 that are composed of different materials to emit a particular color (eg, wavelength). In a non-limiting example, (i) for green light, there may be four nanowires 16 for sub-pixels 14a, 14d, (ii) for blue light, there may be nine nanowires 16 for sub-pictures For the 14b, and (iii) for red light, there may be four nanowires for the sub-pixel 14c. Although sub-pixel 14d is shown as redundant for sub-pixel 14a, it should be understood that sub-pixel 14d may be redundant for any of sub-pixels 14a-14c. Alternatively, sub-pixel 14d may be empty, such as without any nanowires.

Although not critical to the understanding of the invention, the nanowires 16 can be composed of different materials to provide different wavelengths. For example, Table 1 below shows an exemplary combination of semiconductor materials that can be used for nanowires.

2 shows a cross section of a microluminescent diode assembly and corresponding fabrication process in accordance with an aspect of the present invention. As shown in FIG. 2, the micro-light-emitting diode assembly 20 includes sub-pixels 14a, 14b, each of which has a plurality of nanowires 16. In the illustrated example, the cross section of the micro-light-emitting diode assembly 20 shows the sub-pixels 14a, 14b of each pixel 10a, 10b.

As further shown in FIG. 2, the micro-light-emitting diode assembly 20 further includes a substrate 22 having a plurality of TSVs 24 connected to a metal pad 26 electrically connected to each of the pixels 10a, 10b (eg, sub-pixels 14a, 14b). (eg copper pad). As shown, each pixel uses a single TSV 24, where the diameter of the TSV 24 is approximately 1/2 of the pixel pitch. For example, in an illustrative embodiment, TSV 24 may have a diameter/width of less than about 3 [mu]m for pixels having a pitch of about 6 [mu]m; however, thinner grains may have smaller dimensions. In a particular embodiment, pad 26 can be in direct electrical communication with pGaN sub-pixels 14a, 14b, and all pixels share overlay nGaN connections 28, and vice versa. In this representation, pad 26a and TSVs 24a can be connected to conductive terminal layer 30. As such, there is no need for separate TSVs or conductive terminals for each pixel.

Figure 3 shows another structure and corresponding manufacturing procedure in accordance with aspects of the present invention. In this configuration, the pixel 10 is schematically represented as a stacked structure composed of a plurality of layers 100a-100f, each of which is connected to a TSV 24 formed in a substrate 22. In a specific embodiment, the layer comprises: nGaN 100a, InGaN 100b, pGaN 100c, terminal layer 100d, phosphor layer 100e, and color filter 100f. It will be appreciated that these layers are provided as illustrative examples and should not be considered as limiting features of the invention. To simplify the description, the common pGaN terminals wired to the individual TSVs are not shown.

In each of Figures 2 and 3, the ILED wafers are individually formed and bonded to a TSV carrier wafer (e.g., wafer 22). Furthermore, the formation of the TSVs 24 can be via a conventional backgrinding process and then via a deep etch (eg, Bosch etch) to form vias aligned with and exposed to the pads formed on the front side of the wafer (and its versus pixel) Electrical contact). The via is then coated with a dielectric liner such as an inorganic material such as SiO ₂ . In a particular embodiment, the dielectric liner will be deposited to a thickness of about 200 nm; however, other thicknesses are contemplated herein. A barrier metal (such as Ta or TiN) can be formed on the dielectric liner to prevent copper from diffusing to the oxide layer and the wafer. The seed layer can be sputtered onto the barrier metal and then subjected to an electroplating process, such as a copper electroplating process. Any remaining material can be removed by a chemical mechanical grinding step. It should be understood that reference numeral 24 denotes a different material within the via itself.

4 shows a cross section of a micro-light emitting diode display assembly in accordance with aspects of the present invention. More specifically, FIG. 4 shows a plurality of micro-light emitting diode assemblies 20 mounted on the interposer 30. In a specific embodiment, the interposer 30 can be a germanium interposer composed of an integrated ILED pixel driving circuit. In other embodiments, the interposer 30 can be a glass interposer or an active die. In a particular embodiment, a plurality of micro-light emitting diode assemblies 20 (eg, at least two ILED dies comprising TSV interconnects) are placed equidistantly on interposer 30, as further described herein.

The back end of the process (BEOL) wiring 35 is (for example, bonded) between the plurality of micro-light-emitting diode assemblies 20 and the interposer 30. In a specific embodiment, the BEOL wiring 35 includes a wiring scheme that electrically connects each of the pixels 10 of the plurality of micro-light-emitting diode assemblies 20 to the interposer 30. More specifically, each of the TSVs 24 of each pixel of each micro-light-emitting diode assembly 20 is connected to a micropillar interconnect 45, which in turn is connected to the wiring scheme of the BEOL wiring 35. . In a particular embodiment, the pitch of the micro-pillar interconnects 45 will match the TSVs 24, such as a 5-10 [mu]m pitch. It will be understood by those skilled in the art that the micro-pillar interconnect 45 can be a conventional controlled flip-chip bonding (C4) solder interconnect. In other embodiments, a plurality of micro-light emitting diode assemblies 20 can be group soldered to the BEOL wiring 35.

Still referring to FIG. 4, the wiring scheme of the BEOL wiring 35 is connected to a plurality of TSVs 50 of the interposer 30. The TSVs 50 of the interposer 30 can be fabricated by the same method as the TSVs 24 of each pixel of the micro-light-emitting diode assembly 20. In a specific embodiment, when a plurality of TSVs 50 of the interposer 30 are connected, the cross-grain pixel pitch/pitch "X" is preferably equal to the intra-grain pixel pitch/pitch "X''' to avoid damaging the whole. The display of the pixel array. In other embodiments, the interposer 30 includes a solder connection 55 that is electrically coupled to the TSVs 50 of the interposer 30. Thus, the solder connection 55 provides external interconnection to the micro-light-emitting diode assembly 20. .

Figure 5 shows a perspective view of a micro-light emitting diode display assembly in accordance with aspects of the present invention. More specifically, FIG. 5 shows a plurality of micro-light emitting diode assemblies 20 mounted on the interposer 30. In a particular embodiment, a plurality of micro-light emitting diode assemblies 20 (eg, at least two ILED dies) each comprise a plurality of light emitting diode pixels 10 having TSV interconnects that are equally spaced in the intermediary On layer 30. The BEOL interposer 35 is located between the plurality of micro-light-emitting diode assemblies 20 and the interposer 30. Interposer 30 includes solder connections 55 to provide external interconnection to micro-light emitting diode assembly 20.

Figure 6 shows a flow chart of a manufacturing process in accordance with aspects of the present invention. In particular, to fabricate the structure illustrated in Figures 2 through 5, an LED device (e.g., pixel 10) is fabricated on the wafer using a conventional CMOS process in step 600. At step 605, the wafer is flipped and a backgrinding process is performed. In a particular embodiment, the backside grinding process can thin the wafer (e.g., tantalum) to about 50 microns. At step 610, the backside of the wafer is then etched (ie, Bosch etched) to form vias that align with and expose the pads formed on the front side of the wafer (and that are in electrical contact with the pixels). In step S615, a dielectric liner is formed in the via. The dielectric liner can be, for example, an organic spin-on material (SiCOH) or a polyimide material. In a particular embodiment, the dielectric liner will be deposited to a thickness of about 200 nm. At step 620, barrier metal may be formed on the dielectric liner to prevent copper from diffusing to the oxide layer and the wafer. In a specific embodiment, the barrier metal may be Ta or TiN deposited by a sputtering chemical vapor deposition process. At step 625, an electroplating process is performed. For example, the seed layer is sputtered onto the barrier metal and then the via is filled with an electroplating process such as a copper electroplating process. At step 630, any remaining material may be removed from the back surface of the wafer by a chemical mechanical polishing (CMP) process. At step 635, an interconnect can be formed that is electrically coupled directly to the metal material of the TSV. At step 640, for example, the micro-light emitting diode arrays can be assembled into a larger array by attaching each micro-light emitting diode array to the interposer.

The above method is used in the fabrication of integrated circuit wafers. The formed integrated circuit wafer can be dispensed by the manufacturer in the form of an original wafer (i.e., as a single wafer having a plurality of unpackaged wafers) as a bare die, or as a package. In the latter case, the wafer is mounted in a single wafer package (eg, a plastic carrier with leads attached to a motherboard or other higher level carrier) or in a multi-chip package (eg, with surface interconnects or buried interconnects) One or both of them are ceramic carriers). In any event, the wafer is then integrated with other wafers, discrete circuit components, and/or other signal processing devices as part of either (a) an intermediate product (such as a motherboard) or (b) an end product. The final product can be any product that includes integrated circuit chips ranging from toys or other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

The description of the various embodiments of the invention has been presented for purposes of illustration Many modifications and variations will be apparent to those of ordinary skill in the art. The terms used herein are chosen to best explain the principles of the specific embodiments, the actual application, or technical modifications of the techniques found in the market, or to enable those of ordinary skill in the art to understand the specific embodiments disclosed herein. .

Claims (20)

 A structure comprising: an interposer; and a plurality of micro-light emitting diode arrays each comprising a plurality of vias connecting the plurality of pixels of the plurality of micro-light emitting diode arrays to the interposer.    The structure of claim 1, wherein the interposer is a buffer interposer having a plurality of driving circuits.    The structure of claim 1, wherein the interposer is a glass interposer.    The structure of claim 1, wherein the through holes are through-through holes.    The structure of claim 4, wherein each of the pixels is connected to the interposer by a separate through-hole technique.    The structure of claim 1, wherein the pixels are composed of GaN, and the through holes are copper through-holes integrated into a same crystal grain as the pixels.    The structure of claim 1, wherein the through holes are connected to the interposer by a plurality of micro-pillars that match a pitch of the through holes.    The structure of claim 1, wherein the plurality of micro-light emitting diode arrays are equally spaced on the interposer.    The structure of claim 8, wherein a cross-grain pixel pitch/pitch is equal to a pixel pitch/pitch in each of the plurality of micro-light emitting diode arrays.    The structure of claim 1, wherein a diameter of the through holes is about one-half of a pixel pitch.    A structure comprising: an interposer comprising a plurality of through holes; a plurality of micro-light emitting diode arrays each comprising a plurality of through holes connected to each of the plurality of micro-light emitting diode arrays; And a back-end process interposer comprising a wiring scheme for connecting the through-holes of each of the pixels to the through-holes of the interposer.    For example, the structure described in claim 11 of the patent application, wherein. The plurality of micro-light emitting diode arrays are equally spaced apart; and a cross-grain pixel pitch/pitch is equal to a pixel pitch in each of the plurality of micro-light emitting diode arrays/ spacing.    The structure of claim 12, wherein the pixels are composed of GaN, and the through holes are copper through-holes integrated into a same crystal grain as the pixels.    The structure of claim 13, wherein the through-holes are connected to the back-end process interposer by a plurality of micro-pillars.    The structure of claim 14, wherein the microcolumns are welded connections.    The structure of claim 14, wherein the microcolumns are matched to a pitch of the through holes.    The structure of claim 13, wherein each of the through holes has a diameter of about one-half of a pixel pitch.    The structure of claim 11, wherein the interposer is a tantalum interposer having a plurality of driving circuits.    The structure of claim 11, wherein the interposer is a glass interposer.    A method comprising: forming a plurality of through holes connected to a plurality of pixels of a plurality of micro light emitting diode arrays in a substrate; and the plurality of micro holes aligned in a connection with a single interposer, the plurality of micro holes The pixels of each of the array of light emitting diodes are connected to the interposer.