TW201838771A - Carrier for double-side polishing device, double-side polishing device arranged by use thereof, and double-side polishing method - Google Patents

Carrier for double-side polishing device, double-side polishing device arranged by use thereof, and double-side polishing method Download PDF

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Publication number
TW201838771A
TW201838771A TW106140846A TW106140846A TW201838771A TW 201838771 A TW201838771 A TW 201838771A TW 106140846 A TW106140846 A TW 106140846A TW 106140846 A TW106140846 A TW 106140846A TW 201838771 A TW201838771 A TW 201838771A
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Taiwan
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carrier
double
side polishing
semiconductor wafer
polishing apparatus
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TW106140846A
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Chinese (zh)
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淺井一將
高野智史
古川大輔
轟翔
木田隆廣
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日商信越半導體股份有限公司
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Publication of TW201838771A publication Critical patent/TW201838771A/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/27Work carriers
    • B24B37/28Work carriers for double side lapping of plane surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

To provide a carrier for a double-side polishing device, which can prevent the worsening of the wafer shape while keeping improvement of the wafer surface imperfection when double-side polishing a semiconductor wafer; a double-side polishing device arranged by use thereof; and a double-side polishing method. A carrier for a double-side polishing device is to be disposed between upper and lower flat plates with polishing cloth attached thereto in the double-side polishing device, and has one or more holding holes formed therein for holding a semiconductor wafer between the upper and lower flat plates in polishing. The surface of the carrier has a region covered with a DLC film and a region not covered with the DLC film. On each of upper and lower faces of the carrier, the region of no more than 30% of the area of one face of the carrier, which extends inward from the bottom of teeth of a gear in an outer periphery of the carrier, is covered with the DLC film.

Description

雙面研磨裝置用載體及使用此載體的雙面研磨裝置以及雙面研磨方法Carrier for double-side polishing apparatus, double-side polishing apparatus using the same, and double-side polishing method

本發明係關於一種於雙面研磨裝置中,於研磨半導體晶圓時用以支承半導體晶圓的雙面研磨裝置用載體。The present invention relates to a carrier for a double-side polishing apparatus for supporting a semiconductor wafer in polishing a semiconductor wafer in a double-side polishing apparatus.

於以雙面研磨裝置同時研磨半導體晶圓的兩面時,係藉由雙面研磨裝置用載體支承半導體晶圓。此載體形成為厚度較半導體晶圓薄,具有用以支承半導體晶圓的支承孔。半導體晶圓被支承於此支承孔內,藉由於上下定盤所貼附的研磨布而半導體晶圓自兩面被夾入,在於研磨面供給研磨劑的同時進行半導體晶圓的雙面研磨。When the both sides of the semiconductor wafer are simultaneously polished by the double-side polishing apparatus, the semiconductor wafer is supported by the carrier by the double-side polishing apparatus. The carrier is formed to be thinner than the semiconductor wafer and has a support hole for supporting the semiconductor wafer. The semiconductor wafer is supported in the support hole, and the semiconductor wafer is sandwiched between the both surfaces by the polishing cloth attached to the upper and lower fixed plates, and the semiconductor wafer is double-sided polished while the polishing surface is supplied with the polishing agent.

雙面研磨裝置用載體,若持續使用則載體的外周部將磨損而產生厚度差異。如此,若載體的厚度差異變大,則會產生雙面研磨後的半導體晶圓的形狀不穩定的問題。在此,為了使載體的磨損減少而使半導體晶圓的形狀穩定,而延長載體的壽命的目的,使用有於載體表面形成有DLC膜(diamond-like carbon film)的載體(例如專利文獻1)。The carrier for the double-side polishing apparatus, if continuously used, the outer peripheral portion of the carrier will be worn to cause a thickness difference. As described above, when the difference in thickness of the carrier is increased, the shape of the semiconductor wafer after double-side polishing is unstable. Here, in order to stabilize the shape of the semiconductor wafer to reduce the wear of the carrier and to extend the life of the carrier, a carrier having a diamond-like carbon film formed on the surface of the carrier is used (for example, Patent Document 1) .

藉由以如此附有DLC膜的載體將半導體晶圓加工(雙面研磨),被期待能夠使載體的硬度提升而載體的厚度、扭曲的變化變小而使晶圓形狀穩定,並延長載體壽命。 〔先前技術文獻〕By processing the semiconductor wafer (double-side polishing) with the carrier having the DLC film as described above, it is expected that the hardness of the carrier can be increased, the variation of the thickness and distortion of the carrier can be reduced, the wafer shape can be stabilized, and the carrier life can be extended. . [Previous Technical Literature]

專利文獻1:日本特開2011-143477號公報Patent Document 1: Japanese Laid-Open Patent Publication No. 2011-143477

但是,若是使用載體全表面實施有DLC覆膜的載體將半導體晶圓雙面研磨,則雖然晶圓的表面不良(傷痕、微粒)被改善,但有雙面研磨中對半導體晶圓的研磨劑的介入量大幅變化而晶圓形狀惡化的問題。However, if the semiconductor wafer is polished on both sides by using a carrier having a DLC film on the entire surface of the carrier, although the surface defects (scars, fine particles) of the wafer are improved, there is an abrasive for the semiconductor wafer in double-side polishing. The amount of intervention greatly changes and the shape of the wafer deteriorates.

本發明鑑於上述問題,提供一種雙面研磨裝置用載體,能夠於半導體晶圓的雙面研磨時,在改善晶圓表面不良的同時,防止晶圓形狀的惡化,以及使用此載體的雙面研磨裝置及雙面研磨方法。The present invention has been made in view of the above problems, and provides a carrier for a double-side polishing apparatus capable of preventing deterioration of a wafer surface while improving wafer surface defects during double-side polishing of a semiconductor wafer, and double-side polishing using the carrier. Device and double side grinding method.

為了解決上述問題,本發明提供一種種雙面研磨裝置用載體,係於雙面研磨裝置中,被配設於經貼附研磨布的上定盤與下定盤之間,且形成有一個以上的支承孔,用以支承於研磨時被夾於該上定盤與下定盤之間的半導體晶圓,其中該載體的表面具有披覆有DLC膜的區域、及未披覆有該DLC膜的區域,在該載體的上表面及下表面中,自該載體的外周的齒輪的齒底向內側,該載體的其中一面的面積的30%以下的區域披覆有該DLC膜。In order to solve the above problems, the present invention provides a carrier for a double-side polishing apparatus, which is disposed in a double-side polishing apparatus, and is disposed between an upper fixed plate and a lower fixed plate to which a polishing cloth is attached, and is formed with one or more a support hole for supporting a semiconductor wafer sandwiched between the upper and lower fixed plates during polishing, wherein a surface of the carrier has a region covered with a DLC film, and an area not covered with the DLC film In the upper surface and the lower surface of the carrier, the DLC film is coated on a region from the tooth bottom of the outer circumference of the carrier to the inner side of the carrier, and a region of 30% or less of the area of one side of the carrier.

若為如此的雙面研磨裝置用載體,則僅於厚度變化大的載體的外周部以DLC膜部分披覆,而能夠得到平坦而表面狀態良好的半導體晶圓。進一步,由於能夠縮小載體的厚度變動,而能夠使載體壽命提升。When the carrier for the double-side polishing apparatus is used, the outer peripheral portion of the carrier having a large thickness variation is partially covered with the DLC film, and a semiconductor wafer having a flat surface state and a good surface state can be obtained. Further, since the thickness variation of the carrier can be reduced, the life of the carrier can be improved.

此時,以該載體的上表面及下表面中的至少一面中,自該載體的外周的齒輪的齒底向內側,該載體的其中一面的面積的5%以上的區域披覆有該DLC膜為佳。At this time, in at least one of the upper surface and the lower surface of the carrier, the DLC film is coated on a region of 5% or more of the area of one side of the carrier from the tooth bottom of the outer periphery of the carrier. It is better.

若為如此,則能夠更加確實地一邊維持晶圓表面不良的改善,一邊防止晶圓形狀的惡化。If so, it is possible to more reliably prevent the deterioration of the wafer surface while preventing the deterioration of the wafer shape.

又於此時,以自該載體的外周的該齒輪的齒底,至該支承孔的該載體的外周側為止的區域披覆有該DLC膜為佳。Further, at this time, it is preferable that the DLC film is coated in a region from the tooth bottom of the gear on the outer circumference of the carrier to the outer peripheral side of the carrier of the support hole.

本發明能夠於如此的區域形成DLC膜,能夠在維持晶圓表面不良的改善的同時,防止晶圓形狀的惡化。According to the present invention, the DLC film can be formed in such a region, and the deterioration of the wafer surface can be prevented while maintaining the deterioration of the wafer surface.

又於此時,以該DLC膜的厚度為0.1μm至5μm,於該載體的上表面與下表面中對應的區域披覆有該DLC膜為佳。Further, at this time, it is preferable that the DLC film has a thickness of 0.1 μm to 5 μm, and the DLC film is coated on a corresponding region of the upper surface and the lower surface of the carrier.

若為如此之物,則能夠有作為載體表面的保護的充分的厚度。If it is such a thing, it can have sufficient thickness as a protection of a carrier surface.

又依據本發明,提供具備有前述的本發明的雙面研磨裝置用載體的雙面研磨裝置。Further, according to the present invention, there is provided a double-side polishing apparatus comprising the carrier for a double-side polishing apparatus of the present invention described above.

若為如此之物,則由於為具備上述本發明的雙面研磨裝置用載體之物,因此能夠得到平坦且表面狀態良好的半導體晶圓。進一步,由於能夠使載體壽命提升,而能夠降低載體的交換頻率,而能夠降低成本,效率良好地將半導體晶圓雙面研磨。In the case of the above-described material for the double-side polishing apparatus of the present invention, it is possible to obtain a semiconductor wafer which is flat and has a good surface condition. Further, since the carrier lifetime can be improved, the exchange frequency of the carrier can be reduced, and the cost can be reduced, and the semiconductor wafer can be polished on both sides efficiently.

又依據本發明,提供一種半導體晶圓的雙面研磨方法,係於經貼附研磨布的上定盤與下定盤之間配設如上述的雙面研磨裝置用載體,於形成於該載體的該支承孔支承該半導體晶圓,夾入該上定盤與下定盤之間而進行雙面研磨。According to the present invention, there is provided a double-side polishing method for a semiconductor wafer, wherein a carrier for a double-side polishing apparatus as described above is disposed between an upper fixed plate and a lower fixed plate to which the polishing cloth is attached, and formed on the carrier. The support hole supports the semiconductor wafer, and is sandwiched between the upper fixed plate and the lower fixed plate to perform double-side polishing.

如此一來,由於使用上述本發明的雙面研磨裝置用載體,因此能夠得到平坦且表面狀態良好的半導體晶圓。進一步,由於能夠使載體壽命提升,而能夠降低載體的交換頻率,而能夠降低成本,效率良好地將半導體晶圓雙面研磨。As described above, since the carrier for the double-side polishing apparatus of the present invention described above is used, it is possible to obtain a semiconductor wafer which is flat and has a good surface condition. Further, since the carrier lifetime can be improved, the exchange frequency of the carrier can be reduced, and the cost can be reduced, and the semiconductor wafer can be polished on both sides efficiently.

依據本發明,藉由僅於厚度變化大的載體外周部以DLC膜部分披覆,能夠得到平坦且表面狀態良好的半導體晶圓,進一步,由於能夠縮小載體的厚度變動,因此能夠提供能夠使載體壽命提升的雙面研磨裝置用載體,以及使用該載體的雙面研磨裝置及雙面研磨方法。According to the present invention, it is possible to obtain a semiconductor wafer which is flat and has a good surface state by being partially covered with a DLC film only on the outer peripheral portion of the carrier having a large thickness variation, and further, it is possible to provide a carrier capable of reducing the thickness variation of the carrier. A carrier for a double-side polishing apparatus having an improved life, and a double-side polishing apparatus and a double-side polishing method using the carrier.

以下雖詳細說明本發明的實施型態,但本發明並非限定於此。Hereinafter, the embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

如同前述,若是使用載體的全表面實施有DLC覆膜的載體將半導體晶圓雙面研磨,則會有對半導體晶圓的研磨劑的介入量大幅變化而晶圓形狀惡化的問題。As described above, when the semiconductor wafer is polished on both sides by using a carrier having a DLC film on the entire surface of the carrier, there is a problem in that the amount of the polishing agent for the semiconductor wafer largely changes and the wafer shape is deteriorated.

在此,本案發明人為了解決如此問題而反覆精心研討。結果,設想出若是載體的表面具有披覆有DLC膜的區域、及未披覆有該DLC膜的區域,在該載體的上表面及下表面中,自該載體的外周的齒輪的齒底向內側,該載體的其中一面的面積的30%以下的區域披覆有該DLC膜,則能夠得到平坦且表面狀態良好的半導體晶圓,進一步,能夠使載體壽命提升。並且審視用以實施此些的最佳型態,而使本發明完成。Here, the inventor of the present invention has repeatedly elaborated in order to solve such a problem. As a result, it is conceivable that if the surface of the carrier has a region coated with the DLC film and a region not covered with the DLC film, the upper and lower surfaces of the carrier are oriented from the bottom of the gear of the outer periphery of the carrier. On the inner side, a region of 30% or less of the area of one side of the carrier is coated with the DLC film, whereby a semiconductor wafer having a flat surface and a good surface state can be obtained, and further, the life of the carrier can be improved. The present invention is also completed by reviewing the best mode for carrying out such.

本發明係關於將半導體晶圓的雙面同時研磨的雙面研磨機中,支承半導體晶圓的載體的改良,首先使用圖2說明關於雙面研磨裝置的概要。The present invention relates to an improvement of a carrier for supporting a semiconductor wafer in a double-side polishing machine that simultaneously polishes both sides of a semiconductor wafer. First, an outline of the double-side polishing apparatus will be described with reference to FIG.

具備有本發明的雙面研磨裝置用載體1的雙面研磨裝置10,具有設置為上下相對的下定盤11及上定盤12,各定盤11、12的相對面側,分別貼附有研磨布11a、12a。又上定盤12的上部設置有供給研磨漿的噴嘴15,上定盤12設置有貫通孔16。並且於上定盤12與下定盤11之間的中心部設置有太陽齒輪13,於周緣部設置有內齒輪14。半導體晶圓W被支承於載體1的支承孔2,被夾入於上定盤12與下定盤11之間。The double-side polishing apparatus 10 including the carrier 1 for a double-side polishing apparatus according to the present invention has a lower fixed plate 11 and an upper fixed plate 12 which are disposed to face each other, and the opposite faces of the fixed plates 11 and 12 are attached to each other. Cloth 11a, 12a. Further, an upper portion of the upper plate 12 is provided with a nozzle 15 for supplying a slurry, and the upper plate 12 is provided with a through hole 16. Further, a sun gear 13 is provided at a center portion between the upper platen 12 and the lower platen 11, and an internal gear 14 is provided at a peripheral portion thereof. The semiconductor wafer W is supported by the support hole 2 of the carrier 1 and sandwiched between the upper fixed plate 12 and the lower fixed plate 11.

雙面研磨裝置中,藉由於太陽齒輪13及內齒輪14的各齒部使載體1的外周部的齒嚙合,以進行載體1的支承及載體1的自轉及公轉。此時半導體晶圓W為被載體1的支承孔所支承,以上研磨布11a及下研磨布12a將雙面同時研磨。另外,於研磨時,研磨漿自噴嘴15通過貫通孔16被供給。In the double-side polishing apparatus, the teeth of the outer peripheral portion of the carrier 1 are meshed by the respective tooth portions of the sun gear 13 and the internal gear 14, so that the support of the carrier 1 and the rotation and revolution of the carrier 1 are performed. At this time, the semiconductor wafer W is supported by the support holes of the carrier 1, and the above polishing cloth 11a and the lower polishing cloth 12a are simultaneously polished on both sides. Further, at the time of polishing, the slurry is supplied from the nozzle 15 through the through hole 16.

在此使用圖1於以下說明關於上述雙面研磨裝置10所具備的本發明的雙面研磨裝置用載體1。Here, the carrier 1 for a double-side polishing apparatus of the present invention provided in the above-described double-side polishing apparatus 10 will be described below with reference to FIG.

雙面研磨裝置用載體1的表面,具有披覆有DLC膜3的區域4a,及未披覆有DLC膜3的區域4b。並且,載體1的上表面及下表面的各自的面中,自該載體1的外周的齒輪的齒底5向內側,載體1的其中一面的面積的30%以下的外周區域披覆有DLC膜3。The surface of the carrier 1 for double-side polishing apparatus has a region 4a covered with the DLC film 3, and a region 4b not covered with the DLC film 3. Further, in the respective surfaces of the upper surface and the lower surface of the carrier 1, the outer peripheral region of 30% or less of the area of one surface of the carrier 1 is covered with the DLC film from the tooth bottom 5 of the gear of the outer periphery of the carrier 1. 3.

若為如此之物,則藉由僅於厚度變化大的載體1的外周部以DLC膜部分披覆,而由於對半導體晶圓W的研磨劑的流入量、載體1與研磨布的接觸的變化成為與未披覆載體相同,而能夠得到平坦而表面狀態良好的半導體晶圓W。進一步,由於能夠縮小載體1的厚度變動,而能夠使載體壽命提升。In the case of such a thing, the DLC film is partially covered by the outer peripheral portion of the carrier 1 having a large thickness variation, and the amount of the inflow of the abrasive to the semiconductor wafer W and the contact of the carrier 1 with the polishing cloth are changed. The semiconductor wafer W which is flat and has a good surface state can be obtained in the same manner as the uncoated carrier. Further, since the thickness variation of the carrier 1 can be reduced, the life of the carrier can be improved.

習知的雙面研磨裝置用載體中,由於於全表面進行DLC覆膜,雙面研磨中對半導體晶圓的研磨劑的介入量大幅變化,難以將半導體晶圓處理為與無覆膜時相同的晶圓形狀。在此,本發明僅於載體的厚度變化大(容易磨損)的位置的外周部實施DLC覆膜。在此,所謂載體的外周部,能夠為例如自此齒輪的齒底部至準備孔(支承孔)直徑的外周側1/4為止的位置。In the conventional carrier for a double-side polishing apparatus, since the DLC film is formed on the entire surface, the amount of the polishing agent for the semiconductor wafer in the double-side polishing greatly changes, and it is difficult to process the semiconductor wafer to be the same as when the film is not coated. Wafer shape. Here, in the present invention, the DLC film is applied only to the outer peripheral portion of the position where the thickness of the carrier changes greatly (easy to wear). Here, the outer peripheral portion of the carrier can be, for example, a position from the tooth bottom of the gear to the outer peripheral side 1/4 of the diameter of the preparation hole (support hole).

此時,於載體1的上表面及下表面的任一面中,自載體1的外周的齒輪的齒底5向內側,載體1的其中一面的面積的5%以上的區域披覆有DLC膜3為佳。若為如此之物,則能夠在維持晶圓表面不良的改善的同時,更加確實地防止晶圓形狀的惡化。At this time, on either of the upper surface and the lower surface of the carrier 1, the DMC film 3 is covered with a region of 5% or more of the area of one side of the carrier 1 from the tooth bottom 5 of the outer circumference of the carrier 1. It is better. According to this, it is possible to more reliably prevent the deterioration of the wafer shape while maintaining the improvement of the wafer surface defect.

又於此時,以於自該載體1的外周的的齒輪的齒底5,至支承孔的載體1的外周側為止的區域披覆有DLC膜3為佳。若為如此之物,則能夠在維持晶圓表面不良的改善的同時,更加確實地防止晶圓形狀的惡化。At this time, it is preferable that the DMC film 3 is coated on the region from the tooth bottom 5 of the gear of the outer periphery of the carrier 1 to the outer peripheral side of the carrier 1 of the support hole. According to this, it is possible to more reliably prevent the deterioration of the wafer shape while maintaining the improvement of the wafer surface defect.

又於此時,以DLC膜3的厚度為0.1μm至5μm,於載體1的上表面與下表面中對應的區域披覆有DLC膜3為佳。若為如此之物,則能夠有作為載體1表面的保護的充分的厚度,又能夠為抑制形成DLC膜3時的成本。Further, at this time, it is preferable that the DLC film 3 has a thickness of 0.1 μm to 5 μm, and the DLC film 3 is coated on a corresponding region of the upper surface and the lower surface of the carrier 1. If it is such a thing, it can have sufficient thickness as the protection of the surface of the carrier 1, and can suppress the cost at the time of formation of the DLC film 3.

如此的本發明的載體1,能夠藉由例如自Ti板切下,進行研光、拋光後,進行如圖3所示的(1)遮罩加工步驟、(2)DLC覆膜步驟及(3)遮罩剝除步驟,之後,藉由嵌件接著以製作。The carrier 1 of the present invention can be subjected to polishing and polishing, for example, by cutting from a Ti plate, and then performing (1) mask processing step, (2) DLC coating step, and (3) as shown in FIG. The mask stripping step is followed by an insert followed by fabrication.

此時以(1)遮罩加工步驟具有(1-1)鹼液洗淨步驟、(1-2)層壓(抗蝕膜)步驟、(1-3)曝光、顯影步驟、(1-4)烘烤步驟,(3)遮罩剝除步驟具有(3-1)藉由鹼液浸漬所進行的抗蝕膜剝離步驟、(3-2)潤洗步驟為佳。At this time, the (1) mask processing step has (1-1) lye washing step, (1-2) lamination (resist film) step, (1-3) exposure, development step, (1-4) The baking step, (3) the mask stripping step is preferably (3-1) a resist stripping step by a lye impregnation, and (3-2) a rinsing step.

又若為具備有如同前述的本發明的雙面研磨裝置用載體1的,如圖2所示的本發明的雙面研磨裝置10,則能夠得到平坦且表面狀態良好的半導體晶圓W。進一步,由於能夠使載體壽命提升,而能夠降低載體的交換頻率,而能夠降低成本,效率良好地將半導體晶圓W雙面研磨。Further, in the double-side polishing apparatus 10 of the present invention having the carrier 1 for a double-side polishing apparatus of the present invention as described above, a semiconductor wafer W having a flat surface and a good surface state can be obtained. Further, since the carrier lifetime can be improved, the exchange frequency of the carrier can be reduced, and the cost can be reduced, and the semiconductor wafer W can be polished on both sides efficiently.

並且,能夠將上述本發明的雙面研磨裝置用載體1配設於雙面研磨裝置10的貼附有研磨布11a、12a的上定盤12與下定盤11之間,以支承孔2將半導體晶圓W支承而夾入上定盤12與下定盤11之間,在供給研磨漿的同時將半導體晶圓W雙面研磨。Further, the carrier 1 for a double-side polishing apparatus according to the present invention described above can be disposed between the upper fixed plate 12 and the lower fixed plate 11 to which the polishing cloths 11a and 12a of the double-side polishing apparatus 10 are attached, and the semiconductors can be supported by the holes 2 The wafer W is supported and sandwiched between the upper fixed plate 12 and the lower fixed plate 11, and the semiconductor wafer W is double-side polished while the slurry is supplied.

若為如此,則由於使用上述本發明的雙面研磨裝置用載體,能夠得到平坦且表面狀態良好的半導體晶圓。進一步,由於能夠使載體壽命提升,而能夠降低載體的交換頻率,而能夠降低成本,效率良好地將半導體晶圓W雙面研磨。In this case, by using the carrier for a double-side polishing apparatus of the present invention described above, a semiconductor wafer having a flat surface and a good surface state can be obtained. Further, since the carrier lifetime can be improved, the exchange frequency of the carrier can be reduced, and the cost can be reduced, and the semiconductor wafer W can be polished on both sides efficiently.

以下雖顯示本發明的實施例及比較例以更加具體說明本發明,但本發明並不限定於此。Hereinafter, the present invention will be more specifically described by showing examples and comparative examples of the invention, but the invention is not limited thereto.

(實施例1) 使用具備本發明的雙面研磨裝置用載體的雙面研磨裝置,進行了半導體晶圓的雙面研磨。(Example 1) Double-side polishing of a semiconductor wafer was performed using the double-side polishing apparatus provided with the carrier for double-side polishing apparatuses of this invention.

首先,準備如圖1所示,於載體1的上表面及下表面中,自載體1的外周的齒輪的齒底5向內側,載體1的其中一面的面積的5%的區域披覆有DLC膜3的載體1。在此,載體1為於上表面及下表面的對應的區域披覆有DLC膜3之物。First, as shown in Fig. 1, in the upper surface and the lower surface of the carrier 1, from the tooth bottom 5 of the outer circumference of the carrier 1 to the inner side, a region of 5% of the area of one side of the carrier 1 is covered with DLC. Carrier 1 of membrane 3. Here, the carrier 1 is a material in which the DLC film 3 is coated on a corresponding region of the upper surface and the lower surface.

使用具備如此的本發明的雙面研磨裝置用載體1的如圖2所示的雙面研磨裝置10,依照本發明的雙面研磨方法進行半導體晶圓W(矽晶圓)的雙面研磨,評估雙面研磨後的半導體晶圓W的晶圓形狀及晶圓表面缺陷發生率。Using the double-side polishing apparatus 10 shown in FIG. 2 including the carrier 1 for a double-side polishing apparatus of the present invention, the double-side polishing of the semiconductor wafer W (tantalum wafer) is performed according to the double-side polishing method of the present invention. The wafer shape and wafer surface defect occurrence rate of the semiconductor wafer W after double-side polishing were evaluated.

並且,將雙面研磨後的半導體晶圓的晶圓形狀及晶圓表面缺陷發生率(以比較例2為1時)的結果,與後述的實施例2至3及比較例1至4一同顯示於表1及圖4至7。此時,作為晶圓形狀,分別測定Roll off值(以比較例2為0時)、GBIR(以比較例2為100時)、ESFQRmax(以比較例2為100時)。Further, as a result of the wafer shape of the semiconductor wafer after double-side polishing and the wafer surface defect occurrence rate (when Comparative Example 2 is 1), the results are shown together with Examples 2 to 3 and Comparative Examples 1 to 4 which will be described later. In Table 1 and Figures 4 to 7. At this time, as the wafer shape, the Roll off value (when Comparative Example 2 was 0), GBIR (when Comparative Example 2 was 100), and ESFQRmax (when Comparative Example 2 was 100) were measured.

又測定了載體使用前的厚度及使用10000min後的厚度的變化。測定位置為於各支承孔周圍各6點,一片載體18點,合計測定5片載體,合計測定90點。Further, the thickness of the carrier before use and the change in thickness after 10,000 minutes of use were measured. The measurement position was 6 points around each support hole, and one carrier was 18 points, and five pieces of the carrier were measured in total, and 90 points were measured in total.

(實施例2) 除了作為雙面研磨裝置用載體,使用於如圖9所示的載體1a的上表面及下表面中,自該載體1a的外周的齒輪的齒底5向內側,載體1a的其中一面的面積的15%的區域披覆有DLC膜3的載體1a以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。在此,載體1a為於上表面及下表面的對應的區域披覆有DLC膜3之物。(Example 2) In addition to the carrier for the double-side polishing apparatus, the upper surface and the lower surface of the carrier 1a shown in Fig. 9 are used, and the carrier bottom 1 is inward from the tooth bottom 5 of the outer circumference of the carrier 1a. The semiconductor wafer was subjected to double-side polishing in the same manner as in Example 1 except that 15% of the area of one surface was coated with the carrier 1a of the DLC film 3. Here, the carrier 1a is a material in which the DLC film 3 is coated on a corresponding region of the upper surface and the lower surface.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

(實施例3) 除了作為雙面研磨裝置用載體,使用於如圖10所示的載體1b的上表面及下表面中,自載體1b的外周的齒輪的齒底5向內側,載體1b的其中一面的面積的30%的區域披覆有DLC膜3的載體1b以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。在此,載體1b為於上表面及下表面的對應的區域披覆有DLC膜3之物。(Embodiment 3) In addition, as a carrier for a double-side polishing apparatus, it is used in the upper surface and the lower surface of the carrier 1b shown in FIG. 10, the tooth bottom 5 of the gear of the outer periphery of the carrier 1b is inward, and the carrier 1b is The semiconductor wafer was subjected to double-side polishing in the same manner as in Example 1 except that the region of 30% of the area on one side was covered with the carrier 1b of the DLC film 3. Here, the carrier 1b is a material in which the DLC film 3 is coated on a corresponding region on the upper surface and the lower surface.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

(比較例1) 除了作為雙面研磨裝置用載體,使用於如圖11所示的載體100a的上表面及下表面的整體表面披覆有DLC膜103的載體100a以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。(Comparative Example 1) The same as Example 1 except that the carrier for the double-side polishing apparatus was used as the carrier 100a in which the upper surface and the lower surface of the carrier 100a shown in Fig. 11 were coated with the DLC film 103. The method performs double-sided polishing of a semiconductor wafer.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

(比較例2) 除了作為雙面研磨裝置用載體,使用於如圖12所示的載體100b的上表面及下表面皆未披覆有DLC膜的載體100b以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。(Comparative Example 2) The same method as in Example 1 was used except that the carrier for the double-side polishing apparatus was used as the carrier 100b in which the upper surface and the lower surface of the carrier 100b shown in Fig. 12 were not covered with the DLC film. Perform double-sided polishing of the semiconductor wafer.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

此時,將比較例2的載體100b的使用前的厚度及使用10000min後的厚度的變化的測定結果顯示於圖13。如圖13所示,可得知載體100b的外周部的測定點1的位置變化最大。At this time, the measurement results of the thickness of the carrier 100b of Comparative Example 2 before use and the change of the thickness after 10,000 minutes of use are shown in FIG. As shown in FIG. 13, it can be seen that the positional change of the measurement point 1 of the outer peripheral part of the carrier 100b is the largest.

又將比較例2的載體100b的載體使用時間與平坦度及載體厚度分散的關係顯示於圖14。如圖14所示,比較例2中隨著載體的使用時間推進,載體的厚度分散變大,晶圓不再維持於目的形狀。Further, the relationship between the carrier use time of the carrier 100b of Comparative Example 2 and the flatness and the thickness dispersion of the carrier is shown in FIG. As shown in FIG. 14, in Comparative Example 2, as the use time of the carrier progresses, the thickness dispersion of the carrier becomes large, and the wafer is no longer maintained in the intended shape.

(比較例3) 除了作為雙面研磨裝置用載體,使用於如圖15所示的載體100c的上表面及下表面中,自載體100c的外周的齒輪的齒底105向內側,載體100c的其中一面的面積的40%的區域披覆有DLC膜103的載體100c以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。(Comparative Example 3) In addition to the carrier for the double-side polishing apparatus, the upper surface and the lower surface of the carrier 100c as shown in Fig. 15 are inwardly from the tooth bottom 105 of the outer circumference of the carrier 100c, and the carrier 100c is therein. The semiconductor wafer was double-sided polished in the same manner as in Example 1 except that the 40% area of one surface was covered with the carrier 100c of the DLC film 103.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

(比較例4) 除了作為雙面研磨裝置用載體,使用於如圖16所示的載體100d的上表面及下表面中,自載體100d的外周的齒輪的齒底105向內側,載體100d的其中一面的面積的55%的區域披覆有DLC膜103的載體100d以外,以與實施例1相同的方法進行半導體晶圓的雙面研磨。(Comparative Example 4) In addition to the carrier for the double-side polishing apparatus, the upper surface and the lower surface of the carrier 100d shown in Fig. 16 are inwardly from the tooth bottom 105 of the outer circumference of the carrier 100d, and the carrier 100d is therein. The double-side polishing of the semiconductor wafer was carried out in the same manner as in Example 1 except that the region of 55% of the area on one side was covered with the carrier 100d of the DLC film 103.

並且,與實施例1同樣測定雙面研磨後的半導體晶圓的晶圓形狀、晶圓表面不良、及載體的厚度變化分散,將其結果顯示於表1及圖4至8。Further, in the same manner as in Example 1, the wafer shape, the wafer surface defect, and the thickness variation dispersion of the semiconductor wafer after double-side polishing were measured, and the results are shown in Table 1 and FIGS. 4 to 8.

【表1】 【Table 1】

結果如表1及圖4至6所示,於比較例1、3、4中雙面研磨後的半導體晶圓的外周下垂,又GBIR及ESFQRmax亦高,無法得到平坦的半導體晶圓。另一方面,實施例1至3中,能夠使Roll Off、GBIR及ESFQRmax為與沒有DLC膜比較例2相同程度,能夠得到平坦的半導體晶圓。As a result, as shown in Table 1 and FIGS. 4 to 6, in the comparative examples 1, 3, and 4, the outer periphery of the semiconductor wafer after double-side polishing was drooped, and GBIR and ESFQRmax were also high, and a flat semiconductor wafer could not be obtained. On the other hand, in the first to third embodiments, the Roll Off, GBIR, and ESFQRmax can be made to be the same as in the case of the DLC film-less Comparative Example 2, and a flat semiconductor wafer can be obtained.

又於圖17,顯示實施例1、比較例1、2中雙面研磨後的半導體晶圓的晶圓形狀。如圖17所示,可得知於僅於載體的外周部以DLC膜部分披覆的實施例1中,與全表面以DLC膜披覆的比較例1相比,雙面研磨後的半導體晶圓的形狀變化較少。Further, Fig. 17 shows the wafer shape of the semiconductor wafer after double-side polishing in Example 1 and Comparative Examples 1 and 2. As shown in Fig. 17, in Example 1 in which the outer peripheral portion of the carrier was partially covered with the DLC film, the semiconductor crystal after double-side polishing was compared with Comparative Example 1 in which the entire surface was coated with the DLC film. The shape of the circle changes less.

進一步,於實施例1至3中,如表1及圖7所示,能夠使傷痕及微粒等的晶圓表面缺陷的發生率與比較例1、3、4為相同程度,能夠得到表面狀態良好的半導體晶圓。另一方面,於比較例2中,由於完全沒有進行DLC膜的覆膜,因此與實施例1至3相比,晶圓表面缺陷發生率較高。Further, in Examples 1 to 3, as shown in Table 1 and FIG. 7, the occurrence rate of wafer surface defects such as scratches and fine particles can be made to be the same as in Comparative Examples 1, 3, and 4, and the surface state can be obtained well. Semiconductor wafers. On the other hand, in Comparative Example 2, since the film of the DLC film was not formed at all, the wafer surface defect occurrence rate was higher than that of Examples 1 to 3.

又實施例1至3中,如圖8所示,能夠使載體的厚度變化分散與比較例1、3、4為相同程度,能夠得到表面狀態良好的半導體晶圓。另一方面於比較例2中,由於完全沒有進行DLC膜的覆膜,因此與實施例1至3相比厚度變化分散較大。如此,由於實施例1至3中,能夠縮小載體的厚度變動,因此能夠使載體壽命提升。Further, in Examples 1 to 3, as shown in Fig. 8, the thickness variation of the carrier can be dispersed to the same extent as in Comparative Examples 1, 3, and 4, and a semiconductor wafer having a good surface state can be obtained. On the other hand, in Comparative Example 2, since the film of the DLC film was not formed at all, the thickness variation was larger than that of Examples 1 to 3. As described above, in the first to third embodiments, the thickness variation of the carrier can be reduced, so that the life of the carrier can be improved.

另外,本發明並不為前述實施例所限制。前述實施例為例示,具有與本發明的申請專利範圍所記載的技術思想實質相同的構成,且達成同樣作用效果者,皆包含於本發明的技術範圍。Further, the present invention is not limited by the foregoing embodiments. The above-described embodiments are exemplified, and have substantially the same configuration as the technical idea described in the patent application scope of the present invention, and the same effects are achieved in the technical scope of the present invention.

10‧‧‧雙面研磨裝置10‧‧‧Double-side grinding device

1‧‧‧載體1‧‧‧ Carrier

1a‧‧‧載體1a‧‧‧ Carrier

1b‧‧‧載體1b‧‧‧ Carrier

100a‧‧‧載體100a‧‧‧ Carrier

100b‧‧‧載體100b‧‧‧Vector

100c‧‧‧載體100c‧‧‧ carrier

100d‧‧‧載體100d‧‧‧ carrier

103‧‧‧DLC膜103‧‧‧DLC film

105‧‧‧齒底105‧‧‧ tooth bottom

11‧‧‧下定盤11‧‧‧Definition

11a‧‧‧研磨布11a‧‧‧ polishing cloth

12‧‧‧上定盤12‧‧‧Upright

12a‧‧‧研磨布12a‧‧‧ polishing cloth

13‧‧‧太陽齒輪13‧‧‧Sun Gear

14‧‧‧內齒輪14‧‧‧Internal gear

15‧‧‧噴嘴15‧‧‧ nozzle

16‧‧‧貫通孔16‧‧‧through holes

2‧‧‧支承孔2‧‧‧Support hole

3‧‧‧DLC膜3‧‧‧DLC film

4a‧‧‧區域4a‧‧‧Area

4b‧‧‧區域4b‧‧‧Area

5‧‧‧齒底5‧‧‧ tooth bottom

W‧‧‧半導體晶圓W‧‧‧Semiconductor Wafer

圖1係顯示本發明的雙面研磨裝置用載體之一例的概略圖。 圖2係顯示具備有本發明的雙面研磨裝置用載體的雙面研磨裝置之一例的概略圖。 圖3係顯示製作本發明的雙面研磨裝置用載體之一例的步驟圖。 圖4係顯示實施例及比較例中雙面研磨後的半導體晶圓的Roll off值的量表圖。 圖5係顯示實施例及比較例中雙面研磨後的半導體晶圓的GRIB值的量表圖。 圖6係顯示實施例及比較例中雙面研磨後的半導體晶圓的ESFQRmax值的量表圖。 圖7係顯示實施例及比較例中雙面研磨後的半導體晶圓的晶圓表面缺陷發生率的量表圖。 圖8係顯示實施例及比較例中雙面研磨後的半導體晶圓的厚度變化分散的量表圖。 圖9係顯示實施例2中所使用的雙面研磨裝置用載體的概略圖。 圖10係顯示實施例3中所使用的雙面研磨裝置用載體的概略圖。 圖11係顯示比較例1中所使用的雙面研磨裝置用載體的概略圖。 圖12係顯示比較例2中所使用的雙面研磨裝置用載體的概略圖。 圖13係顯示比較例2中所使用的雙面研磨裝置用載體的使用前厚度與使用10000min後的厚度變化測定結果的量表圖。 圖14係顯示比較例2中的載體使用時間與平坦度及載體厚度分散的關係的量表圖。 圖15係顯示比較例3中所使用的雙面研磨裝置用載體的概略圖。 圖16係顯示比較例4中所使用的雙面研磨裝置用載體的概略圖。 圖17係顯示實施例1、比較例1、2中雙面研磨後的半導體晶圓的晶圓形狀的量表圖。Fig. 1 is a schematic view showing an example of a carrier for a double-side polishing apparatus of the present invention. Fig. 2 is a schematic view showing an example of a double-side polishing apparatus including a carrier for a double-side polishing apparatus of the present invention. Fig. 3 is a view showing a procedure for producing an example of a carrier for a double-side polishing apparatus of the present invention. 4 is a graph showing the amount of Roll off values of the semiconductor wafer after double-side polishing in the examples and the comparative examples. Fig. 5 is a graph showing the GRIB value of the semiconductor wafer after double-side polishing in the examples and the comparative examples. Fig. 6 is a graph showing the ESFQRmax value of the semiconductor wafer after double-side polishing in the examples and the comparative examples. Fig. 7 is a graph showing the incidence of wafer surface defects in the semiconductor wafer after double-side polishing in the examples and the comparative examples. Fig. 8 is a graph showing the dispersion of the thickness variation of the semiconductor wafer after double-side polishing in the examples and the comparative examples. Fig. 9 is a schematic view showing a carrier for a double-side polishing apparatus used in Example 2. Fig. 10 is a schematic view showing a carrier for a double-side polishing apparatus used in Example 3. Fig. 11 is a schematic view showing a carrier for a double-side polishing apparatus used in Comparative Example 1. Fig. 12 is a schematic view showing a carrier for a double-side polishing apparatus used in Comparative Example 2. Fig. 13 is a graph showing the measurement results of the thickness before use and the thickness change after 10,000 minutes of the carrier for the double-side polishing apparatus used in Comparative Example 2. Fig. 14 is a graph showing the relationship between the use time of the carrier in Comparative Example 2 and the flatness and dispersion of the carrier thickness. Fig. 15 is a schematic view showing a carrier for a double-side polishing apparatus used in Comparative Example 3. Fig. 16 is a schematic view showing a carrier for a double-side polishing apparatus used in Comparative Example 4. Fig. 17 is a chart showing the wafer shape of the semiconductor wafer after double-side polishing in Example 1 and Comparative Examples 1 and 2.

Claims (9)

一種雙面研磨裝置用載體,係於雙面研磨裝置中,被配設於經貼附研磨布的上定盤與下定盤之間,且形成有一個以上的支承孔,用以支承於研磨時被夾於該上定盤與下定盤之間的半導體晶圓,其中 該載體的表面具有披覆有DLC膜的區域、及未披覆有該DLC膜的區域, 在該載體的上表面及下表面中,自該載體的外周的齒輪的齒底向內側,該載體的其中一面的面積的30%以下的區域披覆有該DLC膜。A carrier for a double-side polishing apparatus is disposed in a double-side polishing apparatus, and is disposed between an upper fixed plate and a lower fixed plate to which a polishing cloth is attached, and is formed with one or more support holes for supporting during grinding a semiconductor wafer sandwiched between the upper and lower fixed plates, wherein a surface of the carrier has a region covered with a DLC film, and a region not covered with the DLC film, on an upper surface and a lower surface of the carrier In the surface, the DLC film is coated on the inner side of the gear of the outer periphery of the carrier, and the area of 30% or less of the area of one side of the carrier. 如請求項1所述的雙面研磨裝置用載體,其中在該載體的上表面及下表面中的至少一面中,自該載體的外周的齒輪的齒底向內側,該載體的其中一面的面積的5%以上的區域披覆有該DLC膜。The carrier for a double-side polishing apparatus according to claim 1, wherein in at least one of an upper surface and a lower surface of the carrier, an area of one side of the carrier is inward from a tooth bottom of a gear of an outer circumference of the carrier More than 5% of the area is covered with the DLC film. 如請求項1所述的雙面研磨裝置用載體,其中自該載體的外周的該齒輪的齒底,至該支承孔的該載體的外周側為止的區域披覆有該DLC膜。The carrier for a double-side polishing apparatus according to claim 1, wherein the DLC film is coated from a tooth bottom of the gear on the outer circumference of the carrier to a region on the outer peripheral side of the carrier of the support hole. 如請求項2所述的雙面研磨裝置用載體,其中自該載體的外周的該齒輪的齒底,至該支承孔的該載體的外周側為止的區域披覆有該DLC膜。The carrier for a double-side polishing apparatus according to claim 2, wherein the DLC film is coated from a tooth bottom of the gear on the outer circumference of the carrier to a region on the outer peripheral side of the carrier of the support hole. 如請求項1至4中任一項所述的雙面研磨裝置用載體,其中該DLC膜的厚度為0.1μm至5μm,於該載體的上表面與下表面中對應的區域披覆有該DLC膜。The carrier for a double-side polishing apparatus according to any one of claims 1 to 4, wherein the DLC film has a thickness of 0.1 μm to 5 μm, and the DLC is coated on a corresponding one of the upper surface and the lower surface of the carrier. membrane. 一種雙面研磨裝置,具備有如請求項1至4中任一項所述的雙面研磨裝置用載體。A double-side polishing apparatus comprising the carrier for a double-side polishing apparatus according to any one of claims 1 to 4. 一種雙面研磨裝置,具備有如請求項5所述的雙面研磨裝置用載體。A double-side polishing apparatus comprising the carrier for a double-side polishing apparatus according to claim 5. 一種半導體晶圓的雙面研磨方法,係於經貼附研磨布的上定盤與下定盤之間配設如請求項1至4中任一項所述的雙面研磨裝置用載體,於形成於該載體的該支承孔支承該半導體晶圓,夾入該上定盤與下定盤之間而進行雙面研磨。A double-side polishing method for a semiconductor wafer, wherein a carrier for a double-side polishing apparatus according to any one of claims 1 to 4 is disposed between the upper and lower fixed plates to which the polishing cloth is attached, and is formed The support hole of the carrier supports the semiconductor wafer, and is sandwiched between the upper fixed plate and the lower fixed plate to perform double-side polishing. 一種半導體晶圓的雙面研磨方法,係於經貼附研磨布的上定盤與下定盤之間配設如請求項5所述的雙面研磨裝置用載體,於形成於該載體的該支承孔支承該半導體晶圓,夾入該上定盤與下定盤之間而進行雙面研磨。A double-sided polishing method for a semiconductor wafer, wherein a carrier for a double-side polishing apparatus according to claim 5 is disposed between an upper fixed plate and a lower fixed plate to which the polishing cloth is attached, and the support formed on the carrier The hole supports the semiconductor wafer, and is sandwiched between the upper and lower fixed plates to perform double-side polishing.
TW106140846A 2016-12-26 2017-11-24 Carrier for double-side polishing device, double-side polishing device arranged by use thereof, and double-side polishing method TW201838771A (en)

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