TW201838091A - Isolation structure and method of fabricating the same - Google Patents

Abstract

A method of fabricating an isolation structure including following steps is provided. A mask layer is formed on a substrate. The mask layer has an opening to expose a surface of the substrate. The substrate exposed by the opening is removed to form a trench in the substrate. A dielectric material is formed on the mask layer and on sidewalls and a bottom surface of the trench. A structural damage treatment is performed to the dielectric material to form a first dielectric layer. A second dielectric layer is filled into the trench and covers the first dielectric layer. The first dielectric layer and the second dielectric layer above the mask layer is removed. The mask layer is removed.

Description

Isolation structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to an isolation structure and a method of fabricating the same.

The shallow trench isolation (STI) structure has good isolation effect and small occupied area, and is commonly used as an isolation structure for isolating adjacent transistors in a semiconductor. However, in the process of the shallow trench isolation structure, due to the influence of the loading effect, the shallow trench isolation structure located in the isolation area is prone to dishing, which affects the subsequent process. Therefore, avoiding the problem of dishing and increasing the process margin of the shallow trench isolation structure is one of the issues that current R&D personnel need to solve.

The present invention provides an isolation structure having good flatness and a method of fabricating the same.

An embodiment of the invention provides a method of fabricating an isolation structure that includes the following steps. A mask layer is formed on the substrate, and the mask layer has an opening. The substrate at the bottom of the opening is removed to form a trench in the substrate. A layer of dielectric material is formed on the sidewalls and the bottom surface of the trench and the mask layer. The dielectric material layer is subjected to a structural destruction process to form a first dielectric layer. The second dielectric layer is filled in the trench and covered on the first dielectric layer. The first dielectric layer and the second dielectric layer on the mask layer are removed. Remove the mask layer.

In an embodiment of the invention, the structural destruction process includes a porosification process.

In an embodiment of the invention, the porosification treatment includes a gas cluster ion beam.

In an embodiment of the invention, the porosity of the first dielectric layer is greater than the porosity of the second dielectric layer.

In an embodiment of the invention, the trench includes a first trench and a second trench smaller than the first trench, the first trench is located in the first region of the substrate, the second trench is located in the second region of the substrate, and the structural damage The treatment is performed selectively on the layer of dielectric material located in the first region.

In an embodiment of the invention, the dielectric material layer does not fill the first trench and the second trench. The second dielectric layer fills the first trench and the second trench.

In an embodiment of the invention, the dielectric material layer does not fill the first trench and fills the second trench. The second dielectric layer fills the first trench and does not fill the second trench.

An embodiment of the invention provides an isolation structure including a first dielectric layer and a second dielectric layer. The first dielectric layer has a porous structure, and the first dielectric layer is located on the sidewall and the bottom surface of the first trench in the substrate. The second dielectric layer is located in the first trench and on the first dielectric layer.

In an embodiment of the invention, the first dielectric layer and the second dielectric layer are made of the same material.

In an embodiment of the invention, the porosity of the first dielectric layer is greater than the porosity of the second dielectric layer.

In an embodiment of the invention, a layer of dielectric material is further included. The layer of dielectric material covers sidewalls and bottom surfaces of the second trench in the substrate. The second dielectric layer is further filled in the second trench and covers the dielectric material layer, wherein the size of the first trench is larger than the size of the second trench.

In an embodiment of the invention, a layer of dielectric material is further included. The layer of dielectric material fills the sidewalls and the bottom surface of the second trench in the substrate, wherein the size of the first trench is larger than the size of the second trench.

In an embodiment of the invention, the dielectric material layer is the same material as the first dielectric layer and the second dielectric layer.

In an embodiment of the invention, the porosity of the first dielectric layer is greater than the porosity of the dielectric material layer and greater than the porosity of the second dielectric layer.

Based on the above, the isolation structure and the manufacturing method thereof provided by the above embodiments of the present invention are structurally damaged to form a first dielectric layer having a porous structure, so that the first dielectric layer is removed. The rate is greater than the rate at which the second dielectric layer is removed. Therefore, after removing the first dielectric layer and the second dielectric layer on the mask layer, the top surface of the second dielectric layer in the trench may be higher than or equal to the top surface of the mask layer to improve the isolation structure. The process margin makes the isolation structure have good stability.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

1A-1F are schematic views of a method of fabricating an isolation structure in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The semiconductor substrate may be free of dopants or have dopants. The dopant may be P-type or N-type. The P-type dopant is, for example, boron. The N-type dopant is, for example, phosphorus or arsenic. Substrate 100 can also be, for example, an undoped epitaxial (Non-EPI) layer, a doped epitaxial layer, a blanket insulating (SOI) substrate, or a combination thereof.

A mask layer 104 is formed on the substrate 100. The mask layer 104 has an opening 106 that exposes the surface of the substrate 100. In some embodiments, the mask layer 104 is formed by, for example, forming a layer of mask material (not shown) prior to the substrate 100. Next, the mask material layer is patterned to form a mask layer 104 having a surface opening 106 of the exposed substrate 100. This patterning step includes a lithography process and an etch process. The material of the mask material layer is, for example, tantalum nitride. The method of forming the mask material layer is, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer vapor deposition (ALD), or a combination thereof. In order to buffer the stress between the mask layer 104 and the substrate 100 and to avoid damage or contamination of the substrate 100 during the subsequent removal of the mask layer 104, in some embodiments, the pad layer 102 may be formed prior to the substrate 100. A mask layer 104 is formed on the underlayer 102. That is, the bedding layer 102 is located between the substrate 100 and the mask layer 104 to protect the substrate 100 and to relieve stress between the mask layer 104 and the substrate 100. The material of the underlayer 102 is, for example, cerium oxide. The formation method of the underlayer 102 is, for example, thermal oxidation, CVD, ALD, or a combination thereof.

Referring to FIGS. 1A and 1B simultaneously, the exposed substrate 100 of the opening 106 is removed to form a trench 108 in the substrate 100. In some embodiments, the method of forming the trench 108 is such as etching the mask 100 with the mask layer 104 as an etch mask to etch the substrate 100 exposed by the opening 106 to form a trench 108 in the substrate 100. Additionally, the method of etching the exposed substrate 100 of the opening 106 may be a dry etch, such as reactive ion etching (RIE).

Next, a dielectric material layer 110 is formed on the sidewalls and the bottom surface of the trench 108 and the mask layer 104. In some embodiments, the dielectric material layer 110 is conformally formed on the surface of the trench 108 and the mask layer 104. The method of forming the dielectric material layer 110 is, for example, CVD, ALD, spin coating, or a combination thereof. The CVD is, for example, flow chemical vapor deposition (FCVD).

The material of the dielectric material layer 110 is, for example, ruthenium oxide. The thickness of the dielectric material layer 110 is, for example, 50 angstroms to 500 angstroms.

Referring to FIG. 1C, the dielectric material layer 110 is subjected to a structural destruction process to form a first dielectric layer 110a. The film quality of the first dielectric layer 110a obtained by the structural destruction treatment is lower than that of the dielectric material layer 110 subjected to the structural destruction treatment. The structural destruction treatment is, for example, a porous treatment. The first dielectric layer 110a is, for example, a porous structure. The porosification treatment is carried out, for example, by using a gas cluster ion beam (GCIB), but is not limited thereto. Further, the time of the structural destruction treatment can be appropriately adjusted depending on the amount of energy of the structural destruction treatment, the range of the structural destruction treatment, or the material of the dielectric material layer 110.

Referring to FIG. 1C and FIG. 1D simultaneously, a second dielectric layer 112 is formed on the substrate 100. The second dielectric layer 112 covers the first dielectric layer 110a and is filled in the trench 108. In some embodiments, the second dielectric layer 112 may be the same or different from the material of the first dielectric layer 110a, but the second dielectric layer 112 has better structure (or film quality) than the first dielectric layer 110a. Structural (or film quality). For example, the density of the second dielectric layer 112 is higher than the density of the first dielectric layer 110a, or the porosity of the second dielectric layer 112 is smaller than the porosity of the first dielectric layer 110a. The material of the second dielectric layer 112 is, for example, ruthenium oxide. The method of forming the second dielectric layer 112 may be the same as or different from the method of forming the dielectric material layer 110. The method of forming the second dielectric layer 112 is, for example, CVD, ALD, or a combination thereof. The thickness of the second dielectric layer 112 is, for example, 2900 angstroms or more.

Referring to FIG. 1E, the second dielectric layer 112 and the first dielectric layer 110a on the mask layer 104 are removed. In some embodiments, the method of removing the second dielectric layer 112 and the first dielectric layer 110a on the mask layer 104 may employ a planarization process. The planarization process is performed, for example, by using the mask layer 104 as a polishing stop layer, and performing a chemical mechanical polishing process (CMP) process on the first dielectric layer 110a and the second dielectric layer 112 on the mask layer 104. In some embodiments, the first dielectric layer 110a is the same material as the second dielectric layer 112, but the first dielectric layer 110a has poorer structure (or film quality) (eg, lower density or porosity). Large), while the second dielectric layer 112 has better structure (or film quality) (for example, higher density or smaller porosity), therefore, the first dielectric layer 110a has a higher polishing rate than the second dielectric layer. The polishing rate of 112. That is, after the second dielectric layer 112 and the first dielectric layer 110a above the mask layer 104 are removed to expose the top surface of the mask layer 104, the second dielectric layer 112a in the trench 108 The top surface is still higher than or equal to the top surface of the mask layer 104. Therefore, the problem of dishing of the second dielectric layer 112a in the trench 108 can be avoided or reduced.

Referring to FIG. 1E and FIG. 1F simultaneously, the pad layer 102 and the mask layer 104 on the substrate 100 are removed to expose the surface of the substrate 100 and form the isolation structure 114 in the substrate 100. In some embodiments, the first dielectric layer 110b and the second dielectric layer 112a on the substrate 100 are also removed when the pad layer 102 is removed, so the isolation structure 114 formed in the substrate 100 includes the first dielectric. Layer 110c and second dielectric layer 112b. The method of removing the mask layer 104 is, for example, wet etching using a hot phosphoric acid (H ₃ PO ₄ ) solution. The method of removing the underlayer 102 is, for example, wet etching using a hydrofluoric acid (HF) solution.

Referring to FIG. 1F, the isolation structure 114 includes a first dielectric layer 110c and a second dielectric layer 112b. The first dielectric layer 110c has a porous structure and is located on the sidewall and bottom surface of the trench 108 in the substrate 100. The second dielectric layer 112b is located in the trench 108 and on the first dielectric layer 110c.

Referring to FIG. 1E and FIG. 1F , since the polishing rate of the first dielectric layer 110 a is greater than the polishing rate of the second dielectric layer 112 , the second dielectric layer 112 and the first dielectric are located above the mask layer 104 . After the layer 110a is removed to expose the top surface of the mask layer 104, the top surface of the second dielectric layer 112a in the trench 108 is still higher than or equal to the top surface of the mask layer 104. Therefore, the process window of the over-polishing can be improved, and the problem of the dishing of the second dielectric layer 112b in the trench 108 can be avoided or reduced, so that the formed isolation structure 114 has a good flatness. degree.

2A-2G are schematic views of a method of fabricating an isolation structure in accordance with another embodiment of the present invention.

Referring to FIG. 2A, a pad layer 102 and a mask layer 204 are sequentially formed on the substrate 100. The mask layer 204 has a first opening 206 that exposes the surface of the substrate 100 and a second opening 216 that is smaller in size than the first opening 206. The first opening 206 and the second opening 216 are respectively located in the first region R1 and the second region R2 of the substrate 100. In some embodiments, the first region R1 may be, for example, a region where the isolation structure is more prone to dishing, and the second region R2 may be, for example, a region where the isolation structure is less prone to dishing. In some exemplary embodiments, the first zone R1 may be, for example, an isolation area; the second zone R2 may be, for example, a dense area. The method and material for forming the mask layer 204 are similar to those of the mask layer 104, and details are not described herein again.

Referring to FIG. 2B, the first opening 206 and the substrate 100 exposed by the second opening 216 are removed to form a first trench 208 in the substrate 100 of the first region R1, and a smaller size than the first trench in the second region R2. The second trench 218 of 208.

Referring to FIG. 2C, a dielectric material layer 110 is formed on the substrate 100. In one embodiment, the thickness of the dielectric material layer 110 is less than half of the trench width of the second trench 218, such that the dielectric material layer 110 is conformally formed on the first trench 208 and the second region R2 of the first region R1. The second trench 218 and the surface of the mask layer 104 do not fill the first trench 208 and the second trench 218. The thickness of the dielectric material layer 110 is, for example, 50 angstroms to 500 angstroms.

Referring to FIG. 2D, the dielectric material layer 110 of the first region R1 is selectively subjected to a structural destruction process G to form a first dielectric layer 110a in the first region R1, while the second region R2 is maintained. A layer of dielectric material 110. The film quality of the first dielectric layer 110a obtained by performing the structural destruction treatment G is lower than that of the dielectric material layer 110 subjected to the structural destruction treatment. The structural destruction treatment G is, for example, a porous treatment such that the first dielectric layer 110a has a porous structure. The porosification treatment is carried out, for example, by using GCIB. In some embodiments, the mask layer M may be formed on the first region R1 where the structural damage treatment is not required to be shielded to selectively perform structural damage treatment on the dielectric material layer 110 of the first region R1. . The material of the mask layer M is, for example, a photoresist material. The method of forming the mask layer M is, for example, a spin coating method. In some embodiments, the mask layer M is removed after selectively subjecting the dielectric material layer 110 of the first region R1 to a structural damage process G. The method of removing the mask layer M is, for example, an ashing process. In other embodiments, the mask layer M may not be formed on the first region R1, and the dielectric material layer 110 of the first region R1 may be selectively damaged by the positioning system of the machine. G. The time of the structural destruction treatment G can be appropriately adjusted depending on the energy amount of the structural destruction treatment G, the range of the structural destruction treatment G, or the material of the dielectric material layer 110. After the structural damage treatment G (for example, the porous treatment), the material of the first dielectric layer 110a is still the same as the dielectric material layer 110 (for example, yttrium oxide), but the structure of the first dielectric layer 110a (or The film quality) is inferior to the structure (or film quality) of the dielectric material layer 110 (for example, the porosity of the first dielectric layer 110a is greater than the porosity of the dielectric material layer 110), so when the removal process is subsequently performed, The removal rate of the first dielectric layer 110a can be increased.

Referring to FIG. 2D and FIG. 2E , the second dielectric layer 112 is filled in the first trench 208 and the second trench 218 and covers the first dielectric layer 110 a and the dielectric material layer 110 . In some embodiments, the second dielectric layer 112 may be the same or different from the material of the first dielectric layer 110. The second dielectric layer 112 may be the same or different from the material of the first dielectric layer 110a, but the structure (or film quality) of the second dielectric layer 112 is superior to the structure of the first dielectric layer 110a (or film) quality). For example, the density of the second dielectric layer 112 is higher than the density of the first dielectric layer 110a, or the porosity of the second dielectric layer 112 is smaller than the porosity of the first dielectric layer 110a. The material of the second dielectric layer 112 is, for example, ruthenium oxide. The method of forming the second dielectric layer 112 may be the same as or different from the method of forming the dielectric material layer 110. The method of forming the second dielectric layer 112 is, for example, CVD, ALD, or a combination thereof.

Referring to FIG. 2F, the dielectric material layer 110, the first dielectric layer 110a, and the second dielectric layer 112 on the mask layer 204 are removed. In some embodiments, the method of removing the dielectric material layer 110, the first dielectric layer 110a, and the second dielectric layer 112 on the mask layer 204 may employ a planarization process. The planarization process is performed, for example, by using the mask layer 204 as a polishing stop layer, and performing a CMP process on the dielectric material layer 110, the first dielectric layer 110a, and the second dielectric layer 112 on the mask layer 204. In some embodiments, the dielectric material layer 110, the first dielectric layer 110a and the second dielectric layer 112 are of the same material, but the first dielectric layer 110a is less structural (eg, lower density or porosity). The structure of the dielectric material layer 110 and the second dielectric layer 112 is better (for example, the density is higher or the porosity is smaller), and therefore, the polishing rate of the first dielectric layer 110a is greater than that of the dielectric material layer. 110 and the polishing rate of the second dielectric layer 112. In some exemplary embodiments, the polishing rate ratio of the first dielectric layer 110b to the dielectric material layer 111 is, for example, 1.5 to 3.

That is, after the first trench 208 and a portion of the second dielectric layer 112 on the second trench 218 are removed to expose the first dielectric layer 110a and the dielectric material layer 110, the second dielectric layer 112 is removed. The polishing rate is less than the polishing rate of the first dielectric layer 110a. Therefore, after the first dielectric layer 110a and the dielectric material layer 110 are removed to expose the mask layer 204, the first trench 208 of the first region R1 The top surface of the second dielectric layer 112a may be higher than the top surface of the first dielectric layer 110a, for example, still higher than or equal to the top surface of the mask layer 204. In addition, in some embodiments, the dielectric material layer 110 of the second region R2 is the same material as the second dielectric layer 112, and has substantially the same polishing rate, but the second trench 218 located in the second region R2 is larger in size. Small, therefore, when the dielectric material layer 110 on the mask layer 204 is removed, the top surface of the second dielectric layer 112a in the second trench 218 and the top surface of the mask layer 204 can be substantially coplanar . Therefore, the process margin can be increased to avoid the problem that the second dielectric layer 112a in the second trench 218 is dished.

Referring to FIG. 2F and FIG. 2G simultaneously, the pad layer 102 and the mask layer 204 on the substrate 100 are removed to expose the surface of the substrate 100 and form the isolation structure 114 in the substrate 100 of the first region R1 and the second region R2, respectively. And an isolation structure 214. In some embodiments, the first dielectric layer 110b, the dielectric material layer 111, and the second dielectric layer 112a on the substrate 100 are also removed when the pad layer 102 is removed, thus the substrate 100 of the first region R1. The isolation structure 114 formed therein includes a first dielectric layer 110c and a second dielectric layer 112b, and the isolation structure 214 formed in the substrate 100 of the second region R2 includes a dielectric material layer 111a and a second dielectric layer 112b. The method of removing the mask layer 204 is, for example, wet etching with a hot phosphoric acid solution. The method of removing the underlayer 102 is, for example, a wet etching process using a hydrofluoric acid solution. In some exemplary embodiments, in the wet etching process of removing the pad layer 102, the etching selectivity ratio of the first dielectric layer 110b and the second dielectric layer 112a is, for example, 1.5 to 3; the first dielectric layer 110b and The etching selection ratio of the dielectric material layer 111 is, for example, 1.5 to 3.

3A-3E are schematic views of a method of fabricating an isolation structure in accordance with still another embodiment of the present invention. First, the process of FIGS. 2A and 2B is performed to form a first trench 208 in the substrate 100 of the first region R1, and a second trench 218 having a smaller size than the first trench 208 in the second region R2.

Next, referring to FIG. 3A, a dielectric material layer 310 is formed on the substrate 100. The thickness of the dielectric material layer 310 is greater than half the trench width of the second trench 218, but less than half the trench width of the first trench 208. Thus, the conformal material layer 310 conforms to fill the second trench 218, but the first trench 208 is a conformal layer that only covers and covers the surface of the mask layer 204 without filling the trench 208. The material of the dielectric material layer 310 is, for example, ruthenium oxide. The method of forming the dielectric material layer 310 is, for example, CVD, ALD, or a combination thereof. The thickness of the dielectric material layer 310 is, for example, 50 angstroms to 500 angstroms or more.

Referring to FIG. 3B, the dielectric material layer 310 of the first region R1 is selectively subjected to a structural destruction process G to form a first dielectric layer 310a in the first region R1, and the second region R2 maintains the original dielectric layer. Electrical material layer 310. The film quality of the first dielectric layer 310a obtained by performing the structural destruction treatment G is lower than that of the dielectric material layer 310 subjected to the structural destruction treatment. The structural destruction treatment G is, for example, a porous treatment such that the first dielectric layer 310a has a porous structure. The porosification treatment is carried out, for example, by using GCIB. In some embodiments, the structural destruction process G of the dielectric material layer 310 of the first region R1 can be selectively performed by the positioning system of the machine. In other embodiments, the mask layer M may be masked on the first region R1 where the structural damage process G is not required to be selectively performed to selectively perform the dielectric material layer 310 of the first region R1. Structural damage treatment G. Further, the time of the structural destruction process G can be appropriately adjusted depending on the energy amount of the structural destruction process G, the range of the structural destruction process G, or the material of the dielectric material layer 310. After performing a structural destruction treatment (for example, a porous treatment), the material of the first dielectric layer 310a is still the same as the dielectric material layer 310 (for example, yttrium oxide), but the structure of the first dielectric layer 310a (or film) The quality) is inferior to the structure (or film quality) of the dielectric material layer 310 (for example, the porosity of the first dielectric layer 310a is greater than the porosity of the dielectric material layer 310), so that when the removal process is subsequently performed, The removal rate of the first dielectric layer 310a is increased. In some exemplary embodiments, the polishing rate ratio of the first dielectric layer 310a to the dielectric material layer 310 is, for example, 1.5 to 3.

Referring to FIG. 3B and FIG. 3C , the second dielectric layer 112 is filled in the first trench 208 and covers the first dielectric layer 310 a and the dielectric material layer 310 . In these embodiments, the dielectric material layer 310 has filled the second trench 218, and thus the second dielectric layer 112 is not filled in the second trench 218. The material of the second dielectric layer 112 may be the same as or different from the material of the dielectric material layer 310. That is, the material of the second dielectric layer 112 may be the same as or different from the material of the first dielectric layer 310a, but the structure (or film quality) of the second dielectric layer 112 is superior to the first dielectric layer 310a. Structural (or film quality). For example, the density of the second dielectric layer 112 is higher than the density of the first dielectric layer 310a, or the porosity of the second dielectric layer 112 is less than the porosity of the first dielectric layer 310a. The material of the second dielectric layer 112 is, for example, ruthenium oxide. The method of forming the second dielectric layer 112 may be the same as or different from the method of forming the dielectric material layer 310. The method of forming the second dielectric layer 112 is, for example, CVD, ALD, or a combination thereof.

Referring to FIG. 3C and FIG. 3D simultaneously, the dielectric material layer 310, the first dielectric layer 310a, and the second dielectric layer 112 on the mask layer 204 are removed. In some embodiments, the method of removing the dielectric material layer 310, the first dielectric layer 310a, and the second dielectric layer 112 on the mask layer 204 may employ a planarization process. The planarization process is performed, for example, by using the mask layer 204 as a polishing stop layer, and performing a CMP process on the dielectric material layer 310, the first dielectric layer 310a, and the second dielectric layer 112 on the mask layer 204. In some embodiments, the dielectric material layer 310, the first dielectric layer 310a and the second dielectric layer 112 are of the same material, but the first dielectric layer 310a has poorer structure (or film quality) (eg, density is higher). Low or high porosity), while the dielectric material layer 310 and the second dielectric layer 112 are better in structure (or film quality) (for example, higher density or smaller porosity), therefore, the first dielectric The polishing rate of layer 310a is greater than the polishing rate of dielectric material layer 310 and second dielectric layer 112. That is, when a portion of the second dielectric layer 112 is removed to expose the first dielectric layer 310a (and the dielectric material layer 310), the polishing rate of the second dielectric layer 112 is less than the first dielectric. The polishing rate of the layer 310a, therefore, when the first dielectric layer 310a in the first region R1 is removed to expose the mask layer 204, the top surface of the second dielectric layer 112a in the first trench 208 is high. The top surface of the first dielectric layer 310a is, for example, still higher than or equal to the top surface of the mask layer 204. In addition, the second trench 218 located in the second region R2 is smaller in size, and the polishing rate of the second dielectric layer 112 is comparable to the polishing rate of the dielectric material layer 310, and therefore, the removal on the mask layer 204 is removed. After the layer of electrical material 310, the top surface of the dielectric material layer 311 in the second trench 218 remains substantially coplanar with the top surface of the mask layer 204. As a result, the process margin can be increased to avoid or reduce the problem of dishing of the dielectric material layer 311 in the second trench trench 218.

Referring to FIG. 3D and FIG. 3E simultaneously, the pad layer 102 and the mask layer 204 on the substrate 100 are removed to expose the surface of the substrate 100 and form the isolation structure 314 in the substrate 100 of the first region R1 and the second region R2, respectively. And an isolation structure 311a. In some embodiments, the removal of the pad layer 102 also removes the first dielectric layer 310b, the dielectric material layer 311, and the second dielectric layer 112a on the substrate 100, thus forming in the substrate 100 of the first region R1. The isolation structure 314 includes a first dielectric layer 310c and a second dielectric layer 112b, and an isolation structure 311a is formed in the substrate 100 of the second region R2. The method of removing the mask layer 204 is, for example, wet etching with a hot phosphoric acid solution. The method of removing the underlayer 102 is, for example, wet etching with a hydrofluoric acid solution. In some exemplary embodiments, in the wet etching process of removing the pad layer 102, the etching selectivity ratio of the first dielectric layer 310b and the second dielectric layer 112a is, for example, 1.5 to 3; the first dielectric layer 310b and The etching selection ratio of the dielectric material layer 311 is, for example, 1.5 to 3.

In summary, the isolation structure and the manufacturing method thereof described in the above embodiments are structurally damaged on the dielectric material layer formed on the sidewall and the bottom of the trench to form a poor film quality (for example, a porous structure). The first dielectric layer is such that the rate at which the first dielectric layer is removed is greater than the rate at which the second dielectric layer is removed. Therefore, when the first dielectric layer on the mask layer is removed, the top surface of the second dielectric layer in the trench is still higher than or equal to the top surface of the mask layer. In this way, the process margin of over-grinding of the isolation structure can be improved to avoid or reduce the problem that the isolation structure of the open area generates dishing, so that the isolation structure has good flatness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧ cushion

104, 204, M‧‧ ‧ cover layer

106‧‧‧ openings

108‧‧‧ Ditch

110, 111, 310, 311, 111a‧‧‧ dielectric material layer

110a, 110b, 110c, 310a, 310b, 310c‧‧‧ first dielectric layer

112, 112a, 112b‧‧‧ second dielectric layer

114, 214, 311a, 314‧‧ ‧ isolation structure

206‧‧‧ first opening

216‧‧‧ second opening

208‧‧‧First ditches

218‧‧‧Second ditches

R1‧‧‧ first area

R2‧‧‧ second area

G‧‧‧Structural damage treatment

1A-1F are schematic views of a method of fabricating an isolation structure in accordance with an embodiment of the present invention. 2A through 2G are schematic views showing a method of fabricating an isolation structure in accordance with another embodiment of the present invention. 3A-3E are schematic views of a method of fabricating an isolation structure in accordance with still another embodiment of the present invention.

Claims (14)

A method of fabricating an isolation structure, comprising: forming a mask layer on a substrate, the mask layer having an opening; removing the substrate at the bottom of the opening to form a trench in the substrate; Forming a dielectric material layer on the sidewall and the bottom surface and the mask layer; structurally destroying the dielectric material layer to form a first dielectric layer; filling the trench into the first layer The dielectric layer is covered with a second dielectric layer; the first dielectric layer and the second dielectric layer on the mask layer are removed; and the mask layer is removed. The method of manufacturing an isolation structure according to claim 1, wherein the structural destruction treatment comprises a porous treatment. The method of manufacturing an isolation structure according to claim 2, wherein the porosification treatment comprises a gas cluster ion beam. The method of fabricating the isolation structure of claim 1, wherein the first dielectric layer has a porosity greater than a porosity of the second dielectric layer. The method of manufacturing the isolation structure of claim 1, wherein the trench comprises a first trench and a second trench smaller than the first trench, the first trench being located in a first region of the substrate The second trench is located in a second region of the substrate, and the structural destruction treatment selectively performs on the dielectric material layer located in the first region. The method of manufacturing the isolation structure of claim 5, wherein: the dielectric material layer does not fill the first trench and the second trench; and the second dielectric layer fills in The first trench and the second trench are described. The method of manufacturing the isolation structure of claim 5, wherein: the dielectric material layer does not fill the first trench and fills the second trench; and the second dielectric layer Filling the first trench without filling the second trench. An isolation structure comprising: a first dielectric layer having a porous structure, the first dielectric layer being located at a sidewall and a bottom surface of the first trench in the substrate; and a second dielectric layer located in the first trench And located on the first dielectric layer. The isolation structure of claim 8, wherein the first dielectric layer and the second dielectric layer are of the same material. The isolation structure of claim 9, wherein the first dielectric layer has a porosity greater than a porosity of the second dielectric layer. The isolation structure of claim 9, further comprising: a dielectric material layer covering a sidewall and a bottom surface of the second trench in the substrate; and the second dielectric layer is further filled in the second And covering the dielectric material layer in the trench, wherein the size of the first trench is larger than the size of the second trench. The isolation structure of claim 9, further comprising: a dielectric material layer filling a sidewall and a bottom surface of the second trench in the substrate, wherein the size of the first trench is larger than that of the second trench size. The isolation structure of claim 11 or 12, wherein the dielectric material layer is the same material as the first dielectric layer and the second dielectric layer. The isolation structure of claim 13, wherein the first dielectric layer has a porosity greater than a porosity of the dielectric material layer and greater than a porosity of the second dielectric layer.