TW201834388A - Amplifier - Google Patents

Abstract

An amplifier including a current adjuster, a first control circuit, a second control circuit, a first output transistor, and a second output transistor is provided. The current adjuster compares an output voltage and a reference voltage and generates two adjustment signals according to the compared result. The first control circuit generates a first control signal according to the two adjustment signals. The second control circuit generates a second control signal according to the two adjustment signals. The first output transistor outputs a first output current according to the first control signal. The second output transistor outputs a second output current according to the second control signal. When the output voltage is higher than the reference voltage, the first output current is maintained and the second output current is increased. When the output voltage is not higher than the reference voltage, the first output current is increased and the second output current is maintained.

Description

   Amplifier   

The present invention relates to an amplifier, and in particular to an amplifier in which a quiescent current is not affected by power or power supply of an external load.

In a common circuit, a sensor often detects a change in position, angle, or pressure, and the sensor converts the detection result into a current or voltage signal and provides it to the back-end processor. The processor calculates the amount of physical change by measuring the current or voltage signal output by the sensor. However, sometimes the current or voltage signal generated by the sensor is small, so that the back-end processor cannot operate according to the output signal of the sensor.

To solve the above problems, the present invention provides an amplifier, which includes a current adjusting device, a first control circuit, a second control circuit, a first output transistor and a second output transistor. The current adjustment device compares an output voltage and a reference voltage to generate a comparison result, and then generates a first adjustment signal and a second adjustment signal according to the comparison result. The first control circuit generates a first control signal according to the first and second adjustment signals. The second control circuit generates a second control signal according to the first and second adjustment signals. The first output transistor outputs a first output current according to the first control signal. The second output transistor outputs a second output current according to the second control signal. When the output voltage is greater than the reference voltage, the first output current does not change and the second output current increases. When the output voltage is less than the reference voltage, the first output current increases and the second output current does not change.

100‧‧‧ amplifier

110, 400‧‧‧ current adjustment device

120, 130‧‧‧ control circuit

OM1, OM2‧‧‧ output transistor

ND1, ND2‧‧‧ operation node

VDD‧‧‧ Operating voltage

GND‧‧‧ ground voltage

VOUT‧‧‧Output voltage

REF‧‧‧Reference voltage

SA1, SA2‧‧‧ Adjustment signal

PG, NG‧‧‧ control signal

I _OM1 , I _OM2 ‧‧‧ output current

ND3‧‧‧ output node

210, 220‧‧‧ curves

310, 320‧‧‧ control circuit

CC1 ~ CC7‧‧‧Current source

M1 ~ M12‧‧‧Transistors

I1‧‧‧first current

I2‧‧‧second current

230, 240‧‧‧ interval

140‧‧‧load

FIG. 1 is a schematic diagram of an amplifier of the present invention.

FIG. 2 is a schematic diagram showing the relationship between the output current and the output voltage of the present invention.

FIG. 3 is a schematic diagram of a control circuit of the present invention.

FIG. 4 is a possible embodiment of the current adjustment device of the present invention.

In order to make the objects, features, and advantages of the present invention more comprehensible, embodiments are exemplified below and described in detail with the accompanying drawings. The description of the present invention provides different embodiments to explain the technical features of different embodiments of the present invention. Wherein, the arrangement of the elements in the embodiments is for the purpose of illustration and is not intended to limit the present invention. In addition, the part of the figures in the embodiments is repeated for the sake of simplifying the description, and does not mean the correlation between different embodiments.

FIG. 1 is a schematic diagram of an amplifier of the present invention. As shown, the amplifier 100 includes a current adjusting device 110, control circuits 120, 130, and output transistors OM1 and OM2. The current adjusting device 110 is coupled to the operation nodes ND1 and ND2, and is used for receiving the operation voltage VDD and the ground voltage GND. In this embodiment, the current adjusting device 110 compares an output voltage VOUT and a reference voltage REF to generate a comparison result, and then generates adjustment signals SA1 and SA2 according to the comparison result. In a possible embodiment, the adjustment signals SA1 and SA2 are current signals. The control circuits 120 and 130 generate control signals PG and NG according to the adjustment signals SA1 and SA2 to control the magnitude of the output current I _OM1 and the output current I _OM2 flowing through the output transistor OM1.

The control circuits 120 and 130 are coupled to the operation nodes ND1 and ND2, and are used for receiving the operation voltage VDD and the ground voltage GND. The control circuit 120 generates a control signal PG according to the adjustment signals SA1 and SA2. The control circuit 130 generates a control signal NG according to the adjustment signals SA1 and SA2. In this embodiment, the control signal PG is used to control the magnitude of the current I _OM1 flowing through the output transistor OM1, and the control signal NG is used to control the magnitude of the current I _OM2 flowing through the output transistor OM2.

The output transistors OM1 and OM2 are connected in series between the operation nodes ND1 and ND2, and the output transistors OM1 and OM2 are commonly coupled to the output node ND3. The voltage at the output node ND3 is used as the output voltage VOUT. In this embodiment, the output transistor OM1 outputs an output current I _OM1 according to the control signal PG. The output transistor OM2 outputs an output current I _OM2 according to the control signal NG.

In a possible embodiment, the output current I _{OM1 is} provided to the load 140. When the load 140 draws a larger current, the voltage VOUT of the output node ND3 drops slightly. Since the output voltage VOUT is not equal to the reference voltage REF, the current adjustment device 110 generates adjustment signals SA1 and SA2 according to the difference between the output voltage VOUT and the reference voltage REF, and the control circuits 120 and 130 generate control signals according to the adjustment signals SA1 and SA2, respectively PG and NG are used to increase the output current I _OM1 flowing through the output transistor _OM1 and maintain the output current I _OM2 flowing through the output transistor OM2 at a minimum value, such as 10uA. At this time, the output current I _{OM2 is} called a quiescent current. The invention does not limit the magnitude of the quiescent current. The quiescent current is related to the characteristics (channel aspect ratio) of the output transistor OM2. In this embodiment, the output current I _OM1 flowing through the output transistor _{OM1 is} larger than the output current I _OM2 flowing through the output transistor _OM2 . As the output current I _OM1 gradually increases, the voltage VOUT of the output node ND3 gradually increases. When the voltage VOUT of the output node ND3 is equal to the reference voltage REF, the current adjusting device 110 controls the output transistor OM1 through the adjustment signals SA1 and SA2, so that the output current I _OM1 is equal to the output current I _OM2 .

In another possible embodiment, when the amplifier 100 receives the output current I _OM2 from the load 140, the voltage VOUT of the output node ND3 increases slightly. Since the output voltage VOUT is not equal to the reference voltage REF, the current adjusting device 110 generates corresponding adjustment signals SA1 and SA2 according to the gap between the output voltage VOUT and the reference voltage REF. The control circuits 120 and 130 generate control signals PG and NG according to the adjustment signals SA1 and SA2, respectively, to increase the output current I _OM2 flowing through the output transistor _OM2 and maintain the output current I _OM1 flowing through the output transistor OM1 at a Minimum value, such as 10uA (quiescent current of output transistor OM1). Therefore, the output current I _OM2 flowing through the output transistor _{OM2 is} larger than the output current I _OM1 flowing through the output transistor _OM1 . As the output current I _OM2 gradually increases, the voltage VOUT of the output node ND3 gradually decreases. When the voltage VOUT of the output node ND3 is equal to the reference voltage REF, the current adjusting device 110 controls the output transistor OM2 through the adjustment signals SA1 and SA2 to make the output current I _OM2 equal to the output current I _OM1 .

In this embodiment, the output transistor OM1 is a P-type transistor, and its gate receives the control signal PG, its source is coupled to the operation node ND1 to receive the operating voltage VDD, and its drain is coupled to the output node ND3 . The output transistor OM1 determines the magnitude of the output current I _OM1 according to the control signal PG. In a possible embodiment, the output current I _OM1 is a positive current.

The output transistor OM2 is an N-type transistor. Its gate receives the control signal NG, its source is coupled to the operation node ND2 to receive the ground voltage GND, and its drain is coupled to the output node ND3. The output transistor OM2 determines the magnitude of the output current I _OM2 according to the control signal NG. In a possible embodiment, the output current I _OM2 is a negative current.

FIG. 2 is a schematic diagram showing the relationship between the output current and the output voltage of the present invention. The curve 210 represents the output current I _OM1 flowing through the output transistor _OM1 . The curve 220 represents the output current I _OM2 flowing through the output transistor _OM2 . In section 230, the amplifier 100 operates in a source mode. In this mode, the amplifier 100 provides an output current I _OM1 to the load 140 through the output transistor OM1. Therefore, the output current I _OM1 flowing through the output transistor OM1 continuously changes according to the demand of the load 140. In the interval 230, the output current I _OM2 flowing through the output transistor _OM2 remains unchanged, such as 10uA.

In the interval 240, the amplifier 100 operates in a sink mode. In this mode, the amplifier 100 receives the current provided by the load 140 through the output transistor OM2. Therefore, the output current I _OM2 flowing through the output transistor OM2 continuously changes according to the current supplied by the load 140. In the interval 240, the output current I _OM1 flowing through the output transistor _OM1 remains unchanged, such as 10uA.

In this embodiment, since the amplifier 100 does not change its static current because the external load consumes electricity (ie, the amplifier 100 provides current to the load 140) or discharges (ie, the load 140 provides current to the amplifier 100), the amplifier 100 can be increased 100% efficiency.

FIG. 3 is a schematic diagram of a control circuit of the present invention. As shown, the control circuit 310 includes transistors M1 and M2. Transistors M1 and M2 are connected in series between the operating node ND1 and the current source CC1. The gate of the transistor M1 is coupled to the current source CC1 to provide a control signal PG. Its source is coupled to the operation node ND1 to receive the operating voltage VDD. Its drain is coupled to the source of the transistor M2. The gate of the transistor M2 is coupled to the current sources CC3 and CC4. The drain of the source transistor M1 is coupled to the current source CC1. In this embodiment, the transistors M1 and M2 are both P-type transistors, but the invention is not limited thereto. In other embodiments, the transistors M1 and M2 are N-type transistors.

The current source CC1 is coupled between the transistor M2 and the operation node ND2, and generates a first current I1 according to the adjustment signal SA1. The current sources CC3 and CC4 are connected in series between the operating nodes ND1 and ND2, and are coupled to the gate of the transistor M2. In this embodiment, the current source CC3 generates a first current I1 according to the adjustment signal SA1, and the current source CC4 generates a second current I2 according to the adjustment signal SA2. The present invention does not limit the circuit architecture of the current sources CC1, CC3, and CC4. Any circuit capable of generating a current based on an adjustment signal can be used as the current source CC1, CC3 or CC4. In a possible embodiment, a transistor can be used as a current source. In this example, the transistor adjusts the amount of current flowing through the source-drain according to the adjustment signal.

The control circuit 320 includes transistors M3 and M4. Transistors M3 and M4 are connected in series between the operating node ND2 and the current source CC2. The gate of the transistor M3 is coupled to the current source CC2 and provides a control signal NG. Its source is coupled to the operation node ND2 to receive the ground voltage GND, and its drain is coupled to the source of the transistor M4. The gate of the transistor M4 is coupled to the current sources CC5 and CC6. The drain of the source transistor M3 is coupled to the current source CC2. In this embodiment, the transistors M3 and M4 are both N-type transistors, but they are not intended to limit the present invention. In other embodiments, the transistors M3 and M4 may be replaced by P-type transistors.

The current source CC2 is coupled between the operation node ND1 and the transistor M4, and generates a second current I2 according to the adjustment signal SA2. The current sources CC5 and CC6 are connected in series between the operating nodes ND1 and ND2, and are coupled to the gate of the transistor M4. In this embodiment, the current source CC5 generates a first current I1 according to the adjustment signal SA1, and the current source CC6 generates a second current I2 according to the adjustment signal SA2. The invention does not limit the circuit architecture of the current sources CC2, CC5 and CC6. Any circuit capable of generating a current based on an adjustment signal can be used as the current sources CC2, CC5, and CC6. In a possible embodiment, a transistor can be used as a current source. In this example, the transistor adjusts the amount of current flowing through the source-drain according to the adjustment signal.

In this embodiment, when the output voltage VOUT is less than the reference voltage REF, the current adjusting device 110 increases the first current I1 and decreases the second current I2 through the adjustment signals SA1 and SA2. Since the first current I1 is increased, the transistor M2 is not turned on, so the control circuit 310 does not provide a diode connection. However, since the first current I1 increases, the crystal M4 is turned on. Since the gate and the drain of the transistor M3 are coupled together, the transistor M3 and M4 provide a diode connection to make the output current I _OM2 flowing through the output transistor _OM2 equal to a quiescent current. In a possible embodiment, the output current I OM2 of the output transistor _{OM2 is} as shown in formula (1): I _OM2 = K ₁ * I _M3 ……………………………… (1)

among them ;among them Is the channel aspect ratio of the output transistor OM2; Is the channel aspect ratio of transistor M3; I _M3 is the current flowing through transistor M3. Assume that when K ₁ = 10 and I _M3 = 1uA, the output current I _OM2 = 10uA.

At this time, the output transistor OM1 controls the magnitude of the output current I _OM1 according to the control signal PG. As the first current I1 is larger, the output current I _OM1 flowing through the output transistor OM1 is larger. Therefore, the output voltage VOUT gradually increases until the output voltage VOUT is equal to the reference voltage REF.

When the output voltage VOUT is greater than the reference voltage REF, the current adjusting device 110 reduces the first current I1 and increases the second current I2 through the adjustment signals SA1 and SA2. Since the first current I1 is reduced, the transistor M2 is turned on. Since the gate and the drain of the transistor M1 are coupled together, the transistors M1 and M2 provide a diode connection to maintain the output current I _OM1 flowing through the output transistor OM1 at a fixed value. In a possible embodiment, the output current I OM1 of the output transistor _{OM1 is} as shown in formula (2): I _OM1 = K ₂ * I _M1 ……………………………… (2)

among them ;among them Is the channel aspect ratio of the output transistor OM1; Transistor M1 as the aspect ratio of the channel; the I is the current through transistor _M1 M1 stream. Assume that when K ₂ = 10 and I _M1 = 1uA, the output current I _OM1 = 10uA.

At this time, as the second current I2 increases, the transistor M4 is not turned on. Therefore, the control circuit 320 does not provide a diode connection. As the second current I2 increases, the voltage level of the control signal NG also increases. Therefore, the output current I _OM2 flowing through the output transistor OM2 is increased and the output voltage VOUT is decreased until the output voltage VOUT is equal to the reference voltage REF.

FIG. 4 is a possible embodiment of the current adjustment device of the present invention. As shown, the current adjusting device 400 includes transistors M5 to M12 and a current source CC7. In this embodiment, the transistors M5, M6, M9, and M11 are P-type transistors, and the transistors M7, M8, M10, and M12 are N-type transistors, but the invention is not limited thereto. In other embodiments, the transistors M5, M6, M9, and M11 are N-type transistors, and the transistors M7, M8, M10, and M12 are P-type transistors.

The gate of the transistor M5 receives the output voltage VOUT, its source is coupled to the current source CC7, its drain is coupled to the drain of the transistor M7, and an adjustment signal SA1 is provided. The gate and the drain of the transistor M7 are coupled to the drain of the transistor M5, and the source is coupled to the operation node ND2 to receive the ground voltage GND.

The gate of the transistor M6 receives the reference voltage REF, its source is coupled to the source of the transistor M5 and the current source CC7, its drain is coupled to the drain of the transistor M8, and provides an adjustment signal SA2. The gate and the drain of the transistor M8 are coupled to the drain of the transistor M6, and the source is coupled to the operation node ND2 to receive the ground voltage GND.

The current source CC7 is coupled between the operation node ND1 and the source of the transistor M5 to provide a current 2I. The current 2I may be twice the first current I1 or the second current I2. In this embodiment, when the output voltage VOUT is equal to the reference voltage REF, the first current I1 is equal to the second current I2.

The source of the transistor M9 is coupled to the operation node ND1, and its gate and drain are coupled to the drain of the transistor M10. The gate of the transistor M10 is coupled to the gate of the transistor M7, its drain is coupled to the drain of the transistor M9, and its source is coupled to the operation node ND2 to receive the ground voltage GND. In this embodiment, when the output voltage VOUT is smaller than the reference voltage REF, the transistor M5 is turned on, and therefore, the first current I1 flows through the transistor M7. The magnitude of the first current I1 is related to the difference between the output voltage VOUT and the reference voltage REF. When the difference between the output voltage VOUT and the reference voltage REF is larger, the first current I1 is larger. At this time, due to the characteristics of the current mirror, the current flowing through the transistors M9 and M10 is also equal to the first current I1.

The source of the transistor M11 is coupled to the operation node ND1, and its gate and drain are coupled to the drain of the transistor M12. The gate of the transistor M12 is coupled to the gate of the transistor M8, its drain is coupled to the drain of the transistor M11, and its source is coupled to the operation node ND2 to receive the ground voltage GND. In this embodiment, when the output voltage VOUT is greater than the reference voltage REF, the transistor M6 is turned on. Therefore, the second current I2 flows through the transistor M8. The magnitude of the second current I2 is related to the difference between the output voltage VOUT and the reference voltage REF. When the difference between the output voltage VOUT and the reference voltage REF is larger, the second current I2 is larger. At this time, due to the characteristics of the current mirror, the current flowing through the transistors M11 and M12 is also equal to the second current I2.

By controlling the magnitude of the first current I1 and the second current I2, the output voltage VOUT can be changed. When the output voltage VOUT is less than the reference voltage REF, the amplifier 100 increases the output current I _OM1 flowing through the output transistor OM1 to increase the output voltage VOUT. At this time, the output current I _OM2 flowing through the output transistor _OM2 remains unchanged. When the output voltage VOUT is greater than the reference voltage REF, the amplifier 100 increases the output current I _OM2 flowing through the output transistor OM2 to reduce the output voltage VOUT. At this time, the output current I _OM1 flowing through the output transistor _OM1 remains unchanged. Since the quiescent current of the amplifier 100 is not affected by the output voltage VOUT, the efficiency of the amplifier 100 can be increased.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those having ordinary knowledge in the technical field to which this invention belongs. In addition, unless explicitly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with its meaning in articles in the relevant technical field, and should not be interpreted as ideal or overly formal.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method according to the embodiments of the present invention may be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims (10)

    An amplifier includes: a current adjusting device that compares an output voltage and a reference voltage to generate a comparison result, and then generates a first adjustment signal and a second adjustment signal according to the comparison result; a first control circuit, Generating a first control signal according to the first and second adjustment signals; a second control circuit generating a second control signal according to the first and second adjustment signals; a first output transistor according to the first control The signal outputs a first output current; and a second output transistor outputs a second output current according to the second control signal, wherein when the output voltage is greater than the reference voltage, the first output current does not change, and the The second output current increases. When the output voltage is less than the reference voltage, the first output current increases, and the second output current does not change.         The amplifier according to item 1 of the patent application range, wherein when the output voltage is greater than the reference voltage, the first output current is smaller than the second output current, and when the output voltage is less than the reference voltage, the first output current Greater than the second output current, when the output voltage is equal to the reference voltage, the first output current is equal to the second output current.         The amplifier according to item 1 of the scope of patent application, wherein the first and second output transistors are commonly coupled to an output node, and the voltage of the output node is the output voltage.         The amplifier according to item 1 of the scope of patent application, wherein when the output voltage is less than the reference voltage, the second control circuit provides a diode connection, and when the output voltage is greater than the reference voltage, the first control circuit Provide a diode connection.         The amplifier according to item 1 of the scope of patent application, wherein the first control circuit includes: a first transistor coupled to a first operating node; and a second transistor connected in series with the first transistor and a Between the first current sources, wherein the first current source generates a first current according to the first adjustment signal and is coupled to a second operation node.         The amplifier according to item 5 of the patent application, wherein a gate of the first transistor is coupled to the first current source and provides the first control signal.         According to the amplifier in claim 5, the second control circuit includes: a third transistor coupled to the second operating node; and a fourth transistor connected in series with the third transistor and a Between the second current sources, wherein the second current source generates a second current according to the second adjustment signal and is coupled to the first operation node.         The amplifier according to item 7 of the patent application, wherein a gate of the third transistor is coupled to the second current source for providing the second control signal.         The amplifier according to item 7 of the patent application scope, wherein the first and second transistor systems are P-type transistors, and the third and fourth transistor systems are N-type transistors.         The amplifier according to item 7 of the scope of patent application, further comprising: a third current source coupled between the first operation node and the gate of the second transistor, and generating the A first current; a fourth current source coupled between the gate of the second transistor and the second operating node, and generating the second current according to the second adjustment signal; a fifth current source Is coupled between the first operating node and the gate of the fourth transistor and generates the first current according to the first adjustment signal; and a sixth current source is coupled to the fourth transistor Between the gate and the second operation node, and generating the second current according to the second adjustment signal.