TW201833924A - Memory control circuit unit, memory storage device and signal receiving method - Google Patents

Abstract

A memory control circuit unit, a memory storage device and a signal receiving method are provided. In one exemplary embodiment, a memory interface of the memory control circuit unit receives first signal from a volatile memory and adjust a voltage value of the first signal to a voltage range, where a central value of the voltage range is different from a default voltage value, and the default voltage value is equal to half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground value. Then, the memory interface generates an input signal according to a voltage relative relation between the first signal and an internal reference voltage.

Description

Memory control circuit unit, memory storage device and signal receiving method

The present invention relates to a signal receiving technology, and more particularly to a memory control circuit unit, a memory storage device, and a signal receiving method.

Digital cameras, mobile phones and MP3 players have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Because the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable. It is built into various portable multimedia devices exemplified above.

Some types of storage devices are also equipped with rewritable non-volatile memory modules and dynamic random access memory (DRAM) volatile memory to provide long-term storage and temporary buffering of data. In a memory device configured with a volatile memory, a termination resistor is generally provided in the memory interface circuit as a signal receiving end of the volatile memory to maintain the signal quality of the high-speed signal from the volatile memory. However, the setting of the termination resistor also increases the power consumption at the signal receiving end.

The invention provides a memory control circuit unit, a memory storage device and a signal receiving method, which can reduce the power consumption of the memory interface circuit when receiving signals from the volatile memory.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling volatile memory. The memory control circuit unit includes a memory controller and a memory interface circuit. The memory interface circuit is coupled to the memory controller. The memory interface circuit is configured to receive a first signal from the volatile memory. The memory interface circuit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit. The intermediate value of the voltage range is not equal to the preset voltage value. The preset voltage value is half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. The memory interface circuit is further configured to generate an input signal according to a voltage relationship between the first signal and an internal reference voltage.

In an exemplary embodiment of the present invention, the memory interface circuit includes an impedance component for providing the internal impedance, wherein the first end of the impedance component is coupled to the receiving path of the first signal, And the second end of the impedance element is coupled to the supply voltage or the reference ground voltage.

In an exemplary embodiment of the present invention, the memory interface circuit is further configured to receive a second signal from the volatile memory before receiving the first signal. The memory interface circuit is further configured to perform a voltage dividing operation on the second signal to generate the internal reference voltage.

In an exemplary embodiment of the invention, the memory interface circuit is further configured to send a preset read command sequence to indicate that the preset data of the volatile memory is read. The volatile memory is configured to generate the second signal according to the preset read command sequence.

In an exemplary embodiment of the invention, the memory interface circuit includes a comparison circuit. The comparison circuit is configured to compare the internal reference voltage with the voltage value of the first signal to generate the input signal.

In an exemplary embodiment of the invention, the memory interface circuit includes a first connection interface, a second connection interface, and a reference voltage generator. The first connection interface is configured to be coupled to the memory controller. The second connection interface is configured to be coupled to the volatile memory. The reference voltage generator is coupled to the first connection interface and the second connection interface. The reference voltage generator is configured to detect the internal impedance via the first connection interface, detect an external impedance of the volatile memory via the second connection interface, and generate the internal according to the detection result Reference voltage.

In an exemplary embodiment of the present invention, the reference voltage generator includes a voltage detecting circuit for detecting an impedance element in the memory interface circuit in response to the internal impedance and the external impedance. The first voltage. The voltage value of the first voltage is positively related to the voltage value of the supply voltage.

In an exemplary embodiment of the invention, the reference voltage generator further includes a voltage dividing circuit and a voltage output circuit. The voltage dividing circuit is coupled to the voltage detecting circuit and configured to perform a voltage dividing operation on the second voltage of the output end of the voltage detecting circuit. The voltage output circuit is coupled to the voltage dividing circuit and configured to generate the internal reference voltage in response to a third voltage at an output of the voltage dividing circuit.

Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, a volatile memory, and a memory control circuit unit. The connection interface unit is configured to be coupled to a host system. The memory control circuit unit is coupled to the connection interface unit, the rewritable non-volatile memory module, and the volatile memory. The memory control circuit unit is configured to receive a first signal from the volatile memory. The memory control circuit unit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory control circuit unit. The intermediate value of the voltage range is not equal to the preset voltage value. The preset voltage value is half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. The memory control circuit unit is further configured to generate an input signal according to a voltage relationship between the first signal and an internal reference voltage.

In an exemplary embodiment of the invention, the memory control circuit unit includes an impedance element for providing the internal impedance. The first end of the impedance element is coupled to the receiving path of the first signal, and the second end of the impedance element is coupled to the supply voltage or the reference ground voltage.

In an exemplary embodiment of the invention, the third end of the impedance element is configured to receive an enable signal, wherein the impedance element provides the internal impedance in response to the enable signal.

In an exemplary embodiment of the invention, the enabling time of the enable signal is positively related to the total number of consecutive bits transmitted via the first signal.

In an exemplary embodiment of the present invention, before receiving the first signal, the memory control circuit unit is further configured to receive a second signal from the volatile memory. The memory control circuit unit is further configured to perform a voltage dividing operation on the second signal to generate the internal reference voltage.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to send a preset read command sequence to instruct to read the preset data of the volatile memory. The volatile memory is configured to generate the second signal according to the preset read command sequence.

In an exemplary embodiment of the invention, the memory control circuit unit includes a comparison circuit. The comparison circuit is configured to compare the internal reference voltage with the voltage value of the first signal to generate the input signal.

In an exemplary embodiment of the invention, the volatile memory is used to provide an external impedance. The voltage value of the first signal is further adjusted to the voltage range in response to the external impedance.

Another exemplary embodiment of the present invention provides a signal receiving method for a memory storage device including a volatile memory, the signal receiving method including: receiving, by the memory interface circuit, the first memory from the volatile memory a signal; adjusting a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, wherein an intermediate value of the voltage range is not equal to a preset voltage value, and the preset voltage The value is a half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage; and an input signal is generated according to a voltage relationship between the first signal and an internal reference voltage.

In an exemplary embodiment of the present invention, the signal receiving method further includes: providing the internal impedance by an impedance component of the memory interface circuit, wherein a first end of the impedance component is coupled to the first a receiving path of a signal, and the second end of the impedance element is coupled to the supply voltage or the reference ground voltage.

In an exemplary embodiment of the present invention, the signal receiving method further includes: receiving, by the third end of the impedance element, an enable signal; and providing, by the impedance element, the signal in response to the enable signal Internal impedance.

In an exemplary embodiment of the present invention, the signal receiving method further includes: controlling an enabling time of the enabling signal, so that the enabling time is positively correlated with multiple consecutive transmissions via the first signal The total number of bits.

In an exemplary embodiment of the present invention, the signal receiving method further includes: receiving, by the memory interface circuit, a second signal from the volatile memory before receiving the first signal; The second signal performs a voltage division operation to generate the internal reference voltage.

In an exemplary embodiment of the present invention, the signal receiving method further includes: transmitting a preset read command sequence to indicate reading the preset data of the volatile memory; and determining, by the volatile memory The preset read command sequence generates the second signal.

In an exemplary embodiment of the present invention, the step of generating the input signal according to the voltage relative relationship between the first signal and the internal reference voltage comprises: comparing the internal reference voltage with the first The voltage value of the signal; and generating the input signal according to the comparison result.

In an exemplary embodiment of the present invention, the signal receiving method further includes: providing an external impedance by the volatile memory; and adjusting the voltage value of the first signal to the external impedance to The voltage range.

In an exemplary embodiment of the invention, the volatile memory comprises a fourth generation double data rate synchronous dynamic random access memory.

Based on the above, the present invention proposes to set a specific receiving end circuit in the memory interface circuit to adjust the voltage value of the first signal from the volatile memory to the voltage range and analyze the first using a suitable internal reference voltage. Signal. Thereby, the correctness of the generated input signal can be maintained, and the power consumption when receiving the first signal can be reduced.

The above described features and advantages of the invention will be apparent from the following description.

The following examples are presented to illustrate the invention, but the invention is not limited to the illustrated exemplary embodiments. Also suitable combinations are allowed between the example embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the invention. Referring to FIG. 1, the memory storage device 10 includes a memory control circuit unit 11 and a volatile memory 12. The memory control circuit unit 11 may be packaged as a wafer or composed of electronic circuits disposed on at least one circuit board. In the present exemplary embodiment, the volatile memory 12 is a fourth-generation Double Data Rate 4 Synchronous Dynamic Random Access Memory (DDR 4 SDRAM). In another exemplary embodiment, the volatile memory 12 may also include other types of volatile memory, such as third generation double data rate synchronous dynamic random access memory (DDR 3 SDRAM). Further, the total number of volatile memories 12 may be one or more.

The memory control circuit unit 11 and the volatile memory 12 are mounted on one or more circuit boards in the memory storage device 10. The memory control circuit unit 11 supports a data access operation for the volatile memory 12. In an exemplary embodiment, the memory control circuit unit 11 is regarded as a control chip of the volatile memory 12, and the volatile memory 12 is regarded as a cache memory or buffer of the memory control circuit unit 11. Memory (buffer).

The memory control circuit unit 11 includes a memory controller 111 and a memory interface circuit 112. The memory controller 111 is coupled to the memory interface circuit 112. The memory controller 112 is used to control the volatile memory 12. In an exemplary embodiment, memory controller 112 is also referred to as a DRAM controller.

The memory interface circuit 112 is used to connect the memory controller 111 to the volatile memory 12. When the data is to be read from the volatile memory 12 or stored in the volatile memory 12, the memory controller 111 sends a sequence of instructions to the volatile memory 12 via the memory interface circuit 112. When the volatile memory 12 receives the command sequence, the volatile memory 12 stores the write data corresponding to the command sequence or returns the read data corresponding to the command sequence to the memory via the memory interface circuit 112. Controller 111. In addition, in the memory interface circuit 112, writing data or reading data is transmitted in the form of a data signal. For example, the data signal can be used to transfer bit data including bit "1" and bit "0".

In the present exemplary embodiment, the volatile memory 12 is a double data rate synchronous dynamic random access memory, so the rising edges and falling edges of the clock signal of the memory interface circuit 112 are both It can be used to parse (eg, sample) data signals from volatile memory 12. In other words, within one clock cycle, the memory interface circuit 112 can perform two data writes or reads to the volatile memory 12.

In the present exemplary embodiment, the memory interface circuit 112 conforms to a Stub Series Terminated Logic (SSTL) I/O standard, such as SSTL-2, SSTL-3, SSTL-15, or SSTL-18. . In the present exemplary embodiment, the memory interface circuit 112 includes a connection interface 1311 (also referred to as a first connection interface) and a connection interface 1312 (also referred to as a second connection interface). The connection interface 1311 is used to connect the memory controller 111 and the memory interface circuit 112, and the connection interface 1312 is used to connect the memory interface circuit 112 and the volatile memory 12. In the present exemplary embodiment, the connection interface 1312 includes a plurality of conductive pins. The memory interface circuit 112 is connected to the volatile memory 12 via the conductive pins. In this exemplary embodiment, the conductive pins include at least one pin (also referred to as a data pin) for transmitting data signals. For example, the data pin can be a DQ pin. Thereby, the data signal can be transmitted between the memory interface circuit 112 and the volatile memory 12 via the data pin. In another exemplary embodiment, the conductive pins may also include other functional pins as long as the connection standards used are met. Moreover, in an exemplary embodiment, the connection interface 1311 may also include at least one conductive pin. The total number of conductive pins in the connection interface 1311 may be the same or different than the total number of conductive pins in the connection interface 1312.

2 is a schematic diagram of a memory interface circuit according to an exemplary embodiment of the invention. Referring to FIG. 1 and FIG. 2, the memory interface circuit 112 receives the signal SRX (also referred to as the first signal) from the volatile memory 12. The memory interface circuit 112 then analyzes the signal SRX and generates a signal SIN (also referred to as an input signal). For example, according to the state of the signal SIN, the memory controller 111 can recognize that the bit data represented by the signal SRX is the bit "0" or "1".

In the present exemplary embodiment, the memory interface circuit 112 includes an impedance element 21, an impedance element 22, and a comparison circuit 23. The comparison circuit 23 is coupled to the impedance element 21 and the impedance element 22. The first end of the impedance element 21 is coupled to the receiving path of the signal SRX, and the second end of the impedance element 21 is coupled to the supply voltage VDD of the memory interface circuit 112. In addition, the first end of the impedance element 22 is also coupled to the receiving path of the signal SRX, and the second end of the impedance element 22 is coupled to the reference ground voltage GND of the memory interface circuit 112. From another point of view, the impedance elements 21 and 22 are connected in series between the supply voltage VDD of the memory interface circuit 112 and the reference ground voltage GND.

The impedance elements 21 and 22 are used to provide a path of impedance to the signal SRX. In the present exemplary embodiment, the impedance provided by impedance elements 21 and 22 is also referred to as the internal impedance of memory interface circuit 112. For example, the internal impedance can have a resistance value or a reactance value. In the present exemplary embodiment, the impedances provided by impedance elements 21 and 22 have the same (or close) resistance or reactance values. In another exemplary embodiment, the impedance provided by impedance element 21 and the impedance provided by 22 have different resistance values or reactance values. In an exemplary embodiment, at least one of the impedance elements 21 and 22 is also referred to as an on-die termination (OTT) impedance element of the memory interface circuit 112.

In the present exemplary embodiment, the impedance element 21 includes at least one transistor TA, and the impedance element 22 includes at least one transistor TB. The transistors TA and TB can provide the equivalent impedance of this internal impedance together or separately. However, in another exemplary embodiment, the impedance elements 21 and 22 may also include at least one electrical component that can be used to provide a resistance value or a reactance value, respectively.

In the exemplary embodiment, the third end of the impedance element 21 is for receiving the signal ENA, and the third end of the impedance element 22 is for receiving the signal ENB. The signal ENA is an enable signal for activating the impedance element 21, and the signal ENB is an enable signal for activating the impedance element 22. When the signal ENA is received, the impedance element 21 is activated. If the impedance element 21 is activated, the path between the receiving path of the signal SRX and the supply voltage VDD (also referred to as the first impedance path) is turned on, and the signal SRX is affected by the impedance provided by the impedance element 21. On the other hand, if the signal ENA is not received, the impedance element 21 is not activated, and the signal SRX is not affected by the impedance provided by the impedance element 21. In other words, the impedance element 21 can provide an internal impedance to the receive path of the signal SRX in response to the signal ENA.

On the other hand, when the signal ENB is received, the impedance element 22 is activated. If the impedance element 22 is activated, the path between the receive path of the signal SRX and the reference ground voltage GND (also referred to as the second impedance path) will be turned on, and the signal SRX will be affected by the impedance provided by the impedance element 22. Conversely, if the signal ENB is not received, the impedance element 22 is not activated and the signal SRX is not affected by the impedance provided by the impedance element 22. In other words, the impedance element 22 can provide an internal impedance to the receive path of the signal SRX in response to the signal ENB.

FIG. 3 is a schematic diagram of a first signal according to an exemplary embodiment of the invention. Referring to FIG. 2 and FIG. 3, in a certain time range, if the impedance elements 21 and 22 are simultaneously activated (ie, the signals ENA and ENB are simultaneously present), in response to the impedance provided by the impedance elements 21 and 22, The voltage value of the signal SRX is adjusted to a voltage range (also known as the preset voltage range). The upper threshold voltage of the preset voltage range is close to (or equal to) the voltage value of the supply voltage VDD, and the lower threshold voltage of the preset voltage range is close to (or equal to) the voltage value of the reference ground voltage GND, as shown in FIG. Show. In other words, affected by the impedance provided by the impedance elements 21 and 22, the voltage value of the signal SRX fluctuates between the voltage value of the supply voltage VDD and the voltage value of the reference ground voltage GND. However, it should be noted that the voltage value of the signal SRX is not higher than the voltage value of the supply voltage VDD nor lower than the voltage value of the reference ground voltage GND.

On the other hand, a signal VREF (also known as the internal reference voltage) is used to determine whether the current signal SRX is used to pass the bit "1" or "0". For example, in the exemplary embodiment of FIG. 3, the voltage value of the signal VREF (about) is equal to an intermediate value (also referred to as a preset voltage value) between the voltage value of the supply voltage VDD and the voltage value of the reference ground voltage GND. For example, the preset voltage value (about) is equal to half the sum of the voltage value of the supply voltage VDD and the voltage value of the reference ground voltage GND. If the voltage value of the current signal SRX is higher than the voltage value of the signal VREF, it indicates that the current signal SRX is used to transfer the bit "1". If the voltage value of the current signal SRX is lower than the voltage value of the signal VREF, it indicates that the current signal SRX is used to transfer the bit "0".

It should be noted that, in another exemplary embodiment of FIG. 3, if the voltage value of the current signal SRX is higher than the voltage value of the signal VREF, the current signal SRX may be regarded as a bit "0". If the voltage value of the current signal SRX is lower than the voltage value of the signal VREF, it can be regarded that the current signal SRX is used to transmit the bit "1".

Specifically, the memory interface circuit 112 generates the signal SIN according to the voltage relative relationship between the signal SRX and the signal VREF. For example, the comparison circuit 23 can include an operational amplifier (OPA). The comparison circuit 23 receives the signal SRX and the signal VREF and compares the voltage values of the signal SRX and the signal VREF. By comparing the voltage values of the signal SRX and the signal VREF, the voltage relative relationship between the signal SRX and the signal VREF can be obtained. If the voltage relationship between the signal SRX and the signal VREF is such that the voltage value of the signal SRX is higher than the voltage value of the signal VREF, the signal SIN corresponding to a certain bit data (for example, the bit "1") is output. If the voltage relationship between the signal SRX and the signal VREF is such that the voltage value of the signal SRX is lower than the voltage value of the signal VREF, the signal SIN corresponding to another bit data (for example, the bit "0") is output. In other words, according to the voltage relationship between the signal SRX and the signal VREF, the bit data transmitted by the signal SRX can be obtained.

In the present exemplary embodiment, the memory interface circuit 112 also dynamically generates signals according to the impedance (ie, internal impedance) provided by the current memory interface circuit 112 and the impedance (also referred to as external impedance) provided by the volatile memory 12. VREF. For example, at least one impedance element is also provided in the volatile memory 12 for providing this external impedance. In an exemplary embodiment, the impedance element in the volatile memory 12 for providing this external impedance is also referred to as an off-chip driver (OCD) impedance element. More specifically, in the exemplary embodiment of FIG. 3, the signal SRX from the volatile memory 12 is actually affected by the internal impedance of the memory interface circuit 112 and the external impedance of the volatile memory 12, so that the signal The voltage value of SRX is adjusted to the preset voltage range of FIG.

In an exemplary embodiment, when the signal VREF is to be generated, the volatile memory 12 transmits a signal (also referred to as a second signal) that meets a specific condition to the memory interface circuit 112. The memory interface circuit 112 can receive the second signal on the receiving path of the signal SRX. In other words, the second signal is also affected by the internal impedance of the memory interface circuit 112 and the external impedance of the volatile memory 12. Then, the memory interface circuit 112 performs a voltage division operation on the second signal to generate a signal VREF.

In an exemplary embodiment, the second signal refers to a signal for transmitting at least one particular bit. For example, in an exemplary embodiment, the particular bit is bit "0", so the voltage value of the second signal will be the same (or close) to the lower threshold voltage of the preset voltage range in FIG. Then, according to the instantaneously detected supply voltage VDD, a voltage dividing operation is performed on the second signal, and the signal VREF can be dynamically generated.

FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an exemplary embodiment of the invention. Referring to FIG. 1 to FIG. 4 , in an exemplary embodiment, the memory interface circuit 112 further includes a reference voltage generating circuit 40 coupled to the connection interfaces 1311 and 1312 . For example, the input end of the reference voltage generating circuit 40 is coupled to the receiving path of the signal SRX, and the output end of the reference voltage generating circuit 40 is coupled to the comparing circuit 23. Therefore, the reference voltage generating circuit 40 can detect the internal impedance of the memory interface circuit 112 via the connection interface 1311 and detect the external impedance of the volatile memory 12 via the connection interface 1312 and then generate the signal VREF according to the detection result.

In the exemplary embodiment of FIG. 4, the reference voltage generating circuit 40 includes a voltage detecting circuit 41, a voltage dividing circuit 42, and a voltage output circuit 43. When the memory interface circuit 112 is coupled to the volatile memory 12, the voltage detecting circuit 41 is coupled between the impedance element R1 and the impedance element R2. The impedance element R1 represents an equivalent resistance that provides the internal impedance of the memory interface circuit 112, and the impedance element R2 represents an equivalent resistance that provides the external impedance of the volatile memory 12.

When the memory interface circuit 112 receives the second signal, the voltage detecting circuit 41 detects between the impedance element R1 and the impedance element R2 in response to the internal impedance provided by the impedance element R1 and the external impedance provided by the impedance element R2. Signal V1 (ie, the second signal) and generates a signal V2. In an exemplary embodiment, the signal V1 refers to a voltage (also referred to as a first voltage) at one end of the impedance element R1, and the voltage value thereof is positively related to the voltage value of the supply voltage VDD coupled to the other end of the impedance element R1. In addition, the signal V2 is also referred to as a second voltage. For example, the voltage value of signal V2 will be locked to the voltage value of signal V1. For example, the voltage value of the signal V2 will be the same (or close to) the voltage value of the signal V1. Taking FIG. 3 as an example, the voltage value of the signal V2 will be the same (or close to) the lower threshold voltage of the preset voltage range.

The voltage dividing circuit 42 is coupled to the voltage detecting circuit 41 and configured to perform a voltage dividing operation on the signal V2 at the output end of the voltage detecting circuit 41. For example, the voltage dividing circuit 42 includes impedance elements R3 and R4. The first end of the impedance element R3 is coupled to the supply voltage VDD, the first end of the impedance element R4 is coupled to the voltage detecting circuit 41 to receive the signal V2, and the second end of the impedance element R3 is coupled to the first of the impedance element R4. Two ends. In addition, impedance elements R3 and R4 provide the same (or similar) impedance values. The voltage dividing circuit 42 performs a voltage dividing operation according to the supply voltage VDD and the signal V2 and generates a signal V3 (also referred to as a third voltage). The voltage value of the signal V3 is (about) equal to half the sum of the voltage value of the supply voltage VDD and the voltage value of the signal V2.

The voltage output circuit 43 is coupled to the voltage dividing circuit 42 and generates a signal VREF in response to the signal V3 at the output of the voltage dividing circuit 42. For example, the voltage value of the signal VREF will be locked to the voltage value of the signal V3. For example, the voltage value of the signal VREF will be the same (or close to) the voltage value of the signal V3. Then, the signal VREF can be supplied to the comparison circuit 23 of FIG. Moreover, in an exemplary embodiment, the voltage value or generation parameter of the signal VREF can be recorded in a storage element such as a register. Thereby, after stopping receiving the second signal, the voltage output circuit 43 (or the memory interface circuit 112) can still generate the signal VREF according to the recorded voltage value or the generated parameter. In addition, in an exemplary embodiment, after stopping receiving the second signal, at least one of the voltage detecting circuit 41 and the voltage dividing circuit 42 may be disabled to save power.

In an exemplary embodiment, the operation of generating the signal VREF according to the second signal may also be regarded as an internal reference signal generating operation. For example, the internal reference signal generation operation is performed before the signal VREF is actually used to generate the signal SIN and is used to dynamically determine the voltage value of the signal VREF. That is, in an exemplary embodiment, before receiving the first signal, the memory interface circuit 112 receives the second signal and determines a subsequent voltage value for parsing the internal reference signal of the first signal according to the second signal.

In an exemplary embodiment, the memory controller 111 sends at least one predetermined read command to the volatile memory 12 via the memory interface circuit 112. The preset read command is used to instruct reading of one of the preset data of the volatile memory 12. This preset material includes at least one specific bit (for example, bit "0"). According to the preset read command, the volatile memory 12 generates the second signal.

In an exemplary embodiment, according to the preset read command, the volatile memory 12 automatically stores the preset data and continues to perform the operation of reading the preset data to generate the second signal. Thereby, the memory controller 111 does not send an additional write command to instruct the preset data to be stored in the volatile memory 12 before transmitting the preset read command. In addition, in an exemplary embodiment, according to the preset read command, the volatile memory 12 can generate the second signal without actually performing a data access operation. Alternatively, in another exemplary embodiment, the preset data may also be sent by the memory controller 111 to send a preset read command to indicate that the preset data is stored in the volatile memory. In the 12th, the invention is not limited.

In an exemplary embodiment, impedance elements 21 and 22 are only selectively activated. For example, in a certain time range, if the signal ENA is present and the impedance element 21 is activated, the signal ENB will not be present. At this time, the activated impedance element 21 can provide an internal impedance to the receive path of the signal SRX, while the unactivated impedance element 22 does not provide an internal impedance. Alternatively, within a certain time range, if the signal ENB is present and the impedance element 22 is activated, the signal ENA will not be present. At this time, the activated impedance element 22 can provide an internal impedance to the receive path of the signal SRX, while the unactivated impedance element 21 does not provide an internal impedance. By starting only one of the impedance elements 21 and 22, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be reduced.

In an exemplary embodiment, the coincidence time of the signal ENA or ENB can also be dynamically adjusted. For example, the enable time of the signal ENA or ENB may be positively related to the total number of consecutive bits transmitted via the signal SRX. It should be noted that the above enabling time refers to the existence time of the signal. For example, the enable time of the signal ENA will be positively related to the length of time the impedance element 21 is in the active state, and the enable time of the signal ENB will be positively related to the length of time the impedance element 22 is in the activated state.

In an exemplary embodiment, it is assumed that the transmission specification of the signal SRX is to continuously transmit bit data of n bits. For example, n can be 4, 8, 16 or 32 or more or less. If n is larger, the enable time of the signal ENA or ENB will be longer. Thereby, it is ensured that (at least) one of the impedance elements 21 and 22 will remain in the activated state before the bit data from the volatile memory 12 is completely received. After the bit data from the volatile memory 12 is completely received, the signal ENA or ENB can be stopped. Thereby, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be further reduced.

In an exemplary embodiment, impedance elements 21 and 22 are only selectively disposed in memory interface circuit 112. Thereby, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be reduced, and the layout area of the receiving end circuit in the memory interface circuit 112 can be further reduced.

FIG. 5 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. FIG. 6 is a schematic diagram of a first signal according to another exemplary embodiment of the invention. Referring to FIG. 5 and FIG. 6, in the exemplary embodiment, the memory interface circuit 112 is provided with the impedance element 21, but the impedance element 22 is not disposed. The voltage value of the signal SRX is adjusted to a voltage range (also referred to as a first voltage range) in response to the internal impedance provided by the impedance element 21. The first voltage range has an upper threshold voltage VIH (also referred to as a first threshold voltage) and a lower threshold voltage VIL (also referred to as a second threshold voltage). The voltage value of the upper threshold voltage VIH is higher than the voltage value of the lower threshold voltage VIL. In other words, in the exemplary embodiment of FIGS. 5 and 6, the voltage value of the signal SRX is fluctuated within the first voltage range by the internal impedance provided by the impedance element 21, depending on the transmitted bit material. Moreover, in an exemplary embodiment of FIGS. 5 and 6, the voltage value of the signal SRX does not exceed the first voltage range.

It should be noted that in the exemplary embodiments of FIG. 5 and FIG. 6, the first voltage range is different from the preset voltage range in FIG. 3, and an intermediate value of the first voltage range is different from the voltage of one preset voltage VCEN. value. For example, the intermediate value of the first voltage range may be higher than the voltage value of the preset voltage VCEN. Wherein, the intermediate value of the first voltage range is equal to half of the sum of the voltage value of the upper threshold voltage VIH and the voltage value of the lower threshold voltage VIL, and the voltage value of the preset voltage VCEN (ie, the preset voltage value) is equal to the supply voltage The voltage value of VDD is half of the sum of the voltage values of the reference ground voltage GND. In addition, the voltage value of the upper threshold voltage VIH may be the same (or close to) the voltage value of the supply voltage VDD. It should be noted that although FIG. 6 is a graph showing that the voltage value of the lower threshold voltage VIL is higher than the voltage value of the preset voltage VCEN, in another exemplary embodiment of FIG. 6, the voltage value of the lower threshold voltage VIL may also be The voltage value lower than the preset voltage VCEN depends on the configured internal impedance and external impedance.

In the exemplary embodiment of FIGS. 5 and 6, signal VREF is also dynamically generated by memory interface circuit 112. For example, according to the exemplary embodiment of FIG. 4, the voltage value of the signal V2 (or the signal V1) will be the same (or close) to the voltage value of the lower threshold voltage VIL in FIG. After the voltage dividing operation is performed according to the signal V2 and the supply voltage VDD, the signal VREF can be generated. For example, the voltage value of the signal VREF will be the same (or close to) the intermediate value of the first voltage range, as shown in FIG. For specific details of the generation of the signal VREF, reference may be made to the foregoing description, and will not be described herein.

In addition, in another exemplary embodiment of FIG. 5, the impedance element 21 may also be implemented by at least one resistor or the like that can be used to provide a resistance value or a reactance value. Thereby, the impedance element 21 can continue to provide the receiving path of the internal impedance signal SRX without being controlled by the signal ENA.

FIG. 7 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. FIG. 8 is a schematic diagram of a first signal according to another exemplary embodiment of the invention. Referring to FIG. 7 and FIG. 8, in the exemplary embodiment, the memory interface circuit 112 is provided with the impedance element 22, but the impedance element 21 is not disposed. The voltage value of the signal SRX is adjusted to another voltage range (also referred to as a second voltage range) in response to the internal impedance provided by the impedance element 22. The second voltage range also has an upper threshold voltage VIH and a lower threshold voltage VIL. The voltage value of the upper threshold voltage VIH is higher than the voltage value of the lower threshold voltage VIL. In other words, in the exemplary embodiment of FIGS. 7 and 8, the voltage value of the signal SRX is affected by the internal impedance provided by the impedance element 22 and fluctuates within the second voltage range, depending on the transmitted bit material. Moreover, in an exemplary embodiment of FIGS. 7 and 8, the voltage value of the signal SRX does not exceed the second voltage range.

It should be noted that in the exemplary embodiments of FIG. 7 and FIG. 8, the second voltage range is different from the preset voltage range in FIG. 3, and an intermediate value of the second voltage range is different from the voltage value of the preset voltage VCEN. . Wherein, the intermediate value of the second voltage range is equal to half of the sum of the voltage value of the upper threshold voltage VIH and the voltage value of the lower threshold voltage VIL. For example, the intermediate value of the second voltage range may be lower than the voltage value of the preset voltage VCEN. In addition, the voltage value of the lower threshold voltage VIL may be the same (or close to) the voltage value of the reference ground voltage GND. It should be noted that although FIG. 8 is a graph showing that the voltage value of the upper threshold voltage VIH is lower than the voltage value of the preset voltage VCEN, in another exemplary embodiment of FIG. 8, the voltage value of the upper threshold voltage VIH may also be The voltage value higher than the preset voltage VCEN depends on the configured internal impedance and external impedance.

In the exemplary embodiment of FIGS. 7 and 8, the signal VREF is also dynamically generated by the memory interface circuit 112. For example, according to the exemplary embodiment of FIG. 4, the voltage value of the signal V2 (or the signal V1) will be the same (or close to) the voltage value of the upper threshold voltage VIH in FIG. If the supply voltage VDD coupled to the voltage dividing circuit 42 is replaced with the reference ground voltage GND, the signal VREF can be generated after the voltage dividing operation is performed according to the signal V2 and the reference ground voltage GND. For example, the voltage value of the signal VREF will be the same (or close to) the intermediate value of the second voltage range, as shown in FIG.

Moreover, in another exemplary embodiment of FIG. 7, the impedance element 22 may also be implemented by at least one resistor or the like that can be used to provide a resistance value or a reactance value. Thereby, the impedance element 22 can continue to provide the receiving path of the internal impedance signal SRX without being controlled by the signal ENB.

FIG. 9 is a schematic diagram of a memory storage device according to another exemplary embodiment of the invention. Referring to FIG. 9, the memory storage device 90 is, for example, a solid state drive (SSD) or the like, and includes a rewritable non-volatile memory module 906 and a non-volatile memory 908. The memory storage device 90 can be used with a host system that can write data to or read data from the memory storage device 90. The host system mentioned is any system that can substantially cooperate with the memory storage device 90 to store data, such as a desktop computer, a notebook computer, a digital camera, a video camera, a communication device, an audio player, and a video player. Or a tablet, etc.

Specifically, the memory storage device 90 includes a connection interface unit 902, a memory control circuit unit 904, a rewritable non-volatile memory module 906, and a volatile memory 908. The connection interface unit 902 is used to connect the memory storage device 90 to the host system. In the present exemplary embodiment, the connection interface unit 902 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 502 may also be a Parallel Advanced Technology Attachment (PATA) standard, a Peripheral Component Interconnect Express (PCI Express) standard. Universal Serial Bus (USB) standard or other suitable standard. The connection interface unit 902 can be packaged in a chip with the memory control circuit unit 904, or the connection interface unit 902 can also be disposed outside a wafer including the memory control circuit unit 904.

The memory control circuit unit 904 is configured to perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 906 according to an instruction of the host system. The rewritable non-volatile memory module 906 is coupled to the memory control circuit unit 904 and is used to store data written by the host system. The rewritable non-volatile memory module 906 can be a single-level memory cell (SLC) NAND-type flash memory module (ie, one memory cell can store one bit of flash memory). Module), Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in a memory cell), and complex memory cells ( Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), other flash memory modules, or other memory with the same characteristics Body module.

In the present exemplary embodiment, the memory control circuit unit 904 also has the same or similar function and/or electronic circuit structure as the memory control circuit unit 11 mentioned in the exemplary embodiments of FIGS. 1 to 8, and is volatile. Memory 908 is the same or similar to volatile memory 12 as mentioned in the exemplary embodiment of FIG. Therefore, for the description of the memory control circuit unit 904 and the volatile memory 908, please refer to the exemplary embodiments of FIG. 1 to FIG. 8 , and details are not described herein.

It is worth mentioning that the electronic circuit structure illustrated in FIG. 2, FIG. 4, FIG. 5 and FIG. 7 is only a schematic diagram of the memory interface circuit in some exemplary embodiments, and is not intended to limit the present invention. In some applications not mentioned, more electronic components can be added to the memory interface circuitry to provide additional functionality. Moreover, in some applications not mentioned, the circuit layout and/or component coupling relationship of the memory interface circuit can also be appropriately changed to meet practical requirements.

FIG. 10 is a flowchart of a signal receiving method according to an exemplary embodiment of the invention. This signal receiving method can be applied to the memory storage device mentioned in the exemplary embodiment of FIG. 1 or 9. Hereinafter, the memory storage device 10 of Fig. 1 will be described with reference to Fig. 10 .

Referring to FIG. 1 and FIG. 10, in step S1001, the first signal from the volatile memory 12 is received by the memory interface circuit 112. In step S1002, the voltage value of the first signal is adjusted by the memory interface circuit 112 to a voltage range in response to the internal impedance of the memory interface circuit 112. For example, this voltage range may be the first voltage range shown in FIG. 6 or the second voltage range shown in FIG. In step S1003, the memory interface circuit 112 generates an input signal according to a voltage relationship between the first signal and the internal reference voltage.

However, the steps in FIG. 10 have been described in detail above, and will not be described again here. It should be noted that the steps in FIG. 10 can be implemented as multiple codes or circuits, and the present invention is not limited. In addition, the method of FIG. 10 may be used in combination with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, the present invention proposes to set a specific receiving end circuit in the memory interface circuit to adjust the voltage value of the first signal from the volatile memory to a specific voltage range and analyze it using a suitable internal reference voltage. The first signal. Thereby, the correctness of the generated input signal can be maintained, and the power consumption when receiving the first signal can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 90‧‧‧ memory storage device

11, 904‧‧‧ memory control circuit unit

111‧‧‧Memory Controller

112‧‧‧Memory interface circuit

12, 908‧‧‧ volatile memory

21, 22, R1, R2, R3, R4‧‧‧ impedance components

23‧‧‧Comparative circuit

ENA, ENB, SRX, SIN, VREF, V1, V2, V3‧‧‧ signals

TA, TB‧‧‧ transistor

OPA‧‧‧Operational Amplifier

VDD‧‧‧ supply voltage

GND‧‧‧reference ground voltage

40‧‧‧reference voltage generation circuit

41‧‧‧Voltage detection circuit

42‧‧‧voltage circuit

43‧‧‧Voltage output circuit

VCEN‧‧‧Preset voltage

VIH‧‧‧ upper threshold voltage

VIL‧‧‧ lower threshold voltage

902‧‧‧Connecting interface unit

906‧‧‧Reusable non-volatile memory module

S1001‧‧‧Step (receiving the first signal from the volatile memory by the memory interface circuit)

S1002‧‧‧Step (adjusting the voltage value of the first signal to a voltage range in response to the internal impedance of the memory interface circuit)

S1003‧‧‧Step (generating an input signal according to the voltage relationship between the first signal and the internal reference voltage)

FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the invention. 2 is a schematic diagram of a memory interface circuit according to an exemplary embodiment of the invention. FIG. 3 is a schematic diagram of a first signal according to an exemplary embodiment of the invention. FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an exemplary embodiment of the invention. FIG. 5 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. FIG. 6 is a schematic diagram of a first signal according to another exemplary embodiment of the invention. FIG. 7 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. FIG. 8 is a schematic diagram of a first signal according to another exemplary embodiment of the invention. FIG. 9 is a schematic diagram of a memory storage device according to another exemplary embodiment of the invention. FIG. 10 is a flowchart of a signal receiving method according to an exemplary embodiment of the invention.

Claims (30)

A memory control circuit unit for controlling a volatile memory, the memory control circuit unit comprising: a memory controller; and a memory interface circuit coupled to the memory controller, wherein the memory The interface circuit is configured to receive a first signal from the volatile memory, wherein the memory interface circuit is further configured to adjust a voltage value of the first signal to one in response to an internal impedance of the memory interface circuit a voltage range, wherein an intermediate value of the voltage range is not equal to a predetermined voltage value, wherein the preset voltage value is half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage The memory interface circuit is further configured to generate an input signal according to a voltage relationship between the first signal and an internal reference voltage. The memory control circuit unit of claim 1, wherein the memory interface circuit includes an impedance component for providing the internal impedance, wherein the first end of the impedance component is coupled to the first signal a receiving path, wherein the second end of the impedance element is coupled to the supply voltage or the reference ground voltage. The memory control circuit unit of claim 2, wherein the third end of the impedance element is configured to receive a uniform energy signal, wherein the impedance element provides the internal impedance in response to the enable signal. The memory control circuit unit of claim 3, wherein the enabling time of the enable signal is positively correlated with a total number of the plurality of bits continuously transmitted via the first signal. The memory control circuit unit of claim 1, wherein the memory interface circuit is further configured to receive a second signal from the volatile memory before receiving the first signal, wherein the memory The interface circuit is further configured to perform a voltage division operation on the second signal to generate the internal reference voltage. The memory control circuit unit of claim 5, wherein the memory interface circuit is further configured to send a preset read command sequence to indicate a preset data of the volatile memory, wherein the The volatile memory is configured to generate the second signal according to the preset read command sequence. The memory control circuit unit of claim 1, wherein the memory interface circuit comprises a comparison circuit, wherein the comparison circuit is configured to compare the internal reference voltage with the voltage value of the first signal to generate the Enter the signal. The memory control circuit unit of claim 1, wherein the volatile memory is configured to provide an external impedance, wherein the voltage value of the first signal is further adjusted to the voltage in response to the external impedance. range. The memory control circuit unit of claim 1, wherein the volatile memory comprises a fourth generation double data rate synchronous dynamic random access memory. The memory control circuit unit of claim 1, wherein the memory interface circuit comprises: a first connection interface for coupling to the memory controller; and a second connection interface for coupling Connecting to the volatile memory; and a reference voltage generator coupled to the first connection interface and the second connection interface, wherein the reference voltage generator is configured to detect the internal impedance via the first connection interface, via The second connection interface detects an external impedance of the volatile memory and generates the internal reference voltage according to the detection result. The memory control circuit unit of claim 10, wherein the reference voltage generator comprises: a voltage detecting circuit for detecting the memory interface circuit in response to the internal impedance and the external impedance a first voltage of an impedance component, wherein a voltage value of the first voltage is positively related to the voltage value of the supply voltage. The memory control circuit unit of claim 11, wherein the reference voltage generator further comprises: a voltage dividing circuit coupled to the voltage detecting circuit and configured to output the voltage detecting circuit A second voltage of the terminal performs a voltage dividing operation; and a voltage output circuit coupled to the voltage dividing circuit and configured to generate the internal reference voltage in response to a third voltage at an output of the voltage dividing circuit. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module; a volatile memory; and a memory control circuit unit coupled The memory control circuit unit is configured to receive a first signal from the volatile memory, wherein the memory device is configured to receive the first signal from the volatile memory The control circuit unit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory control circuit unit, wherein an intermediate value of the voltage range is not equal to a predetermined voltage value, The preset voltage value is half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage, wherein the memory control circuit unit is further configured to use the first signal and an internal A voltage relative relationship between the reference voltages produces an input signal. The memory storage device of claim 13, wherein the memory control circuit unit includes an impedance component for providing the internal impedance, wherein the first end of the impedance component is coupled to the first signal a receiving path, wherein the second end of the impedance element is coupled to the supply voltage or the reference ground voltage. The memory storage device of claim 14, wherein the third end of the impedance element is configured to receive a uniform energy signal, wherein the impedance element provides the internal impedance in response to the enable signal. The memory storage device of claim 15, wherein the enabling time of the enabling signal is positively correlated with a total number of the plurality of bits continuously transmitted via the first signal. The memory storage device of claim 13, wherein the memory control circuit unit is further configured to receive a second signal from the volatile memory, wherein the memory is received before the receiving the first signal The control circuit unit is further configured to perform a voltage dividing operation on the second signal to generate the internal reference voltage. The memory storage device of claim 17, wherein the memory control circuit unit is further configured to send a preset read command sequence to indicate reading a preset data of the volatile memory, wherein the The volatile memory is configured to generate the second signal according to the preset read command sequence. The memory storage device of claim 13, wherein the memory control circuit unit comprises a comparison circuit, wherein the comparison circuit is configured to compare the internal reference voltage with the voltage value of the first signal to generate the Enter the signal. The memory storage device of claim 13, wherein the volatile memory is configured to provide an external impedance, wherein the voltage value of the first signal is further adjusted to the voltage range in response to the external impedance. . The memory storage device of claim 13, wherein the volatile memory comprises a fourth generation double data rate synchronous dynamic random access memory. A signal receiving method for a memory storage device including a volatile memory, the signal receiving method comprising: receiving a first signal from the volatile memory by a memory interface circuit; responsive to the memory An internal impedance of the interface circuit adjusts a voltage value of the first signal to a voltage range, wherein an intermediate value of the voltage range is not equal to a predetermined voltage value, wherein the predetermined voltage value is a memory interface circuit And comparing a voltage value of a supply voltage to a voltage value of a reference ground voltage; and generating an input signal according to a voltage relationship between the first signal and an internal reference voltage. The signal receiving method of claim 22, further comprising: providing the internal impedance by an impedance component of the memory interface circuit, wherein the first end of the impedance component is coupled to a receiving of the first signal a path, wherein the second end of the impedance element is coupled to the supply voltage or the reference ground voltage. The method for receiving a signal according to claim 23, further comprising: receiving, by the third end of the impedance element, a uniform energy signal; and providing the internal impedance by the impedance element in response to the enable signal. The method for receiving a signal according to claim 24, further comprising: controlling a consistent energy time of the enable signal, such that the enable time is positively correlated with a total number of consecutive bits transmitted through the first signal. . The method for receiving a signal according to claim 22, further comprising: receiving, by the memory interface circuit, a second signal from the volatile memory before receiving the first signal; and the second signal A voltage division operation is performed to generate the internal reference voltage. The method for receiving a signal according to claim 26, further comprising: transmitting a preset read command sequence to indicate reading a preset data of the volatile memory; and determining, by the volatile memory The read command sequence is generated to generate the second signal. The method for receiving a signal according to claim 22, wherein the step of generating the input signal according to the voltage relationship between the first signal and the internal reference voltage comprises: comparing the internal reference voltage with the first signal The voltage value; and generating the input signal according to a comparison result. The signal receiving method of claim 22, further comprising: providing an external impedance from the volatile memory; and adjusting the voltage value of the first signal to the voltage range in response to the external impedance. The signal receiving method according to claim 22, wherein the volatile memory comprises a fourth generation double data rate synchronous dynamic random access memory.