TW201832629A - Printing complex electronic circuits using a printable solution defined by a patterned hydrophobic layer - Google Patents

Abstract

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Description

Printing complex electronic circuits using a printable solution defined by a patterned hydrophobic layer

The present invention relates to printing preformed micro-semiconductor devices, such as transistors and diodes, in separate groups on a substrate, where randomly distributed devices in each group are connected in parallel and interconnect the groups to produce more complex A circuit, such as a logic circuit.

Through the work of the assignee himself, how to form and print microscopic vertical light emitting diodes (LEDs) on a conductive substrate with proper orientation and connect the LEDs in parallel to form a light plate. Details of this printing of LEDs can be found in US Application Publication US 2012/0164796, titled Method of Manufacturing a Printable Composition of Liquid or Gel Suspension of Diodes, which was assigned to the assignee and cited by reference Incorporated herein. FIG. 1 is a cross-sectional view of one layer of an LED 16 that can be printed using the following procedure. Each LED 16 includes a standard semiconductor GaN layer, including an n-layer, an active layer, and a p-layer. An LED wafer (containing thousands of vertical LEDs) is fabricated such that the bottom metal cathode electrode 18 of each LED 16 includes a reflective layer. The top metal anode electrode 20 of each LED 16 is small to allow almost all LED light to escape from the anode side. A carrier wafer bonded to the "top" surface of the LED wafer through an adhesive layer can be used to access both sides of the LED for metallization. Subsequently, the LED 16 is singulated, such as by etching the trench down to the adhesive layer around each LED and dissolving the exposed adhesive layer or by thinning the carrier wafer. Subsequently, the micro LED is uniformly impregnated in a solvent containing a viscosity-modified polymer resin to form an LED ink for printing, such as screen printing or offset printing. If the anode electrode 20 needs to be oriented in a direction opposite to the substrate 22 after printing, the electrode 20 is made high so that the LED 16 is rotated in a solvent by hydraulic pressure when they are stabilized on the substrate surface. The LED 16 is rotated to one of the smallest resistances. More than 90% of similar orientations have been reached. In FIG. 1, a starting substrate 22 is provided. If the substrate 22 itself is not conductive, a reflective conductor layer 24 (eg, aluminum) is deposited on the substrate 22, such as by printing. The substrate 22 may be thin and flexible. Subsequently, such as by printing the LED 16 on the conductor layer 24 by offset printing, one of the patterns on a rotating plate determines the deposition for the reel process, or by screen printing using an appropriate screen to allow the LED to pass And control the thickness of the layer. Due to the relatively low concentration, the LEDs 16 will be printed as a single layer and distributed fairly evenly over the conductor layer 24. Subsequently, the solvent is evaporated by heating using, for example, an infrared oven. After curing, the LED 16 remains attached to the underlying conductor layer 24, with a small amount of residual resin dissolved in the LED ink as a viscosity modifier. The adhesive properties of the resin and the reduction in volume of the resin under the LED 16 during curing press the bottom LED electrode 18 against the underlying conductor 24, thereby making an ohmic contact therewith. Subsequently, a dielectric layer 26 is printed over the surface to encapsulate the LED 16 and further secure it in place. Subsequently, a top transparent conductor layer 28 is printed over the dielectric layer 26 to electrically contact the electrode 20 and the top transparent conductor layer 28 is cured in an oven suitable for the type of transparent conductor used. If current needs to be spread, the metal bus bars 30 to 33 are then printed along the opposite edges of the conductor layers 24 and 28 and electrically terminated at the anode and cathode leads (not shown) for powering the LED 16 respectively. The bus bars 30 to 33 will eventually be connected to a positive or negative drive voltage. FIG. 2 is a top view of FIG. 1. The cross section of FIG. 2 is the horizontal bisect of FIG. 3. The positions of the LEDs 16 in the printed layer are random. If a proper voltage difference is applied to the anode and cathode leads, all LEDs 16 with the proper orientation will be illuminated. FIG. 1 shows a light beam 38. The above procedure is strictly used in combination with a two-terminal device having a top electrode and a bottom electrode. This is because the position of the LED on the substrate is random, and the LED can only be placed between two conductive layers of any thickness Occasionally interconnected. In addition, the above procedure is strictly used to form an LED array for generating light. LEDs are not intended to perform any type of logic function because the array of LEDs connected in parallel forms only a single diode. It would be desirable to adapt the printing / curing procedures described above to produce complex printed circuits involving three-terminal transistors, diodes, and possibly additional types of components to perform logic functions.

The present invention relates generally to printing preformed micro (e.g., sizes between 10 microns and 200 microns) electronic devices in small separate groups on a substrate (such as a flexible circuit), including transistors and two Polar body. Each group may contain, for example, about 10 devices. The devices in each group are connected in parallel via printed conductor layers. Each group acts as a single device (eg, a single transistor or a single diode) because the same device is connected in parallel in each group. At any time after the group is formed, the group is then interconnected (stylized) to form a customized circuit, such as a logic circuit for performing a specified function. In one embodiment, the printing device is a transistor or a diode and the programming step forms a plurality of logic gates. In another embodiment, the substrate is initially processed to form an array of logic gates from the group, and a subsequent "stylized" step customizes the substrate by interconnecting the gates to form a complex logic circuit. Therefore, a programmable gate array can be formed through the printed substrate. In one embodiment, "stylization" to form a circuit is performed by forming a hydrophobic mask on a substrate; defining an interconnect pattern; and subsequently depositing a conductive material to form an interconnect metal on the substrate Trace. In another embodiment, the interconnect traces are printed directly on the substrate by offset printing or screen printing. The group of devices may all be the same device (eg, a transistor) or multiple devices (eg, a transistor and a diode). The circuit may be a circuit other than a logic circuit, such as a control circuit, a switching circuit, an analog circuit, and the like. Many types of electrical components use three terminals, such as MOSFET, bipolar transistor, JFET, thyristor, silicon controlled rectifier, and so on. Those skilled in these components typically have three terminals on the top for horizontal devices or two terminals on the top and one terminal on the bottom for vertical devices. It is known to form thin film transistors by printing various transistor layers over a substrate, but the performance of these printed transistors is poor due to the difficulty of printing a single crystal. If a transistor (or other three-terminal device) can be more conventionally formed in a semiconductor wafer and then singulated to produce a micro device printed as an ink, the quality of the device can be the most advanced technology currently available. However, to date, it is unknown how to design such devices or interconnect these three-terminal micro devices to perform complex functions after printing. In one embodiment, a semiconductor (eg, silicon) wafer is formed as a three-terminal device (such as a transistor). The transistor is formed in the wafer to have a bottom electrode, a top electrode, and an intermediate electrode positioned on a shelf somewhere between the top and bottom of the device. The starting wafer is finally attached to a carrier wafer with an adhesive to access both surfaces of the transistors when making the transistors. The transistors are singulated into individual transistors by forming a trench around each transistor, such as to form a hexagonal device. The trench extends down to the adhesive layer and the adhesive layer is dissolved in a solution to release all transistors from the carrier wafer. Subsequently, the transistors are uniformly mixed into a solution to form an ink. The shape of the transistor causes most of them to be printed on a substrate in the desired orientation. Subsequently, the transistor is printed on an associated first conductor layer portion above a substrate to form an array of groups of transistors, and the ink is cured (heated and evaporated) so that the bottom electrode of each transistor is in ohmic contact there. Wait for the first conductor layer. Due to the relatively low density of the transistors in the solution, the transistors will be printed as a loose monolayer. Any layer of the product can be printed by offset printing (especially suitable for roll-type processes), screen printing (especially suitable when forming flat plates), or other types of printing. Subsequently, a first dielectric layer is printed over the first conductor layer portion. The first dielectric layer does not cover the intermediate electrode. Subsequently, a second conductor layer portion aligned with the first conductor layer portion is printed, which contacts the intermediate electrode but does not cover the top electrode. The various thin printed layers are self-planarized by strong surface tension, so that the layer does not cover any of the features of "higher" layer thickness. Alternatively, the layers may be blanket etched after curing to expose any electrodes. Subsequently, a second dielectric layer is printed over the second conductor layer portion but does not cover the top electrode. Subsequently, the top (third) conductor layer portion is printed to contact the top electrodes of the transistors in each group. Therefore, the top electrode of the transistor is connected in parallel, the bottom electrode is connected in parallel, and the middle electrode (or a subset thereof) is connected in parallel to conduct a wide range of current. As described above, the groups can then be interconnected to form a logic gate or more complex circuit in a stylization step. Microscopic vertical diodes can be printed instead of transistors and only two conductor layers are required to connect the diodes in each group in parallel. For simple passive devices (such as resistors), the resistive material itself (rather than printing ink containing individual resistors) can be printed in a small area and determined by where a conductor touches the resistor along its length resistance. Different areas of the substrate may be printed with different devices or the same device, and the devices in each area are connected in parallel. Therefore, each area is essentially a single device. The conductor layer is terminated in a connector area on the substrate next to each area. In one embodiment, the substrate may have a designated "patch" area in which interconnects of groups or gates are made. This simplifies the design of stylized interconnects because patch areas can be optimized for stylized steps. The devices are formed so that the functions of properly oriented devices in the group are not adversely affected if some of the devices in a group are printed upside down or made a poor connection. The printing procedure can use a reel-type procedure under atmospheric pressure. The cost of a printed programmable substrate is much lower than the cost of a comparable programmable substrate formed using conventional techniques. In another embodiment, a region on which a device ink and a conductor are formed is defined by a patterned lyophobic layer on the substrate. This enables more accurate dot shape printing without ink diffusion, enabling smaller dots and denser dot arrays. Therefore, more electrical components can be printed in a unit area to form more complicated circuits. The entire circuit can be formed by printing under atmospheric conditions. Other embodiments are disclosed.

Cross-Reference to Related Applications This application is US Application No. 15 / 405,601 filed by William Johnstone Ray et al. On January 13, 2017 (which is US Application No. 14 / filed on March 11, 2014 Partial continuation case No. 204,800), which is assigned to the assignee and incorporated herein by reference. The printed programmable circuit of the present invention may use any combination of passive devices (eg, capacitors, resistors), two-terminal inorganic semiconductor devices (eg, diodes), and three-terminal inorganic semiconductor devices (eg, transistors). The most complex device to be printed and electrically connected to is a three-terminal device. In some cases, a three-terminal device, such as a bipolar transistor, can be used as a diode by using only two terminals or connecting the two terminals to the same conductor. The three-terminal device used in the embodiments of the present invention may be smaller than the diameter of human hair, so that the devices are essentially invisible to the naked eye when they are sparsely scattered across a substrate. The size of the device can range from about 10 microns to 200 microns. The number of microdevices per unit area can be freely adjusted when the microdevices are applied to the substrate. The device can be printed as ink using offset printing, screen printing, or other forms of printing. The conventional design of the three-terminal device can be easily adapted to form the microdevice of the present invention. The accuracy of photolithography is exactly within the accuracy required to form a microdevice. Since many microdevices will operate in parallel, the efficiency of each microdevice is not critical. FIG. 3 is a perspective view of one of the three-terminal devices 40 that can be suspended in a solvent and printed as an ink on a substrate. The device 40 may be a bipolar transistor, a MOSFET, a JFET, a three MOS device, or any other three-terminal device, and generally includes two current-carrying terminals and a control terminal. The device 40 may be a lateral or vertical transistor because the positions of the three electrodes do not indicate the position of the semiconductor layer / area or gate inside the device 40. The electrodes can use any position in the through-hole contact device 40. The device 40 is completely formed on a semiconductor wafer (including electrode metallization) by using one or more carrier wafers to access both surfaces for metallization during processing. Although the growth wafer may be silicon, the carrier wafer may be of any material. The silicon wafer is attached to the carrier wafer using an adhesive or other suitable material. The shape of each device 40 is defined by masking and etching. The various layers or regions can be doped using a mask implant or by doping the layer while epitaxially growing. After the devices are formed on the wafer, light lithography defines grooves around each device 40 in the front surface of the wafer and the grooves are etched down to the adhesion layer. One preferred shape of each device 40 is a hexagon. The trench etch exposes the underlying wafer bonding adhesive. Subsequently, the adhesive is dissolved in a solution to release the device 40 from the carrier wafer. Alternatively, the singulation can be performed by thinning the rear surface of the carrier wafer up to the singulation device 40. Subsequently, the micro device 40 is uniformly impregnated in a solvent containing a viscosity-modified polymer resin to form an ink for printing such as screen printing or offset printing. A similar technique can be used to form a two-terminal device, such as a vertical diode with one electrode on the top and the other electrode on the bottom. The diode may have a shape similar to one of the shapes shown in FIG. 3, but without an intermediate electrode. Details regarding the shaping of vertical LEDs (two-end devices) in a wafer and subsequent singulation of the LEDs for printing as inks are described in U.S. Application Publication entitled Method of Manufacturing a Printable Composition of Liquid or Gel Suspension of Diodes In case US 2012/0164796, the case was assigned to the assignee and incorporated herein by reference. Those skilled in the art can adapt these procedures to form a three-terminal device 40 and a non-LED diode. The device 40 has two sections: a lower section 42 (or base section) and an upper section 44. The upper section 44 is made relatively high and narrow, so that the device 40 is rotated in a solvent by hydraulic pressure while it is settled on the substrate surface. The device 40 is rotated to one of the minimum resistance orientations. More than 90% of similar orientations have been achieved, but satisfactory performance can be achieved with more than 75% of the devices 40 in the same orientation. The lower section 42 should be shaped so that the device 40 lies flat on the substrate after the ink is cured. FIG. 4 illustrates three printing devices 40, of which only two printing devices 40 are printed in the correct orientation. The device 40 includes a metal top electrode 46, a metal intermediate electrode 48, and a metal bottom electrode (not shown in FIG. 3). The shape of the intermediate electrode 48 provides a large side surface area for good electrical contact with an intermediate conductor layer. The middle electrode 48 should be offset relative to the middle of the device 40 so that one of the devices 40 is improperly oriented after printing, causing the middle electrode 48 not to make electrical contact with the middle conductor layer. In the example, the middle electrode 48 is below the middle of the device (ie, H2 <½H1). In FIG. 4, a starting substrate 50 is provided. For light weight, low cost, good heat conduction to air or a heat sink, and ease of handling, the substrate 50 should be thin and flexible. The substrate 50 may be a suitable polymer, such as polycarbonate, PMMA, or PET and may be flexible to be dispensed from a roll. The substrate 50 may be any size suitable for the final product. The substrate 50 may be a conventional flexible circuit substrate, in which metal (eg, copper) traces have been formed on the substrate 50 in a conventional manner before the following processing steps. If the substrate 50 has not yet formed metal traces thereon like a flexible circuit, a conductor layer 52 (eg, silver, aluminum, copper) is deposited on the substrate 50, such as by printing. A conductive via 54 passing through the substrate 50 may be used to couple the conductor layer 52 to a metal layer 56 formed on a bottom surface of the substrate 50. In various examples, the conductor layer 52 is printed as an array of dots on the substrate 50 (see FIG. 11). The dots are electrically isolated from each other to allow groups of devices 40 to be interconnected in any manner to form a logic circuit. Instead of dots, the conductor layer 52 may be printed as square dots or other shaped dots. Subsequently, the device 40 is printed on the conductor layer 52 such as by offset printing or by screen printing using a suitable screen to allow the device 40 to pass through and control the thickness of the layer. Due to the relatively low density, the device 40 will be printed as a loose single layer and distributed fairly evenly over the conductor layer 52. The printed position of the device 40 is aligned with the printed dot position of the conductor layer 52. Subsequently, the solvent is evaporated by heating using, for example, an infrared oven. After curing, the device 40 remains attached to the underlying conductor layer 52 with a small amount of residual resin dissolved in the ink as a viscosity modifier. The adhesive properties of the resin and the decrease in the volume of the resin under the device 40 during curing press the bottom electrode 58 against the underlying conductor layer 52, thereby making an ohmic contact therewith. Subsequently, a thin dielectric layer 60 is printed to cover the conductor layer 52, and the device 40 is further fixed in place. The dielectric layer 60 is designed to self-planarize by surface tension during curing to pull off the top electrode 46 and the middle electrode 48, or to remove wetting and the like. Therefore, there is no need to etch the dielectric layer 60. If the dielectric layer 60 covers the electrodes 46/48, a blanket etch may be used to expose the electrodes 46/48. Subsequently, an intermediate conductor layer 62 aligned with the point of the conductive layer 52 is printed over the dielectric layer 60 to electrically contact the intermediate electrode 48, and the intermediate conductor layer 62 is cured in one of the furnaces suitable for the type of conductor used. The various conductor layers may be metal (or contain metal) or may be any other type of printable conductor layer. Another thin dielectric layer 64 is printed over the intermediate conductor layer 62 so as not to cover the top electrode 46. Subsequently, one of the top conductor layers 66 aligned with the point of the intermediate conductor layer 62 is printed over the dielectric layer 64 to electrically contact the top electrode 46 and the top conductor layer 66 is cured in one of the furnaces suitable for the type of conductor used . Subsequently, a thicker metal layer 68 may be printed over the conductor layer 66 to improve electrical and / or thermal conductivity. The intermediate conductor layer 62 extends from the edge of the point to form one of the terminals of the group of the device 40. FIG. 4 illustrates that the only steps required to form the structure of FIG. 4 are a printing step 67 and a curing step 69. The random pattern of the device 40 may be similar to the pattern of the LED 16 in FIG. 2. FIG. 4 illustrates the rightmost device 40A oriented in the opposite direction. However, the intermediate electrode 48 remains floating, so the device 40A is not operated and has no effect on the resulting circuit. The printing device 40 is connected in parallel via a conductor layer. Appropriate operating voltages and control voltages are applied to the conductor layers to operate the device 40. In the example of FIG. 4, the top electrode 46 is a control electrode of the device 40 (eg, for a gate or a base). The remaining two electrodes are current-carrying electrodes (eg, source / drain, emitter / collector). Since the middle electrode 48 of the improperly oriented device 40A is floating, the device 40 remains closed and is an open circuit. FIG. 5 illustrates how the device 40 can be an npn bipolar transistor 40B, wherein the middle electrode 48 is a base electrode. The intermediate electrode 48 may be connected to any other semiconductor layer in the device 40B using a through hole. FIG. 6 illustrates how the device 40 may be a p-channel MOSFET 40C, wherein the middle electrode 48 is a source electrode. The intermediate electrode 48 may be connected to any other layer in the device 40C using a through hole. If the device 40 is to be connected as a diode, only the conductor layers 62 and 52 or 66 and 62 can be used. Therefore, the effective polarity of the diode can be selected by which two conductor layers are used to contact the diode. Alternatively, two conductive layers may be connected via a distal end to form a diode. Any number of devices 40 can be connected in parallel in a group for handling a wide range of currents. In one embodiment, approximately 10 devices 40 are positioned in each group. Groups of devices 40 are two-dimensional arrays printed in groups such as by using a pattern on a roller in an offset printing process or by using a mask on a screen printing screen, and various conductor layers Similar patterning can be used so that the devices 40 in each group are connected in parallel, but the groups are electrically isolated from each other. Therefore, each group forms a separate component. "Stylized" conductor traces on the substrate 50 can then be used to selectively interconnect groups to form more complex circuits, such as logic circuits. A metal flexible circuit pattern on the substrate 50 can be used to interconnect groups of devices 40 to form a logic circuit. In one embodiment, since the groups can be as small as one millimeter per side or one millimeter in diameter, the two-dimensional array of such groups can exceed thousands of groups. Groups within a small area can be interconnected to form logic gates, and the gates of the gates can be interconnected during programming to perform any logic function. FIG. 7 illustrates how the improper orientation of the device 40A in FIG. 4 does not adversely affect the operation of the appropriate orientation devices 40 connected in parallel in the group. The device 40 / 40A is assumed to be an npn bipolar transistor having a top electrode 46 serving as a base, a bottom electrode 58 serving as an emitter, and an intermediate electrode 48 serving as a collector. Since the device 40A is undesirably inverted during printing (shown in FIG. 4), its base is shorted to the emitter of the device 40 and its emitter is shorted to the base of the device 40. When the base / emitter junction of the device 40 is forward biased to turn on the device 40, the device 40A remains closed without affecting the operation of the device 40. Note that by using an intermediate electrode 48 (as shown in FIGS. 3 and 4) that is offset from the middle of the device 40, the intermediate electrode 48 of the device 40A will be floating, making its effect more obvious. FIG. 8 is similar to FIG. 9, but the devices 40 and 40A are MOSFETs. FIG. 9 is a table showing possible connections of the top, bottom, and middle electrodes of the device 40 formed as a MOSFET or a bipolar transistor such that improper orientation does not adversely affect the function of a properly oriented device 40 connected in parallel. FIG. 10 illustrates two groups 72 and 74 of a printed npn bipolar transistor (eg, device 40), where the transistors in each group are connected in parallel so that each group acts as a single transistor. The printed patterns of the device 40 and the conductor layer are grouped as dots, but dots of any shape can be used. The interconnection of the group in Figure 4 makes the circuit an AND gate. The conductive traces 75 are connected to various conductor layers in FIG. 4 for each group. Two transistors (ie, groups 72 and 74) are connected in series between the supply voltage terminals 76 and 78, the bases of the transistors are connected to the input terminals 80 and 82, and the output terminal 84 is connected to the group formed by the group 74 The emitter of a transistor. Various terminals may be near or near the edge of the substrate 50. The resistors r1 and r2 are shown as being connected between the input terminals 80/82 and the base for current control. Due to the simplicity of the resistor, the resistive material can be patterned directly on the substrate using an offset printing using a patterning roller or a mask on a screen used to print the resistive material. The shape of the resistance material can determine the resistance or the position of the connector along its length can determine the resistance. A resistor may also be included on each device 40. Capacitors can also be formed by printing capacitor layers. The substrate 50 may contain hundreds or thousands of these AND gates or other gates, and the gates may be interconnected to form more complex functions. In this case, the gates are equivalent to a programmable gate array. For a more flexible circuit, the group may initially be unconnected, and the interconnected stylized masks may determine the final circuit. 3D stylization can be used to allow the intersection of traces. Any combination of gates and other logic circuits can be generated. Some groups may contain transistors and other groups may contain other devices, such as diodes. Analog circuits can also be formed by interconnecting various groups. Due to the random but substantially uniform distribution of the devices 40 in the ink, each group of the same area will have approximately the same number of devices 40. A slight difference in the number of devices 40 in a group will not affect the performance of a logic circuit. In one embodiment, due to the required low current, there may be approximately 10 identical devices in each group. The cost of devices 40 in a single group, which represents a single transistor, is about 0.143 cents. Therefore, the resulting circuit board can be made relatively inexpensive. As shown in FIG. 11, in order to simplify the programming of groups that can be printed as an ordered two-dimensional array, the conductive traces 85 from the conductor layer (FIG. 4) of all the groups can be terminated on one of the substrates 50 At patch area 86, the product is now a programmable circuit board 87. These traces 85 may be part of the "standard" design of the circuit board 87, which is then subsequently customized for a specific use. This enables the printing procedure used to form the traces 85 to be optimized to connect to the conductor layers in the group and the stylization procedure to be optimized for interconnecting the ends of the terminals 88. For example, the stylized program may be executed at a time after the circuit board 87 has been fabricated and the stylized steps may be executed by a special device under the control of a computer. In addition, the interconnect pattern can be much more complicated than the trace 85 that electrically connects the transistor terminals to the patch area 86. In the example of FIG. 11, the stylization in patch area 86 forms the AND gate of FIG. 10. For more complex circuits, the stylized traces 90 may need to cross and multiple layers may be formed to avoid shorting the traces. In another embodiment, groups of devices 40 may initially be interconnected adjacent to the group to form separate logic gates, such as AND, NAND, NOR gates, and the leads of each gate are terminated in patch area 86 for subsequent programming To customize substrates for a specific customer. Therefore, the universal circuit forms a programmable gate array. A plurality of spaced apart patch areas may be provided on the circuit board 87 to simplify interconnection wiring. In one embodiment, terminals for all input signals are provided on one level in a patch area and output terminals are provided on another level. If the programming of the interconnect is complex, it may not be sufficient to print the interconnect directly in one of the X-Y planes on the substrate 50. The direct printing of conductors on the substrate is limited because one of the minimum gaps between the conductors is about 30 microns to avoid cross bridging, and thin conductors have a tendency to break by surface tension. In a case where it is not desired to directly print a conductor line, a mask layer is first formed on a substrate, and then a conductive ink is deposited over the mask layer as follows. One of the groups of patterned interconnect traces or any other traces on the patterned circuit board 87 or patterning device 40 is to form a hydrophobic mask. The mask can be deposited by printing (eg, using a patterned roller or screen printing) or can be patterned by a photolithography process (if printing cannot achieve the desired accuracy). A suitable masking substance is a thoroughly cleaned diatomaceous earth particle which is saturated with a solution as an ink. Print the ink with a pattern that is concave with respect to the wiring / device pattern to be matched. After curing, the resulting film is activated via a fluorination process, resulting in a superhydrophobic surface (ie, it is not wetted by conductor ink or device ink). The area of the substrate exposed by the film will be moderately hydrophilic or super-hydrophilic (ie, it will be wetted by the conductor ink or device ink). To form a trace, a hydrophilic conductive ink is prepared and deposited over a hydrophobic mask. The exposed substrate area will be covered with ink, and the conductive ink that has been deposited on the surface of the hydrophobic mask will accumulate in the exposed area. This results in a larger cross-sectional area of the conductive ink (for good conductivity and mechanical strength) and prevents cross-bridges. FIG. 12 is a top view of one of the hydrophobic masks 94 defining a region 96 of the exposed substrate. FIG. 13 is a cross-sectional view showing a single conductor 98 formed in one of the regions 96. Note that the conductor 98 is thicker than the shield 94. The height of the conductor 98 is determined by the amount of conductive ink deposited above the mask. For a mask that defines a large exposed area of the substrate, more conductive ink needs to be deposited to ensure that the exposed area is completely covered by the ink. At the termination area of the trace, such as to connect the ends of the trace to other conductors, an enlarged pad area should be formed to ease the alignment tolerance for a subsequent printed layer and improve the resulting electrical connection. After the conductive ink is cured, a dielectric ink is subsequently deposited over the same mask, where the dielectric ink contains sufficient surfactant to cover the surface of the mask and the conductor and neutralize the hydrophobic effect of the mask. Additional mask and trace layers can be formed to produce a three-dimensional matrix of interconnects. Vertical vias can be used for interconnections between conductor layers. FIG. 14 illustrates the use of a hydrophobic mask 100 over the circuit board 87 of FIG. 11 when interconnections between groups 72 and 74 are created to form an AND gate. In another embodiment, the mask 100 is used only in the patch area 86 for stylization, and the traces 85 leading to the various groups are formed when various conductor layers of the group are printed. This general masking procedure can also be used for groups and conductor layers of the patterning device 40. Groups of the same or different devices can be stacked to allow the formation of very complex circuits. After the standard features of the circuit board 87 have been formed, a stylized procedure can be performed inexpensively on a large number of flexible circuit boards 87 in a reel-type procedure. After final stylization, the circuit board 87 can be singulated from the roll. As can be seen, no vacuum processing or hazardous materials are used to make and program the circuit board 87. FIG. 15 illustrates how the resistors R1 and R2 in FIG. 14 can be formed by offset printing or screen printing a resistive material on a substrate, wherein a mask on the screen defines the shape of the resistive material. Other deposition techniques can be used. The shape (length, width, height) of the resistance material can determine the resistance or the position of the connector 102 or 103 along its length can determine the resistance. If the position of the connector determines the resistance, all the resistors can be formed identically. The resistance can also be selected by interconnecting the resistors in series and / or in parallel. 16 illustrates a bottom view and a cross-sectional view of a circuit board 106 in which groups of devices such as groups 72 and 74 on the bottom and other groups 110 and 110 on the top have been printed on both sides of the substrate 108. 112. Traces 114 and 116 interconnect the groups. The through-hole 118 connects a circuit on one side to a circuit on the other side. Prior to printing the interconnect layer, the vias are perforated in the substrate 108 and filled with, for example, UV-cured hole-filled conductors. If a mirror image is formed, this simplifies the interconnect design because the patch areas on both sides can be the same. Instead of a through hole, a wraparound connector can be used. Since the substrate 108 can be a very thin and flexible film (such as a flexible circuit), the resulting circuit board 106 can be folded to reduce its size. Flexible guides formed from ink are commercially available. There may be special areas on the substrate 108 that define the location of the foldable circuit board 106 without damaging the circuit. In order to improve the reliability and flexibility of the use of the circuit board, a "base" circuit board 120 (Fig. 17) can be made to have specific basic features and connection terminals. After the circuit board 120 has been tested and approved, the additional circuit boards 122 and 124 can be electrically attached to the base circuit board 120 to customize performance for a specific application. In the embodiment of FIG. 17, the tested and approved circuit boards 122 and 124 have an adhesive applied to their surfaces, which will be adhered to the base circuit board 120. The terminals 126 of the circuit boards 122 and 124 are aligned with the terminals on the base circuit board 120. The terminals 126 are coated with a conductive adhesive. The circuit boards 122 and 124 are then aligned with the base circuit board 120 and adhered to the surface of the base circuit board 120. In one embodiment, the "device side" of circuit boards 122 and 124 faces the device side of base circuit board 120. By forming various functional units individually, the pass rate of each unit during the test will be higher, and the functional units can be connected in various combinations to increase more functional possibilities. In one embodiment, the circuit boards 122/124 are formed in a reel-to-reel process, and after testing, an adhesive is applied to the final station. The circuit boards 122/124 may have test tabs cut during singulation. After singulation, the circuit boards 122/124 are adhered to the base circuit board 120. As an arbitrary example, one circuit board 122 may be an A / D converter, and the other circuit board may be a D / A converter. FIG. 18 illustrates another technique for mounting the circuit board 122 to the base circuit board 120. In FIG. 18, the circuit board 122 is perforated at the electrical connection position at the area 128. Subsequently, a dielectric adhesive is used to coat the bottom side (not the device side) of the circuit board 122 and the circuit board 122 is adhered to the base circuit board 120, so the perforations are above the connection terminals on the base circuit board 120. Subsequently, a conductive adhesive 130 is deposited through the through holes to connect the terminals of the base circuit board 120 to the top terminals of the circuit board 122. For example, the traces 132 and 134 are connected by a conductive adhesive 130. This technique can also be used in conjunction with the double-sided circuit board of FIG. 16. Using a large number of redundant arrays of devices (e.g., device 40 in FIG. 11) and standard passive devices in patch area 86 (e.g., resistors R1 to R3 in FIG. 11) allows the board to have very high throughput rates and Generate a programmable circuit board that can then be programmed to make unique devices as needed. For higher density device groups, multiple insulating layers of the group can be printed to form a three-dimensional structure. Vertical vias can be used to access various layers. Groups of devices can be connected in series using vertically aligned groups. FIG. 19 schematically illustrates one possible assembly line for manufacturing a circuit by printing in a reel process. The roll 136 contains a substrate material and the roll 138 is a take-up roll. Mark various stations. The program sequentially prints the various layers and cures the layers. Offset printing is preferably used for printing using a roll-to-roll process. The number of layers depends on the complexity of the printed circuit and device. Depending on a particular customer need, the reel-to-roll process can produce unprogrammed circuit boards and a separate system can be used for the final programming step. Various directional attributes (such as bottom, top, and vertical) as used herein should not be interpreted as conveying an absolute direction relative to the surface of the earth, but rather to convey the orientation relative to the drawing when the chart is held vertically. In a practical embodiment, these terms still apply to a product regardless of its absolute orientation relative to the surface of the earth. For complex circuits that require a large number of electrical components, very small dots with high density of printing devices in highly defined areas, such as in an array, may be desirable. Each point acts as a single electrical component. One of the limiting factors of the printed dots is the presence of some diffusion of the liquid (ie, the ink containing the device) on the substrate, regardless of the printed pattern. The liquid used in the device ink is designed for the hydrodynamics needed to achieve the proper orientation of the microelectronic device and has not been optimized to limit the diffusion after printing on the substrate. In addition, conventional printing masks, such as screen printing, have limited resolution, where the resolution must take into account that the mask must pass through an electronic device. The following methods can be used to greatly reduce the size of points, increase the density of points, and improve the accuracy of positioning of points. Using the following method, the separation of dots can be reduced to about 3 microns, and the diameter of the dots can be smaller than the diameter of dots that can be achieved using conventional printing methods using device inks. Generally, the method requires patterning a hydrophobic (or lyophobic) layer on a substrate. Patterning can be patterned by using high-resolution printed masks or even photolithography. Hydrophobic materials are optimized for printing (eg, optimized viscosity for limited diffusion), so they can be patterned to much higher resolution and accuracy than device ink printing. The hydrophobic layer is patterned to form extremely small and dense openings that expose the substrate. The bottom conductor layer can be printed so that each opening in the hydrophobic layer contains a device contact pad and a trace leading to a patch area on the substrate. The conductive layer can be painted across the surface to fill the opening, or the hydrophobic layer can pattern the conductive layer by its hydrophobic effect, or both. Therefore, the conductor layers and traces are self-aligned with the patterned hydrophobic layer. The device ink can then be deposited over the patterned hydrophobic layer and the conductor layer, and the ink will repel from the hydrophobic layer and only reside in the opening. Capillary action causes all liquid to reside in the opening, forming a device point. Therefore, it is the patterned defined points of the hydrophobic layer rather than a device ink printing mask. To use the ink more economically, the ink can be blanket-deposited without a printing mask or a printing mask can be used to pattern the dots coarsely. The device ink can also be applied across the hydrophobic layer to fill the opening. The device ink is then cured and the electrical components, such as transistors or diodes, are properly oriented so that the bottom terminal of the device is ohmically connected to the bottom conductor layer. A dielectric layer is then printed, and then a top conductor layer is printed over the device to connect the devices in each opening in parallel. The top conductor layer may include traces extending to the patch area. Therefore, the top conductor layer can also be self-aligned to the device using a hydrophobic layer. The hydrophobic layer repels all printed devices and conductive ink. The hydrophobic layer can also form a wall, so one or more printed layers can be applied over the surface to reside only in the opening. In either case, the resolution and positioning of all layers is defined by the hydrophobic layer. Multiple hydrophobic layers can be patterned to define different printed layers. FIG. 20 is a top view of a programmable circuit 150, where each point 152 represents a group of printed electrical devices (eg, device 40 in FIG. 3), and the mid-point area is defined by a patterned lyophobic layer 154. The lyophobic layer 154 may also define conductor areas and traces 156 that lead to the patch area 158 for interconnecting the top and bottom conductors of each point 152 to form virtually any type of digital circuit or even a digital circuit. Analog circuit. For a three-terminal device, such as a transistor, there will be three or more conductor layers. The array of dots 152 may include a variety of devices, such as bipolar and MOS transistors, resistors, diodes, and the like. The electrical terminals of the circuit may include a power supply terminal V + and ground, differential input terminals In1 and In2, and differential output terminals Out1 and Out2. The entire circuit 150 may be formed by printing under atmospheric conditions. FIG. 21 is a cross section of one of the circuits 150 of FIG. 20 divided into four points 152 after printing the lyophobic layer 154 and after printing a bottom conductor layer 160. The lyophobic layer 154 need not be formed directly on the surface of the substrate 162. The bottom conductor layer 160 forms an isolated contact for a subsequent printing device and may include traces leading to the patch area 158 shown in FIG. 20. The liquid-repellent layer may be a conventional liquid-repellent material printed using screen printing, offset printing, or other printing methods. Such a material may be a fluorine-based material such as Teflon or other commercially available materials. Various materials are known to repel different liquids, and the choice of these lyophobic materials will depend on the solution used for the device ink and the conductor ink. The solution may be alcohol-based. The lyophobic layer 154 may be a hydrophobic layer. The lyophobic layer 154 can also be a layer with very fine roughening, which causes the overlying layer to be essentially supported by an air cushion to prevent wetting. The lyophobic material can be optimized for fine patterning, which can be much finer than using conventional screen printing and offset printing patterning device inks. For example, the device ink solution is selected for proper fluid dynamics to allow microdevices to have proper orientation as they settle on the bottom conductor. The device ink solution may have an extremely low viscosity, which causes the dots to spread, thereby limiting the density of the dots. In addition, device ink printing resolution can be limited due to the size of the micro-devices in the ink. In contrast, lyophobic materials have no such restrictions and can be patterned to a resolution of only a few microns. In addition, any small diffusion of the liquid-lyophobic layer 154 will desirably make the openings smaller, and thus the dot size smaller, because it is a negative image of the dot pattern. In one embodiment, the lyophobic material is first printed and cured to define various dot areas and conductor patterns. Light lithography can also be used for finer patterning. The substrate 162 may be any suitable material, such as PMMA, FR-4, paper, and the like. A conductive ink is then printed, which may include metal particles in a solution. The conductive ink may be printed in the openings of the lyophobic layer 154, or may be blanket-deposited and applied over the surface to fill the openings in the lyophobic layer 154. In one embodiment, the conductive ink layer extends to the height of the lyophobic layer 154 before curing, so that the surface is flat. Curing the conductive ink layer to form the bottom conductive layer 160 will cause some shrinkage. Any subsequent device ink or conductor ink will also repel from the hydrophobic surface and accumulate above the bottom conductor layer 160. Therefore, all printed layers are self-aligned. FIG. 22 shows the structure after the printing device ink 166, in which the lyophobic layer 154 defines the shapes of the points 152 and the conductor. Even with the blanket printing device ink 166, all ink will remain in the opening due to the repellency of the liquid-repellent layer 154. FIG. 23 illustrates a structure after the device ink is cured to form a single-layer electrical device 170, and the bottom terminals of the single-layer electrical device 170 are in electrical contact (eg, ohmic contact) with the bottom conductor layer 160. A dielectric layer (such as dielectric layer 60 in FIG. 4) is then printed to insulate the bottom conductor layer 160. Next, a top conductor layer 172 is printed and cured to ohmically contact the top terminal of the electrical device 170. If the electrical device 170 has three layers of terminals, such as the transistor shown in FIG. 4, an additional conductor layer and a dielectric layer will be printed. The top conductor layer 172 may be defined using another patterned lyophobic layer (outside of the cross section of FIG. 23), which causes the top conductor to overlap the bottom conductor. In this embodiment, the liquid-repellent properties of the first liquid-repellent layer 154 may need to be neutralized by a corona treatment process to deposit another liquid-repellent layer above it and over any other portion of the surface. The good or poor wetting of a material by a liquid depends primarily on the chemical properties of both the liquid and the surface. Wetting is defined as the ratio between the surface energy of a liquid and a surface. In general, the following rules apply: If the surface energy (= dyn / cm) of a material is higher than the surface energy of a liquid, the material will be wetted. If not, there will be a sticking problem. Pretreatment provided by the corona treatment may be required to obtain sufficient wetting and adhesion before printing. Corona discharge unit optimizes wetting and adhesion. This corona technique has proven to be highly effective and cost-effective and can occur online. This corona treatment is well known. The top and bottom conductor layers for each point 152 area are electrically isolated and may have patch areas 158 extending to FIG. 20 for interconnecting with a stylized mask to customize the circuit traces 156 (FIG. 20 ). Programming can be performed by depositing a metal or by other techniques. Examples of circuits that can be formed include state machines, memories, clocks, logic circuits, and even analog circuits. Some groups of electrical devices can be connected in parallel for conducting higher currents, such as for LED drivers. For an array of large numbers of dots 152, the conductor pattern can become excessively complex, and large parasitic capacitances of the overlying traces can occur. FIG. 24 illustrates an alternative embodiment in which, for each isolated point 152, the bottom conductor layer 160 is extended to the bottom side of the substrate 162 by using a conductive via 174 to facilitate the wiring of the traces and reduce the parasitic capacitance effect. Therefore, the bottom side of the substrate 162 will contain all the bottom conductor traces leading to the patch area 158 (FIG. 20). FIG. 25 illustrates how a programmable circuit can include any number of device layers to increase device density. In FIG. 25, a dielectric layer 178 is printed over the conductor layer 174, then another conductor layer 180 is printed, then another device layer 182 is printed, and then another conductor layer 184 is printed. Basically, the steps are the same as forming the layers of FIGS. 21 to 24. Any number of layers can be formed for any circuit complexity. FIG. 26 is a flowchart identifying steps for forming the programmable circuit 150 of FIG. 20. In step 190, a suitable substrate is provided. In step 192, a lyophobic layer is printed in a pattern to expose a region of the substrate surface where the isolation device dots will be formed and also define a conductor pattern. The conductor pattern may include traces leading to a patch area. In step 194, a bottom conductor layer is printed, where the conductor ink resides only in the openings in the lyophobic layer. The conductor ink printing program can rough define the conductor pattern, and the lyophobic layer then accurately defines the conductor pattern. The conductive ink is then cured. In step 196, the device ink is printed over the surface so that the device ink is defined by the patterning (opening) of the lyophobic layer. In step 198, the device ink is cured to cause the bottom terminal of the device to be electrically (eg, ohmic) connected to the bottom conductor layer. In step 200, the surface of the lyophobic layer is optionally subjected to a corona treatment to neutralize the surface. This allows subsequent layers to be formed over the middle and lyophobic layers, such as for printing a new lyophobic layer that defines one of the subsequent layers. In step 202, a dielectric layer is printed over the bottom conductor layer and between the electrical devices for insulating the bottom conductor layer. In step 204, a second lyophobic layer may be printed to define a top conductive layer. In step 206, the top conductor layer is printed and cured to electrically (e.g., ohms) contact the top terminals of the electrical device and connect all electrical devices in a single point in parallel, such as shown in FIG. The programmable circuit is now complete, assuming the device requires only two terminals. In step 208, the programming of the circuit is performed, for example, by interconnecting various leads of the bottom and top conductor layers to form any type of logic circuit or analog circuit upon request from a customer. Although specific embodiments of the invention have been shown and described, those skilled in the art will understand that changes and modifications can be made without departing from the broader aspects of the invention, and therefore the scope of the accompanying patent application for invention will fall within their scope It is intended to cover all such changes and modifications that fall within the true spirit and scope of the invention.

16‧‧‧Light Emitting Diode (LED)

18‧‧‧ bottom metal cathode electrode / bottom light emitting diode (LED) electrode

20‧‧‧ Top metal anode electrode

22‧‧‧ substrate

24‧‧‧Reflective conductor layer / under conductor

26‧‧‧ Dielectric layer

28‧‧‧ Top transparent conductor layer

30‧‧‧Metal bus bar

31‧‧‧Metal bus bar

32‧‧‧Metal bus bar

33‧‧‧Metal bus bar

38‧‧‧light

40‧‧‧Three-terminal device / device

40A‧‧‧device

40B‧‧‧npn bipolar transistor / device

40C‧‧‧p-channel MOSFET / device

42‧‧‧ lower section

44‧‧‧ Upper Section

46‧‧‧Metal top electrode

48‧‧‧metal intermediate electrode

50‧‧‧ starting substrate

52‧‧‧conductor layer

54‧‧‧ conductive via

56‧‧‧ metal layer

58‧‧‧ bottom electrode

60‧‧‧ Dielectric layer

62‧‧‧Intermediate conductor layer

64‧‧‧ Dielectric layer

66‧‧‧Top conductor layer

67‧‧‧Printing steps

68‧‧‧metal layer

69‧‧‧Cure step

72‧‧‧group

74‧‧‧group

75‧‧‧ conductive trace

76‧‧‧ supply voltage terminal

78‧‧‧ supply voltage terminal

80‧‧‧input terminal

82‧‧‧input terminal

84‧‧‧output terminal

85‧‧‧Conductive traces / traces

86‧‧‧ Patch area

87‧‧‧ Programmable circuit board / circuit board

88‧‧‧Terminal

90‧‧‧ stylized trace

94‧‧‧ hydrophobic mask

96‧‧‧ area

98‧‧‧Conductor

100‧‧‧ hydrophobic mask

102‧‧‧Connector

103‧‧‧ Connector

106‧‧‧Circuit Board

108‧‧‧ substrate

110‧‧‧group

112‧‧‧group

114‧‧‧trace

116‧‧‧trace

118‧‧‧through hole

120‧‧‧Circuit Board

122‧‧‧Circuit Board

124‧‧‧Circuit Board

126‧‧‧Terminal

128‧‧‧ area

130‧‧‧Conductive Adhesive

132‧‧‧trace

134‧‧‧trace

136‧‧‧roller

138‧‧‧roller

150‧‧‧ programmable circuit

152‧‧‧ points

154‧‧‧lyophobic layer

156‧‧‧Conductor area / trace / second conductor layer / conductive wire / electrical connector

158‧‧‧ patch area / second conductor layer / interconnect area / termination area

160‧‧‧ bottom conductor layer

162‧‧‧ substrate

166‧‧‧device ink

170‧‧‧Electric device

172‧‧‧Top conductor layer

174‧‧‧ conductive via

178‧‧‧ Dielectric layer

180‧‧‧conductor layer

182‧‧‧device level

184‧‧‧conductor layer

190‧‧‧step

192‧‧‧step

194‧‧‧step

196‧‧‧step

198‧‧‧step

200‧‧‧ steps

202‧‧‧step

204‧‧‧step

206‧‧‧step

208‧‧‧step

r1‧‧‧ resistor

r2‧‧‧ resistor

R1‧‧‧ resistor

R2‧‧‧ resistor

R3‧‧‧ resistor

Figure 1 is a cross-section of a loose monolayer of a printed micro vertical LED that can be formed using the assignee's prior art procedures. FIG. 2 is a top view of one of the structures of FIG. 1, where FIG. 1 is obtained across FIG. 3 is a perspective view of a single three-terminal transistor that has been singulated from a wafer according to an embodiment of the present invention. The transistor is mixed into a solution to form an ink for printing on a substrate. Fig. 4 is a cross section of a small portion of a printed layer of one of the transistors of Fig. 3 connected in parallel using three planes of a conductor layer. Approximately ten parallel-connected transistors can be printed in each individual group, and an array of one group can be printed above the substrate. FIG. 5 illustrates how the transistor of FIG. 3 can be an npn bipolar transistor. FIG. 6 illustrates how the transistor of FIG. 3 can be a p-channel MOSFET. Figures 7 and 8 illustrate how some transistors can be "incorrectly" interconnected by improper orientation of the transistors during printing, where the interconnection does not adversely affect the function of the improperly oriented transistors. FIG. 9 is a diagram for identifying one of the preferred functions of the top electrode, the bottom electrode, and the middle electrode of the MOSFET and the bipolar transistor. FIG. 10 illustrates interconnecting groups of transistors to form a logic circuit. FIG. 11 illustrates how the leads of various groups of a device can be brought to a patch area of a substrate for interconnecting the groups. In another embodiment, the leads of a logic gate (eg, a NAND gate) made of a group can be brought to the patch area. Figure 12 is a top view of one of the conductors patterned using a hydrophobic mask. FIG. 13 is a cross-sectional view of one of the conductor lines formed using the mask of FIG. 12. FIG. 14 illustrates how a hydrophobic mask can be used to form conductor lines to interconnect groups of devices to form a logic circuit. FIG. 15 illustrates how a resistor value can be determined by the position where a conductor contacts a printed resistive material. FIG. 16 illustrates how devices can be printed on both sides of a substrate and interconnected by a via. FIG. 17 illustrates how a circuit can be printed on and tested on a relatively small substrate, and the small substrate is then attached to a larger "base" substrate during a customization step. FIG. 18 illustrates how the electrodes on the small substrate of FIG. 17 can be bonded to the electrodes on the base substrate. FIG. 19 illustrates one of the scroll programs that can be used to form a circuit. FIG. 20 is a top view of a programmable circuit, in which each point represents a group of printed electrical devices, and a mid-point area is defined by a patterned lyophobic layer (or hydrophobic layer). Fig. 21 is a cross section of one of the circuits of Fig. 20 divided into four points after printing the lyophobic layer and after printing a bottom conductor layer. The bottom conductor layer forms isolated contacts for subsequent printing devices, and may include traces leading to the patch area shown in FIG. 20. FIG. 22 shows the structure after the ink of the printing device, where the lyophobic layer defines the points and the shape of the conductor. FIG. 23 shows the structures after the device ink is cured, after the dielectric layer is printed, and after the top conductor layer is printed. FIG. 24 illustrates an alternative embodiment in which for each isolated point, the bottom conductor layer extends to the bottom side of the substrate to facilitate the wiring of the traces and reduce the parasitic capacitance effect. FIG. 25 illustrates how a programmable circuit can include any number of device layers to increase device density. FIG. 26 is a flowchart identifying steps for forming the programmable circuit of FIG. 20. In the various figures, similar or identical elements are labeled with the same numerals.

Claims (25)

A method for forming a circuit (150), comprising: patterning a first material (154) overlying a substrate (162) to define one or more openings; and depositing a first material over the first material. A first solution (166) containing a pre-formed, semiconductor electrical device (40), wherein the first material prevents wetting by the first solution such that the first solution resides substantially only in the first Or the plurality of openings; curing the first solution so that the electrical terminals (18, 58) of the electrical devices in the one or more openings make at least electrical contact with a first conductor layer (160) overlying the substrate ; And forming at least a second conductor layer (156, 172) to interconnect at least some of these electrical devices to achieve an electrical function. The method of claim 1, further comprising: forming one or more input terminals (In1, In2) for supplying an input signal; and forming one or more output terminals (Out1, Out2) for supplying an output signal , Wherein the input signal is transformed by the electrical devices, and the transformed signal is output at the one or more output terminals. The method of claim 1, wherein the electrical devices (40) positioned in each of the one or more openings form a separate group (152) of the electrical devices, the The electrical devices are connected in parallel by at least the second conductor layer (172). The method of claim 3, wherein the electric devices (40) are randomly distributed in each group (152) on the substrate. The method of claim 3, further comprising: forming at least the second conductor layer (156, 158) to interconnect the separate groups (152) of the electrical device (40) to achieve the electrical function. The method of claim 5, further comprising forming an interconnect region (158) on the substrate (162), wherein at least the second conductor layer provides lead from the separate groups (152) of the electrical devices to the Interconnected areas are conductive wires (156) for electrically interconnecting the groups to achieve the electrical function. The method of claim 1, further comprising forming at least the second conductor layer (156, 172) to interconnect the electrical devices (40) to form a logic gate. The method of claim 7, further comprising interconnecting the logic gates to achieve the electrical function. The method of claim 1, wherein the first material (154) is lyophobic. The method of claim 1, wherein the first material (154) is hydrophobic. A circuit includes: a substrate (162); a first material (154) overlying the substrate and patterned to define one or more openings; a preformed, semiconductor electrical device (40) A plurality of separate groups (152), which have been mixed in a first solution (166), deposited on the substrate, and cured, wherein the first material prevents wetting by the first solution such that The first solution resides only in the one or more openings; at least one first conductor layer (160) overlies the substrate exposed through the one or more openings so that the one or more openings The first electrical terminals (18, 58) of the electrical devices are in electrical contact with at least the first conductor layer; and at least one second conductive layer (156, 172), which contacts the second electrical terminals of the electrical devices ( 20, 46) to interconnect at least some of these electrical devices to achieve an electrical function. The circuit of claim 11, wherein at least the second conductor layer (172) connects the electrical devices (40) in each of the one or more openings in parallel to form a separate group (152) of the electrical devices ), The circuit further includes at least the second conductor layer (158) interconnecting the separate groups of electrical devices to achieve the electrical function. The circuit of claim 12, wherein at least the second conductor layer (158) forms an interconnected conductor pattern to interconnect at least some of the groups (152) of the devices (40) together to achieve the Electric function. The circuit according to claim 13, further comprising: one or more input terminals (In1, In2) for supplying an input signal; and one or more output terminals (Out1, Out2) for supplying an output signal, wherein The input signal is transformed by the electrical devices (40) after the interconnection conductor pattern is formed, and the transformed signal is output at the one or more output terminals. The circuit of claim 11, wherein the electrical devices (40) are randomly distributed in each of the one or more openings in the first material (154) on the substrate (162). The circuit of claim 11, wherein the first material (154) is hydrophobic. The circuit of claim 11, wherein the first material (154) is lyophobic. The circuit of claim 11, wherein the first conductor layer (160) is defined by the one or more openings in the first material (154). The circuit of claim 11, further comprising: a second material (204), which is deposited over the first material (154) and is patterned to have a second opening; and a conductive material (206), which After being deposited in the second openings, the conductive material is deposited in a second solution, wherein the second material prevents wetting by the second solution, so that the second solution resides only in the second openings. Therefore, the conductive material is defined by the second openings in the second material. As claimed in the circuit of item 11, the electrical devices (40) within each of the one or more openings form a group (152) of the electrical devices, wherein each group has its own associated group The extended at least one electrical connector (156), wherein each electrical connector is terminated in a termination area (158), and an interconnecting conductor pattern electrically interconnects the groups in the termination area. If the circuit of claim 11, wherein the electrical devices (40) include the same first device (16), the circuit further includes: a plurality of separate groups of pre-formed, semiconductor second electrical devices (40), which After having been mixed in a second solution, deposited in the one or more openings above the substrate (162) and cured, the second electrical devices are different from the first electrical devices; and at least the first Two conductor layers (156, 172) that interconnect the groups of the first electrical devices and the second electrical devices to achieve the electrical function. For example, the circuit of claim 11, wherein the electrical devices (40) are randomly distributed in each group (152) on the substrate (162). The circuit of claim 11, wherein at least the second conductor layer (156, 172) interconnects the groups (152) to form a logic gate and an interconnection between the logic gates to achieve the electrical function. The circuit of claim 11, wherein the electric devices include at least one of a diode (16) and a transistor (40). The circuit of claim 11, further comprising connecting conductive conductive layers (118, 174) to form a three-dimensional structure.