TW201824714A - Rectifier circuit applied to various linear and non-linear inputs and loads capable of improving power supply efficiency, reducing complexity of circuit design, and avoiding circuit malfunction - Google Patents

Abstract

The present invention relates to a rectifier circuit applied to various linear and non-linear inputs and loads, which includes an input voltage, a bridge rectifier circuit, a load circuit, a voltage level holding drive circuit, a current phase timing detection circuit, a high voltage side and low voltage side drive circuit, an input voltage phase timing detection circuit, a mono-stable circuit, and a transistor conduction control circuit. By simultaneously detecting the voltage conduction phase of the input signal and the conduction phase of the current in the total circuit, the present invention determines the conduction time of the switch devices in the bridge rectifier circuit, so that the bridge rectifier circuit can be applied to the input signal of arbitrary waveforms and various combinations of linear or non-linear circuits while achieving a high efficiency, thereby further improving the power supply efficiency, reducing circuit design complexity, and avoiding circuit malfunction.

Description

   Rectifier circuits for various linear and non-linear inputs and loads   

The invention relates to a rectifier circuit, in particular to a rectifier circuit applied to various linear and non-linear inputs and loads.

Improving the efficiency of the rectifier circuit is one of the important methods to improve the efficiency of the circuit. In the power conversion circuit, as the power is increased, the importance for conversion efficiency is increasing. The input signal and load of the circuit are composed of a mixture of linear and non-linear characteristics. Traditionally, only the input signal of a sine wave is matched with a resistive linear load, and according to the input voltage phase, the corresponding switching element connected in parallel with the rectifier diode However, when the load is non-linear or the input signal is DC, the switching element connected in parallel with the rectifier diode will fail or become unusable.

Further, the diode rectifier used in the rectifier circuit increases in power consumption with the increase of the passing current. In order to reduce the loss of the diode, a switching element such as a MOSFET is connected in parallel at both ends, and the diode is connected to the diode. The MOSFET is turned on when the body is turned on to reduce the power loss of the diode. However, the conventional rectifier circuit detects the phase of the input voltage and determines whether the switching element is turned on or not. If the load circuit includes a capacitive element or other non-resistive load circuit and the input voltage presents a non-linear signal, the load The circuit will generate reverse current, further causing short-circuit problems, which will cause the rectifier circuit to fail; or, when the input is an extremely long period of AC or DC signal, the floating bootstrap power supply will lose the power supply effect, making the control circuit Failure.

In view of the above problems, the present invention discloses a rectifier circuit applied to various linear and non-linear inputs and loads, including an input voltage, a bridge rectifier circuit, a load circuit, a plurality of voltage level maintaining driving circuits, and a current phase timing detection. Circuit, a plurality of high-voltage side and low-voltage side drive circuits, a plurality of input voltage phase timing detection circuits, a monostable circuit, and a transistor conduction control circuit. The bridge rectifier circuit receives the input voltage. The load circuit is electrically connected to the bridge rectifier circuit. The plurality of voltage level maintaining driving circuits are electrically connected to the bridge rectifier circuit to maintain the voltage level of the conducting bridge rectifier circuit. The current phase timing detection circuit is electrically connected to the load circuit and the bridge rectifier circuit to detect a current signal on the bus line. The plurality of high-voltage side and low-voltage side driving circuits are electrically connected to the plurality of voltage level maintaining driving circuits, and generate at least one driving signal to the bridge rectifier circuit, so that the bridge rectifier circuit operates according to the at least one driving signal. The plurality of input voltage phase timing detection circuits are electrically connected to the bridge rectifier circuit and the input voltage to adjust the peak value of the input voltage. The monostable circuit receives a clock signal. The transistor continuity control circuit receives output signals from a plurality of input voltage phase timing detection circuits, monostable circuits, and current phase timing detection circuits to generate at least one logic control signal, so that the plurality of high-side and low-side drive circuits are based on At least one logic control signal is actuated, wherein the bridge rectifier circuit is actuated according to a plurality of driving signals generated by a plurality of high-voltage side and low-voltage side driving circuits.

As mentioned above, the rectifier circuit applied to various linear and non-linear inputs and loads of the present invention determines the voltage conducting phase of the input signal and the conducting phase of the current on the bus line at the same time to determine the switching element on the bridge rectifier circuit. On-time, therefore, while achieving high efficiency, the bridge rectifier circuit can be operated on various combinations of input signals of arbitrary waveforms and linear or non-linear circuits, further improving the efficiency of power supply use and reducing the complexity of circuit design. It can avoid malfunction of the circuit. In addition, the floating switching element driving circuit in the conventional technology must additionally provide a voltage source as a driving power source, but in the present invention, a built-in oscillator circuit or an external input clock signal is used to adjust the duty cycle through a monostable circuit. Driving an isolation transformer does not require an external power supply, so it can operate normally even when the input signal is AC, DC, or an arbitrary waveform with an extremely long period.

1‧‧‧Rectifier circuit applied to various linear and nonlinear inputs and loads

11‧‧‧Voltage level maintaining driving circuit

12‧‧‧Current phase timing detection circuit

13‧‧‧High-side and low-side drive circuits

14‧‧‧Input voltage phase timing detection circuit

141‧‧‧First input voltage phase timing detection circuit

142‧‧‧Second input voltage phase timing detection circuit

15‧‧‧monostable circuit

16‧‧‧ Transistor control circuit

17‧‧‧Load circuit

18‧‧‧ clock signal

19‧‧‧ Disable Circuit

Q1, Q2, Q3, Q4, Q5, Q6‧‧‧MOSFET transistors

Q7 ~ Q11‧‧‧Transistors

D1 ~ D13‧‧‧‧Diode

Vi‧‧‧ input voltage

V1, V2, V3, V4, V5‧‧‧ constant voltage

Vs‧‧‧input

Vgp, Vgn‧‧‧Logic control signal

Voltage extremes of VgsQ1, VgsQ2, VgsQ3, VgsQ4

Viload‧‧‧ output signal

VRVDN, VRVDL‧‧‧ output signal

AC +, V + ‧‧‧Positive terminal

AC-, V-‧‧‧ negative power terminal

R1, R7, R8, R9, R10, R13, R14, R15, R17 ~ R29, Rload‧‧‧ resistance

U1‧‧‧amplifier

U2‧‧‧ Comparator

U3, U4, U5‧‧‧Logic and gate

Cload, C2 ~ C7‧‧‧ capacitor

TR1, TR2‧‧‧ conversion circuit

Figure 1 is a block diagram of the rectifier circuit applied to various linear and non-linear inputs and loads according to the present invention; Figure 2A is a circuit diagram of an input voltage phase timing detection circuit; Figures 2B and 2C are input voltages. And timing diagram of voltage phase timing detection circuit output; Figure 3A is a circuit diagram of current phase timing detection circuit; Figures 3B and 3C are input signals, output signals and input of current phase timing detection circuit Timing diagram of voltage; Figure 4A is a logic circuit diagram of the transistor conduction control circuit; Figure 4B is a phase conduction timing diagram of each signal; Figures 5A and 5B are the high-voltage and low-voltage side drive circuits and voltage The circuit diagram and block diagram of the level maintaining drive circuit; and Fig. 5C is a timing diagram of the gate terminals of the logic control signal and the four MOSFET transistors of the rectifier circuit.

Please refer to FIG. 1, which is a block diagram of a rectifier circuit applied to various linear and non-linear inputs and loads according to the present invention. Rectifier circuit 1 applied to various linear and non-linear inputs and loads includes an input voltage Vi, a bridge rectifier circuit (composed of MOSFET transistors Q1, Q2, Q3, Q4 and diodes D1, D2, D3, D4), A load circuit 17, a plurality of voltage level maintaining driving circuits 11, a current phase timing detection circuit 12, a plurality of high-voltage and low-voltage side driving circuits 13, a plurality of input voltage phase timing detection circuits 14, and a monostable state The circuit 15 and a transistor turn-on control circuit 16. The bridge rectifier circuit is electrically connected to the input voltage Vi and receives the input voltage Vi. The load circuit 17 is electrically connected to a bridge rectifier circuit. The plurality of voltage level maintaining driving circuits 11 are electrically connected to the bridge rectifier circuit to maintain the voltage level of the conducting bridge rectifier circuit. The current phase timing detection circuit 12 is electrically connected to the load circuit 17 and the bridge rectifier circuit to detect a current signal on the bus line. The plurality of high-voltage side and low-voltage side driving circuits 13 are electrically connected to the plurality of voltage level maintaining driving circuits 11 and generate at least one driving signal to the bridge rectifier circuit, so that the bridge rectifier circuit operates according to the at least one driving signal. The plurality of input voltage phase timing detection circuits 14 are electrically connected to the bridge rectifier circuit and the input voltage Vi to adjust the peak value of the input voltage Vi. The monostable circuit 15 receives a clock signal 18. The transistor continuity control circuit 16 receives the output signals of a plurality of input voltage phase timing detection circuits 14, a monostable circuit 15, and a current phase timing detection circuit 12, to generate at least one logic control signal Vgp, Vgn, so that a plurality of high voltages The low-side and low-side drive circuits 13 operate according to at least one logic control signal Vgp, Vgn. The bridge rectifier circuit operates according to multiple drive signals generated by the plurality of high-side and low-side drive circuits 13.

The bridge rectifier circuit includes four MOSFETs and a diode in parallel with the four MOSFETs. The load circuit 17 includes a linear load circuit or a non-linear load circuit, which is illustrated by the resistor Rload and the capacitor Cload in FIG. 2A.

In the conventional circuit, only the signal of the input voltage Vi is detected. However, in the present invention, the current signal on the bus line is further detected. The current signal detected by the current phase timing detection circuit 12 is input to the transistor conduction control circuit 16 together with the input voltage signal detected by the plurality of input voltage phase timing detection circuits 14 and the signal output by the monostable circuit 15 to Generate logic control signals Vgp, Vgn.

Please refer to FIG. 2A, which is a circuit diagram of an input voltage phase timing detection circuit. In order to clearly understand the connection relationship between the input voltage phase timing detection circuit 14 and the input voltage Vi and the bridge rectifier circuit, the input voltage Vi and the bridge rectifier circuit are redrawn on the left in FIG. 2. The zener diodes connected in parallel with the respective MOSFET transistors Q1, Q2, Q3, and Q4 in the first figure are omitted, and the resistor R1 not shown in the first figure is shown in the second figure. The MOSFET gates of the plurality of input voltage phase timing detection circuits 14 are connected to a certain voltage V3, V5, and the drain terminals are respectively connected to both ends of the input voltage Vi, that is, the drain terminals of the first input voltage phase timing detection circuit 141 are connected to the inputs. The positive electrical terminal AC + of the voltage Vi and the drain terminal of the second input voltage phase timing detection circuit 142 are connected to the negative electrical terminal AC- of the input voltage Vi. Accordingly, after the on-voltages of the MOSFET transistors Q5 and Q6 are subtracted, the voltage can be taken out from the source terminal of the input voltage phase timing detection circuit 14 and output to the transistor conduction control circuit 16. In addition, the voltage phase timing detection circuit 14 takes the divided voltage from the source terminal and outputs the voltage to the transistor turn-on control circuit 16. However, its design is not limited to the design that must be divided, but can be based on the actual circuit design. Adjusted by resistors R7, R8, R9, R10. Furthermore, the circuit shown in the figure is only an example. It is not the design of the limited voltage phase timing detection circuit 14, but any circuit that can adjust the peak value of the input voltage Vi belongs to the scope of the voltage phase timing detection circuit 14, such as the voltage level. Voltage level shifting circuit.

Please refer to FIG. 2B and FIG. 2C, which are timing diagrams of output signals of the input voltage and voltage phase timing detection circuit. After the peak value of the input voltage Vi is adjusted by the voltage phase timing detection circuit 14, the input voltage Vi can be converted from a high voltage to a low voltage. In order to clarify the change of the waveform, the drawing is not drawn according to the size ratio. In addition, it can be seen from FIG. 2B that the input voltage Vi is not limited to a linear or non-linear signal, and includes a linear or non-linear arbitrary waveform voltage.

Please refer to FIG. 3A, which is a circuit diagram of a current phase timing detection circuit, and FIGS. 3B and 3C are timing diagrams of an input signal, an output signal, and an input voltage of the current phase timing detection circuit. The current phase timing detection circuit 12 is used to amplify the detected current signal. The signal at the input terminal Vs comes from a general transformer or resistance sensor signal, and is connected to a bridge rectifier circuit (see Figure 2A). The current is amplified by the amplifier U1. After the signal is compared with the voltages of the comparators U2 and V2, the output terminal outputs a signal of the voltage phase and the on-time to the transistor conduction control circuit 16. The current phase timing detection circuit 12 includes the resistors R13, R14, R15, R17, R18, the capacitor C2, and the constant voltages V1, V2, and V4. The connection relationship and the detailed operating principle are not detailed here. Among them, V + and V -Department of positive and negative electrical terminals. Similarly, the circuit in the figure is only an example, and is not a design of the limited current phase timing detection circuit 12, but any circuit that can amplify the current signal belongs to the category of the current phase timing detection circuit 12, such as a current detector .

Please refer to FIG. 4A, which is a logic circuit diagram of a transistor conduction control circuit. The transistor continuity control circuit 16 is composed of a plurality of logic AND gates U3 and U4, and receives the output signals VRVDN, VRVDL, signals of the monostable circuit 15 and the current phase timing detection circuit 12 of the input voltage phase timing detection circuit 14. The output signal Viload generates logic control signals Vgp and Vgn to the plurality of high-voltage and low-voltage driving circuits 13 so that the plurality of high-voltage and low-voltage driving circuits 13 act according to at least one logic control signal Vgp, Vgn.

FIG. 4B is a phase conduction timing diagram of each signal. After being input to the logic of the transistor conduction control circuit 16 and the gates U3 and U4, logic control signals Vgp and Vgn are generated. In addition, the monostable circuit 15 is input by a clock signal 18, which is a higher frequency (KHz) than the frequency (Hz) of other signals, so it is not shown in the figure. The clock signal 18 comes from a signal generated by a square wave oscillator circuit or a load circuit including a PWM signal. Since the duty cycle of the signal from an external source or the signal generated by the circuit itself is not fixed, the duty cycle of the signal can be adjusted to a fixed cycle by using the monostable circuit 15.

Please refer to FIG. 5A and FIG. 5B, which are a circuit diagram and a block diagram of a high-voltage side and a low-voltage side driving circuit and a voltage level maintaining driving circuit. The input terminals of the high-side and low-side drive circuits 13 receive logic control signals Vgp and Vgn generated by the transistor conduction control circuit 16 to turn on or off according to the logic control signals Vgp and Vgn. The plurality of voltage level maintaining driving circuits 11 are electrically connected to the gate terminals of the four MOSFET transistors Q1, Q2, Q3, and Q4 of the bridge rectifier circuit. The transistors Q1, Q2, Q3, and Q4 operate according to at least one driving signal generated by the plurality of high-side and low-side driving circuits 13, respectively.

Further, in the circuit diagram of FIG. 5A, the logic control signal Vgp is taken as the high signal level as an example. The high-side and low-side drive circuits 13 are turned on. The skilled artisan should be able to use the circuit diagram to And the connection relationship between the gate U5, the diodes D5 to D13, the transistors Q7 to Q11, the capacitors C3 to C7, and the resistors R19 to R29) can infer the operation of the high-voltage side and low-voltage side drive circuit 13 and will not be repeated here. The voltage level maintaining driving circuit 11 is used to maintain the level of the conduction signal, so that each voltage level maintaining driving circuit 11 corresponds to the MOSFET transistors Q1, Q2, Q3, and Q4 connected to the bridge rectifier circuit when they need to be turned on. For example, when the input signal Vi is a positive half cycle, the MOSFET transistors Q1 and Q4 are turned on, and when the input signal Vi is a negative half cycle, the MOSFET transistors Q2 and Q3 are turned on.

Figure 5C is the turn-on timing diagram of the gate extreme voltages VgsQ1, VgsQ2, VgsQ3, and VgsQ4 of the four MOSFET transistors Q1, Q2, Q3, and Q4 of the logic control signals Vgp, Vgn and the rectifier circuit. The MOSFET transistors Q1, Q2, Q3, and Q4 of the rectifier circuit are turned on only when the corresponding logic control signals Vgp and Vgn are turned on.

In addition, the high-voltage and low-voltage driving circuits 13 and the voltage level maintaining driving circuit 11 are coupled by, for example, transformer conversion circuits TR1 and TR2. Therefore, it is not necessary to provide additional power outside the circuit. Further, the logic control signal Vgp is taken as an example. After the logic control signal Vgp passes through the high-voltage and low-voltage drive circuits 13, the conversion circuit TR1 is driven, and the N1 side (the high-voltage and low-voltage drive circuits 13) of the self-conversion circuit TR1 is driven. Side) converts the signal to the N2 side (voltage level maintaining drive circuit 11 side), and uses this signal level to drive the connected MOSFET transistor Q1 of the bridge rectifier circuit, and the other end is a logic control signal Vgp that has not been converted by the conversion circuit TR1 Then, the MOSFET transistor Q4 connected to the bridge rectifier circuit is driven after the driving circuit 11 is maintained through the voltage level. Therefore, the present invention does not need to use a floating voltage supply as a power source for the driving bridge rectifier circuit, that is, it is not necessary to provide a driving power source on the transistors Q1 and Q2 sides.

Furthermore, the rectifier circuit applied to various linear and non-linear inputs and loads further includes a disable circuit 19, which is electrically connected to a plurality of high-side and low-side drive circuits 13, and receives the transistor conduction control circuit 16. At least one logic control signal Vgp, Vgn to generate at least one disable signal, so that the plurality of high-side and low-side drive circuits 13 stop operating according to at least one disable signal, thus avoiding the MOSFET transistor Q1 of the bridge rectifier circuit. When Q2, Q3, and Q4 receive external interference signals, the MOSFET transistors that do not need to be turned on are turned on, that is, short circuits between the MOSFET transistors Q1 and Q3 and the MOSFET transistors Q2 and Q4 are avoided. Therefore, the disable circuit 19 has the effect of protecting the circuit. Similarly, a skilled artisan should be able to infer the action of the disabling circuit 19 through the circuit diagram, and further determine whether the high-voltage and low-voltage side drive circuits 11 and 13 of its electrical connection are disabled. Here, No longer.

In summary, the rectifier circuit applied to various linear and non-linear inputs and loads of the present invention determines the phase of the voltage of the input signal and the phase of the current of the bus road at the same time to determine the switching element of the bridge rectifier circuit. On-time, therefore, while achieving high efficiency, the bridge rectifier circuit can be operated on various combinations of input signals of arbitrary waveforms and linear or non-linear circuits, further improving the efficiency of power supply use and reducing the complexity of circuit design. It can avoid malfunction of the circuit. In addition, the floating switching element driving circuit in the conventional technology must additionally provide a voltage source as a driving power source, but in the present invention, it is driven by a built-in oscillator circuit or an external input clock signal, which is adjusted by a monostable circuit. Cycle-driven isolation transformers do not require an external power supply, so they can operate normally even when the input signal is AC, DC, or arbitrary waveforms with extremely long periods.

Claims (8)

    A rectifier circuit applied to various linear and non-linear inputs and loads includes: an input voltage; a bridge rectifier circuit receiving the input voltage; a load circuit electrically connected to the bridge rectifier circuit; a plurality of voltage levels maintained The driving circuit is electrically connected to the bridge rectifier circuit to maintain a voltage level of conducting the bridge rectifier circuit; a current phase timing detection circuit is electrically connected to the load circuit and the bridge rectifier circuit to detect A current signal on a bus line; a plurality of high-voltage side and low-voltage side drive circuits are electrically connected to the plurality of voltage levels to maintain the drive circuit, and generate at least one drive signal to the bridge rectifier circuit, so that the bridge rectifier circuit Actuated according to the at least one driving signal; a plurality of input voltage phase timing detection circuits electrically connected to the bridge rectifier circuit and the input voltage to adjust a peak value of the input voltage; a monostable circuit to receive a clock signal ; And a transistor conduction control circuit, receiving the plurality of input voltage phase timing detection circuits, the monostable circuit, and the An output signal of one of the flow phase timing detection circuits generates at least one logic control signal, so that the plurality of high-voltage side and low-voltage side drive circuits act according to the at least one logic control signal; wherein the bridge rectifier circuit is based on the plurality of A plurality of driving signals generated by the high-side and low-side driving circuits act.         The rectifier circuit applied to various linear and non-linear inputs and loads as described in item 1 of the scope of the patent application, wherein the current phase timing detection circuit includes a current detector.         The rectifier circuit applied to various linear and non-linear inputs and loads as described in item 1 of the scope of patent application, wherein the input voltage includes a voltage of an arbitrary waveform.         The rectifier circuit applied to various linear and non-linear inputs and loads, as described in item 1 of the scope of the patent application, wherein the load circuit includes a linear load circuit or a non-linear load circuit.         The rectifier circuit applied to various linear and non-linear inputs and loads, as described in item 1 of the scope of the patent application, further includes a disable circuit that receives the at least one logic control signal of the transistor conduction control circuit to Generate at least one disable signal so that the plurality of high-side and low-side drive circuits stop operating according to the at least one disable signal.         The rectifier circuit applied to various linear and non-linear inputs and loads as described in item 1 of the scope of the patent application, wherein the bridge rectifier circuit includes four MOSFETs and a diode in parallel with the four MOSFETs.         The rectifier circuit applied to various linear and non-linear inputs and loads as described in item 6 of the scope of the patent application, wherein the plurality of voltage levels maintain the driving circuit electrically connected to the gate ends of the four MOSFETs, so that the four The MOSFET operates according to the at least one driving signal generated by the plurality of high-side and low-side driving circuits, respectively.         The rectifier circuit applied to various linear and non-linear inputs and loads, as described in item 1 of the scope of patent application, further includes a conversion circuit coupled to the plurality of high-voltage and low-voltage drive circuits and the plurality of voltage levels to maintain Drive circuit.