TW201824288A - Shift register - Google Patents

Abstract

A shift register comprises a first signal control circuit, a voltage boosting circuit, a driving circuit, a first pull down circuit, a second signal control circuit and a voltage stabilizing circuit. The first signal control circuit receives a first control signal and a second control signal and output a driving control signal. The voltage boosting circuit receives the first control signal, a third control signal, and a fourth control signal, and outputs the driving control signal. The driving circuit receives the driving control signal and outputs a driving signal. The first pull-down circuit receives a first clock signal and the driving signal. The second signal control circuit receives the drive control signal and the second clock signal and outputs a voltage regulation control signal. The voltage stabilizing circuit receives the voltage regulation control signal, the driving control signal and the driving signal.

Description

Shift register circuit

The present invention relates to a shift register circuit, and more particularly to a shift register circuit with increased driving capability.

The conventional display device includes a gate driving circuit. The gate driving circuit includes a plurality of shift register circuits. The shift register circuits are used to correctly output a plurality of driving signals to drive multiple rows of pictures in the display device. Vegetarian. However, due to the booming development of display device related technologies and consumer requirements for display device display capabilities, display devices already have high-resolution display capabilities, such as 4K resolution display device specifications. However, in order to achieve the effect of high resolution, the driving time of each column of pixels of the display device will be relatively reduced, which may easily cause pixels to write wrong display data, and then affect the quality of the display screen.

In order to solve the above-mentioned shortcomings, the present invention provides an embodiment of a shift register circuit. The shift register circuit includes a first signal control circuit, a booster circuit, a driving circuit, a first pull-down circuit, and a second signal. Control circuit and voltage regulator circuit. The first signal control circuit is configured to receive the first control signal and the second control signal and output a driving control signal. The boosting circuit is electrically coupled to the first signal control circuit, and is used for receiving the first control signal, the third control signal and the fourth control signal and outputting the driving control signal. The driving circuit is electrically coupled to the first signal control circuit and the booster circuit. The driving circuit is used to receive the driving control signal and output the driving signal. The first pull-down circuit is electrically coupled with the driving circuit, and is used for receiving the first clock signal and the driving signal. The second signal control circuit is used for receiving the driving control signal and the second clock signal and outputting the voltage stabilization control signal. The voltage stabilizing circuit is electrically coupled to the second signal control circuit. The voltage stabilizing circuit is used to receive the voltage stabilizing control signal, the driving control signal and the driving signal.

The shift register circuit of the present invention has the booster circuit, which can keep the driving circuit with a better driving ability after the driving circuit outputs the driving signal, so it can quickly and accurately maintain the driving signal at a relatively low level. The voltage level prevents the pixels corresponding to the driving signal from being turned on by mistake due to the instability of the driving signal and effectively maintains the excellent display picture quality. Therefore, the user has a better viewing effect when viewing the display picture.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with reference to preferred embodiments and the accompanying drawings.

Please refer to FIG. 1 first. FIG. 1 is a schematic diagram of an embodiment of a display device 10. The display device 10 is, for example, an electronic device such as a liquid crystal display. The display device 10 includes a data driver 11, a gate driver 12, and a plurality of pixel units 13. The data driver 11 is electrically coupled to the plurality of pixel units 13. The data driver 11 is used to receive a plurality of display data DSs to be displayed. And output to the corresponding display data lines D ₁ , D ₂ … D _M , and the display data lines D ₁ , D ₂ … D _M send data signals DS to the corresponding multiple pixel units 13, where M is not zero Positive integer. The gate driver 12 is electrically coupled to a plurality of pixel units 13. The gate driver 12 includes a plurality of shift register circuits. The gate driver 12 is used to generate multiple driving signals, as shown in FIG. 1. The signals G _N-2 , G _N-1 , G _N , G _{N + 1} … G _{N + P} , N and P are non-zero positive integers, and the gate driver 12 transmits the driving signal to the corresponding gate line The pixel unit 13 electrically coupled to the gate line decides whether to receive and display one of the display data lines D ₁ , D ₂ … D _M according to the driving signal.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of an embodiment of the shift register circuit 20 of the present invention. The shift register circuit 20 of the present invention can be adapted to the display device 10 described above, but is not limited thereto. The N-th stage shift register circuit 20 that outputs the N-th stage driving signal G _N will be described as an example. The shift register circuit 20 of FIG. 2 includes a first signal control circuit 21, a driving circuit 22, a booster circuit 23, a first pull-down circuit 24, a second signal control circuit 25, and a voltage stabilization circuit 26.

The first signal control circuit 21 is used to receive the control signal S1 and the control signal S2, and is used to output a driving control signal Q _N. The first signal control circuit 21 includes a transistor T1 and a transistor T2. The transistor T1 has a first terminal, a control terminal, and a second terminal. The first terminal and the control terminal of the transistor T1 receive the control signal S1 and the transistor T1. The second terminal is used to output a drive control signal Q _N. Transistor T2 has a first terminal, a control terminal, and a second terminal. The first terminal of transistor T2 is used to receive the driving control signal Q _N , the control terminal of transistor T2 is used to receive the control signal S2, and the third terminal of transistor T2 is The terminal receives a low voltage level VSS, which is, for example, a logic low potential.

The driving circuit 22 is electrically coupled to the first signal control circuit 21 and the boosting circuit 23. The driving circuit 22 is used to receive the driving control signal Q _N and the clock signal CK2, and output the current driving signal G _N. The driving circuit 22 includes a transistor T3. The transistor T3 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T3 is used to receive the clock signal CK2, and the control terminal of the transistor T3 is used to receive driving. The control signal Q _N. The second terminal of the transistor T3 is used to output the driving signal G _N. In addition, the transistor T3 further includes a parasitic capacitor C _P2 coupled between the first terminal and the control terminal and coupled to the first terminal. The parasitic capacitance C _P1 between the two terminals and the control terminal.

The booster circuit 23 is electrically coupled to the first signal control circuit 21 and the driving circuit 22. The booster circuit 23 is used to receive the control signal S1, the control signal S3 and the control signal S4. The booster circuit 23 includes a transistor T4, a transistor T5, a capacitor C1, and a capacitor C2. Transistor T4 has a first terminal, a control terminal, and a second terminal. The first terminal of transistor T4 receives the control signal S4, the control terminal of transistor T4 receives the drive control signal Q _N , the second terminal of transistor T4 and the capacitor C1 Electrically coupled. Transistor T5 has a first terminal, a control terminal, and a second terminal. The first terminal of transistor T5 receives the control signal S3. The control terminal of transistor T5 receives the control signal S1. The second terminal of transistor T5 is connected to capacitor C1 and the capacitor. C2 is electrically coupled. The capacitor C1 has a first terminal and a second terminal. The first terminal of the capacitor C1 is electrically coupled to the second terminal of the transistor T5, and the second terminal of the capacitor C1 is electrically coupled to the second terminal of the transistor T4. The capacitor C2 has a first terminal and a second terminal. The first terminal of the capacitor C2 is electrically coupled to the first signal control circuit 21 and the driving circuit 22 to output a driving control signal Q _N. The second terminal of the capacitor C2 is electrically connected to the power. The second terminal of the crystal T5 is electrically coupled. In this embodiment, the capacitance value of the capacitor C2 is greater than the capacitance C1.

The first pull-down circuit 24 is electrically coupled to the driving circuit 22. The first pull-down circuit 24 is used to receive the clock signal CK1 and decide whether to disable the driving signal G _N according to the clock signal CK1. The first pull-down circuit 24 includes a transistor T6. The transistor T6 has a first terminal, a control terminal, and a second terminal. The first terminal of the transistor T6 is electrically coupled to the second terminal of the transistor T3. The control terminal receives the clock signal CK1, and the second terminal of the transistor T6 is used to receive the above-mentioned low voltage level VSS.

The second signal control circuit 25 is used to receive the drive control signal Q _N and the clock signal CK2, and output the voltage stabilization control signal P _{N accordingly} . The second signal control circuit 25 includes a capacitor C3 and a transistor T9. The capacitor C3 has a first terminal and a second terminal. The first terminal of the capacitor C3 is used to receive the clock signal CK2, and the second terminal of the capacitor C3 is used to output the aforementioned signal. Voltage stabilization control signal P _N. Transistor T9 has a first terminal, a control terminal, and a second terminal. The first terminal of transistor T9 is used to receive the voltage-stabilizing control signal P _N , the control terminal of transistor T9 receives the drive control signal Q _N , and the first terminal of transistor T9 is The two terminals are used to receive the low voltage level VSS.

The voltage stabilization circuit 26 is electrically coupled to the second signal control circuit 25. The voltage stabilization circuit 26 is configured to receive the voltage stabilization control signal P _N , the drive control signal Q _N and the drive signal G _N. The voltage stabilizing circuit 26 includes a transistor T7 and a transistor T8. The transistor T7 includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor T7 is electrically coupled to the second terminal of the transistor T3. The control terminal of T7 receives the voltage stabilization control signal P _N , and the second terminal of the transistor T7 receives the low voltage level VSS. The transistor T8 includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor T8 receives the driving control signal Q _N , the control terminal of the transistor T8 receives the voltage stabilization control signal P _N , and the second terminal of the transistor T8 Receive low voltage level VSS.

Please refer to FIG. 3, which is a schematic diagram of a signal embodiment of the present invention. FIG. 3 includes a clock signal CK1, a clock signal CK2, a driving signal G _N-2 , a driving signal G _N-1 , a driving signal G _N , and a driving signal. G _{N + 1} and the driving signal G _{N + 2} and the driving control signal Q _N. FIG. 3 further includes potential changes of the node A and the node B in FIG. 2. The level transition time of the clock signal CK1 is earlier than the clock signal CK2, and the enabling start time of the clock signal CK1 is earlier than the clock signal CK2. The enabling periods of the clock signal CK1 and the clock signal CK2 do not overlap with each other. The driving signals are sequentially driven to each other, that is, the driving signals are converted from the disabled level to the enabled level according to their order. Taking this embodiment as an example, the order is the driving signal G _N-2 and the driving signal G in this order. _N-1, drive signals G _N, G _{N + 1} drive signals and drive signals G _{N + 2.} The level transition time of the drive signal G _N-2 is earlier than the level transition time of the drive signal G _N-1 , and the level transition time of the drive signal G _N-1 is earlier than the level transition time of the drive signal G _N. The drive signal The level transition time of G _N is earlier than the level transition time of the drive signal G _{N + 1} , and the level transition time of the drive signal G _{N + 1} is earlier than the drive signal G _{N + 2} . Drive signals G _N-1 during the enable partial period enabling _N-2 driving signals G overlapped, driving signals G _N actuation period can be partially overlapped with the period enabling drive signals G _N-1, the drive signals G _N The enabling period of ₊₁ partially overlaps the enabling period of the driving signal G _N , and the enabling period of the driving signal G _{N + 2} partially overlaps the enabling period of the driving signal G _{N + 1} . The following will cooperate with FIG. 2 and FIG. 3, and the control signal S1 may be the drive signal G _N-2 , the control signal S2 may be the drive signal G _{N + 2} , and the control signal S3 may be the N-1 level drive signal G _N-1 And the control signal S4 can be an embodiment of the _{N +} 1th stage driving signal G _{N + 1} to explain the operation method of the shift register circuit 20 embodiment of the present invention.

During the period t ₁ , the clock signal CK1 and the driving signal G _N-2 are enabled voltage levels, and the clock signal CK2, the driving signal G _N-1 , the driving signal G _{N + 1,} and the driving signal G _{N + 2} are disabled. Since the transistor T1 is turned on and the transistor T2 is turned off, the driving control signal Q _N is converted from the disabled voltage level to the voltage level V ₁ because the transistor T1 is turned on. Transistor T3 is turned on because the drive control signal Q _N is the voltage level V ₁ , but at the same time the clock signal CK2 is the disabled voltage level, and the drive signal G is the disabled voltage level because of the clock signal CK2. Transistor T4 is turned on because the drive control signal Q _N is at the first voltage level V ₁ , and at the same time the drive signal G _{N + 1} is at the disabled voltage level, so the node B is maintained at the voltage level V _B1 . Transistor T5 is turned on by the driving signal G _N-2 , and at the same time the driving signal G _N-1 is the disabled voltage level. Therefore, the node A is maintained at the voltage level V _A1 and the transistor T6 is turned on by the clock signal CK1. , Keep the driving signal G at the disabled voltage level. Transistor T9 is turned on because of the drive control signal Q _N. Therefore, the voltage stabilization control signal P _{N is} maintained at the disabled voltage level. Transistor T8 and transistor T7 are turned off accordingly.

At time t ₂ , the clock signal CK1, the driving signal G _N-1 and the driving signal G _N-2 are the enable voltage levels, and the clock signal CK2, the driving signal G _{N + 1} and the driving signal G _{N + 2} are Disabling voltage level. Transistor T1 and transistor T2 are off. Transistor T3 is turned on because of the driving control signal Q _N. Driving signal G is the disabling voltage level because of the clock signal CK2. The transistor T4 still maintains the node B at the voltage level V _B1 because the driving signal G _{N + 1} is the disabled voltage level. Transistor T5 remains on because of the driving signal G _N-2 , while the driving signal G _N-1 is the enable voltage level, the voltage level of node A is therefore converted to the voltage level V _A2 , and is coupled to the capacitor C2 to The driving control signal Q _{N is} , therefore, the potential of the driving control signal Q _N is converted from the voltage level V ₁ to the voltage level V ₂ . Transistor T6 is turned on by the clock signal CK1, and the driving signal G is maintained at the disabled voltage level. Transistor T9 remains on due to the drive control signal Q _N, and transistors T8 and T7 remain off.

At time t ₃ , the driving signal G _N-1 is the enable voltage level. The clock signal CK1, the clock signal CK2, the driving signal G _N-2 , the driving signal G _{N + 1,} and the driving signal G _{N + 2} are Disable voltage level. Transistor T1 and transistor T2 remain off, transistor T3 remains on, transistor T4 remains on, transistor T5 is turned off due to drive signal G _N-2 , transistor T6 is turned off due to clock signal CK1, and transistor T9 remains on Since the voltage-stabilizing control signal P _{N is} maintained at the disabled voltage level, the transistor T7 and the transistor T8 are kept off.

At time t ₄ , the clock signal CK2 and the driving signal G _N-1 are the enable voltage levels. The clock signal CK1, the driving signal G _N-2 , the driving signal G _{N + 1,} and the driving signal G _{N + 2} are Disable voltage level. Therefore, the transistor T1 and the transistor T2 remain off, and the transistor T3 remains on, and because the clock signal CK2 is an enable voltage level, the driving signal G _N is turned to the enable voltage level by the clock signal CK2. Transistor T4 remains on because of the drive control signal Q _N , node B remains at the voltage level V _B1 , and transistor T5 remains off. Transistor T6 is kept off because of the clock signal CK1, transistor T9 is kept on, and the voltage-stabilizing control signal _{PN is} maintained at the disabled voltage level, so transistor T7 and transistor T8 remain off. During this period, since the clock signal CK2 turns to the enable voltage level, the enable voltage level will be coupled to the control terminal of the transistor T3 through the parasitic capacitances C _P1 and C _{P2 of the} transistor T3, so the control signal is driven. Q _N will change from voltage level V ₂ to voltage level V ₃ during this period.

At time t ₅ , the clock signal CK2, the driving signal G _N and the driving signal G _{N + 1} are the enabled voltage levels, the clock signal CK1, the driving signal G _N-1 , the driving signal G _N-2 , and the driving signal. The signal G _{N + 2} is the disabled voltage level. Therefore, the transistor T1 and the transistor T2 are kept off, the transistor T3 is kept on, and the driving signal G _{N is} maintained at the enable voltage level. Transistor T4 remains on due to the drive control signal Q _N , transistor T5 remains off, and the drive signal G _{N + 1} is converted from the disabled voltage level to the enabled voltage level, so the potential at node B is changed from the voltage level V _{B1 is} converted to voltage level V _B2 , and the potential difference between voltage level V _B1 and voltage level V _B2 is coupled to node A through capacitor C1, so the potential of node A is converted from voltage level V _A2 to voltage level V _A3 , and the potential difference between the voltage level V _A2 and the voltage level V _A3 will be coupled to the driving control signal Q _N through the capacitor C2, so the potential of the driving control signal Q _N will be converted by the voltage level V ₃ Is the voltage level V ₄ . Transistor T9 is kept turned on because the drive control signal Q _{N is} kept on, and the steady-state control signal P _{N is} kept at the disabled voltage level, so transistor T7 and transistor T8 are kept off.

At time t ₆ , the driving signal G _{N + 1} is the enable voltage level. The clock signal CK1, the clock signal CK2, the driving signal G _N-1 , the driving signal G _N-2, and the driving signal G _{N + 2} are Disable voltage level. Therefore, transistor T1 and transistor T2 remain off and transistor T3 remains on, but at this time, the clock signal CK2 is converted from the enabled voltage level to the disabled voltage level, so the driving signal G _N is converted from the enabled voltage level To disable the voltage level, the driving control signal Q _N is converted from the voltage level V ₄ to the voltage level V ₅ . And since the drive control signal in the period t ₅ Q _N when drive signals G _{N + 1} is coupled to a higher voltage level V _4, thus in the period t ₆ when the driving control signal Q _N while the voltage level V ₄ Conversion It is the voltage level V ₅ , but the transistor T3 can still maintain a relatively good driving ability, so the driving signal G _N can be quickly converted from the enabled voltage level to the disabled voltage level. Transistor T4 remains on because of the drive control signal Q _N , power-saving B remains at voltage level V _B2 , and transistor T5 remains off. Transistor T6 remains off. Transistor T9 remains on because the drive control signal Q _N remains on, and the voltage stabilization control signal P _N remains on the disabled voltage level. Therefore, transistor T7 and transistor T8 remain off.

During the period t ₇ , the clock signal CK1, the driving signal G _{N + 1} and the driving signal G _{N + 2} are the enabled voltage levels, and the clock signal CK2, the driving signal G _N-1 and the driving signal G _N-2 are disabled. Energy voltage level. Transistor T1 remains off, transistor T2 is turned on due to the drive signal G _{N + 2} , and the drive control signal Q _{N is} therefore converted from the voltage level V5 to the disabled voltage level. Transistor T3, transistor T4, and transistor T5 are turned off. Transistor T6 is turned on due to the clock signal CK1, and the driving signal G _{N is} maintained at the disabled voltage level. Transistor T9 is turned off due to the drive control signal Q _N. At this time, since the clock signal CK2 is the disabled voltage level, the transistor T7 and the transistor T8 remain turned off.

At time t ₈ , the clock signal CK1 and the driving signal G _{N + 2} are the enable voltage levels, and the clock signal CK2, the driving signal G _N-1 , the driving signal G _N-2, and the driving signal G _{N + 1} are Disable voltage level. Transistor T1 remains off, and transistor T2 remains on due to the drive signal G _{N + 2} . Transistor T3, transistor T4, and transistor T5 are off. Node B is discharged because of the driving signal G _{N + 1.} Transistor T6 is kept on because of the clock signal CK1. Transistor T9 is turned off due to the drive control signal Q _N , and the clock signal CK2 is the disabled voltage level, so transistor T7 and transistor T8 remain off.

At time t ₉ , the clock signal CK1, the clock signal CK2, the driving signal G _N-2 , the driving signal G _N-1 , the driving signal G _{N + 1,} and the driving signal G _{N + 2} are the disabled voltage levels. Transistor T1, Transistor T2, Transistor T3, Transistor T4, and Transistor T5 are turned off. Transistor T6 is turned off because the clock signal CK1 is the disabled voltage level. Transistor T9 is turned off because of the drive control signal Q _N The clock signal CK2 is the disabled voltage level, so the transistor T7 and the transistor T8 remain off.

At time t ₁₀ , the clock signal CK2 is the enable voltage level. The clock signal CK1, the drive signal G _N-2 , the drive signal G _N-1 , the drive signal G _{N + 1,} and the drive signal G _{N + 2} are Disable voltage level. Transistor T1, Transistor T2, Transistor T3, Transistor T4, Transistor T5, and Transistor T6 are turned off. Transistor T9 is turned off due to the drive control signal Q _N. At this time, the clock signal CK2 is the enable voltage level. The voltage regulator control signal P _N is converted from the disabled voltage level to the enabled voltage level. Therefore, the transistor T7 and the transistor T8 are turned on, and the transistor T7 maintains the driving signal G _N at the disabled voltage level. The transistor T8 maintains the drive control signal Q _N at the disabled voltage level, and the shift register circuit 20 ends its operation in a single frame.

To sum up, the embodiment of the shift register circuit 20 proposed by the present invention can cause the drive control signal Q _{N to} be coupled to the higher voltage level V ₄ by the booster circuit 23 during the above-mentioned period t ₅ . At time t ₆ , although the driving control signal Q _{N is} converted to the voltage level V ₅ , the transistor T3 still maintains a relatively good driving ability, so the driving signal G _N can be quickly converted from the enabled voltage level to Disabling the voltage level effectively prevents the pixel unit 13 from being turned on by the driving signal at the wrong time, thereby maintaining the display image quality of the display device 10 and improving the viewing experience of the viewer.

Although the present invention has been disclosed as above by way of example, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

10‧‧‧ display device

11‧‧‧Data Drive

12‧‧‧Gate driver

13‧‧‧ Pixel Unit

20‧‧‧shift register circuit

21‧‧‧The first signal control circuit

22‧‧‧Drive circuit

23‧‧‧Boost circuit

24‧‧‧First pull-down circuit

25‧‧‧Second signal control circuit

26‧‧‧Regulator

S1, S2, S3, S4‧‧‧ Control signals

T1, T2, T3, T4, T5, T6, T7, T8, T9‧‧‧ transistors

C1, C2, C3‧‧‧ capacitors

C _P1 , C _P2 ‧‧‧ Parasitic capacitance

CK1, CK2‧‧‧clock signal

VSS‧‧‧ Low Voltage Level

Q _N ‧‧‧Drive control signal

P _N ‧‧‧Regulatory control signal

DS‧‧‧ Display data

D ₁ , D ₂ , D _M ‧‧‧ Display data line

G _N-2 , G _N-1 , G _N , G _{N + 1} , G _{N + 2} , G _{N + P} ‧‧‧ drive signals

A, B‧‧‧ nodes

FIG. 1 is a schematic diagram of an embodiment of a display device. FIG. 2 is a schematic diagram of an embodiment of a shift temporary storage circuit according to the present invention. FIG. 3 is a schematic diagram of a signal embodiment of the present invention.

Claims (9)

A shift register circuit includes: a first signal control circuit for receiving a first control signal and a second control signal and outputting a driving control signal; a booster circuit for controlling the first signal The circuit is electrically coupled, the booster circuit is used to receive the first control signal, a third control signal and a fourth control signal and output the driving control signal; a driving circuit, the first signal control circuit and the The booster circuit is electrically coupled, the driving circuit is used to receive the driving control signal and output a driving signal; a first pull-down circuit is electrically coupled to the driving circuit, and is used to receive a first clock signal and The driving signal; a second signal control circuit for receiving the driving control signal and a second clock signal and outputting a voltage stabilization control signal; and a voltage stabilization circuit electrically coupled to the second signal control circuit The voltage stabilizing circuit is used to receive the voltage stabilizing control signal, the driving control signal and the driving signal. The shift register circuit according to claim 1, wherein the first signal control circuit includes: a first transistor having a first terminal, a control terminal, and a second terminal; The first terminal and the control terminal of a transistor receive the first control signal, and the second terminal of the first transistor outputs the driving control signal; and a second transistor, the second transistor has a A first terminal, a control terminal, and a second terminal; the first terminal of the second transistor is electrically coupled with the second terminal of the first transistor; the control terminal of the second transistor is used for The second control signal is received, and the second terminal of the second transistor is used to receive a low voltage level. The shift register circuit according to claim 1, wherein the boost circuit includes: a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor Electrically coupled with the first signal control circuit and the driving circuit; a first transistor having a first terminal, a control terminal and a second terminal, the first terminal of the first transistor receiving the A third control signal, the control terminal of the first transistor receives the first control signal, the second terminal of the first transistor is electrically coupled to the second terminal of the first capacitor; a second capacitor Has a first terminal and a second terminal, the first terminal of the second capacitor is electrically coupled to the second terminal of the first transistor; and a second transistor having a first terminal Terminal, a control terminal and a second terminal, the first terminal of the second transistor is used to receive the fourth control signal, the control terminal of the second transistor is used to receive the drive control signal, the first The second terminal of the two transistors is electrically coupled to the second terminal of the second capacitor. The shift register circuit according to claim 3, wherein a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor. The shift register circuit according to claim 1, wherein the driving circuit includes a first transistor having a first terminal, a control terminal, and a second terminal. The first terminal is used to receive the second clock signal, the control terminal of the first transistor is used to receive the driving control signal, and the second terminal of the first transistor is used to output the driving signal. The shift register circuit according to claim 1, wherein the first pull-down circuit includes a first transistor having a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is electrically coupled to the driving circuit, the control terminal of the first transistor is used to receive the first clock signal, and the second terminal of the first transistor is used to receive a low voltage. Voltage level. The shift register circuit according to claim 1, wherein the second signal control circuit includes: a first capacitor having a first terminal and a second terminal, the first capacitor One end is used to receive the second clock signal, the second end of the first capacitor is used to output the voltage stabilization control signal; and a first transistor having a first terminal, a control terminal, and a first Two terminals, the first terminal of the first transistor and the second terminal of the first capacitor are electrically coupled, the control terminal of the first transistor is used to receive the driving control signal, and the first transistor The second terminal is used to receive a low voltage level. The shift register circuit according to claim 1, wherein the voltage stabilizing circuit includes: a first transistor having a first terminal, a control terminal, and a second terminal, the first circuit The first terminal of the crystal is electrically coupled to the first signal control circuit, the driving circuit, and the booster circuit. The control terminal of the first transistor is used to receive the voltage stabilization control signal. The first transistor The second terminal is used for receiving a low voltage level; and a second transistor having a first terminal, a control terminal and a second terminal, the first terminal of the second transistor and the driver The circuit is electrically coupled, the control terminal of the second transistor is used to receive the voltage stabilization control signal, and the second terminal of the second transistor is used to receive the low voltage level. The shift register circuit according to claim 1, wherein the level change time of the first control signal is earlier than the level change time of the third control signal and the level change of the third control signal The time is earlier than the level change time of the drive signal, the level change time of the drive signal is earlier than the level change time of the fourth control signal, and the level change time of the fourth control signal is earlier than the second control signal. The level changes time.