TW201821999A - Switch system - Google Patents

Abstract

A switch system is provided. The switch system comprises a first multiplexer and a Baseboard Management Controller (BMC). The first multiplexer is coupled to a fist Electrically-Erasable Programmable Read-Only Memory (EEPORM). The BMC transmits a first control signal to the first multiplexer by a first multiplexer control channel. Wherein, the first control signal controls the first multiplexer coupling to a first Serial Peripheral Interface (SPI) bus. The BMC transmits a first system parameter to the first multiplexer by the fist SPI bus. The first multiplexer writes the first system parameter by a second SPI bus to the fist EEPROM.

Description

Exchanger system

The present invention relates to an exchanger system and a method of operating the same, and more particularly to an exchanger system using a multiplexer and a method of operating the same.

In general, the traditional switch system needs to wait until after entering the operating system to obtain relevant information through the interface of the operating system, and then through the Peripheral Component Interconnect Express (PCIe) bus to the relevant data. Transfer to the corresponding switch, and finally the system must be restarted to complete all relevant settings.

However, after the traditional switch system writes information to the EEPROM through the PCIe bus, it must wait for the reboot time, and after restarting, it needs to be loaded again into the operating system, so the user needs to wait for the boot time. It is time consuming. In addition, when the PCIe signal is weak and the PCIe communication capability is poor, the information cannot be completely written into the EEPROM. Therefore, how to provide a switch system to efficiently complete the relevant settings before the boot process ends. And reducing the waiting time for rebooting has become one of the urgent problems in the field.

In order to solve the above problems, an aspect of the present invention provides a switch system including a first multiplex control channel, a first electronic erasable rewritable read-only memory, a first sequence peripheral interface bus, A second sequence of peripheral interface busbars, a first multiplexer, and a baseboard management controller. The first multiplexer is coupled to the first electronic erasable rewritable read-only memory, and is selectively electrically coupled to the first sequence peripheral interface bus. The substrate management controller is electrically coupled to the first multiplex control channel and the first multiplexer, and transmits a first control signal to the first multiplexer through the first multiplex control channel, where the first control signal is used Controlling the first multiplexer to be electrically coupled to the first sequence peripheral interface, and the substrate management controller transmits a first system parameter to the first multiplexer through the first sequence peripheral interface bus; wherein, the first The multiplexer writes the first system parameter into the first electronic erasable rewritable read-only memory through the second sequence peripheral interface bus.

In summary, after the switch system and the switch method shown in the present invention are activated by the system, the baseboard management controller is also ready, even before the switch is fully started, the baseboard management controller can The parameters are written to the corresponding switch through the transmission path provided by the multiplexer. Therefore, before the boot process ends, the switch system can configure the relevant settings of the switches, thereby completing the process of the present invention. It is no longer necessary to load the operating system multiple times to complete the setup, so the effect of saving the boot time can be achieved. In addition, the substrate management controller can effectively adjust the signal strength of the transmitted data or the bandwidth interface for different line requirements, and provide an optimized transmission mode of the signal.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms "first", "second", etc., used herein are not intended to refer to the order or order, nor are they intended to limit the invention, only to distinguish between elements or operations described in the same technical terms. Only. Please refer to FIG. 1. FIG. 1 is a schematic diagram of an exchanger system 100 according to an embodiment of the invention.

In one embodiment, the switch system 100 includes a processing unit 10, a Peripheral Component Interconnect Express Switch (PCIe Switch) 20, a switch PEX1~PEX3, and an electronic erasable rewritable read-only memory. (Electrically-Erasable Programmable Read-Only Memory, EEPORM) ER1~ER3 and port PT1~PT6. In an embodiment, the processing unit 10 is configured to process various operations, and may be implemented as a volume circuit such as a micro control unit, a microprocessor, a digital signal processor, or a special application integrated circuit. (application specific integrated circuit, ASIC) or logic circuit. In one embodiment, the fast peripheral component interconnect switch 20 can be a switch that includes a PCIe interface. In one embodiment, the switches PEX1 to PEX3 are, for example, those of the PEX 9797 manufactured by PLX Technologies.

In one embodiment, as shown in FIG. 1, the processing unit 10 is coupled to the fast peripheral component interconnect switch 20 by a PCIe bus bar La1. The fast peripheral component interconnection switch 20 is connected to the switches PEX1, PEX2, and PEX3 via PCIe bus bars La2, La3, and La4, respectively. The switches PEX1, PEX2, and PEX3 are connected to the electronic erasable rewritable read-only memory ER1, ER2, and ER3 by Serial Peripheral Interface (SPI) bus bars Ls1, Ls2, and Ls3, respectively. The switch PEX1 is connected to the ports PT1 and PT2 through the PCIe bus bars La5 and La6 respectively. The switch PEX2 is connected to the ports PT3 and PT4 through the PCIe bus bars La7 and La8 respectively. The switch PEX3 is connected to the bus bar La9 through the PCIe bus. La10 is connected to the ports PT5 and PT6, respectively. In one embodiment, the ports PT1~PT6 are respectively connected to the external server (or other devices) S1~S6 by wireless (or wired) communication links Lb1~Lb6.

Referring to FIG. 2, FIG. 2 is a flow chart showing a method 200 of operating the switch system 100 according to an embodiment of the invention. The components described in the method of operation of the exchanger system 200 can be implemented by the exchanger system 100 of FIG.

In step S210, a power supply button on a motherboard is triggered to activate the switch system 100. In one embodiment, the user can press the power button of the switch system 100 to activate the switch system 100. In another embodiment, the user can press the power button on the server housing that is electrically coupled to the switch system 100 to activate the switch system 100.

In step S220, the switch system 100 loads a Basic Input/Output System (BIOS) to execute a boot process. In one embodiment, when the power button of the switch system 100 is pressed, the switch system 100 loads the basic input output system to perform the boot process.

In step S230, the switch system 100 loads the operating system. After the switch system 100 is loaded into the operating system, the switches PEX1~PEX3 can respectively transmit the respective current setting data to the fast peripheral component interconnection switch 20 through the PCIe bus bars La2~La4, and the fast peripheral components are interconnected and exchanged. The device 20 transmits this current setting information to the processing unit 10.

In an embodiment, the current setting information includes system parameters added or changed by the user during the booting process, wherein the current setting information includes, for example, a connection port position of the switches PEX1~PEX3, a connection current setting, and a pin. Set (pin-strap) information, interface card to the main server or terminal server, etc.

In step S240, the processing unit 10 determines whether the initial setting information needs to be modified according to the current setting information. If the processing unit 10 determines that the initial setting information needs to be modified, the process proceeds to step S250. If the processing unit 10 determines that the initial setting information is not required to be modified, the process proceeds to step S280, and the normal boot process is entered in step S280.

In an embodiment, when the processing unit 10 determines that the current setting information from each of the switches PEX1 P PEX3 is inconsistent with the initial setting information of the switch system 100, it is determined that the current setting information needs to be modified.

In another embodiment, the initial setting information is, for example, setting information that is burned in the electronic erasable rewritable read-only memory when the switch system 100 is shipped from the factory. On the other hand, the user enters in the switch system 100. After the operating system, you can adjust the parameters or add a new configuration method to generate the current setting information. The content of the current setting information may include definitions: the ports PT1~PT3 are set to be connected to the host server S1~S3 respectively, and the ports PT4~PT6 are set to be respectively connected to the terminal server ( End server) is connected to the external server S4~S6.

When the processing unit 10 knows that the switch system 100 receives the current setting information, it determines that the switch system 100 is set according to the current setting information, and therefore proceeds to step S250.

In step S250, the processing unit 10 transmits the current setting information to the fast peripheral component interconnection switch 20 through the PCIe bus bar La1, and the fast peripheral component interconnection switch 20 transmits the current setting information according to the content of the current setting information. Go to the corresponding switch (such as switch PEX1).

In an embodiment, the current setting information transmitted by the processing unit 10 through the PCIe bus line La1 includes the switch position or number corresponding to the current setting information, so that the fast peripheral component interconnection switch 20 can transmit the corresponding information. According to the switch location or numbered PCIe bus (such as PCIe bus La2), the current setting information is immediately transmitted to the switch (such as switch PEX1).

In step S260, the current setting information is written into the electronic erasable rewritable read-only memory (such as an electronic device) through a serial peripheral interface bus (such as the serial peripheral interface bus Ls1) by an exchange (such as the switch PEX1). Erase can be rewritten in read-only memory ER1).

Thereby, the processing unit 10 transmits the contents of the electronic erasable rewritable read-only memory ER1, ER2, ER3 through the docking with the switches PEX1 P PEX3.

In step S270, the switch system 100 is restarted, and steps S220-S230 are sequentially executed to enter the operating system again, and the read-only memory can be rewritten according to the electronic erasing type (such as the electronic erasable rewritable read-only memory). The current setting information in ER1) is set to start the switch system 100.

It can be seen from the above that when the switch system 100 is powered on, the processing unit 10 needs to wait until after entering the operating system, obtain the current setting information through the interface of the operating system, and then transmit the current setting information to the PCIe bus (such as the PCIe bus La2). In the corresponding switch (such as the switch PEX1), the corresponding switch PEX1 transmits the current setting information to the electronic erasable rewritable read-only memory through the sequence peripheral interface bus (such as the sequence peripheral interface bus Ls1). (such as electronic erasing rewritable read-only memory ER1). Finally, after the switch system 100 is restarted and the operating system is re-entered, the processing unit 10 can obtain the current setting information from the electronic erasable rewritable read-only memory ER1, and apply the current setting information to the switch system 100. In each device.

However, in the above example, after the switch system 100 writes information to the electronic erasable rewritable read-only memory ER1 by the serial peripheral interface bus Ls1 (step S260), it must wait for the time to restart the switch system ( Step S270), and after restarting, the BIOS and the operating system need to be loaded again (steps S220-S230) to reset the system. In other words, the operation method 200 loads at least two operating systems during the entire booting process to apply all current setting information. Therefore, the boot time that the user needs to wait is more time consuming. In addition, when the PCIe bus La2 signal is weak, and the PCIe bus La2 communication capability is poor, the information cannot be completely written into the electronic erasable rewritable read-only memory ER1.

Accordingly, the following provides a switch system 300 and its method of operation 400 that can more efficiently complete the relevant settings prior to the end of the boot process, and can reduce the wait for reboot time.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of an exchanger system 300 according to an embodiment of the invention. The switch system 300 of FIG. 3 is different from the switch system 100 of FIG. 1 in that the switch system 300 of FIG. 3 further includes a Baseboard Management Controller (BMC) 30 and a multiplexer MUX1. .

In an embodiment, the switch system 300 of FIG. 3 may include a plurality of multiplexers MUX1 M MUX3. In one embodiment, the multiplexer MUX2 is coupled to the switch PEX2 and the electronic erasable rewritable read-only memory ER2, and the multiplexer MUX3 is coupled to the switch PEX3 and the electronic erasable rewritable read-only memory. ER3.

In one embodiment, the multiplexer MUX1 is coupled to the switch PEX1 through the sequence peripheral interface bus Ls10, and the multiplexer MUX2 is coupled to the switch PEX2 through the serial peripheral interface bus Ls20, and the multiplexer MUX3 is transmitted through the sequence peripheral interface. The bus bar Ls30 is coupled to the switch PEX3.

In one embodiment, the switch system 300 further includes a processing unit 10, a fast peripheral component interconnect switch 20, switches PEX1~PEX3, ports PT1~PT6, and external servers S1~S6. The coupling and operation methods of these components are similar to those of Figure 1, and therefore will not be described here.

In one embodiment, the multiplexer MUX1 is coupled to the electronic erasable rewritable read-only memory ER1 through the serial peripheral interface bus Ls11, and the substrate management controller 30 is configured to transmit through the multiplex control channel (Multiplexer control channel). Control signal Cs1 to multiplexer MUX1. The control signal Cs1 is used to control the multiplexer MUX1 to be electrically coupled to the serial peripheral interface bus S1. For example, when the terminal c of the multiplexer MUX1 is connected to the terminal b, the control signal Cs1 can be controlled. The multiplexer MUX1 is switched to connect the endpoint c to the endpoint a, so that the multiplexer MUX1 is electrically connected to the sequence peripheral interface bus Sp1.

Next, the substrate management controller 30 transmits a first system parameter to the multiplexer MUX1 through the sequence peripheral interface bus S1, and the multiplexer MUX1 writes the first system parameter to the electronic erasable rewritable through the serial peripheral interface bus Ls11. Read memory ER1.

In an embodiment, the multiplexers MUX2 and MUX3 also include endpoints a~c, which operate in a similar manner to the multiplexer MUX1, and therefore will not be repeatedly described herein.

In one embodiment, the substrate management controller 30 transmits the control signal Cs3 to the multiplexer MUX2 through the second multiplex control channel, and the control signal Cs3 controls the multiplexer MUX2 to be electrically coupled to the serial peripheral interface bus S3. Then, the substrate management controller 30 transmits a second system parameter to the multiplexer MUX2 through the sequence peripheral interface bus bar Sp3, and the multiplexer MUX2 transmits the second system parameter to the electronic erasable rewritable read-only through the sequence peripheral interface bus bar Ls21. Memory ER2.

In one embodiment, the substrate management controller 30 transmits the control signal Cs5 to the multiplexer MUX3 through the third multiplex control channel, and the control signal Cs5 controls the multiplexer MUX3 to be electrically coupled to the serial peripheral interface bus S5. Then, the substrate management controller 30 transmits a second system parameter to the multiplexer MUX3 through the sequence peripheral interface bus bar Sp5, and the multiplexer MUX3 transmits the second system parameter to the electronic erasable rewritable read-only through the sequence peripheral interface bus bar Ls31. Memory ER3.

Next, the processing unit 10 loads the basic input/output system, and the basic input/output system causes the switch PEX1 to pass through the multiplexer MUX1 to read the first system parameter in the electronic erasable rewritable read-only memory ER1, and the switch PEX1 At least one set value is set according to the first system parameter, wherein at least one set value is, for example, connection related information of the connection port PT1 to the external device.

Referring to FIG. 4, FIG. 4 is a flow chart showing a method 400 of operating the switch system 300 according to an embodiment of the invention.

In step S410, a power supply button on a motherboard is triggered to activate the switch system 300. In one embodiment, the user can press the power button of the switch system 300 to activate the switch system 300. In another embodiment, the user can press the power button on the server housing that is electrically coupled to the switch system 300 to activate the switch system 300. In one embodiment, after the switch system 300 is activated, the baseboard management controller 30 is also activated simultaneously.

In one embodiment, after the switch system 300 is activated, the baseboard management controller 30 is ready to receive or transmit data. For example, the substrate management controller 30 can receive signals from various devices in the startup switch system 300.

In step S420, the substrate management controller 30 transmits the first system parameter to the multiplexer MUX1 via the sequence peripheral interface bus S1.

More specifically, the substrate management controller 30 first transmits the control signal Cs1 to the multiplexer MUX1 through the multiplex control channel, and the control signal Cs1 is used to control the multiplexer MUX1 to be electrically coupled to the serial peripheral interface bus S1, for example, The control signal Cs1 can switch the multiplexer MUX1 to connect the endpoint c with the endpoint a, whereby the baseboard management controller 30 can transmit the first system parameter to the multiplexer MUX1 via the sequence peripheral interface bus Sp1.

In an embodiment, the first system parameter includes a connection port position of the switch PEX1, a connection port setting, a pin setting information, or a connection port connection server information, and the information may be stored in the substrate management in advance. The storage device of the controller 30 is stored in another storage device. In an embodiment, when the switch system 300 is turned on, the substrate management controller 30 first reads the preset values of the various devices by the electronic erasable rewritable read-only memory ER1, and then adjusts according to the user's needs. These preset values are thereby used to generate the first system parameter.

In step S430, the multiplexer MUX1 writes the first system parameter to the electronic erasable rewritable read-only memory ER1 by the sequence peripheral interface bus Ls11.

Thereby, the switch system 300 can utilize the first system parameter to be written into the electronic erasable rewritable read-only memory when the substrate management controller 30 is ready after the power is turned on and the operating system is not loaded yet. The body ER1 enables the switch PEX1 to directly read the first system parameter located in the electronic erasable rewritable read-only memory ER1 in a subsequent step (such as step S440) to perform setting, so that the switch system 300 The switch PEX1 has completed the setup before all power-on steps have been completed.

In step S440, the processing unit 10 loads the basic input/output system, and the basic input/output system causes the switch PEX1 to set at least one set value according to the first system parameter.

More specifically, the substrate management controller 30 can transmit another control signal (eg, a second control signal) to the multiplexer MUX1 through the multiplex control channel. The other control signal (for example, the second control signal) is used to control the multiplexer MUX1 to be electrically coupled to the switch PEX1.

For example, when the endpoint c in the multiplexer MUX1 is connected to the endpoint a, the other control signal (for example, the second control signal) can control the multiplexer MUX1 to switch to the endpoint c to connect with the endpoint b, so that The switch MUX1 is switched to be electrically connected to the switch PEX1, so that the switch PEX1 can read the first system parameter via the multiplexer MUX1 to the electronic erasable rewritable read-only memory ER1, and according to the first system parameter setting At least one set value.

Thereby, the relevant settings of the switch PEX1 have been completed before the processor 10 has loaded the operating system.

In some embodiments, the processing unit 10 is coupled to the integrated circuit bus switch 40 by the PCIe bus bar La1, and the integrated circuit bus bar switch 40 is coupled to the switch PEX1 by the PCIe bus bar La2; When the substrate management controller 30 sends another control signal (for example, the second control signal) to control the multiplexer MUX1 to be electrically coupled to the switch PEX1, the switch PEX1 passes through the multiplexer MUX1 to obtain an electronic erase type. Rewriting the first system parameter stored in the read-only memory ER1, and setting at least one set value according to the first system parameter, or returning the first system parameter to the integrated circuit sink by the PCIe bus bar La2 The bank switch 40, the integrated circuit bus switch 40, transmits the first system parameters back to the processing unit 10.

In step S450, the switch system 300 loads the operating system. For example, the switch system 300 loads the operating system through the processing unit 10.

In step S460, the normal booting process is entered. For example, the switch system 300 executes the operating system through the processing unit 10.

In addition, the operation methods of the multiplexers MUX2 and MUX3 are similar to those of the multiplexer MUX1, and thus the description thereof will not be repeated here.

It can be seen from the above that after the switch system 300 is started, the substrate management controller 30 is simultaneously started, and then the basic input/output system is loaded, and the substrate management controller 30 is ready, the substrate management controller 30 can directly Through the multiplexer (such as multiplexer MUX1), the system parameters (such as the first system parameters) are written to the corresponding switch (such as the switch PEX1) electronically erasable rewritable read-only memory (such as electronic erase) The rewritable read-only memory ER1). Then, after the switch PEX1 is ready, the first system parameter in the electronic erasable rewritable read-only memory ER1 can be read and set, and after the setting is completed, the operating system is entered.

In other words, since the substrate management controller 30 is ready at a very fast speed after the switch system 300 is activated, it can be directly used by the substrate before the switch PEX1 and/or the processing unit 10 has not been fully activated. The management controller 30 writes the system parameters to the electronic erasable rewritable read-only memory ER1 corresponding to the corresponding switch PEX1 through the multiplexer MUX1. Thereby, when the switch PEX1 is ready, the first system parameter in the electronic erasable rewritable read-only memory ER1 can be read to complete the setting of the switch PEX1 according to the first system parameter more quickly.

In addition, the switch system 300 only needs to be loaded once in the operating system, and it is not necessary to first enter the operating system to write information, and then spend time waiting for the reboot and reloading the operating system. In other words, the switch system 300 only needs to load the operating system once, and the relevant settings of the respective switches can be configured before the booting process ends. Therefore, the switch system 300 can save time for booting.

It should be noted that the switch system 300 is not limited to including the switches PEX1~PEX3, and the number of switches can be set according to the actual application. In one embodiment, the switch system 300 can include nine switches, for example, electrically connecting the switches PEX1~PEX3 with another six switches, and each of the six switches and their multiplexers and their electronic wipes The divide-type rewritable read-only memory is electrically coupled, and the coupling mode switches PEX1~PEX3 are the same.

In an embodiment, the substrate management controller 30 shown in FIG. 3 is further configured to analyze system information. When the substrate management controller 30 determines that one of the system information transmission rates is less than a transmission rate threshold, the substrate management controller 30 transmits a transmission adjustment signal to the multiplexer MUX1, and the multiplexer MUX1 transmits the transmission adjustment signal to the electronic erasable rewritable read-only memory ER1, and controls the multiplex when another control signal (such as the second control signal) When the switch MUX1 is electrically coupled to the switch PEX1, the transmission adjustment signal sent by the baseboard management controller 30 can be transmitted to the switch PEX1 through the multiplexer MUX1, so that the switch PEX1 adjusts the signal according to the transmission. A document. The system information may be setting related information from each device of the switch system 300.

In an embodiment, the switch PEX1 can be coupled to other switches. For example, switch PEX1 can be coupled to switch PEX3, which can be used to receive data from one of switches PEX1. On the other hand, the switch PEX3 can also be coupled to a slot. The slot can include multiple ports (such as ports PT5 and PT6), and the ports PT5 and PT6 are used respectively. The external server (such as external server S5 and external server S6) is connected. The external servers S5 and S6 can exchange data with the switch system 300 through the corresponding ports PT5 and PT6.

In one embodiment, the switch system 300 can have multiple slots, and the slots are divided into high-speed bandwidth slots and low-speed bandwidth slots according to the bandwidth of each slot. Among them, the high speed bandwidth slot and the low speed bandwidth slot are defined by the relative bandwidth in multiple slots.

For example, the ports 埠1 and PT2 in FIG. 3 are located in the high-speed bandwidth slot, and the ports PT5 and PT6 are located in the low-speed bandwidth slot, and the ports PT1 and PT5 are connected to a specific external server. When the baseboard management controller 30 determines that a certain piece of data is designated to be transmitted to a specific external server by the switch PEX3, and the transmission rate during transmission is less than a transmission rate threshold, the baseboard management controller 30 can transmit a transmission. The signal is adjusted to the switch PEX3, and the data is designated to be sent to the switch PEX1 via the switch PEX3, and then sent to the port PT1 by the switch PEX1 through the PCIe bus bar La5. Since the port PT1 is located in the high speed bandwidth slot, this data can be quickly sent to the specific external server via the communication link Lb1.

In an embodiment, the substrate management controller 30 is further configured to analyze system information. When the substrate management controller 30 determines that one of the signal strength parameters in the system information is less than a signal strength threshold, the substrate management controller 30 transmits an intensity adjustment. In the signal-to-multiplexer MUX1, the multiplexer MUX1 transmits the intensity adjustment signal to the electronic erasable rewritable read-only memory ER1, and when another control signal (such as the second control signal) controls the multiplexer MUX1 to switch to When the switch PEX1 is electrically coupled, the strength adjustment signal is transmitted to the switch PEX1 through the multiplexer MUX1, so that the switch PEX1 adjusts the signal according to the strength to transmit a data. Thereby, in the signal transmission process, if the signal is weakened, the switch PEX1 can enhance the strength of the transmitted signal to deliver the correct data.

In summary, the switch system shown in the present invention and its operation method are also ready after the system is started, and the baseboard management controller can put the system even before the switch is fully started. The parameters are written to the corresponding switch through the transmission path provided by the multiplexer. Therefore, before the boot process ends, the switch system can configure the relevant settings of the switches, thereby completing the process of the present invention. It is no longer necessary to load the operating system multiple times to complete the setup, so the effect of saving the boot time can be achieved. In addition, the substrate management controller can effectively adjust the signal strength of the transmitted data or the bandwidth interface used for different line requirements, thus providing an optimized transmission mode of the signal.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100, 300‧‧‧ exchanger system

200, 400‧‧‧ methods of operation

10‧‧‧Processing unit

20‧‧‧Fast Peripheral Component Interconnect Switch

PT1~PT6‧‧‧Connector

S1~S6‧‧‧ external server

S210~S280, S410~

S460‧‧‧ steps

30‧‧‧Base Management Controller

ER1~ER3‧‧‧Electronic erasable rewritable read-only memory

PEX1~PEX3‧‧‧ exchanger

MUX1~MUX3‧‧‧

La1~La10‧‧‧PCIe bus

Lb1~Lb6‧‧‧Communication link

Sp1, Sp3, Sp5, Ls10, Ls20, Ls30, Ls11, Ls21, Ls31‧‧‧ sequence peripheral interface bus

Cs1, Cs3, Cs5‧‧‧ control signals

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2 is a flow chart showing an operation method of an exchanger system according to an embodiment of the present invention; FIG. 3 is a schematic diagram showing an exchange system according to an embodiment of the present invention; and FIG. 4 is a diagram according to the present invention. The embodiment shows a flow chart of a method for operating an exchanger system.

Claims (9)

An exchanger system comprising: a first multiplex control channel; a first electronic erasable rewritable read-only memory; a first sequence peripheral interface bus; a second sequence peripheral interface bus; a multiplexer coupled to the first electronic erasable rewritable read-only memory and selectively electrically coupled to the first sequence peripheral interface bus; and a substrate management controller electrically coupled And transmitting, by the first multiplex control channel, a first control signal to the first multiplexer, wherein the first control signal is used to control the first multiplexer The first multiplexer is electrically coupled to the first sequence of peripheral interfaces, and the substrate management controller transmits a first system parameter to the first multiplexer through the first sequence peripheral interface bus; The first multiplexer writes the first system parameter into the first electronic erasable rewritable read-only memory through the second sequence peripheral interface bus. The switch system of claim 1, further comprising: a processing unit; and a first switch; wherein the first multiplexer writes the first system parameter through the second sequence peripheral interface bus After entering the first electronic erasable rewritable read-only memory, the processing unit loads a basic input/output system, and the basic input/output system causes the first switch to pass through the first multiplexer to read the first An electronic erase type rewritable the first system parameter in the read-only memory, and setting at least one set value according to the first system parameter. The switch system of claim 1, wherein the baseboard management controller is further configured to transmit a second control signal to the first multiplexer through the first multiplex control channel; wherein the second control signal is used The first multiplexer is electrically coupled to a first switch. The switch system of claim 3, further comprising: a processing unit, by a first Peripheral Component Interconnect Express (PCIe) bus and an integrated circuit bus switch (Inter- The integrated circuit switch (I2C Switch) is coupled to the first switch by a second fast peripheral component interconnect bus, when the second control signal controls the When the first multiplexer is switched to be electrically coupled to a first switch, the first switch passes through the first multiplexer to obtain the stored in the first electronic erasable rewritable read-only memory. The first system parameter. The switch system of claim 1, wherein the first system parameter comprises a port location of the first switch, a port setting, a pin-strap information or a The connection is connected to the server information. The switch system of claim 1, further comprising: a second switch; a second multiplexer coupled to the second switch and a second electronic erasable rewritable read-only memory; The substrate management controller is configured to transmit a third control signal to the second multiplexer through a second multiplex control channel, and the third control signal is used to control the second multiplexer and a third sequence. The peripheral interface bus is electrically coupled, and the substrate management controller transmits a second system parameter to the second multiplexer through the third sequence peripheral interface bus, and the second multiplexer transmits a fourth sequence peripheral interface The bus bar transmits the second system parameter to the second electronic erasable rewritable read-only memory. The switch system of claim 1, wherein the baseboard management controller is further configured to analyze a system information, and when the baseboard management controller determines that one of the system information transmission rates is less than a transmission rate threshold, the The substrate management controller transmits a transmission adjustment signal to the first multiplexer, and the first multiplexer transmits the transmission adjustment signal to the first electronic erasable rewritable read-only memory; When the control signal is used to control the first multiplexer to be electrically coupled to a first switch, the transmission adjustment signal is transmitted to the first switch through the first multiplexer to enable the first switch. The signal is adjusted according to the transmission to transmit a data. The switch system of claim 1, wherein the baseboard management controller is further configured to analyze a system information, and when the baseboard management controller determines that one of the signal strength parameters in the system information is less than a signal strength threshold, The substrate management controller transmits an intensity adjustment signal to the first multiplexer, and the first multiplexer transmits the intensity adjustment signal to the first electronic erasable rewritable read-only memory; When the first multiplexer is controlled to be electrically coupled to the first switch, the intensity adjustment signal is transmitted through the first multiplexer to the first switch to enable the first exchange. The device adjusts the signal according to the intensity to transmit a data. The switch system of claim 6, further comprising: a third switch for receiving data from the first switch; and a slot coupled to the third switch, And the slot includes a port for communicating with an external server; wherein the external server is configured to obtain the data through the port.