TW201818468A - Structure of critical dimension bar and semiconductor thereof - Google Patents

Abstract

The present invention provides a structure of critical dimension bar, formed on a substrate, comprising: a isolation structure, comprising a first isolation island and a second isolation island; a patterned polysilicon layer, formed on the isolation structure, comprising a first polysilicon pattern and a second polysilicon pattern on the first isolation island and a second isolation island respectively; and a patterned protective layer, formed on the patterned polysilicon layer, comprising a first protective pattern and a second protective pattern, wherein the first isolation island, a first polysilicon pattern, and the first protective pattern together form a first stack, the second isolation island, the second polysilicon pattern, and the second protective pattern together form a second stack, the first and second stacks are separated from and parallel to each other. The present invention also provides a semiconductor structure comprises the above critical dimension bar.

Description

Key size column structure and semiconductor structure

SUMMARY OF THE INVENTION The present invention is directed to a critical dimension bar structure formed on a portion of a substrate of a dicing street having a height corresponding to a memory structure in the component region.

With the advancement of technology, the semiconductor industry has become a very important development area in the technology industry, and the semiconductor manufacturing process has become increasingly complex. In the semiconductor manufacturing process, the yellow etching and polishing process can be said to be an extremely important process step, and the result of the lithography process can determine the quality performance of the product. The patterned material layer has a critical dimension (CD), which can be said to be an important indicator for judging the quality of components. A material layer with a critical dimension or a stack of material layers is called a key dimension bar (CD). Bar) is used to conveniently measure the critical dimensions of components in an integrated circuit or wafer.

In general, components with integrated circuits in the component area are relatively complicated in structure and difficult to measure. Therefore, the critical dimension bar is disposed outside the component area, and its structure should correspond to the critical dimensions of the components in the component area to ensure measurement. The result is a correct response to the critical dimensions in the component area. However, in the prior art, since the components included in different regions are not completely the same, it is not easy to control the edge region of the wafer in the process. For example, in the chemical mechanical polishing process, the grinding thickness deviation of the partial crystal away from the center of the circle is difficult. The larger the value, the measurement result of the key size bar cannot accurately correspond to the measurement result of the component area or the center of the circle.

Accordingly, the present invention is directed to a key size column structure for solving the above problems in the prior art.

The invention provides a key size column structure formed on a substrate, comprising: an isolation structure comprising at least a first isolation island and a second isolation island; and a patterned polysilicon layer formed on the isolation structure, comprising a first polysilicon layer a pattern and a second polysilicon layer pattern respectively on the first isolation island and the second isolation island; and a patterned protection layer formed on the patterned polysilicon layer, including the first protection layer pattern and the second protection layer pattern, wherein The first isolation island, the first polysilicon layer pattern and the first protection layer pattern together form a first stack, and the second isolation island, the second polysilicon layer pattern and the second protection layer pattern together form a second stack, first The stack and the second stack are separated from each other and are parallel to each other.

In a preferred embodiment of the invention, a portion of the isolation structure is embedded in the substrate and has an upper surface that is higher than an upper surface of the substrate.

In a preferred embodiment of the invention, the upper surface of the isolation structure is between 450 and 650 angstroms above the upper surface of the substrate.

In a preferred embodiment of the invention, the first isolation island and the second isolation island have a spacing between 210 and 310 angstroms.

In a preferred embodiment of the present invention, the method further includes: a patterned ONO structure layer formed between the isolation structure and the patterned polysilicon layer, comprising a first ONO structure layer pattern and a second ONO structure layer pattern The first ONO structure layer pattern is included in the first stack, between the first isolation island and the first polysilicon layer pattern, and the second ONO structure layer pattern is included in the second stack. Located between the second isolation island and the second polysilicon layer pattern.

In a preferred embodiment of the present invention, the method further includes: a polysilicon layer formed on the substrate, between the first stack and the second stack, and the polysilicon layer having an in-wafer height difference of less than 60 angstroms .

In a preferred embodiment of the present invention, the first polysilicon layer pattern and the first protective layer pattern together form a portion of the first stack, and the second polysilicon layer pattern and the second protective layer pattern are formed together A portion of the second stack has a spacing between the first isolation island and the second isolation island that is less than a spacing between the portion of the first stack and the portion of the second stack.

In a preferred embodiment of the present invention, the first polysilicon layer pattern and the first protective layer pattern together form a partial third stack, and the second polysilicon layer pattern and the second protective layer pattern together form a partial fourth stack And a spacing between the first isolation island and the second isolation island is greater than a spacing between the portion of the third stack and the portion of the fourth stack.

In a preferred embodiment of the present invention, the method further includes: forming a portion of the polysilicon layer on the substrate, comprising a first portion of the polysilicon layer and a second portion of the polysilicon layer separated from each other, the first portion of the polysilicon layer and the first layer Adjacent to the isolation island, the second partial polysilicon layer is adjacent to the second isolation island, and the first partial polysilicon layer is covered by the first polysilicon layer pattern, and the second partial polysilicon layer is covered by the second polysilicon layer Layer pattern overlay.

The invention also provides a semiconductor structure, comprising: a substrate having an element region and a detection region; and an isolation structure comprising a plurality of component regions, the islands are separated from each other in the component region and are parallel to each other, and the plurality of detection regions are isolated from the detection region. Separating from each other and parallel to each other, wherein the element isolation island and the detection region isolation island have mutually perpendicular extending directions; the first patterned polysilicon layer is formed between the isolation regions of the element region; and the patterned ONO structural layer is formed in the component region a first patterned polysilicon layer, and a plurality of detection regions on the island in the detection region; a second patterned polysilicon layer formed on the patterned ONO structure layer; and a patterned protective layer formed in the second pattern On the polycrystalline layer.

In a preferred embodiment of the present invention, the first patterned polysilicon layer and the element isolation island have a height higher than the substrate 1 and the two heights are between 450 and 650 angstroms.

In a preferred embodiment of the invention, the first patterned polysilicon layer has the same extension direction as the detection region isolation island.

In a preferred embodiment of the present invention, a sidewall of a stacked structure formed by the patterned ONO structure layer, the second patterned polysilicon layer and the patterned protective layer in the detection region One side wall of the isolation zone of the detection zone is coplanar.

In a preferred embodiment of the present invention, the patterned ONO structure layer, the second patterned polysilicon layer and the patterned protection layer in the detection region form a plurality of stacked structures, and the adjacent ones of the stacked The structure has a pitch greater than one of the two isolation regions of the detection zone below the two adjacent stack structures.

In a preferred embodiment of the invention, an upper surface of the first patterned polysilicon layer is coplanar with an upper surface of the isolation island isolation island.

In a preferred embodiment of the present invention, the method further includes: a third patterned polysilicon layer, the first patterned polysilicon layer formed in the element region, the patterned ONO structure layer, and the second patterned polysilicon layer And a plurality of memory stack structures formed together with the patterned protective layer, and the detection region isolation island, the patterned ONO structure layer, the second patterned polysilicon layer and the patterning in the detection region The protective layer has a plurality of key dimension column structures, wherein the third patterned polysilicon layer has an in-wafer height difference of less than 60 angstroms.

Therefore, the present invention utilizes the above-mentioned characteristics that the small block area is smaller than the bulk area removal rate, the small area process has a relatively small intra-area difference value, and the like in the etching and polishing process, by forming the same distribution pattern as the element area. The method of isolating the structure 3 from the detection zone is to improve the problem that the removal rate control of each layer of the critical dimension column structure of the edge region is not easy.

The above-described and other objects, features and advantages of the present invention will become more apparent and understood. Detailed description will be made to make the structure and efficacy of the present invention easier to understand. Also, for convenience of explanation and ease of understanding, elements having the same functions in different embodiments are given the same reference numerals, but are not intended to limit the present invention.

1 is a top plan view of a semiconductor structure according to the present invention, including an element region R1 and a detection region R2, and FIG. 1a is a schematic cross-sectional view showing the structure of the device region R1 and the detection region R2 on the A-A' tangent line in FIG. FIG. 1b is a schematic cross-sectional view showing the structure of the B-B' tangent line and the b-b' tangent line in FIG. 1, respectively corresponding to and showing the cross-sectional structure in the Y direction of the element region R1 and the detection region R2. A plurality of isolation structures 3 are formed in the substrate 1 in the element region R1 and the detection region R2, and the isolation structures 3 are parallel to each other and separated from each other. The isolation structure 3 defines the substrate 1 in the element region R1 and the detection region R2, respectively. The active area R11 is located between the isolation structures 3, and is used as an active area for the components formed later. For example, the configuration shown in FIG. 1 is an active area R11 according to an embodiment of the present invention. But there is no limit here. In addition, a plurality of mutually parallel memory stack structures 20 (including the patterned polysilicon layer 4, the ONO structure layer 5, the polysilicon layer 6 and the protective layer 7) are formed on the substrate 1 in the element region R1, and are formed vertically. a portion of the active region R11 extending in the X direction in the element region R1 is perpendicular to the isolation structure 3; and a plurality of mutually parallel key dimension column structures 21 are formed in the detection region R2 (including the isolation structure 3 and the patterned structure) The ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7) are on the substrate 1. The memory stack structure 20, the critical dimension column structure 21 and the active region R11 are all extended in the Y direction, and the critical dimension column structure 21 is interposed with the active region R1. The arrangement, and the isolation structure 3 in the element region R1 and the detection region R2 extend in different directions, and the isolation structures 3 in the two regions extend in a direction perpendicular to each other. And the isolation structure 3 in the element region R1 and the detection region R2 are higher than the upper surface of the substrate 1, wherein the isolation structure 3 in the device region R1 has a polysilicon layer 4 between them for use as a memory element during process completion. Floating gate. The element area R1 may be a wafer area formed by the memory unit, and the detection area R2 may be a scribe line area surrounding the wafer area. The polysilicon layer 9 is subsequently used as a word line, and is filled on the substrate 1 between the memory stack structure 20 and the key size column structure 21.

In order to more clearly illustrate the structure and efficacy of the present invention, FIGS. 2a-2g show the key dimension column structure drawn in accordance with another embodiment of the present invention in different process steps, corresponding to the tangent A-A' in FIG. Schematic cross-section (the same components are given the same reference numerals, and the dimensional ratios may vary according to different embodiments). As shown in FIG. 2a, the substrate 1 comprises a substrate 11 and a dielectric layer 12 covering the entire substrate 11, and then an isolation structure 3 is formed on the substrate 1, for example, in the dielectric layer 12 (in one embodiment, oxidized). After the nitride layer is formed on the layer, the nitride layer and the dielectric layer 12 are patterned, and then the substrate 11 is etched by using the nitride layer and the dielectric layer 12 as a mask to remove the exposed portion of the substrate 11 to form A plurality of recesses are formed in the recess and cover the nitride layer, followed by a planarization polishing process and removal of the nitride layer to obtain the isolation structure 3 as shown in FIG. 2a. The above description of the method for forming the isolation structure 3 is not intended to limit the present invention. The material selection used for the nitride layer, the dielectric layer 12, and the isolation material layer used in the illustration may also be adjusted, since this part can apply existing knowledge. Therefore, do not repeat them. The isolation structures 3 are separated from each other and are parallel to each other, and the isolation structure 3 formed in the detection region R2 extends in the Y direction, and the isolation structure 3 formed in the element region R1 extends in the X direction as shown in FIG. The isolation structure 3 has an embedded portion 31 embedded in the substrate 1 (the substrate 11 and the dielectric layer 12) and a protruding portion 32 protruding from the substrate 1 (the substrate 11 and the dielectric layer 12), and the protruding portion 32 has The height D1 of the surface of the dielectric layer 12 is between 850 and 1050 angstroms, and the distance between any two adjacent isolation structures 3 is between 210 and 310 angstroms. Moreover, since the isolation structure 3 has an island-like configuration, the single isolation structure 3 can be referred to as an isolation island (the "isolation island" in this description represents a single isolation structure 3). Then depositing a polycrystalline germanium layer on the substrate 1, covering the entire substrate 1 and the isolation structure 3, followed by a chemical mechanical polishing (CMP) process to isolate the structure 3 as a termination layer, resulting in a structure as shown in FIG. 2b, the polysilicon layer 4 The height D2 is also between 850 and 1050 angstroms and has a wafer variation of less than 60 angstroms. In addition, since FIGS. 2a-2g are schematic cross-sectional views of the structure drawn by the tangential line A-A' in FIG. 1, the isolation structure 3 of the element region R1 does not appear in FIGS. 2a-2g, but the process steps in the element region R1 Consistent with the detection zone R2, the resulting structure is also similar to the detection zone R2. In accordance with an embodiment of the present invention, the isolation structure 3 has a pitch of 261 angstroms, D1 and D2 are 950 angstroms, and at least a portion of the upper surface of the polysilicon layer 4 is coplanar with the upper surface of the isolation structure 3.

Then, the polycrystalline germanium layer 4 and the protruding portion 32 of the isolation structure 3 are etched back, so that the polycrystalline germanium layer 4 in the element region R1 and the detecting region R2 and the protruding portion 32 of the isolation structure 3 are both 450~. A height between 650 angstroms (projected from the substrate 1) forms a structure as shown in FIG. 2c, the polysilicon layer 4 is filled between the projections 32 of the isolation structure 3, and the wafer height difference of the polysilicon layer 4 is The within wafer variation is less than 60 angstroms. Then, the ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7 are sequentially formed. The thickness of the ONO structural layer 5 is between 120 and 180 angstroms, and the thickness of the polycrystalline germanium layer 6 is between 700 and 900 angstroms, and the thickness of the protective layer 7 is Between 1200 and 1700 angstroms, as shown in FIG. 2d, the total height after stacking in the component region R1 is consistent with the total height after stacking in the detection region R2, and the total height of the substrate 1 after stacking is projected. At 2470~3400 angstroms. According to an embodiment of the present invention, the height of the polycrystalline germanium layer 4 and the protruding portion 32 of the isolation structure 3 are 450 angstroms, the thickness of the ONO structural layer 5 is 150 angstroms, the thickness of the polycrystalline germanium layer 6 is 800 angstroms, and the thickness of the protective layer 7 is 1500 Å. A).

Thereafter, as shown in Fig. 2e, a memory stack structure 20 is formed in the element region R1, and a critical dimension column structure 21 is formed in the detection region, wherein a portion of the polysilicon layer 4 located between the key size column structures 21 is completely removed. For example, after the ONO structure layer 5, the polysilicon layer 6, and the protective layer 7 are patterned, the patterned ONO structure layer 5, the polysilicon layer 6, and the protective layer 7 have the same width, and the three layers are The formed push-up structure covers only a portion of the protrusions 32 such that the width D6 of the stacked structure formed by the three patterned ones is smaller than the width D5 of the protrusions 32 of the isolation structure 3. Then, a first spacer 81 is formed on the sidewalls of the patterned ONO structure layer 5, the polysilicon layer 6 and the protective layer 7 extending in the stacking direction, and then the patterned ONO structure layer 5 and the polysilicon layer 6 are patterned. The stacked structure of the protective layer 7 and the first spacer 81 are patterned by the mask to remove all of the polysilicon layer 4 in the detection region R2 and the uncovered polysilicon layer in the element region R1. 4, after the second spacer 82 is formed in the element region R1, the polysilicon layer 4, the ONO structure layer 5, the polysilicon layer 6 and the protective layer 7 are extended on the sidewall extending in the stacking direction, and the first spacer 81 is formed. On a side wall of the above-mentioned side wall away from the four, and the protrusion 32 in the isolation structure 3 in the detection area R2 and the patterned ONO structure layer 5, the polysilicon layer 6, and the protective layer 7 are extended on the side wall extending in the stacking direction. The first spacer 81 is separated from a sidewall of the four sidewalls to form a structure as shown in FIG. 2e. The first spacer 81 and the second spacer 82 together form a spacer 8 and the patterned ONO structural layer. 5, polycrystalline germanium layer 6, protective layer 7 three extension The sidewalls extending in the stack direction are coplanar, and the patterned ONO structure layer 5, the polysilicon layer 6, and the protective layer 7 cover only a portion of the isolation structure 3, so that the pitch of the protrusions 32 of the adjacent isolation structures 3 is Less than the spacing between the stacked structures formed by the upper ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7, and the spacing between the stacked structures formed by the three is between 250 and 350 angstroms (the above stacking) The opposite side walls of the structure and the opposite side walls of the underlying isolation structure 3 have a minimum horizontal spacing of approximately 20 angstroms each).

The forming method is either first patterning the stack of the polysilicon layer 4, the ONO structure layer 5, the polysilicon layer 6, and the protective layer 7, and then forming the patterned polycrystalline layer 4 and the ONO structure of the spacer 8 in the element region R1. The layer 5, the polysilicon layer 6 and the protective layer 7 are extended on the sidewall extending in the stacking direction, and the protrusion 32 in the isolation structure 3 in the detection region R2 and the patterned ONO structure layer 5, the polysilicon layer 6, and the protective layer 7 is formed on the side wall extending in the stacking direction to form a structure as shown in FIG. 3, wherein the patterned polycrystalline germanium layer 4, the ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7 in the element region R1 are stacked in the stacking direction. The extended sidewalls are coplanar, and the protrusions 32 of the isolation structure 3 in the detection region R2 and the patterned ONO structure layer 5, the polysilicon layer 6 and the protective layer 7 are coplanar in the stacking direction. The spacers 8 may be of a single layer or a multilayer structure. According to the embodiment of the present invention shown in FIG. 3 formed according to the above method, in the element region R1, the patterned polysilicon layer 4, the ONO structure layer 5, the polysilicon layer 6 and the protective layer 7 have the same width, and the detection region R2 In the patterned ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7, the width D6' of the four stacks is the same as the width D5 of the convex portion 32 of the isolation structure 3. 3 is an embodiment of the present invention, which has another difference from the embodiment shown in FIGS. 2a-2g, that is, the isolation structure 3 has different configurations from the embodiment shown in FIGS. 2a-2g, and the isolation structure of the present invention The configuration of 3 is not limited and can be adjusted according to different processes. The configurations drawn by the present invention are for illustrative purposes only and are not intended to limit the present invention.

The forming method may further be that the ONO structural layer 5, the polycrystalline germanium layer 6, and the protective layer 7 are first patterned to form a structure as shown in FIG. 4a, which can be seen by the detection region R2, and the patterned ONO structure. The layer 5, the polysilicon layer 6, and the protective layer 7 not only completely cover the isolation structure 3, but also the width D6'' of the three stacks is larger than the width D5 of the protrusion 32 of the isolation structure 3, that is, the structure of the two adjacent isolation structures 3. The spacing is greater than the spacing of the two adjacent stacks of three. Next, as shown in FIG. 4b, a first spacer 81 is formed on the sidewalls of the patterned ONO structural layer 5, the polysilicon layer 6 and the protective layer 7 extending in the stacking direction, and then the patterned ONO structural layer is formed. 5. A stacked structure of the polysilicon layer 6 and the protective layer 7, and the first spacer 81 is patterned by the mask to pattern the polysilicon layer 4 to remove the uncovered portion of the polysilicon layer 4 in the element region R1 and the detection region. . Therefore, the polycrystalline germanium layer 4' of the detecting region R2 is retained, the polycrystalline germanium layer 4' is adjacent to the protruding portion 32, located between the isolating structures 3, and the patterned ONO structural layer 5, polycrystalline germanium layer 6, and protective layer 7 The stacked structure of the person and the first spacer 81 are covered. And the sidewall of the portion of the polysilicon layer 4 away from the isolation structure 3 is coplanar with a sidewall of the first spacer 81. Then, a second spacer 82 is formed. As shown in FIG. 4c, on the sidewall of the element region R1 where the first spacer 81 and the polysilicon layer 4' are coplanar, the first spacer 81 and the polysilicon layer 4' are covered. Indirectly covering the patterned ONO structural layer 5, the polycrystalline germanium layer 6 and the protective layer 7 on the side walls extending in the stacking direction, and the above-described patterned polycrystalline germanium layer 4' and the first spacer 81 in the detecting region R2 On the side wall, therefore, the second spacer 82 simultaneously covers the ONO structure layer 5, the polysilicon layer 6 and the protective layer 7 on the side walls extending in the stacking direction. The spacers 8 in the different embodiments may be made of SiO, SiN, SiON, SiCN, or any combination thereof, and the first spacers 81 and the second spacers 82 may be the same material. The use of spacers and associated formation methods can be applied to other process details as they can apply conventional knowledge.

The subsequent steps are illustrated by the embodiment shown in FIG. 2e, but are not intended to limit the present invention. The following description steps can also be applied to the embodiment shown in FIG. 3 and FIG. 4b or other embodiments. Then depositing a polycrystalline germanium layer on the substrate 1 to fill at least between the memory stack structures 20 and between the critical dimension column structures 21, selectively covering the memory stack structure 20 and the critical dimension column structure 21, and then planarizing A process (such as chemical mechanical polishing) forms a polycrystalline germanium layer 9. The polycrystalline germanium layer 9 may be located only between the memory stacked structures 20 and between the critical size column structures 21, so that the protective layer 7 is exposed, so that the upper surface of the polycrystalline germanium layer 9 is coplanar with the upper surface of the protective layer 7; The difference in thickness of the removed polysilicon layer in the planarization process forms a polysilicon layer 9 as shown in FIG. 2f, except that it is located between the memory stack structure 20 and between the critical dimension column structures 21, and also covers the protective layer 7. The upper surface, wherein the height D3 of the polysilicon layer 9 on the substrate 1 is between 2500 and 3500 angstroms. In one embodiment of the invention, the polysilicon layer 9 has a height of about 3000 angstroms. Then, an etch back process is performed. As shown in FIG. 2g, a portion of the polysilicon layer 9 is removed to form a polysilicon layer 9' between the memory stack structure 20 and between the key size column structures 21 for use as a word line. And the etched polycrystalline germanium layer 9' has a height D4 of about 1200 angstroms, and the polysilicon layer 9' has an within wafer variation of less than 60 angstroms. In addition, a doping process such as a well region, a deep well region, a source/drain electrode, and the like may be appropriately inserted between the above steps, which is not limited herein.

Therefore, the key dimension column structure provided by the present invention is formed on the substrate (1), comprising: an isolation structure (3) comprising at least a first isolation island and a second isolation island; and a patterned polycrystalline germanium layer (6) formed On the isolation structure (3), the first polysilicon layer pattern and the second polysilicon layer pattern are respectively disposed on the first isolation island and the second isolation island (corresponding to the patterning on the different isolation islands in the drawing) a polysilicon layer 6); and a patterned protective layer (7) formed on the patterned polysilicon layer, comprising a first protective layer pattern and a second protective layer pattern (corresponding to the patterned ones on different islands in the drawing) a protective layer 7), wherein the first isolation island, the first polysilicon layer pattern and the first poly layer pattern together form a first stack, and the second isolation island, the second polysilicon layer pattern and the second protection layer pattern are formed together The second stack, the first stack and the second stack are separated from each other and are parallel to each other (corresponding to different key size bar structures 21 in the drawing, separated from each other and parallel to each other). The invention also provides a semiconductor structure comprising: a substrate (1) having an element region (R1) and a detection region (R2); an isolation structure (3) comprising a plurality of component region isolation islands (corresponding to the component regions in the drawing) The partial isolation structures 3) in R1 are separated from each other in the element region (R1) and are parallel to each other, and a plurality of detection region isolation islands (corresponding to a partial isolation structure 3 in the detection region R2 in the drawing) are in the detection region (R2). Separating from each other and parallel to each other, wherein the element isolation island and the detection region isolation island have mutually perpendicular extending directions; the first patterned polysilicon layer (corresponding to the patterned polycrystalline germanium layer 4 in the element region R1 in FIGS. 2e-2g) Formed between the isolation regions of the element region; patterned ONO structure layer (5), formed on the first patterned polysilicon layer (4) in the element region (R1), and plural in the detection region (R2) a detection zone isolation island; a second patterned polysilicon layer (corresponding to the patterned polysilicon layer 6 in Figures 2e-2g) formed on the patterned ONO structure layer; and a patterned protective layer (corresponding to Figures 2e-2g) The patterned protective layer 7) is formed on the second patterned polysilicon layer.

In the grinding and etching process, the edge area of the wafer is not easily controlled due to the limitations of the process and the machine itself. Taking a wafer with a radius of 300 mm (mm) as an example, in a critical dimension column structure in an edge region of more than 130 mm from the center of the circle, the height difference in the edge region after the process can be as high as 500 angstroms, which is much larger than the center of the circle. A difference in height in the central region equal to 130 mm, thus leading to the problem in the prior art that the critical dimension bar structure simply does not reflect the measurement results of the component. Although various methods are used in the prior art, such as adjusting process parameters to improve the edge area of the wafer, the process cost is increased, but the problem of difficulty in controlling the edge area of the wafer cannot be fundamentally improved. In view of the above problems, the inventor of the present invention found that although the height dimension column structure in the edge region can have a height difference of up to 500 angstroms after the process, the memory component structure in the edge region is within the process area. The height difference can be maintained below 60 angstroms, and the biggest difference between the memory stack structure and the critical dimension column structure is that the critical dimension column structure exists only for the memory stack structure of the monitoring component area, and thus the structure It does not need to be identical to the component area, as long as the stacking result can be consistent. Therefore, in the prior art, the stacking, density, shape, distribution, etc. of the key size column structure located on the cutting path are not the same as the component area. However, this also indirectly leads to a drop in the rate of removal of the scribe line from the component area during the grinding and etching process. Although it is located in the area closer to the center of the circle, the process control effect is good, so the drop of the removal rate will not be clearly reflected, but the edge area itself has a problem that the process control effect is not easy, thus contributing to the problem of excessive height difference in the area. .

The key dimension column structure provided by the present invention is located in the detection region R2 on the scribe line, and in the step of forming the isolation structure 3 in the element region R1, simultaneously forming the isolation structure 3 having the same distribution pattern in the detection region R2, so that the detection region R2 The isolation structure 3 in the middle has the same height as the polysilicon layer 4 in the memory stack structure 20 in the element region R1 in the subsequent process. In the subsequent process, the layers corresponding to the ONO structure layer 5, the second polysilicon layer 6 and the protective layer 7 in the memory stack structure 20 are formed on the isolation structure 3 in the detection region R2, so the direction detection The isolation structure 3 in the region R2 is perpendicular to the isolation structure 3 in the element region R1, and the remaining distribution conditions, such as shape, pitch, width, etc., are similar or identical to the isolation structure 3 in the element region R1. Therefore, the present invention utilizes the above-described characteristics such that the small block region is smaller than the bulk region removal rate and the small region region process has a relatively small intra-region difference value in the etching and polishing process, and the same distribution pattern as the device region R1 is formed. The isolation structure 3 is in the detection zone R2 method to improve the problem that the removal rate control of each layer of the critical dimension column structure of the edge region is not easy.

In summary, the present invention provides a key dimension column structure having a high degree of isolation from the floating gate polysilicon layer in the memory stack structure of the device region (corresponding to the patterned polysilicon layer 4 in the element region R1 in the figure). The structure (the isolation structure 3 in the detection area R2 in the drawing), so that the subsequently formed stacked layers can correspond to the layers in the memory stack structure in the component region, thereby improving the problem of the difference between the key dimension column structure and the component structure. Moreover, the key dimension column structure provided by the present invention also has the advantage that it can be directly applied to the conventional process steps. Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧Substrate

3‧‧‧Isolation structure

4, 4', 6, 9, 9'‧‧‧ polycrystalline layer

5‧‧‧ONO structural layer

7‧‧‧Protective layer

8, 81, 82‧ ‧ spacers

11‧‧‧Substrate

12‧‧‧Dielectric layer

20‧‧‧Memory stack structure

21‧‧‧Key size bar structure

31‧‧‧ embedded department

32‧‧‧Protruding

D1, D2, D3, D4‧‧‧ height

D5, D6, D6’, D6’’‧‧‧ width

R1‧‧‧ component area

R2‧‧‧ inspection area

R11‧‧‧ active area

A-A’, B-B’, b-b’‧‧‧ tangent

The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. A schematic plan view of the semiconductor structure is drawn; FIG. 1a is a schematic cross-sectional view of the structure of the line A-A' in FIG. 1; FIG. 1b is a cross-sectional view of the structure of the B-B' tangent line and the b-b' tangent line in FIG. Corresponding to and illustrating the cross-sectional structure of the element region R1 and the detection region R2 in the Y direction; FIGS. 2a-2g are schematic diagrams showing the cross-sectional structure of the key dimension column structure drawn in different process steps according to another embodiment of the present invention; 3 is a schematic cross-sectional view taken in accordance with another embodiment of the present invention; and FIGS. 4a-4c are cross-sectional structures showing key dimension columns in different process steps in accordance with another embodiment of the present invention. schematic diagram.

Claims (16)

A key dimension bar structure is formed on a substrate, comprising: an isolation structure formed on the substrate, comprising a first isolation island and a second isolation island; a patterned polysilicon layer formed on the isolation structure a first polysilicon layer pattern and a second polysilicon layer pattern; and a patterned protective layer formed on the patterned polysilicon layer, comprising a first protective layer pattern and a second protective layer a pattern, wherein the first isolation island, the first polysilicon layer pattern and the first protection layer pattern together form a first stack, the second isolation island, the second polysilicon layer pattern and the second protection The layer patterns collectively form a second stack that is separate from each other and parallel to each other. The key dimension column structure of claim 1, wherein a portion of the isolation structure is embedded in the substrate and has an upper surface higher than an upper surface of the substrate. The key dimension column structure of claim 2, wherein the upper surface of the isolation structure is between 450 and 650 angstroms above the upper surface of the substrate. The key size bar structure of claim 1, wherein the first isolation island and the second isolation island have a spacing between 210 and 310 angstroms. The key dimension column structure of claim 1, further comprising: a patterned ONO structure layer formed between the isolation structure and the patterned polysilicon layer, comprising a first ONO structure layer pattern and a second ONO structure a layer pattern, wherein the first ONO structure layer pattern is included in the first stack between the first isolation island and the first polysilicon layer pattern, and the second ONO structure layer pattern is included in the second stack Medium between the second isolation island and the second polysilicon layer pattern. The key dimension column structure of claim 1, further comprising: a polysilicon layer formed on the substrate, between the first stack and the second stack, and the polysilicon layer having an in-wafer height difference is less than 60 angstroms. The key size bar structure of claim 1, wherein the first polysilicon layer pattern and the first protective layer pattern together form a portion of the first stack, the second polysilicon layer pattern and the second protective layer pattern A portion of the second stack is formed together, and a spacing between the first isolation island and the second isolation island is less than a spacing between the portion of the first stack and the portion of the second stack. The key size column structure of claim 1, wherein the first polysilicon layer pattern and the first protective layer pattern together form a portion of a third stack, the second polysilicon layer pattern and the second protective layer pattern A portion of the fourth stack is formed together, and a spacing between the first isolation island and the second isolation island is greater than a spacing between the portion of the third stack and the portion of the fourth stack. The key dimension column structure of claim 1, further comprising: a portion of a polysilicon layer formed on the substrate, comprising a first partial polysilicon layer and a second partial polysilicon layer separated from each other, the first partial polysilicon layer and the Adjacent to the first isolation island, the second partial polysilicon layer is adjacent to the second isolation island, and the first partial polysilicon layer is covered by the first polysilicon layer pattern, and the second partial polysilicon layer is covered by the second The wafer layer pattern is covered. A semiconductor structure comprising: a substrate having an element region and a detection region; an isolation structure comprising a plurality of element regions separated from each other and parallel to each other in the element region, and separated from each other and parallel to each other a detection zone isolation island in the detection zone, wherein the component zone isolation island and the detection zone isolation island have mutually perpendicular extending directions; a first patterned polysilicon layer formed in the component region, the plurality of component regions Separating islands between the islands; a patterned ONO structure layer formed on the first patterned polysilicon layer in the element region, the plurality of detection regions on the isolation island in the detection region; a second patterned polysilicon layer forming On the patterned ONO structure layer; and a patterned protective layer formed on the second patterned polysilicon layer. The semiconductor structure of claim 10, wherein the first patterned polysilicon layer and the element isolation island have a height higher than the substrate 1 and the two heights are between 450 and 650 angstroms. The semiconductor structure of claim 10, wherein the first patterned polysilicon layer has the same extension direction as the detection region isolation island. The semiconductor structure of claim 10, wherein a side wall of the stacked structure formed by the patterned ONO structure layer, the second patterned polysilicon layer and the patterned protection layer in the detection region One side wall of the isolation zone of the detection zone is coplanar. The semiconductor structure of claim 10, wherein the patterned ONO structure layer, the second patterned polysilicon layer and the patterned protection layer in the detection region form a plurality of stacked structures, and the adjacent ones of the stacked The structure has a pitch greater than one of the two isolation regions of the detection zone below the two adjacent stack structures. The semiconductor structure of claim 10, wherein an upper surface of the first patterned polysilicon layer is coplanar with an upper surface of the isolation island isolation island. The semiconductor structure of claim 10, further comprising: a third patterned polysilicon layer, the first patterned polysilicon layer formed in the element region, the patterned ONO structure layer, and the second patterned polysilicon layer And a plurality of memory stack structures formed together with the patterned protective layer, and the detection region isolation island, the patterned ONO structure layer, the second patterned polysilicon layer and the patterning in the detection region The protective layer has a plurality of key dimension column structures, wherein the third patterned polysilicon layer has an in-wafer height difference of less than 60 angstroms.