TW201815121A - Clock and data recovery circuit and electrical device - Google Patents

Abstract

A clock and data recovery (CDR) circuit is provided and includes following units. A selection circuit selects an input signal or a pulse signal as a selection signal. A delay lock loop (DLL) circuit is coupled to the selection circuit and receives the selection signal, and accordingly generate multiple clock signals with different phases. A pulse generating circuit receives at least part of the clock signals and includes a latch and a logic circuit. The latch has an input terminal coupled to the input signal, a clock terminal coupled to a first clock, a reset terminal coupled to a second clock, and an output terminal outputting a bit signal. The logic circuit generates the pulse signal according to the bit signal and the input signal.

Description

 Clock data recovery circuit and electronic device  

The present invention relates to a clock data recovery circuit, and more particularly to a clock data recovery circuit using a delay phase locked loop.

In the serial transmission interface of high-speed transmission, a phase-locked loop (PLL)-based clock and data recovery (CDR) is usually used. However, another option is a clock data recovery circuit based on a delay-locked loop. Usually the delay-based loop-based clock data recovery circuit consumes less power and does not accumulate jitter of the signal, but if there is no additional configuration reference clock, then a specific bit needs to be set in the signal. The element is used to generate the clock for decoding. For example, please refer to FIG. 1. FIG. 1 is a waveform diagram of a training input signal according to a prior art. In this example, every 8 bits D0~D7 will additionally add the bit "01", so the extra overhead of encoding is 20%. In the training phase, the transmitter (TX) transmits a signal 110, and the signal 110 is regarded as a reference clock signal. At this time, the bits D0~D7 cannot be used to transmit data, and the receiver (receiver) , RX) can generate a clock signal for decoding according to the signal 110. After training, the additional bit "01" will continue to be used to generate multiple clock signals with different phases, and these clock signals are used to sample bits D0~D7, respectively.

However, in such a transmission mechanism, the receiving end needs to accurately track the bit "01", especially in the interface of high-speed transmission, the width of each bit will be small, so if there is tracking bit "01" A slightly larger delay may result in a decoding error or even a situation of unlocking.

Embodiments of the present invention provide a clock data recovery circuit including a selection circuit, a delay phase locked loop circuit, and a pulse generating circuit. The selection circuit is configured to select one of the input signal and the pulse signal as the selection signal. The delay-locked loop circuit is coupled to the selection circuit and receives the selection signal, and the delay-locked loop circuit is configured to generate a plurality of clock signals having different phases according to the selection signal. The pulse generating circuit is configured to receive at least a portion of the clock signal, and the pulse generating circuit includes a latch and a logic circuit. The input end of the latch is coupled to the input signal, the clock end is coupled to the first clock signal in the clock signal, and the reset end is coupled to the second clock signal in the clock signal, and the output end is Output bit signal. The logic circuit is configured to generate a pulse signal according to the bit signal and the input signal.

In some embodiments, the logic circuit is configured to generate a pulse signal based on a result of a mutually exclusive OR operation of the bit signal and the input signal.

In some embodiments, the delay locked loop circuit includes a voltage controlled delay line that includes a plurality of delay units. The second clock signal is generated by one delay unit, and the phase of the first clock signal leads the phase of the second clock signal by two delay units.

In some embodiments, the selection circuit includes a multiplexer, and the selection terminal receives the path control signal, the first input terminal is coupled to the input signal, and the second input terminal is coupled to the pulse signal.

In some embodiments, the logic circuit includes the following elements. The first input end of the first anti-gate is coupled to the reverse signal of the input signal, and the second input is coupled to the reverse signal of the second clock signal. The first input end of the second anti-gate is coupled to the input signal, and the second input is coupled to the reverse signal of the second clock signal. The first input end of the first anti-gate is coupled to the reverse signal of the path control signal, the second input is coupled to the reverse signal of the bit signal, and the third input is coupled to the output of the first anti-gate The first input end of the second anti-gate is coupled to the reverse signal of the path control signal, the second input is coupled to the bit signal, and the third input is coupled to the output of the second anti-gate. The first input end of the third anti-gate is coupled to the output end of the first anti-gate, the second input is coupled to the output of the second anti-gate, and the third input is coupled to the first circuit, and the output is The terminal outputs a reverse signal of the pulse signal.

In some embodiments, the first circuit includes the following elements. The first input end of the third NAND gate is coupled to the third clock signal in the clock signal, and the second input end is coupled to the second clock signal. The first input end of the fourth anti-gate is coupled to the third clock signal, and the second input is coupled to the pulse signal. The first input end of the fifth anti-gate is coupled to the output of the third anti-gate, and the second input is coupled to the reverse signal of the fourth clock signal in the clock signal. The input end of the first inverter is coupled to the output end of the fourth reverse gate. The input end of the second inverter is coupled to the output of the fifth reverse gate. The first input end of the fourth anti-gate is coupled to the output end of the second inverter, and the second input end is coupled to the output end of the first inverter. The first input end of the fifth reverse gate is coupled to the reverse signal of the path control signal, the second input end is coupled to the output end of the fourth reverse or gate, and the output end is coupled to the third reverse gate or the third gate Input.

In another aspect, an embodiment of the present invention provides an electronic device including the above-described clock data recovery circuit.

In the clock data recovery circuit and the electronic device proposed by the present invention, the latch signal can be used to quickly generate a pulse signal.

The above described features and advantages of the invention will be apparent from the following description.

110‧‧‧ Signal

D0~D7‧‧‧ bits

200‧‧‧clock data recovery circuit

210‧‧‧Selection circuit

211‧‧‧ buffer

212‧‧‧Multiplexer

220‧‧‧Delayed phase-locked loop circuit

221‧‧‧voltage controlled delay line

222‧‧‧ phase detector

223‧‧‧Charge pump

224‧‧‧Low-pass filter

230‧‧‧ pulse generation circuit

In‧‧‧Input signal

Pcs‧‧‧path control signal

Ps‧‧‧pulse signal

Ss‧‧‧Select signal

Clk, clk_i, clk_i+2, clk_i-2, clk_i+7, clk_0~clk_n‧‧‧ clock signal

301‧‧‧Delay unit

410, 420‧‧‧ clock bits

510‧‧‧Logical Circuit

520‧‧‧Latch

D‧‧‧ input

C‧‧‧ clock end

RST‧‧‧Reset

Q‧‧‧output

Bit0‧‧‧ bit signal

610, 620‧‧ ‧ time interval

NAND1~NAND5‧‧‧Anti-gate

NOR1~NOR5‧‧‧Anti-gate

NOT1, NOT2‧‧‧ reverser

710‧‧‧First circuit

N1, N2, P1, P2, CC, DD, KK, 711‧‧‧ signals

FIG. 1 is a waveform diagram showing a training input signal according to a conventional technique.

FIG. 2 is a circuit diagram showing a clock data recovery circuit according to an embodiment.

FIG. 3 is a circuit diagram showing a voltage controlled delay line according to an embodiment.

FIG. 4 is a waveform diagram showing a pulse signal ps according to an embodiment.

FIG. 5 is a circuit block diagram showing a pulse generating circuit 230 according to an embodiment.

FIG. 6 is a waveform diagram showing generation of a pulse signal according to an embodiment.

FIG. 7 is a circuit diagram showing a logic circuit 510 according to an embodiment.

FIG. 8 is a waveform diagram of each signal in FIG. 7 according to an embodiment.

FIG. 9 is a circuit diagram showing a first circuit 710 according to an embodiment.

FIG. 10 is a waveform diagram of each signal in FIG. 9 according to an embodiment.

The terms "first", "second", "etc." used in this document are not intended to mean the order or the order, and are merely to distinguish between elements or operations described in the same technical terms. In addition, as used herein, "coupled" may mean that two elements are electrically connected, either directly or indirectly. That is, when the following description "the first object is coupled to the second object", other items may be disposed between the first object and the second object.

2 is a circuit diagram showing a clock data recovery circuit according to an embodiment. Referring to FIG. 2, the clock data recovery circuit 200 includes a selection circuit 210, a delay phase locked loop circuit 220, and a pulse generation circuit 230. However, not all components in the clock data recovery circuit 200 are shown in FIG. 2, for example, the clock data recovery circuit 200 may further include a sampling circuit or the like. In some embodiments, the clock data recovery circuit 200 is implemented in an electronic device, and the electronic device may be any device including a serial transmission interface, such as a television, a mobile phone, a video player, etc., and the present invention Not limited to this.

The clock data recovery circuit 200 receives the input signal in from the transmitting end (not shown). In this embodiment, the clock data recovery circuit 200 has a training phase and a decoding phase. In the training phase, the input signal in is similar to the signal 110 of FIG. 1 with two additional bits "01" added; in the decoding phase, the input signal in has an additional bit "01" or " 10". However, in other embodiments, the extra bit added to the input signal in during the training phase may also be the bit "10", which is not limited by the present invention.

The selection circuit 210 is configured to select one of the input signal in and the pulse signal ps as the selection signal ss. For example, the selection circuit 210 includes a buffer 211 and a multiplexer 212. The buffer 211 is coupled between the input signal in and the multiplexer 212. The control end of the multiplexer 212 is coupled to the path control signal pcs. The first input end is coupled to the input signal in through the buffer 211, and the second input end is coupled to the pulse signal ps. The path control signal pcs is used to determine whether the clock data recovery circuit 200 is in the training phase or the decoding phase. In this embodiment, when the path control signal pcs is logic "0", the training phase is indicated, and the multiplexer 212 is at this time. The input signal in is selected as the selection signal ss; when the path control signal pcs is logic "1", the decoding phase is indicated, and the multiplexer 212 selects the pulse signal ps as the selection signal ss.

The delay phase locked loop circuit 220 is coupled to the selection circuit 210 and receives the selection signal ss. The delay phase locked loop circuit 220 generates a plurality of pulse signals clk whose phases are different from each other according to the selection signal ss. For example, the delay phase locked loop circuit 220 includes a voltage controlled delay line 221, a phase detector 222, a charge pump 223, and a low pass filter 224. As shown in FIG. 3, the voltage-controlled delay line 221 includes n delay units 301, n is a positive integer, and each delay unit 301 can determine the delay time according to a voltage (not shown). . The voltage-controlled delay line 221 outputs a clock signal clk_0~clk_n, wherein the clock signal clk_0 does not pass through the delay unit 301, and the clock signal clk_1 passes through a delay unit 301, that is, the phase of the clock signal clk_0 leads. The phase of the pulse signal clk_1 is the delay time of one delay unit 301, and so on. In this embodiment, the delay time of one delay unit 301 is equal to the width of one bit. That is to say, at the end of the training phase, the clock signal clk_0 is synchronized with the input signal in, and the clock signal clk_1 is one bit behind, and so on. However, those skilled in the art will understand the operation of the various components in the delay-locked loop circuit 220, and will not be described herein. The present invention also does not limit the value of the positive integer n.

Referring to FIG. 2, after entering the decoding stage, the pulse generating circuit 230 receives at least part of the clock signal clk, and also receives the input signal in to generate the pulse signal ps, and the multiplexer 212 outputs the pulse signal ps to Voltage controlled delay line 221. Please refer to FIG. 4. FIG. 4 is a waveform diagram of a pulse signal ps according to an embodiment. In the embodiment of FIG. 4, bits D0~D7 are the data to be transmitted, while clock bits 410 and 420 are additional bits. The clock bit 410 is the bit "01", but the clock bit 420 is the bit "10". The reason that the clock bit 410 is different from the clock bit 420 is that in some agreements, the bits on the transmission line must be randomized as much as possible to avoid the continuous occurrence of multiple bits "0" or bit "1". . However, since the delay phase-locked loop circuit 220 tracks the phase of the input signal in according to the rising edge, if the clock signal is generated according to the clock bits 410, 420, the clock bit 420 generates an erroneous clock signal. . In this embodiment, a pulse signal ps is generated, and the rising edge of the pulse signal ps is synchronized with the rising edge or falling edge of the clock bits 410, 420. It should be noted that regardless of whether the clock bits 410, 420 are bits "01" or "10", the pulse signal ps will generate a rising edge. The following describes how to generate the pulse signal ps.

In the embodiment of Fig. 4, an additional 2 bits are added in every 8 bits, but the invention is not limited thereto. For example, in some embodiments an additional 2 bits are added per k bits, and k can be any positive integer. In addition, in the above embodiment, the delay-locked loop circuit 220 tracks the phase of the input signal in according to the rising edge, but in other embodiments, the delay-locked loop circuit 220 can also track the phase of the input signal in according to the falling edge. .

FIG. 5 is a circuit block diagram showing pulse generation circuit 230, in accordance with an embodiment. Referring to FIG. 5, the pulse generating circuit 230 includes a logic circuit 510 and a latch 520. The input terminal D of the latch is coupled to the input signal in, the clock terminal C (or the enable terminal) is coupled to the clock signal clk_i (also referred to as the first clock signal), and the reset terminal RST is coupled. Connected to the clock signal clk_i+2 (also known as the second clock signal), the output terminal Q will output the bit signal Bit0, i is a positive integer. The phase of the clock signal clk_i is the delay time of the two delay units of the phase leading to the clock signal clk_i+2. The circuit 510 generates the pulse signal ps according to the input signal in and the bit signal Bit0.

For example, please refer to FIG. 6. FIG. 6 is a waveform diagram showing the generation of a pulse signal according to an embodiment. Referring to FIG. 5 and FIG. 6, the clock signal clk_i+2 is generated by one delay unit 301, for example, the clock signal clk_1 of FIG. The clock signal clk_i is two bits leading to the clock signal clk_i+2, for example, the clock signal clk_n of FIG. The operation of the latch 520 is such that when the signal on the pulse terminal C is at a low level, the signal at the output terminal Q is equal to the signal at the input terminal D; when the signal at the pulse terminal C is at a high level, the output terminal Q The signal will be fixed even if the signal on the input D changes. When the signal on the reset terminal RST is high, the signal on the output Q will be pulled to the low level. According to the operation of the latch 520, the bit signal Bit0 is used to lock the first bit in the clock bits 410, 420, so in the time interval 610, the bit signal Bit0 is at a low level, and in the time interval. The 620 median signal Bit0 is at a high level. The logic circuit 510 can generate the pulse signal ps according to the result of the exclusive or XOR operation of the input signal in and the bit signal Bit0. It should be noted that the result of the mutual exclusion or operation can determine at least the rising edge of the pulse signal ps, and the width of the pulse signal ps does not affect the operation of the subsequent phase detector 222. However, if the width of the pulse signal ps is too small, it may disappear in the loop. Therefore, the width of the pulse signal ps may be set to be greater than a preset value, but the present invention does not limit the preset value.

FIG. 7 is a circuit diagram showing logic circuit 510, in accordance with an embodiment. In the embodiment of FIG. 7, the logic circuit 510 includes a first reverse gate NAND1, a second reverse gate NAND2, a first inverse OR gate NOR1, a second inverse OR gate NOR2, a third inverse OR gate NOR3, and a first circuit. 710. The first input of the gate NAND1 is coupled to the reverse signal of the input signal in (marked as ), the second input is coupled to the reverse signal of the clock signal clk_i+2 (marked as ). The first input terminal of the NAND gate NAND2 is coupled to the input signal in, and the second input terminal is coupled to the reverse signal of the clock signal clk_i+2. The first input of the inverse OR gate NOR1 is coupled to the reverse signal of the path control signal pcs (marked as ), the second input is coupled to the reverse signal of the bit signal Bit0 (marked as The third input is coupled to the output of the anti-gate NAN1. The first input end of the reverse OR gate NOR2 is coupled to the reverse signal of the path control signal pcs, the second input end is coupled to the bit signal Bit0, and the third input end is coupled to the output end of the second inverse gate NAN2. The first input terminal of the inverse OR gate NOR3 is coupled to the output terminal of the inverse OR gate NOR1, the second input terminal is coupled to the output terminal of the inverse OR gate NOR2, the third input terminal is coupled to the first circuit 710, and the output terminal is coupled to the output terminal Then output the reverse signal of the pulse signal ps (marked as ). The signal 711 output by the first circuit 710 is used to determine the width of the pulse signal ps. The timing diagram of each signal in Figure 7 is shown in Figure 8.

FIG. 9 is a circuit diagram of a first circuit 710, in accordance with an embodiment. Referring to FIG. 9, the first circuit 710 includes a third reverse gate NAND3, a fourth reverse gate NAND4, a fifth reverse gate NAND5, a first inverter NOT1, a second inverter NOT2, and a fourth inverse gate. NOR4 and the fifth inverse or gate NOR5. The first input terminal of the NAND gate NAND3 is coupled to the clock signal clk_i-2 (also referred to as a third clock signal), and the second input terminal is coupled to the clock signal clk_i+2. The first input terminal of the NAND gate NAND4 is coupled to the clock signal clk_i-2, and the second input terminal is coupled to the pulse signal ps. The first input terminal of the NAND gate NAND5 is coupled to the output terminal of the NAND gate NAND3, and the second input terminal is coupled to the reverse signal of the clock signal clk_i+7 (also referred to as the fourth clock signal). The input of the inverter NOT1 is coupled to the output of the NAND gate NAND4. The input of the inverter NOT2 is coupled to the output of the NAND gate NAND5. The first input of the inverse OR gate NOR4 is coupled to the output of the inverter NOT2, and the second input is coupled to the output of the inverter NOT1. The first input end of the reverse OR gate NOR5 is coupled to the reverse signal of the path control signal pcs, the second input end is coupled to the output end of the inverse OR gate NOR4, and the output end outputs the signal 711. The timing diagram of each signal in Figure 9 is shown in Figure 10.

It should be noted that the signal 711 output by the first circuit 710 is used to determine the width of the pulse signal ps. As described above, the width of the pulse signal ps does not affect the generation of the clock signal, and those skilled in the art can design The particular circuit of the first circuit 710 is not limited by the present invention by any suitable first circuit 710. On the other hand, referring to FIG. 2 and FIG. 7, when the path control signal pcs is logic "0" in the training phase, the inverse OR gates NOR1 and NOR2 both output logic "0", that is, the path in the training phase. The control signal pcs are used to disable the pulse signal ps. In some embodiments, since the pulse signal ps is not transmitted to the voltage-controlled delay line 221 during the training phase, the path control signal pcs in FIG. 7 can be omitted. If the logical operation of the path control signal pcs and the signal 711 is omitted, the operation of the logic gate in FIG. 7 can be derived as shown in the following equation (1), in which the clock signal clk_i+2 is represented as clk _{i +2} .

That is to say, in FIG. 7, the logic circuit 510 generates the pulse signal ps based on the result of mutual exclusion or operation between the bit signal Bit0 and the input signal in. In addition, as shown in FIG. 6, the clock signal clk_i+2 does not change in the time interval 610, 620, so the mutual interference between the bit signal Bit0 and the input signal in affecting the rising edge of the pulse signal ps is Operation. The result of this mutex or operation can also be combined with other logic operations to generate the clock signal ps (eg, path control signals pcs and signals 711). Therefore, it is within the scope of the present disclosure to generate the pulse signal ps according to the result of mutual exclusion or operation between the bit signal Bit0 and the input signal in. Moreover, those skilled in the art have many implementations when it is understood that the exclusive or exclusive operation, and the present invention is not limited to the circuit of FIG.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (12)

 A clock data recovery circuit includes: a selection circuit for selecting one of an input signal and a pulse signal as a selection signal; a delay phase locked loop circuit coupled to the selection circuit and receiving the selection a signal, a delay phase-locked loop circuit for generating a plurality of clock signals having different phases according to the selection signal; and a pulse generating circuit for receiving at least part of the clock signals, the pulse generating circuit comprising: a latch The lock is coupled to the input signal, the clock end is coupled to a first clock signal of the clock signals, and the reset end is coupled to a second one of the clock signals a pulse signal, the output terminal outputs a one-dimensional signal; and a logic circuit for generating the pulse signal according to the bit signal and the input signal.    The clock data recovery circuit of claim 1, wherein the logic circuit is configured to generate the pulse signal according to a result of mutually exclusive or computing the bit signal and the input signal.    The clock data recovery circuit of claim 2, wherein the delay-locked loop circuit comprises a voltage-controlled delay line, the voltage-controlled delay line includes a plurality of delay units, and the second clock signal is after 1 The delay unit generates a phase of the first clock signal that leads the phase of the second clock signal by a delay time of two delay units.    The clock data recovery circuit of claim 3, wherein the selection circuit comprises: a multiplexer, the selection end receives a path control signal, the first input end is coupled to the input signal, and the second input is The terminal is coupled to the pulse signal.    The clock data recovery circuit of claim 4, wherein the logic circuit comprises: a first anti-gate, a first input end coupled to the reverse signal of the input signal, and a second input end coupled The second signal is coupled to the input signal, and the second input is coupled to the reverse signal of the second clock signal. a first inverting gate, the first input end is coupled to the reverse signal of the path control signal, the second input end is coupled to the reverse signal of the bit signal, and the third input end is coupled to the first a second anti-gate, the first input end is coupled to the reverse signal of the path control signal, the second input end is coupled to the bit signal, and the third input end is coupled An output terminal connected to the second anti-gate; and a third anti-gate having a first input coupled to the output of the first anti-gate or a second input coupled to the second anti-gate The output end of the gate, the third input end is coupled to a first circuit, and the output end outputs a reverse signal of the pulse signal.    The clock data recovery circuit of claim 5, wherein the first circuit comprises: a third reverse gate, the first input end of which is coupled to a third clock of the clock signals a second input is coupled to the second clock signal; a fourth input is coupled to the third clock signal, and the second input is coupled to the pulse signal; The fifth input gate is coupled to the output end of the third anti-gate and the second input end is coupled to the reverse signal of a fourth clock signal of the clock signals; a first inverter having an input coupled to the output of the fourth reverse gate; a second inverter having an input coupled to the output of the fifth reverse gate; a fourth inverse a first input end of the gate is coupled to the output end of the second inverter, a second input end is coupled to the output end of the first inverter, and a fifth inverse gate or a first input end thereof a reverse signal coupled to the path control signal, the second input end is coupled to the output end of the fourth inverse OR gate, and the output end is coupled to the third reverse gate The third input.    An electronic device includes a clock data recovery circuit, the clock data recovery circuit includes: a selection circuit for selecting one of an input signal and a pulse signal as a selection signal; a delay phase locked loop circuit, Coupling to the selection circuit and receiving the selection signal, the delay phase-locked loop circuit is configured to generate a plurality of clock signals having different phases according to the selection signal; and a pulse generation circuit for receiving at least some of the clocks The signal generating circuit includes: a latch, the input end of which is coupled to the input signal, the clock end is coupled to a first clock signal of the clock signals, and the reset end is coupled to the a second clock signal of the clock signals, the output terminal outputs a bit signal; and a logic circuit for generating the pulse signal according to the bit signal and the input signal.    The electronic device of claim 7, wherein the logic circuit is configured to generate the pulse signal according to a result of mutually exclusive or computing the bit signal and the input signal.    The electronic device of claim 8, wherein the delay-locked loop circuit comprises a voltage-controlled delay line, the voltage-controlled delay line includes a plurality of delay units, and the second clock signal is passed through one delay unit. The phase of the first clock signal is delayed by the delay time of the two delay units of the phase of the second clock signal.    The electronic device of claim 9, wherein the selection circuit comprises: a multiplexer, wherein the selection end receives a path control signal, the first input end is coupled to the input signal, and the second input end is coupled To the pulse signal.    The electronic device of claim 10, wherein the logic circuit comprises: a first anti-gate, the first input end of which is coupled to the reverse signal of the input signal, and the second input end is coupled to the a reverse signal of the second clock signal; a second input gate coupled to the input signal, the second input end coupled to the reverse signal of the second clock signal; The first input terminal is coupled to the reverse signal of the path control signal, the second input end is coupled to the reverse signal of the bit signal, and the third input end is coupled to the first reverse The second input is coupled to the reverse signal of the path control signal, the second input is coupled to the bit signal, and the third input is coupled to the An output terminal of the second anti-gate; and a third anti-gate, the first input end of which is coupled to the output end of the first anti-gate or the second input end is coupled to the output of the second anti-gate The third input end is coupled to a first circuit, and the output end outputs a reverse signal of the pulse signal.    The electronic device of claim 11, wherein the first circuit comprises: a third NAND gate, the first input end of which is coupled to a third clock signal of the clock signals, The second input terminal is coupled to the second clock signal, the fourth input terminal is coupled to the third clock signal, and the second input end is coupled to the pulse signal; And a first input end coupled to the output end of the third anti-gate; the second input end is coupled to a reverse signal of a fourth clock signal of the clock signals; The input end is coupled to the output end of the fourth anti-gate; a second inverter having an input coupled to the output of the fifth anti-gate; a fourth reverse or gate The first input end is coupled to the output end of the second inverter, the second input end is coupled to the output end of the first inverter, and a fifth reverse OR gate, the first input end of which is coupled to The path control signal has a reverse signal, the second input end is coupled to the output end of the fourth inverse or the gate, and the output end is coupled to the third input of the third inverse or gate End.