TW201810569A - Semiconductor device structures - Google Patents

Abstract

Semiconductor device structures are provided, The semiconductor device structures include a semiconductor substrate. An internal metal layer is disposed over the semiconductor substrate. A top-metal layer is disposed over the internal metal layer and has a first portion and a second portion separated from each other, wherein the first portion covers the internal metal layer completely, and the second portion surrounds the first portion. A passivation layer is disposed over the top metal layer, wherein the passivation layer has a hollow pattern to expose the top-metal layer.

Description

Semiconductor device structure

The present invention relates to semiconductor device structures, and more particularly to the layout of passivation layers and top metal layers of semiconductor device structures.

In recent years, semiconductor devices have developed rapidly in the fields of computers and consumer electronics. At present, semiconductor device technology has been widely accepted in the product market of metal oxide semiconductor field effect transistors, and has a high market share.

Thin-film resistors are widely used in various integrated circuits in which a poly resistor is one of the main high-resistance elements. The precision of thin film resistors has been valued in recent years in the booming of smart products, networking and automotive electronics. Although the existing semiconductor devices are sufficient for their intended use, they have not been fully met in all respects. For example, today's semiconductor devices face the problem that the resistance of the thin film resistor has an excessive drift rate, and the mechanical stress (Mechanical stress) is one of the main causes of resistance drift. For example, in the latter stage of a semiconductor device, the stress generated in each process causes the underlying resistor to have a piezoresistance effect. Therefore, how to reduce the drift rate of the resistance value of the thin film resistor by the process or structural improvement is a subject worth studying.

Some embodiments of the present disclosure relate to a semiconductor device structure including a semiconductor substrate, an inner metal layer disposed on the semiconductor substrate, and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, the first portion The inner metal layer is completely covered, the second portion surrounds the first portion, and the first portion is spaced apart from the second portion, and the passivation layer is disposed on the top metal layer, wherein the passivation layer has a hollowed out pattern to expose the top metal layer.

Further embodiments of the present disclosure relate to a semiconductor device structure including a semiconductor substrate, an inner metal layer disposed on the semiconductor substrate, a top metal layer disposed on the inner metal layer, a passivation layer disposed on the top metal layer, and a passivation layer including A passivation portion and a second passivation portion are spaced apart from the first passivation portion, wherein the second passivation portion surrounds the first passivation portion, and a void between the first passivation portion and the second passivation portion exposes the top metal layer.

100‧‧‧Semiconductor substrate

110‧‧‧Polysilicon layer

120‧‧‧ dielectric layer

130, 213, 260‧ ‧ lead holes

210‧‧‧Inner metal layer

220‧‧‧Top metal layer

222‧‧‧Part I

224‧‧‧Part II

230‧‧‧ Passivation layer

232‧‧‧ first passivation

Blocks 232a, 232b, 211a, 212a‧‧

234‧‧‧Second passivation

240‧‧‧Interlayer dielectric layer

250‧‧‧ hollowed out pattern

252‧‧‧First Knockout Area

254‧‧‧Second hollowed out area

256‧‧‧Connecting Department

300‧‧‧Semiconductor device structure

1A is a cross-sectional view showing the structure of a semiconductor device in accordance with some embodiments.

1B is a top view showing the layout of the passivation layer and the top metal layer in the semiconductor device structure as shown in FIG. 1A, in accordance with some embodiments.

2A is a cross-sectional view showing the structure of a semiconductor device in accordance with some embodiments.

2B is a top view showing the layout of the passivation layer and the top metal layer in the semiconductor device structure as shown in FIG. 2A, in accordance with some embodiments.

3A-3B is a top view showing the layout of a passivation layer in a semiconductor device structure in accordance with some embodiments.

Figure 4A shows a schematic cross-sectional view of an inner metal layer in accordance with some embodiments.

Figure 4B shows a top view of the layout of the inner metal layer as shown in Figure 4A, in accordance with some embodiments.

The layout of the semiconductor device structure of the present disclosure will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are provided to provide a brief description of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It is to be understood that the elements specifically described or illustrated may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another. It will be understood that if the illustrated device is flipped upside down, the component described on the "lower" side will be the component on the "higher" side.

Here, the terms "about" and "about" are usually expressed within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

It is noted that the present invention discloses an embodiment of the layout of the passivation layer and the top metal layer in the structure of the semiconductor device, and the above embodiments may be included in an integrated circuit (IC) such as a microprocessor, a memory element, and/or other components. The integrated circuit (IC) may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors (eg, metal-insulator-metal capacitors (MIMCAP)). ), Inductors, Diodes, Metal-Oxide-Semiconductor Field-effect transistors (MOSFETs), Complementary MOS transistors, Bi-carrier junction transistors (BJTs), Lateral Diffusion MOS transistor (LDMOS), high power MOS transistor or other type of transistor. Those of ordinary skill in the art to which the present invention pertains will appreciate that other types of semiconductor components can be used as well.

The present invention is intended to solve the problem that the resistance value of the thin film resistor in the semiconductor device is excessively large, and the embodiment of the present invention utilizes the layout between the passivation layer and the top metal layer in the semiconductor device to alleviate the unequalities in the subsequent process. The pressure is applied to avoid the piezoresistive effect of the underlying components, such as thin film resistors.

Referring to FIG. 1A, FIG. 1A is a cross-sectional view showing a semiconductor device structure 300 in accordance with some embodiments. The semiconductor device structure 300 includes a semiconductor substrate 100. The semiconductor substrate 100 comprises germanium. Alternatively, the semiconductor substrate 100 may include other elemental semiconductors, and may also include a compound semiconductor such as tantalum carbide. (silicon carbide), gallium arsenic, indium arsenide, and indium phosphide. The semiconductor substrate 100 may comprise an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the semiconductor substrate 100 includes an epitaxial layer, for example, the semiconductor substrate 100 has an epitaxial layer on the semiconductor bulk. Furthermore, the semiconductor substrate 100 may comprise a semiconductor-on-insulator (SOI) structure. For example, the semiconductor substrate 100 may comprise a buried oxide (BOX) layer by, for example, separation by implanted oxide (SIMOX) or other suitable techniques, such as wafer bonding and polishing processes. form.

The semiconductor substrate 100 also includes various p-type doped regions and/or n-type doped regions that are implanted by, for example, ion implantation and/or diffusion processes. These doped regions include n-type well regions, p-type well regions, light doped regions (LDD), heavily doped source and drain (S/D), and various channel doping profiles to make up various IC devices, such as complementary metal oxide semiconductor field effect transistors (CMOSFETs), image sensors, and/or thin film resistors. The semiconductor substrate 100 may further comprise other components, such as resistors or capacitors formed in or on the substrate.

The semiconductor substrate 100 can also include isolation features. The isolation features separate the various device regions within the semiconductor substrate 100. The isolation features comprise different structures formed by different process technologies, for example, the isolation features may comprise shallow trench isolation (STI) features. Forming the STI may include etching a trench in the semiconductor substrate 100 and filling the trench with an insulating material, such as hafnium oxide, Niobium nitride, niobium oxynitride or a combination thereof. The filled trench may have a multi-layered structure, such as a thermal oxide liner and tantalum nitride filled into the trench. Chemical mechanical polishing (CMP) may be performed to grind excess insulating material and planarize the upper surface of the spacer member.

The semiconductor device structure 300 includes a polysilicon layer 110 and a dielectric layer 120. As shown in FIG. 1A , the dielectric layer 120 is disposed on the semiconductor substrate 110 , and the polysilicon layer 110 is disposed on the semiconductor substrate 110 and located in the dielectric layer 120 . The polysilicon layer 110 is made of a germanium containing gas comprising dichlorosilane (DCS), decane (SiH ₄ ), methyl decane (SiCH ₆ ), and other suitable gases or combinations thereof. The polysilicon layer 110 can be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable processes. The dielectric layer 120 is made of tantalum nitride, hafnium oxynitride, tantalum carbide, tantalum oxide, tantalum carbide, other suitable materials, or a combination thereof, and the dielectric layer 120 can be formed by a deposition process. The deposition process includes chemical vapor deposition, physical vapor deposition, atomic layer deposition (ALD), high density plasma CVD (HDPCVD), and metal organic chemical vapor deposition (metal organic). CVD, MOCVD), remote plasma CVD (RPCVD), plasma enhanced chemical vapor deposition (PECVD), plating, other suitable methods, or combinations of the foregoing. In some embodiments, the polysilicon layer 110 has a plurality of patterned regions, one of which may serve as a gate structure (not shown) of the semiconductor device structure 130, and another portion may constitute a thin film resistor. In some embodiments, the polysilicon layer 110 can also be replaced with other semiconductor materials.

The semiconductor device structure 300 includes a via 130, as shown in FIG. As shown, the via 130 is disposed on the polysilicon layer 110 and located within the dielectric layer 120 for electrically connecting the polysilicon layer 110 to an internal metal layer 210 over the polysilicon layer 110. The via 130 includes a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (tantalum nitride, TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride , TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other suitable conductive materials or a combination of the foregoing. In some embodiments, as shown in FIG. 1A, a portion of the polysilicon layer 110 is not electrically connected to the inner metal layer 210, that is, a portion of the polysilicon layer 110 is not provided with via holes 130.

The semiconductor device structure 300 further includes a top metal layer 220, a via 260, and an interlayer dielectric (ILD) 240. As shown in FIG. 1A, an interlayer dielectric layer 240 is disposed over the dielectric layer 120. The inner metal layer 210 is disposed on the polysilicon layer 110 and electrically connected to the polysilicon layer 110 via the via 130. The top metal layer 220 is disposed on the inner metal layer 210 and electrically connected to the inner metal layer 210 through the via 260. The inner metal layer 210, the vias 260, and the top metal layer 220 can be considered as interconnect structures of the semiconductor device structure 300.

The formation of the inner metal layer 210, the via hole 260 and the top metal layer 220 may include a damascene process in which an opening of a trench and a via hole is formed in the interlayer dielectric layer 240, followed by a trench and a via hole. The opening is filled with a metal material. The metal material may be formed by electrochemical plating process, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the foregoing, or the like, metal The material may be selected from the group consisting of copper, tungsten, aluminum, silver, gold, combinations of the foregoing, or similar materials. Although only one inner metal layer 210 is illustrated in FIG. 1A, in other embodiments, the inner metal layer 210 further includes a plurality of layers of metal and via structures, and the scope of the present invention is not limited thereto.

In addition, the interlayer dielectric layer 240 may comprise a multilayer structure formed of a plurality of dielectric materials, such as hafnium oxide, tantalum nitride, hafnium oxynitride, phosphosilicate glass (PSG), borophosphosilicate. Glass, BPSG), low dielectric constant (low-k) dielectric material or other suitable dielectric material. The low-k dielectric material comprises fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, and parylene. , but not limited to, bis-benzocyclobutenes (BCB), polyimide. The interlayer dielectric layer 240 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable process. It should be noted that the interlayer dielectric layer 240 may be a single layer or a multilayer structure formed of a plurality of materials, and the scope of the present invention is not limited thereto.

As shown in FIG. 1A, the top metal layer 220 includes a first portion 222 and a second portion 224. In some embodiments, the first portion 222 completely covers the inner metal layer 210, that is, the projected area of the first portion 222 completely covers the projected area of the inner metal layer 210. The second portion 224 surrounds the first portion 222 and is separated from the first portion 222 by an interlayer dielectric layer 240. In some embodiments, from a top perspective, the first portion 222 is a solid rectangular block and the second portion 224 is an annular block. Although only the top metal layer 220 includes two blocks in FIG. 1A, in other embodiments, the second portion 224 of the top metal layer 220 may further include two or more. The first block 222 also includes other solid shapes, and the scope of the present invention is not limited thereto. In some embodiments, the inner metal layer 210 is electrically connected to the first portion 222 of the top metal layer 220 via vias 260. In some embodiments, the second portion 224 of the top metal layer 220 is not electrically connected to the inner metal layer 210.

As shown in FIG. 1A, the semiconductor device structure 300 further includes a passivation layer 230 disposed above the top metal layer 220. The passivation layer 230 is formed of an oxide such as hafnium oxide, undoped silicate glass (USG), or the like. In addition, the passivation layer 230 may also be a composite material layer, for example, the passivation layer 230 includes a ruthenium oxide layer, and a composite material layer composed of a tantalum nitride layer on the ruthenium oxide layer.

In some embodiments, the passivation layer 230 includes a first passivation portion 232 and a second passivation portion 234 having a hollowed out pattern 250 therein to expose the underlying top metal layer 220. The formation of the knockout pattern 250 includes the use of a lithographic patterning process and an etch process. The lithographic patterning process includes photoresist coating (eg, spin coating), soft baking, reticle alignment, exposure, post exposure, development of photoresist, rinsing, drying (eg, hard bake), other suitable processes, or Combination of the foregoing. In addition, the lithography process can be performed or replaced by other suitable methods, such as maskless lithography, electron-beam writing, and ion-beam writing. The etching process includes dry etching, wet etching, or other etching methods.

Next, referring to FIGS. 1A and 1B, FIG. 1B is a top view showing the layout of the passivation layer 230 and the top metal layer 220 in the semiconductor device structure 300 as shown in FIG. 1A, in accordance with some embodiments. In order to clearly show the layout of the passivation layer 230, the hollowed out pattern 250, and the top metal layer 220, other elements are omitted in FIG. 1B.

In some embodiments, the first passivation portion 232 of the passivation layer 230 completely covers the first portion 222 of the top metal layer 220 and covers the second portion 224 of the portion. The hollowed out pattern 250 exposes the second portion 224 of the top metal layer 220. As shown in FIG. 1B, the area of the first passivation portion 232 is greater than the area of the first portion 222 of the top metal layer 220, and the area of the second passivation portion 234 is less than the area of the second portion 224 of the top metal layer 220. In some embodiments, the first passivation portion 232 is a solid rectangular block, and the second passivation portion 234 is an annular block and is separated from the first passivation portion 232 by a hollowed out pattern 250. Although only the passivation layer 230 includes two blocks in FIG. 1A, in other embodiments, the second passivation portion 234 further includes more than two annular blocks, and the first passivation portion 232 also includes other solid shapes. Blocks, the scope of the present invention is not limited thereto.

The area of the knockout pattern 250 is not particularly limited. In some embodiments, the area of the hollowed out pattern 250 and the area ratio of the passivation layer 230 are less than about 25%.

Furthermore, as shown in FIG. 1A, the inner metal layer 210 is not covered by the second portion 224 of the top metal layer 220 and is not covered by the second passivation portion 234. The polysilicon layer 110 is not covered by the second portion 224 of the top metal layer 220 and is not covered by the second passivation portion 234.

Next, referring to Figures 2A-2B, Figure 2A shows a cross-sectional view of a semiconductor device structure 300 in accordance with further embodiments. 2B is a top view showing the layout of passivation layer 230 and top metal layer 200 in semiconductor device structure 300 as shown in FIG. 2A, in accordance with some embodiments. For the purpose of brevity, the elements of the 2A-2B drawings are the same as or similar to those of the above-mentioned 1A-1B, and the description thereof will not be repeated.

The difference between the embodiment shown in FIG. 2A and the embodiment shown in FIG. 1A lies in the layout of the passivation layer 230. As shown in FIG. 2A, in some embodiments, the knockout pattern 250 includes a first hollowed out area 252 and a second hollowed out area 254. The first hollowed out region 252 exposes a first portion 222 of the top metal layer 220 that is partially below the passivation layer 230, and the second hollowed out region 254 exposes the second portion 224 of the top metal layer 220 under the passivation layer 230. As shown in FIG. 2B, the second hollowed out zone 254 surrounds the first hollowed out zone 252 and is spaced apart from the first hollowed out zone 252. In some embodiments, the first passivation portion 232 covers the first portion 222 of the portion of the top metal layer 220 and the second portion 224 of the portion. In this embodiment, the first portion 222 of the top metal layer 220 is not completely covered by the first passivation portion 232. As shown in FIG. 2A, the polysilicon layer 110 corresponds to the first hollowed out region 252 of the hollowed out pattern 250, that is, the polysilicon layer 110 is not covered by the passivation layer 230. In this embodiment, the first passivation portion 232 is a hollowed annular block and the first portion 222 of the top metal layer 220 is exposed via the first hollowed out region 252.

The area of the first hollowed out area 252 is not particularly limited. In some embodiments, the area of the first hollowed out area 252 is greater than the area ratio of the first portion 222 of the top metal layer 220 by more than about 50%.

Next, referring to FIGS. 3A-3B, FIGS. 3A-3B are top views showing the layout of the passivation layer 230 of the semiconductor device structure 300, in accordance with further embodiments. For the sake of brevity, the 3A-3B diagram only shows the block included in the passivation layer 230 and the hollowed out area included in the hollowed out pattern 250.

As shown in FIG. 3A, in some embodiments, the hollowed out pattern 250 further includes one or more connections 256 that are coupled to the second hollowed out area 254 by a joint 256. In this embodiment, the first passivation portion 232 is composed of a plurality of Consisting of blocks 232a. As shown in FIG. 3A, in some embodiments, each of the blocks 232a of the first passivation portion 232 has an L shape. These blocks 232a have a center of rotational symmetry such that the pattern of the blocks 232a (i.e., the layout of the first passivation portion 232) is rotated by 360°/n (n is an integer greater than one) After that, you can get the same pattern. For example, in the embodiment shown in Fig. 3A, the four blocks 232a of the first passivation portion 232 are centered on the center of rotation symmetry with the center of the four blocks 232a, and after rotating by 90, the same pattern can be obtained.

As shown in FIG. 3B, in other embodiments, the corners of the annular first passivation portion 232 of FIG. 2B may be etched away to connect the first hollowed out region 252 with the second hollowed out region 254, ie, A portion of the first passivation portion 232 where the corners are etched away may be considered as the connection region 256. In this embodiment, the first passivation portion 232 is comprised of a plurality of discrete blocks 232b. As shown in FIG. 3B, each of the blocks 232b of the first passivation portion 232 is rectangular. These blocks 232b have a center of rotational symmetry such that the pattern of the blocks 232b (i.e., the layout of the first passivation portion 232) is obtained by rotating 360°/n (n is an integer greater than 1). picture of. For example, in the embodiment shown in Fig. 3B, the four blocks 232b of the first passivation portion 232 are centered on the center of rotation symmetry with the center of the four blocks 232b, and after rotating by 90, the same pattern can be obtained.

Although the embodiment of the 3A-3B diagram only shows that the first passivation portion 232 has four blocks, in other embodiments, the first passivation portion 232 further includes other different numbers of blocks, and each block Other shapes are also included, and the scope of the present invention is not limited thereto.

Referring to Figures 4A-4B, Figure 4A shows, in accordance with some embodiments, A cross-sectional view of the inner metal layer, and FIG. 4B shows a top view of the layout of the inner metal layer as shown in FIG. 4A, in accordance with some embodiments. For the sake of brevity, FIG. 4B only shows the plurality of blocks included in the first inner metal layer 211 and the second inner metal layer 212 included in the inner metal layer 210.

In some embodiments, as shown in FIG. 4A, the inner metal layer 210 includes a first inner metal layer 211, a second inner metal layer 212 disposed on the first inner metal layer 211, and a via 213. The first inner metal layer The second inner metal layer 212 is separated from the second inner metal layer 212 by the interlayer dielectric layer 240 and connected by the via holes 213. As shown in FIG. 4B, in some embodiments, the first inner metal layer 211 and the second inner metal layer 212 are composed of a plurality of discontinuous blocks, for example, the first inner metal layer 211 is composed of a plurality of first directions. The extended inner block 212 is composed of a plurality of blocks 212a extending in the second direction, and the first partial direction is perpendicular to the second direction. In some embodiments, the shape of the block 211a and the block 212a includes a sheet shape, a strip shape, a block shape, or a combination thereof. In some embodiments, block 211a and block 212a are perpendicular to one another, and in some embodiments, block 211a and block 212a may be parallel to each other. Further, as shown in Fig. 4A, a part of the block 212a is connected to the block 211a by the via hole, and a part of the block 212a is not connected to the block 211a. In some embodiments, a portion of the block 211a and the block 212a may also be disposed directly below the second portion 224 of the top metal layer 220 and connected to the second portion 224 of the top metal layer 220 via the via 213.

Although the embodiment of FIG. 4A-4B only shows that the inner metal layer 210 includes the first inner metal layer 211, the second inner metal layer 212, and the via 213, in other embodiments, the inner metal layer 210 further includes other The metal layer or the via hole, and each metal layer is also composed of a sheet, a strip, a block or a combination of the above, and the scope of the present invention is not limited thereto.

The passivation layer of the semiconductor device structure shown in the embodiment of the present invention has a layout manner of various hollow patterns, which reduces the stress caused by the passivation layer, and the top metal layer is disposed on the hollowed out pattern of the passivation layer. Below the zone, the effect of protecting the underlying components, such as the inner metal layer, can be achieved. In addition, the layout of the top metal layer is designed in a strip shape, a sheet shape or a ring shape as a buffer structure between the passivation layer and the semiconductor substrate, and the unequal pressure is generated in the back-end process to prevent the underlying components from being pressed. Resistance effect. The reason why the resistance value of the thin film resistor of the conventional semiconductor device is excessively large is mainly due to the contribution of the piezoresistive effect. The layout of the passivation layer and the top metal layer of the semiconductor device structure of the present disclosure can prevent the piezoresistive of the component under the passivation layer. Effect, therefore, the drift value of the resistance value of the thin film resistor of the semiconductor device of the present disclosure is lower than that of the conventional semiconductor device. For example, the thin film resistor of the semiconductor device of the present disclosure has a tolerance of drift of resistance value of less than 5%, and the resistance of the thin film resistor of the conventional semiconductor device has a tolerance of more than 10%.

Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure It is understood that the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

Claims (20)

A semiconductor device structure comprising: a semiconductor substrate; an inner metal layer disposed on the semiconductor substrate; a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion Wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is spaced apart from the second portion; and a passivation layer disposed on the top metal layer, wherein the passivation layer There is a hollowed out pattern to expose the top metal layer. The semiconductor device structure of claim 1, further comprising: a polysilicon layer between the semiconductor substrate and the inner metal layer, wherein the polysilicon layer is not covered by the second portion of the top metal layer. The semiconductor device structure of claim 2, wherein the hollowed out pattern exposes the first portion of the top metal layer, and the polysilicon layer is not covered by the passivation layer. The semiconductor device structure of claim 2, wherein the hollowed out pattern exposes the second portion of the top metal layer, and the polysilicon layer is covered by the passivation layer. The semiconductor device structure of claim 2, wherein a portion of the polysilicon layer is a thin film resistor. The semiconductor device structure of claim 1, wherein the inner metal layer is not covered by the second portion of the top metal layer. The semiconductor device structure of claim 1, wherein the hollowing out The pattern includes: a first hollowed out area; and a second hollowed out area, wherein the second hollowed out area surrounds the first hollowed out area. The semiconductor device structure of claim 7, wherein the first hollowed out region exposes the first portion of the top metal layer, and the second hollowed out region exposes the second portion of the top metal layer. The semiconductor device structure of claim 7, wherein the hollowed out pattern further comprises: a connecting portion, wherein the first hollowed out area and the second hollowed out area are connected by the connecting portion. The semiconductor device structure of claim 1, wherein the inner metal layer comprises: a first inner metal layer; and a second inner metal layer disposed on the first inner metal layer, wherein the first The metal layer and the second metal layer are composed of discontinuous blocks. The semiconductor device structure of claim 10, wherein the first metal layer is perpendicular to the second metal layer. . A semiconductor device structure comprising: a semiconductor substrate; an inner metal layer disposed on the semiconductor substrate; a top metal layer disposed on the inner metal layer; and a passivation layer disposed on the top metal layer, the The passivation layer includes a first passivation portion and a second passivation portion spaced apart from the first passivation portion, wherein the second passivation portion surrounds the first passivation portion, and the first passivation portion A void between the second passivation portion exposes the top metal layer. The semiconductor device structure of claim 12, wherein the top metal layer has a first portion and a second portion, wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and The first portion is spaced apart from the second portion. The semiconductor device structure of claim 13, wherein the first passivation portion of the passivation layer covers the first portion of the top metal layer and a portion of the second portion of the top metal layer. The semiconductor device structure of claim 14, wherein the first passivation portion of the passivation layer completely covers the first portion of the top metal layer. The semiconductor device structure of claim 14, wherein the first portion of the top metal layer is not completely covered by the first passivation portion of the passivation layer. The semiconductor device structure of claim 16, wherein the first passivation portion of the passivation layer is composed of a plurality of discontinuous blocks. The semiconductor device structure of claim 17, wherein each of the blocks comprises an L-shape or a rectangle, the blocks are arranged in a ring shape, and the blocks have a center of rotational symmetry. . The semiconductor device structure of claim 14, wherein the first passivation portion of the passivation layer comprises a ring shape. The semiconductor device structure of claim 12, further comprising: a polysilicon layer disposed between the semiconductor substrate and the inner metal layer, wherein the polysilicon layer is not covered by the passivation layer, and a portion of the polysilicon layer is Thin film resistors.