TW201805974A

TW201805974A - Capacitor and method for producing capacitor

Info

Publication number: TW201805974A
Application number: TW106125060A
Authority: TW
Inventors: 青木健介; 荒川建夫; 井上徳之; 伊藤賢; 神凉康一; 佐伯洋昌; 岩地直樹
Original assignee: 村田製作所股份有限公司
Priority date: 2016-07-29
Filing date: 2017-07-26
Publication date: 2018-02-16
Also published as: TWI661448B; WO2018021115A1

Abstract

In the present invention, an element body 2 is formed only on one main surface of a foil-like conductive substrate 1. The element body 2 is provided with: a porous substrate 4 comprising a conductive material having fine pores; a dielectric layer 5 formed on a prescribed region of a surface of the porous substrate 4 including the inner surface of the pores; and a conductive section 6 formed on the dielectric layer 5. First and second electrically insulated terminal electrodes 3a, 3b are formed on the main surface of the element body 2. The first terminal electrode 3a is electrically connected to the conductive section 6, while the second terminal electrode 3b is electrically connected to the conductive substrate 1 via a via conductor 12. Due to this configuration, a compact and large-capacity capacitor, the height of which can be further lowered, and a method for producing the same are realized.

Description

Capacitor and manufacturing method thereof

本發明係關於一種電容器、及該電容器之製造方法，更詳細而言關於一種使用具有微小之細孔之多孔基體之電容器及該電容器之製造方法。The present invention relates to a capacitor and a method for manufacturing the capacitor, and more particularly to a capacitor using a porous substrate having minute pores and a method for manufacturing the capacitor.

目前，於個人電腦或攜帶型資訊終端等電子機器，搭載有較多之各種電容器。此種電容器中，固體電解電容器係將陽極氧化之氧化皮膜作為介電層，故而可使介電層薄層化，從而作為能夠小型、大容量化之電容器被廣泛使用。然而，於上述固體電解電容器中，利用以Nb等閥金屬(valve metals)為主體之多孔質燒結體形成陽極，故而缺陷較多且機械強度較差。而且，因藉由陽極氧化而形成介電層，故而對固體電解電容器賦予極性，從而存在使用性較差之類的缺點。因此，於專利文獻1中，如圖16所示，提出有一種電容器，其具備：多孔金屬基體103，其具有空隙率較大且具有微小之細孔之高空隙部101、及空隙率小於該高空隙部101之低空隙部102；剖面コ字狀之導電部104，其與多孔金屬基體103電性連接；保護膜105，其形成於多孔金屬基體103之兩主面；第1端子電極106a，其與多孔金屬基體103之低空隙部102電性連接；及第2端子電極106b，其與導電部104電性連接。於該專利文獻1中，多孔金屬基體103係於金屬芯部之兩主面形成高空隙部101及低空隙部102，並且於包含該高空隙部101之細孔內表面之表面特定區域形成介電層，且於介電層之表面形成有上述導電部104。而且，意圖利用高空隙部101、介電層、及導電部104取得靜電電容，且利用上述低空隙部102確保機械強度。[先前技術文獻][專利文獻][專利文獻1]國際公開2015/118901號(技術方案1～11，圖1、2等])Currently, various electronic devices such as personal computers and portable information terminals are equipped with various capacitors. Among such capacitors, a solid electrolytic capacitor uses an anodized oxide film as a dielectric layer, so that the dielectric layer can be thinned, and thus it is widely used as a capacitor capable of miniaturization and large capacity. However, in the solid electrolytic capacitor described above, the anode is formed by using a porous sintered body mainly composed of valve metals such as Nb, and therefore has many defects and poor mechanical strength. In addition, since a dielectric layer is formed by anodization, there is a disadvantage that the solid electrolytic capacitor is polarized, and thus the workability is poor. Therefore, in Patent Document 1, as shown in FIG. 16, a capacitor is proposed, which includes a porous metal substrate 103 having a high void portion 101 having a large porosity and minute pores, and a porosity smaller than this. Low void portion 102 with high void portion 101; conductive portion 104 with a U-shaped cross section that is electrically connected to porous metal substrate 103; a protective film 105 formed on both main surfaces of porous metal substrate 103; first terminal electrode 106a Is electrically connected to the low-void portion 102 of the porous metal substrate 103; and the second terminal electrode 106b is electrically connected to the conductive portion 104. In this patent document 1, a porous metal substrate 103 forms a high void portion 101 and a low void portion 102 on both main surfaces of a metal core portion, and forms an intermediary region on a specific surface area of the inner surface of the pores including the high void portion 101. An electrical layer, and the conductive portion 104 is formed on the surface of the dielectric layer. In addition, it is intended to obtain the electrostatic capacitance using the high-void portion 101, the dielectric layer, and the conductive portion 104, and to secure the mechanical strength by using the low-void portion 102 described above. [Prior Art Document] [Patent Document] [Patent Document 1] International Publication No. 2015/118901 (Technical Solutions 1 to 11, Figures 1, 2 and the like)

[發明所欲解決之問題]然而，於專利文獻1中，即使利用形成於金屬芯部之兩主面之高空隙部101取得靜電電容，亦因高空隙部101形成於金屬芯部之兩主面，故而電容器之低背化存在極限。又，如上所述，因將高空隙部101形成於金屬芯部之兩主面，故而，於構造上，必須自兩端部之端面至側面部形成端子電極(第1及第2端子電極106a、106b)，亦就該方面而言，低背化存在極限，安裝性亦較差。又，於專利文獻1中，於製造過程中必須對多孔金屬基材103自兩面實施各種加工，需要三維之形成製程，從而存在製造步驟繁雜之類的問題。本發明係鑒於此種情況而完成者，其目的在於提供能夠進一步低背化之小型、大容量之電容器、及可高效率地製作電容器之電容器之製造方法。[解決問題之技術手段]為達成上述目的，本發明之電容器之特徵在於：於箔狀之導電性基板之一主面形成元件本體，並且該元件本體具備：多孔基體，其包含具有微小之細孔之導電材料；介電層，其形成於包含上述細孔之內表面之上述多孔基體之表面特定區域；及導電部，其形成於上述介電層上；於上述元件本體之主面，形成電性絕緣之一對端子電極，上述一對端子電極中之一端子電極電性連接於上述導電部，另一方面，另一端子電極電性連接於上述導電性基板。藉此，能夠使用形成於元件本體之一主面上之一對端子電極進行基板安裝，從而電容器單體之處理變得容易。而且，因能夠將元件本體僅形成於導電性基板之一主面，故可獲得能夠進一步低背化且更小型化之大容量之電容器。又，本發明之電容器較佳為上述多孔基體具有高空隙部，其有助於靜電電容之取得；及低空隙部，其形成於該高空隙部之至少兩端部且空隙率低於上述高空隙部；且上述低空隙部至少形成於上述元件本體之兩端部，於該情形時，較佳為，上述高空隙部被上述低空隙部圍繞。藉此，因高空隙部被低空隙部包圍，故能夠確保機械強度。又，本發明之電容器較佳為於上述一端子電極與上述導電性基板之間介置有包括絕緣性材料之保護層。藉此，能夠確保電容器之更進一步之機械強度。又，本發明之電容器較佳為上述另一端子電極經由第1通孔導體而與上述導電性基板電性連接。進而，本發明之電容器較佳為上述一對端子電極於上述元件本體之主面上形成為同一平面。藉此，能夠抑制於安裝時電容器傾斜。再者，作為用以使一對端子電極形成為同一平面之方法，可採用調整上述保護層之厚度，或者於第1端子電極與導電部之間介置絕緣層等之方法。又，本發明之電容器較佳為將上述導電部分斷為2個，並且於分斷所得之各導電部之表面形成中間電極層，且於上述中間電極層與上述一對端子電極間介置第1絕緣層，將上述一端子電極與上述中間電極層中之一上述中間電極層電性連接，並且將上述另一端子電極經由另一上述中間電極層而與上述導電性基板電性連接，於該情形時，較佳為，將上述一端子電極經由貫通上述第1絕緣層之第2通孔導體而與上述一中間電極層電性連接，將上述另一端子電極經由貫通上述第1絕緣層之第3通孔導體而與上述另一中間電極層電性連接。可藉由如此設置中間電極層進行再配線化，而將自由之形狀之端子電極形成於元件本體上。又，可藉由於中間電極層與端子電極間介置絕緣層，而一邊確保低背化一邊緩和物理性衝擊，從而能夠提昇機械耐久性。又，本發明之電容器較佳為於上述分斷所得之導電部中之一導電部與形成於該導電部上之中間電極層之間介置有第2絕緣層。藉此，可更加緩和物理性衝擊，從而能夠進一步提昇機械耐久性。又，本發明之電容器較佳為於上述導電性基板之另一主面設置有保護構件。藉此，可獲得機械強度能夠進一步提昇之具有更良好之機械耐久性之電容器。又，本發明之電容器較佳為上述介電層以原子層單位沈積而成。藉此，可獲得緻密之介電層，從而可抑制如同固體電解電容器中之陽極氧化般產生缺陷導致絕緣性降低之情形，從而可獲得絕緣性良好之電容器。又，可獲得亦不賦予極性且具有良好可靠性之使用性良好之小型、大容量之電容器。又，本發明之電容器較佳為上述導電部係填充於上述細孔之內部而成。進而，本發明之電容器較佳為上述導電部係以於上述細孔之內部沿著上述介電層之方式形成。即，無論導電部填充於細孔之內部而形成之情形、及以於上述細孔之內部沿著介電層之方式形成之情形之任一情形時，均能夠利用大量之細孔取得靜電電容。又，本發明之電容器較佳為上述導電性基板及上述多孔基體包括金屬材料且一體地形成。又，本發明之電容器較佳為上述導電部由金屬材料及導電性化合物中之任一者形成，進而較佳為上述導電性化合物包含金屬氮化物及金屬氮氧化物。於由低電阻之金屬材料形成導電部之情形時，能夠進一步降低ESR(Equivalent Series Resistance，等效串聯電阻)，又，於由金屬氮化物或金屬氮氧化物等導電性化合物形成導電部之情形時，能夠將具有良好之均一性之導電部形成至細孔內部為止。又，本發明之電容器之製造方法之特徵在於包含如下步驟：準備於箔狀之導電性基板之一主面包含形成有微小之細孔之多孔性之導電材料的集合基體；對上述集合基體進行加工，於該集合基體之特定區域形成高空隙部；將包括絕緣性材料之保護層形成於上述導電性基板上；於包含上述細孔之內表面之上述集合基體之表面特定區域形成介電層；於上述介電層之表面形成導電部；形成貫通上述導電部及上述保護層之通孔，於該通孔中填充導電材料形成第1通孔導體；將上述導電部分斷為不包含上述第1通孔導體而包含上述高空隙部之第1區域及包含上述第1通孔導體之第2區域；於上述第1區域之主面形成連接於上述導電部之一端子電極，且於上述第2區域之主面形成經由上述第1通孔導體連接於上述導電性基板之另一端子電極，製作電性絕緣之一對端子電極；及於實施上述一系列之步驟之後，將上述集合基體單片化。又，本發明之電容器之製造方法之特徵在於包含如下步驟：準備於導電性基板之一主面包含形成有微小之細孔之多孔性之導電材料的集合基體；對上述集合基體進行加工，於該集合基體之特定區域形成高空隙部；將包括絕緣性材料之保護層形成於上述導電性基板上；於包含上述細孔之內表面之上述集合基體之表面特定區域形成介電層；於上述介電層之表面形成導電部；於上述導電部上形成中間電極層；形成貫通上述中間電極層、上述導電部及上述保護層之通孔，至少於上述通孔之內面成膜導電性薄膜，製作第1通孔導體；將上述導電部及上述中間電極層分斷為不包含上述第1通孔導體而包含上述高空隙部之第1區域及包含上述第1通孔導體之第2區域；於包含上述第1區域與第2區域之間隙之上述中間電極層之表面形成第1絕緣層；將電性絕緣之一對端子電極形成於上述第1絕緣層上；製作使上述一對端子電極中之一端子電極與上述第1區域之中間電極層電性導通之第2通孔導體，且製作使另一端子電極與上述第2區域之中間電極層電性導通之第3通孔導體；及於實施上述一系列之步驟之後，將上述集合基體單片化。於該情形時，較佳為，包含於上述第2區域中將第2絕緣層形成於上述導電部與上述中間電極層之間之步驟。又，本發明之電容器之製造方法較佳為調整上述保護層之厚度，將上述一對端子電極以成為同一平面之方式形成。又，本發明之電容器之製造方法較佳為藉由原子層沈積法而形成上述介電層。進而，本發明之電容器之製造方法較佳為藉由原子層沈積法而形成上述導電部。[發明之效果]根據本發明之電容器，於箔狀之導電性基板之一主面形成元件本體，並且該元件本體具備多孔基體，其包含具有微小之細孔之導電材料；介電層，其形成於包含上述細孔之內表面之上述多孔基體之表面特定區域；及導電部，其形成於上述介電層上；且於上述元件本體之主面，形成電性絕緣之一對端子電極，上述一對端子電極中之一端子電極電性連接於上述導電部，另一方面，另一端子電極電性連接於上述導電性基板，故而能夠使用形成於元件本體之一主面上之一對端子電極進行基板安裝，且作為電子零件之電容器單體之操作變得容易。而且，能夠將元件本體僅形成於導電性基板之一主面，故而能夠獲得可更進一步低背化之更小型化之大容量之電容器。又，根據本發明之電容器之製造方法，包含如下步驟：準備上述集合基體；形成高空隙部；將保護層形成於導電性基板上；形成介電層；形成導電部；形成第1通孔導體；將上述保護層分斷為第1區域與第2區域；獲得一對端子電極；及將集合基體單片化；故而，於集合基體之狀態下僅對導電性基板之一主面側實施加工處理即可，從而可使加工製程簡化，能夠以高效率獲得低背化之小型、大容量之電容器。又，關於包含形成中間連接層之步驟等之情形時亦情況相同，於集合基體之狀態下僅對導電性基板之一主面側實施加工處理即可，從而可使加工製程簡化，能夠容易地製造藉由再配線化而具有自由形狀之端子電極之電容器。[Problems to be Solved by the Invention] However, in Patent Document 1, even if the electrostatic capacitance is obtained by using the high void portion 101 formed on both main surfaces of the metal core portion, the high void portion 101 is formed on both main portions of the metal core portion. Surface, so there is a limit to the low backing of the capacitor. As described above, since the high void portion 101 is formed on both main surfaces of the metal core portion, a terminal electrode (first and second terminal electrodes 106a) must be formed from the end surface to the side surface portion of both ends in the structure. 106b). In this respect, there is a limit to low backing, and installation is also poor. Furthermore, in Patent Document 1, various processes must be performed on both sides of the porous metal substrate 103 during the manufacturing process, and a three-dimensional formation process is required, which causes problems such as complicated manufacturing steps. The present invention has been made in view of such a situation, and an object thereof is to provide a capacitor having a small size and a large capacity which can be further downsized, and a method for manufacturing a capacitor capable of efficiently manufacturing the capacitor. [Technical means to solve the problem] In order to achieve the above-mentioned object, the capacitor of the present invention is characterized in that an element body is formed on one of the main surfaces of a foil-shaped conductive substrate, and the element body includes: a porous substrate, which includes fine particles. Conductive material of pores; a dielectric layer formed on a specific region of the surface of the porous substrate including the inner surface of the pores; and a conductive portion formed on the dielectric layer; formed on the main surface of the element body One pair of terminal electrodes that are electrically insulated, one of the pair of terminal electrodes is electrically connected to the conductive portion, and the other terminal electrode is electrically connected to the conductive substrate. Thereby, the terminal electrodes can be mounted on the substrate using one of the main surfaces formed on the element body, and the handling of the capacitor unit becomes easy. In addition, since the element body can be formed only on one main surface of the conductive substrate, a capacitor having a large capacity which can be further reduced in size and reduced in size can be obtained. Further, in the capacitor of the present invention, it is preferable that the porous substrate has a high void portion, which is helpful for obtaining an electrostatic capacitance; and a low void portion, which is formed on at least both end portions of the high void portion and has a void ratio lower than the above-mentioned high. The gap portion is formed at least at both end portions of the element body. In this case, it is preferable that the high gap portion is surrounded by the low gap portion. Thereby, since the high void portion is surrounded by the low void portion, mechanical strength can be secured. In the capacitor of the present invention, a protective layer including an insulating material is preferably interposed between the one terminal electrode and the conductive substrate. Thereby, further mechanical strength of the capacitor can be ensured. In the capacitor of the present invention, it is preferable that the other terminal electrode is electrically connected to the conductive substrate through a first via-hole conductor. Furthermore, in the capacitor of the present invention, it is preferable that the pair of terminal electrodes are formed on the same plane on the main surface of the element body. This makes it possible to suppress the capacitor from being tilted during mounting. Further, as a method for forming a pair of terminal electrodes on the same plane, a method of adjusting the thickness of the protective layer or interposing an insulating layer between the first terminal electrode and the conductive portion may be adopted. Further, in the capacitor of the present invention, it is preferable that the conductive portion is cut into two, an intermediate electrode layer is formed on the surface of each conductive portion obtained by the cutting, and a third electrode is interposed between the intermediate electrode layer and the pair of terminal electrodes. An insulating layer, electrically connecting the one terminal electrode to one of the intermediate electrode layers, and electrically connecting the other terminal electrode to the conductive substrate via the other intermediate electrode layer, and In this case, it is preferable that the one terminal electrode is electrically connected to the one intermediate electrode layer through a second through-hole conductor penetrating the first insulating layer, and the other terminal electrode is penetrated through the first insulating layer. The third via-hole conductor is electrically connected to the other intermediate electrode layer. By providing the intermediate electrode layer in this way for rewiring, a free-form terminal electrode can be formed on the element body. In addition, since an insulating layer is interposed between the intermediate electrode layer and the terminal electrode, physical impact can be mitigated while ensuring low backing, thereby improving mechanical durability. In the capacitor of the present invention, it is preferable that a second insulating layer is interposed between one of the conductive portions obtained by the above-mentioned division and the intermediate electrode layer formed on the conductive portion. Thereby, physical impact can be more mitigated, and mechanical durability can be further improved. In the capacitor of the present invention, a protective member is preferably provided on the other main surface of the conductive substrate. Thereby, a capacitor having a better mechanical durability and a further improved mechanical strength can be obtained. In the capacitor of the present invention, it is preferable that the above-mentioned dielectric layer is deposited in atomic layer units. Thereby, a dense dielectric layer can be obtained, thereby suppressing the occurrence of defects such as anodic oxidation in a solid electrolytic capacitor, which can cause a reduction in insulation, and a capacitor with good insulation can be obtained. In addition, a small and large-capacity capacitor having good usability without imparting polarity and having good reliability can be obtained. In the capacitor of the present invention, it is preferable that the conductive portion is filled in the fine hole. Furthermore, in the capacitor of the present invention, it is preferable that the conductive portion is formed along the dielectric layer inside the pores. That is, regardless of the case where the conductive portion is formed by filling the inside of the pores and the case where the conductive portion is formed along the dielectric layer, the electrostatic capacitance can be obtained using a large number of pores. . In the capacitor of the present invention, it is preferable that the conductive substrate and the porous substrate include a metal material and are integrally formed. In the capacitor of the present invention, it is preferable that the conductive portion is formed of any one of a metal material and a conductive compound, and it is more preferable that the conductive compound includes a metal nitride and a metal oxynitride. When the conductive portion is formed of a metal material with low resistance, the ESR (Equivalent Series Resistance) can be further reduced, and when the conductive portion is formed of a conductive compound such as metal nitride or metal oxynitride In this case, a conductive portion having good uniformity can be formed up to the inside of the pores. The method for manufacturing a capacitor of the present invention is characterized by comprising the steps of: preparing an aggregate base body including a porous conductive material having minute pores formed on one main surface of a foil-shaped conductive substrate; and performing the above-mentioned aggregate base body. Processing to form a high void portion in a specific region of the aggregate substrate; forming a protective layer including an insulating material on the conductive substrate; forming a dielectric layer on a specific region of the surface of the aggregate substrate including the inner surface of the pores Forming a conductive portion on the surface of the dielectric layer; forming a through hole penetrating the conductive portion and the protective layer, and filling the through hole with a conductive material to form a first through-hole conductor; breaking the conductive portion to not include the first 1 through-hole conductor including a first region including the high-void portion and a second region including the first through-hole conductor; a terminal electrode connected to one of the conductive portions is formed on a main surface of the first region, and The main surface of the 2 area is formed with another terminal electrode connected to the conductive substrate through the first through-hole conductor, to make a pair of terminal electrodes for electrical insulation; After the above-described embodiment to a series of steps, the monolithic matrix of said set. The capacitor manufacturing method of the present invention is characterized by including the following steps: preparing an aggregate base body including a porous conductive material having minute pores formed on one main surface of the conductive substrate; processing the aggregate base body, and A high void portion is formed in a specific region of the collective substrate; a protective layer including an insulating material is formed on the conductive substrate; a dielectric layer is formed in a specific region of the surface of the collective substrate including the inner surface of the pores; A conductive portion is formed on the surface of the dielectric layer; an intermediate electrode layer is formed on the conductive portion; a through hole penetrating the intermediate electrode layer, the conductive portion, and the protective layer is formed, and a conductive film is formed at least on the inner surface of the through hole. To produce a first via-hole conductor; divide the conductive portion and the intermediate electrode layer into a first region including the high-void portion and not including the first via-hole conductor, and a second region including the first via-hole conductor ; Forming a first insulating layer on the surface of the intermediate electrode layer including a gap between the first region and the second region; electrically insulating one pair of terminals Formed on the first insulating layer; manufacturing a second via-hole conductor that electrically connects one of the terminal electrodes of the pair of terminal electrodes and the intermediate electrode layer in the first region to the other, and manufacturing the other terminal electrode and the first The third through-hole conductor in which the intermediate electrode layer in region 2 is electrically conductive; and after performing the above-mentioned series of steps, the above-mentioned aggregate substrate is singulated. In this case, it is preferable to include a step of forming a second insulating layer between the conductive portion and the intermediate electrode layer in the second region. In the method for manufacturing a capacitor of the present invention, the thickness of the protective layer is preferably adjusted, and the pair of terminal electrodes are formed so as to be on the same plane. In the capacitor manufacturing method of the present invention, the dielectric layer is preferably formed by an atomic layer deposition method. Furthermore, in the method for manufacturing a capacitor of the present invention, it is preferred that the conductive portion is formed by an atomic layer deposition method. [Effect of the Invention] According to the capacitor of the present invention, an element body is formed on one of the main surfaces of a foil-shaped conductive substrate, and the element body is provided with a porous substrate containing a conductive material having minute pores; a dielectric layer, which A specific area of the surface of the porous substrate formed on the inner surface of the pores; and a conductive portion formed on the dielectric layer; and a pair of terminal electrodes for electrical insulation formed on the main surface of the element body, One terminal electrode of the pair of terminal electrodes is electrically connected to the conductive portion, and the other terminal electrode is electrically connected to the conductive substrate. Therefore, a pair of terminal electrodes formed on one main surface of the element body can be used. The terminal electrodes are mounted on a substrate, and handling as a capacitor unit for electronic parts becomes easy. Furthermore, since the element body can be formed only on one main surface of the conductive substrate, it is possible to obtain a capacitor having a large capacity which can be further reduced in size and reduced in size. In addition, the method for manufacturing a capacitor according to the present invention includes the following steps: preparing the above-mentioned aggregate base; forming a high void portion; forming a protective layer on a conductive substrate; forming a dielectric layer; forming a conductive portion; forming a first through-hole conductor ; Dividing the protective layer into the first region and the second region; obtaining a pair of terminal electrodes; and singulating the collective substrate; therefore, only one main surface side of the conductive substrate is processed in the state of the collective substrate. It can be processed, thereby simplifying the manufacturing process, and obtaining a low-profile, small-capacity capacitor with high efficiency. The same applies to the case where a step of forming an intermediate connection layer is included. In the state of collecting the substrate, only one main surface side of the conductive substrate may be processed. This simplifies the processing process and makes it easy. A capacitor having a free-form terminal electrode by rewiring is manufactured.

其次，對本發明之實施形態進行詳細說明。圖1係模式性表示本發明之電容器之一實施形態(第1實施形態)之剖視圖，圖2係圖1之俯視圖。該電容器係於箔狀之導電性基板1之一主面形成元件本體2，且於上述元件本體2之主面形成有電性絕緣之一對端子電極(第1端子電極3a、第2端子電極3b)。元件本體2具有包括導電材料之多孔基體4、形成於多孔基體4之表面之介電層5、及形成於該介電層5上之導電部6。具體而言，多孔基體4具有：高空隙部7，其有助於靜電電容之取得，且空隙率較大；及低空隙部8，其以圍繞該高空隙部7之方式形成，且空隙率小於高空隙部7。又，於低空隙部8上形成包括絕緣性材料之保護層9，進而於第1及第2端子電極3a、3b與導電部6之間，介置有用以鍍覆形成下述通孔導體(第1通孔導體)12之籽晶電極層11。再者，導電性基板1及多孔基體4(高空隙部7、低空隙部8)係如下所述加工集合基體而一體地形成。圖3係表示圖1之A部詳情之放大剖視圖。於導電性基板1上形成具有微小之細孔7a之高空隙部7，且於該細孔7a之內表面以沿著該內表面之方式形成有介電層5。又，於介電層5上以封閉細孔7a之方式形成導電部6，細孔7a係由形成導電部6之材料填充，並且以沿著籽晶電極層11之方式形成於高空隙部7上。而且，於本實施形態中，由高空隙部7、介電層5及導電部6取得靜電電容。再者，介電層5係以原子層單位沈積而成，藉此緻密地成膜，故而與如固體電解電容器般利用陽極氧化形成介電層之情形不同，缺陷較少且絕緣性良好。又，因未被賦予極性，故而能夠獲得使用性良好之電容器。圖4係表示圖1之B部詳情之放大剖視圖。於導電性基板1上以圍繞高空隙部7之方式形成低空隙部8，且進而於低空隙部8上以圍繞高空隙部7之方式亦形成保護層9、介電層5、導電部6、及籽晶電極層11。而且，於元件本體2之一端面附近形成有使第2端子電極3b與低空隙部8能夠電性導通之通孔導體(第1通孔導體)12。該通孔導體12係形成於將導電部6、介電層5及保護層9貫通之通孔內。即，於通孔之內面成膜籽晶電極層11，且於籽晶電極層11之內面填充形成第2端子電極3b之導電性材料14，由籽晶電極層11與導電性材料14形成通孔導體12。又，於低空隙部8上以如至少嵌入至保護層9之一部分之形態形成有槽部15。而且，端子電極、籽晶電極層11、導電部6、及介電層5係藉由槽部15而分斷為第1區域31與第2區域32之2個區域，藉此，將第1及第2端子電極3a、3b電性絕緣而形成。而且，於該實施形態中，高空隙部7上之第1端子電極3a與低空隙部8上之第1端子電極3a係以具有階差d之方式形成。此處，高空隙部7之空隙率並無特別限定，但根據取得所期望之靜電電容之觀點，較佳為30～80%，更佳為35～65%。另一方面，低空隙部8之空隙率根據確保所期望之機械強度觀點，較佳為25%以下，更佳為10%以下，亦可為不存在空隙之0%。再者，高空隙部7之製作方法並無特別限定，例如，如下所述可藉由蝕刻法、燒結法、去合金化法等而製造，且可將藉由該等製法製作而成之金屬蝕刻箔、燒結體、多孔金屬體等用作高空隙部7。高空隙部7之厚度並無特別限定，但根據確保機械強度同時實現所期望之小型化之觀點，較佳為10～300 μm，更佳為30～150 μm，進而較佳為30～80 μm。又，低空隙部8可如下所述地藉由對形成有高空隙部7之導電性基板1實施衝壓加工或雷射照射等，使多孔基體4(高空隙部7)之細孔7a裂開而形成。高空隙部7與低空隙部8之區域比率係根據應取得之靜電電容而設定。例如，於獲得大容量之電容器之情形時，高空隙部7之區域比率變大，另一方面，於靜電電容變小但需要確保機械強度之情形時，低空隙部8之區域比率變大。再者，於本實施形態中，可藉由提昇機械強度，而將長度L相對於元件本體2之高度H之比設為3以上，較佳為設為5以上，從而能夠獲得低背之小型且大容量之電容器。又，導電性基板1之厚度亦並無特別限定，但根據機械強度與低背化之觀點，較佳為10～100 μm。作為此種導電性基板1之原材料，若具有導電性則並無特別限定，例如，可使用Al、Ta、Ni、Cu、Ti、Nb、Fe等金屬材料或不鏽鋼、杜拉鋁等合金材料。但，導電性基板1根據更有效地降低ESR之觀點，較佳為由良導電性材料、尤其比電阻為10 μΩ・cm以下之金屬材料形成，而如Si之半導體材料欠佳。又，作為形成上述介電層5之材料，若為具有絕緣性之材料則並無特別限定，例如，可使用Al₂ O₃ 等AlO_x 、SiO₂ 等SiO_x 、AlTiO_x 、SiTiO_x 、HfO_x 、TaO_x 、ZrO_x 、HfSiO_x 、ZrSiO_x 、TiZrO_x 、TiZrWO_x 、TiO_x 、SrTiO_x 、PbTiO_x 、BaTiO_x 、BaSrTiO_x 、BaCaTiO_x 、SiAlO_x 等金屬氧化物、AlN_x 、SiN_x 、AlScN_x 等金屬氮化物、或者AlO_x N_y 、SiO_x N_y 、HfSiO_x N_y 、SiC_x O_y N_z 等金屬氮氧化物。又，根據進行緻密之膜形成之觀點，較佳為介電層5無需具有結晶性而使用非晶質膜。介電層5之厚度亦並無特別限定，但根據提昇絕緣性抑制漏電流，且確保較大之靜電電容之觀點，較佳為3～100 nm，更佳為10～50 nm。介電層5之膜厚之不均並無特別限定，但根據取得穩定之所期望之靜電電容之觀點，較佳為膜厚具有均一性。於本實施形態中，可藉由使用下述原子層沈積法，而將膜厚之不均以平均膜厚為基準抑制為以絕對值計為10%以下。又，對於形成導電部6之材料而言，只要具有導電性則並無特別限定，可使用Ni、Cu、AI、W、Ti、Ag、Au、Pt、Zn、Sn、Pb、Fe、Cr、Mo、Ru、Pd、Ta、及該等之合金類(例如CuNi、AuNi、AuSn)、進而TiN、TiAlN、TaN等金屬氮化物、TiON、TiAlON等金屬氮氧化物、PEDOT/PSS(聚(3,4-乙二氧基噻吩)/ 聚苯乙烯磺酸)、聚苯胺、聚吡咯等導電性高分子等，但若考慮對細孔7a之填充性或成膜性，則較佳為金屬氮化物或金屬氮氧化物。再者，於使用此種金屬氮化物或金屬氮氧化物、或者導電性高分子之情形時，為使電阻更進一步低電阻化，較佳為藉由鍍覆法等而於導電部6之表面形成Cu皮膜、Ni皮膜等金屬皮膜。導電部6之厚度亦並無特別限定，但為獲得更低電阻之導電部6，較佳為3 nm以上，更佳為10 nm以上。對於保護層9之形成材料而言，若為具有絕緣性者則並無特別限定，可使用與上述介電層5相同之材料、例如SiN_x 、SiO_x 、AlTiO_x 、AlO_x 等，但較佳為SiO_x ，又，亦可使用環氧樹脂、聚醯亞胺樹脂等樹脂材料或玻璃材料等。對於第1及第2端子電極3a、3b之形成材料或厚度而言，若為具有所期望之導電性者則並無特別限定，例如可使用Cu、Ni、Sn、Au、Ag、Pb等金屬材料或該等之合金等。厚度係形成為0.5～50 μm，較佳為1～20 μm。如此般，該電容器於箔狀之導電性基板1之一主面形成元件本體2，並且該元件本體2具備多孔基體4(高空隙部7及低空隙部8)，其包含具有微小之細孔7a之導電材料；介電層5，其形成於包含細孔7a之內表面之多孔基體4之表面特定區域；及導電部6，其形成於介電層5上；且於元件本體2之主面，形成彼此電性絕緣之第1及第2端子電極3a、3b，且第1端子電極3a與導電部6電性連接，另一方面，第2端子電極3b經由通孔導體12及低空隙部8而與導電性基板1電性連接，故而能夠使用形成於元件本體2之一主面上之第1及第2端子電極3a、3b進行基板安裝。而且，能夠將元件本體2僅形成於導電性基板1之一主面，因此，能夠獲得可更進一步低背化且更小型化之大容量之電容器。其次，基於圖5～圖11對上述電容器之製造方法進行詳細敍述。圖5(a₁ )係成為基材之箔狀之集合基體之立體圖，圖5(a₂ )係圖5(a₁ )之沿X-X箭頭方向觀察之剖視圖。如該圖5(a₁ )、(a₂ )所示，準備於導電性基板1之一主面具有形成有微小之細孔7a之多孔基體4之大尺寸之集合基體16。此處，作為集合基體16，可使用對導電性基板1之一主面實施有擴面處理之金屬蝕刻箔或金屬燒結體、多孔金屬體等。金屬蝕刻箔可藉由對Al等之金屬箔於任意之方向通電特定電流，將金屬箔進行蝕刻加工而製作。金屬燒結體可藉由將Ta或Ni等之金屬粉末成形加工為片狀之後，以低於金屬熔點之溫度進行加熱、煅燒而製作。又，多孔金屬體可藉由使用去合金化法而製作。即，電化學地自貴金屬與賤金屬之二維合金僅將賤金屬於酸等電解液中溶解去除。而且，於將賤金屬溶解去除時，未溶解而殘留之貴金屬形成奈米級之開氣孔，藉此可製作多孔金屬體。以此方式，準備於導電性基板1上形成有多孔基體4之集合基體16。其次，如圖6(b₁ )～(b₃ )所示，對集合基體16實施阻隔處理，將多孔基體4阻隔為高空隙部7與槽狀之低空隙部8。阻隔處理之方法並無特別限定，可藉由使用衝壓加工、雷射照射等，使多孔基體4(高空隙部7)之細孔7a之一部分裂開而形成。例如，於使用衝壓加工進行阻隔處理之情形時，可使用具有特定之寬度尺寸之模具，自上表面對集合基體16進行加壓，阻隔為高空隙部7與低空隙部8。於該情形時，可藉由調整模具等之寬度尺寸而調整高空隙部7與低空隙部8之區域比率，從而可如上所述地控制電容器之靜電電容。又，於使用雷射照射進行阻隔處理之情形時，將YVO₄ 雷射、CO₂ 雷射、YAG(yttrium aluminum garnet，釔鋁石榴石)雷射、準分子雷射、光纖雷射、進而飛秒雷射、微微秒雷射、奈米秒雷射等全固體脈衝雷射照射至多孔基體4之特定位置，使細孔7a之一部分裂開，藉此可形成低空隙部8。再者，於利用此種雷射照射形成低空隙部8之情形時，為更高精度地控制形狀或空隙率，較佳為使用上述全固體脈衝雷射。其次，如圖7(c)所示，將包括絕緣性材料之保護層9形成於低空隙部8之表面。保護層9之形成方法並無特別限定，可利用空氣式分注器、噴射式分注器、噴墨法、網版印刷法、靜電塗佈法等於低空隙部8之表面填充或塗佈絕緣性材料，形成保護層9。亦對於此種保護層用之絕緣性材料而言，若具有絕緣性則並無特別限定，可使用例如聚醯亞胺樹脂、環氧樹脂等。其次，如圖8(d₁ )所示，於高空隙部7及保護層9之表面形成介電層5。圖8(d₂ )係圖8(d₁ )之主要部分放大剖視圖。具體而言，介電層5係如該圖8(d₂ )所示地形成於高空隙部7之細孔7a之內表面及低空隙部8上之保護層9之表面。介電層5之形成方法並無特別限定，亦可利用化學氣相成長(Chemical Vapor Deposition；以下，稱為「CVD」))法、物理氣相成長(Physical Vapor Deposition；以下稱為「PVD」)法等製造，但根據獲得薄膜且緻密且漏電流較小之良好之絕緣性之觀點，較佳為利用原子層沈積(Atomic Layer Deposition；以下稱為「ALD」)法形成。即，於CVD法中，將作為前驅物之有機金屬化合物或水等之反應氣體同時供給至反應室中進行反應而成膜，故而難以將均一膜厚之介電層5較深地形成至奈米級之微小之細孔9a之內表面之裏側。又，於使用固體原料之PVD法之情形時亦情況相同。相對於此，於ALD法中，將有機金屬前驅物供給至反應室且使之化學吸附後，將氣相中過剩地存在之有機金屬前驅物沖洗去除，其後，於反應室中與水蒸氣等反應氣體進行反應，藉此可使原子層單位之薄膜沈積於包含細孔7a之內表面之高空隙部7及低空隙部8上之保護層9之表面特定區域。因此，藉由重複進行上述過程，而以原子層單位積層薄膜，其結果，可將均一且具有特定膜厚之緻密之高品質之介電層5較深地形成至細孔7a之內表面之裏側。藉由如此地利用ALD法製作介電層5，可獲得薄膜且緻密之漏電流較小且具有良好絕緣性之介電層5，從而能夠獲得具有穩定之容量且具有良好之可靠性之大容量之電容器。其次，如圖9(e₁ )所示，於介電層5之表面形成導電部6。圖9(e₂ )係圖9(e₁ )之主要部分放大剖視圖。具體而言，導電部6係如該圖9(e₂ )所示以與介電層5相接之方式填充於細孔7a之內部，且形成於高空隙部7之表面特定區域及低空隙部8上之介電層5之表面。導電部6之形成方法亦無特別限定，例如可使用CVD法、鍍覆法、偏壓濺鍍法、溶膠-凝膠法、導電性高分子填充法等，但為獲得緻密且高精度之導電部6，較佳為與介電層5同樣地使用成膜性優異之ALD法。又，例如，亦可於形成於細孔7a內部之介電層5表面利用ALD法製作導電體層，且於該介電體5上利用CVD法或鍍覆法等方法填充導電性材料，藉此形成導電部6。如圖10(f₁ )及圖10(f₂ )所示，對於特定部位，與端面平行地以等間隔進行雷射照射，形成如貫通保護層9、導電部6、及介電層5而不貫通低空隙部8之複數個通孔17。通孔17之孔徑並無特別限定，例如形成為25 μm左右。又，通孔17之形成部位亦無特別限定，例如，自高空隙部7與低空隙部8之交界朝向低空隙部8內於0.15 mm左右之位置與端面平行地形成5個部位左右。其次，實施Ar電漿處理等，將通孔17之保護層9之殘渣去除之後，如圖11(g)所示，於導電部6之表面及通孔17之內面形成籽晶電極層11。再者，於圖11(g)中，將通孔17之內面之籽晶電極層省略。該籽晶電極層11之形成方法並無特別限定，可利用濺鍍法或非電解鍍覆法等形成。又，籽晶電極層11之形成材料或膜厚亦並無特別限定，可設為例如Ti膜與Cu膜之兩層構造。於該情形時，較佳為Ti膜之膜厚例如為0.1～0.3 μm，Cu膜之膜厚例如為0.5～2.0 μm。其次，如圖11(h)所示，進行導電部6及籽晶電極層11之分斷處理。即，對較通孔17形成位置更靠高空隙部7方向之低空隙部8之特定位置進行雷射照射等，以貫通介電層5、導電部6及籽晶電極層11，且不貫通保護層9之方式進行分斷處理，形成槽部15。以此方式，藉由槽部15而將導電部6分斷為不包含通孔導體12而包含高空隙部7之第1區域31與包含通孔導體12之第2區域32。其次，如圖11(i)所示，實施電鍍，於第1區域31形成第1端子電極3a，且於第2區域32形成第2端子電極3b。此時，藉由電鍍而亦於通孔17將與第2端子電極3b相同之導電性材料填充於通孔17，藉此形成通孔導體12。繼而，最後將集合基體16例如虛線C所示，縱橫地切斷而單片化，藉此製造電容器。再者，集合基體16之切斷方法並無特別限定，例如，可藉由使用由雷射照射之切斷、模具之沖模加工、切割機、超硬刀、切條機、尖錐形刀等切斷工具而容易地切斷。如此般，根據本製造方法，於集合基體16之狀態下僅對導電性基板1之一主面側實施加工處理即可，從而可使加工製程簡化。即，能夠以所謂多片方式自大尺寸之集合基體16以高效率獲得低背化之小型、大容量之電容器，從而可獲得良好之生產性。圖12係模式性表示本發明之電容器之第2實施形態之剖視圖。於本第2實施形態中，於低空隙部8上，使絕緣層18介置於導電部6與籽晶電極層11之間，於元件本體2上以成為同一平面之方式形成第1端子電極3a及第2端子電極3b。而且，藉此，可消除如第1實施形態般於高空隙部7與低空隙部8之間在端子電極間產生階差d之情況，從而能夠避免將電容器傾斜地安裝，即，即便於第1實施形態中，亦可藉由調整保護層9之厚度而避免產生階差d，但於利用ALD法製作介電層5或導電部6之情形時，根據生產技術性之觀點，存在因成膜溫度或原料氣體(氨氣、氯氣等)之環境而導致難以使保護層9之厚度增加之情形。相對於此，如本第2實施形態般，可藉由於低空隙部8上，使絕緣層18介置於導電部6與籽晶電極層11，而於元件本體2上將第1端子電極3a及第2端子電極3b以成為同一平面之方式形成。再者，本第2實施形態之電容器可利用以下之方法容易地製造。即，利用與第1實施形態相同之方法、順序，形成高空隙部7、低空隙部8、介電層5及導電部6之後，對導電部6之整面利用旋轉塗佈法等塗佈感光性環氧樹脂，使用周知之光微影技術，於低空隙部7上依次進行曝光、顯影、硬化之各處理，於低空隙部7上製作絕緣層18。繼而，可與第1實施形態同樣地，藉由形成籽晶電極層11、通孔導體12、第1及第2端子電極3a、3b且進行單片化而容易地製造。圖13係模式性表示本發明之電容器之第3實施形態之剖視圖，且於本第3實施形態中，於分斷為第1區域31及第2區域32之2個區域之各導電部6上形成有中間電極層19。即，於該第3實施形態中，與第1實施形態同樣地，將導電部6於低空隙部8上經由槽部15分斷為第1區域31與第2區域32之2個區域，於分斷所得之各導電部6上分別形成中間電極層19，且該中間電極層19兼作籽晶電極層。具體而言，於低空隙部8上介隔第2絕緣層20而於導電部6之主面形成有中間電極層19，於高空隙部7上於導電部6之表面直接形成有中間電極層19。而且，於包含分斷所得之導電部6間及中間電極層19間之中間電極層19之表面形成有第1絕緣層21，且於第1絕緣層21之表面形成有電性絕緣之第1及第2端子電極22a、22b。而且，第1端子電極22a經由貫通第1絕緣層21之第2通孔導體23連接於中間電極層19，且第2端子電極22b經由貫通第1絕緣層21之第3通孔導體24連接於中間電極層19，進而該中間電極層19於連接於低空隙部8之通孔內面成膜而形成薄膜狀之第1通孔導體25，且第2端子電極22b經由第3通孔導體24、中間電極層19、及第1通孔導體25電性連接於低空隙部8。於該第3實施形態中，可藉由設置中間電極層19進行再配線化，而形成形狀之自由度較高之第1及第2端子電極22a、22b。又，可利用第1絕緣層21被覆高空隙部7整體，從而可緩和物理性衝擊，且可實現機械耐久性之提昇。該第3實施形態可利用以下之方法容易地製造。即，利用與第1實施形態相同之方法、順序，形成高空隙部7、低空隙部8、介電層5、導電部6、第2絕緣層20、及通孔之後，形成中間電極層19，且於通孔內面形成薄膜狀之第1通孔導體25。繼而，與第1實施形態同樣地，進行雷射照射，將中間電極層19、第2絕緣層20、導電部6、介電層5分斷，形成槽部26。其次，於包含槽部26之中間電極層19之表面形成第1絕緣層21，將形成第1絕緣層21之絕緣性材料填充於薄膜狀之第1通孔導體25之內面及槽部26。其次，為使第1端子電極22a與中間電極層19電性導通而將貫通第1絕緣層21之第2通孔導體23形成於特定部位，進而為使第2端子電極22b與中間電極層19電性導通而將貫通第1絕緣層21之第3通孔導體24形成於特定部位。其次，於第1絕緣層21上藉由濺鍍法等，而形成包括例如Ti/Cu之兩層構造之籽晶電極層(未圖示)。繼而，實施電鍍，於籽晶電極層之表面形成第1及第2端子電極22a、22b。最後，將集合基體切斷為特定尺寸進行單片化，藉此獲得電容器。如該第3實施形態般，即便於包含形成中間連接層19之步驟等之情形時，亦與第1實施形態大致同樣地於集合基體16之狀態下僅對導電性基板1之一主面側實施加工處理即可，從而可使加工製程簡化，且能夠容易地製造藉由再配線化而具有自由之形狀之端子電極之電容器。圖14係模式性表示本發明之電容器之第4實施形態之剖視圖。本第4實施形態係於上述第3實施形態中，將介置於低空隙部8上之中間電極層19與導電部6之間之第2絕緣層20省略，亦於低空隙部8上於導電部6上形成有中間電極層19。於本第4實施形態中，雖未設置第2絕緣層20，但可藉由使第1絕緣層21之厚度薄膜化，而將第1端子電極22a與第2端子電極22b形成為同一平面。而且，因未設置第2絕緣層20且使第1絕緣層21薄層化，故而雖機械耐久性稍差，但能夠實現更進一步之低背化。即，可藉由將第3實施形態與第4實施形態根據用途等適當地分開使用，而擴大適用之自由度。圖15係模式性表示本發明之電容器之第5實施形態之剖視圖，本第5實施形態係除了第1實施形態以外，於導電性基板1之與形成有多孔基體4之面為相反側之主面、即另一主面設置有由玻璃材或陶瓷材等形成之保護構件27。可藉由如此般於導電性基板1之另一主面設置保護構件27，而對於墜落或衝擊等物理性損傷，實現進一步之機械耐久性之提昇。再者，本發明並不限定於上述實施形態。例如，於上述各實施形態中，導電部6係填充於形成於細孔7a之介電層5內，但亦可以與介電層5大致相同之膜厚以沿著該介電層5之方式形成。又，於上述實施形態中，於高空隙部之周圍設置有低空隙部，但亦可僅設置於高空隙部之兩端部，或者利用雷射照射等將多孔基體4之一部分去除，於導電性基板1上僅設置高空隙部7。又，槽部15、26係以嵌入至保護層9之一部分之方式形成，但亦可將槽部15、26以嵌入至低空隙部8之一部分之程度形成。又，上述實施形態所示之製造順序係為一例，只要包含上述製造步驟，則步驟順序亦可視需要而適當變更。[產業上之可利用性]實現一種低背且作為零件單體之處理容易之小型、大容量之電容器。Next, an embodiment of the present invention will be described in detail. FIG. 1 is a sectional view schematically showing an embodiment (first embodiment) of a capacitor of the present invention, and FIG. 2 is a plan view of FIG. 1. The capacitor is formed on one main surface of the foil-shaped conductive substrate 1 to form an element body 2, and a pair of terminal electrodes (first terminal electrode 3 a, second terminal electrode) that are electrically insulated are formed on the main surface of the element body 2. 3b). The element body 2 has a porous substrate 4 including a conductive material, a dielectric layer 5 formed on a surface of the porous substrate 4, and a conductive portion 6 formed on the dielectric layer 5. Specifically, the porous substrate 4 has a high void portion 7 which contributes to the acquisition of electrostatic capacitance and has a large void ratio; and a low void portion 8 which is formed so as to surround the high void portion 7 and has a void ratio. Is smaller than the high void portion 7. In addition, a protective layer 9 including an insulating material is formed on the low-void portion 8, and further interposed between the first and second terminal electrodes 3a and 3b and the conductive portion 6 to form a through-hole conductor as described below ( The seed electrode layer 11 of the first through-hole conductor) 12. The conductive substrate 1 and the porous substrate 4 (the high void portion 7 and the low void portion 8) are integrally formed by processing the assembly base as described below. FIG. 3 is an enlarged sectional view showing details of part A of FIG. 1. A high void portion 7 having minute pores 7 a is formed in the conductive substrate 1, and a dielectric layer 5 is formed on the inner surface of the pores 7 a along the inner surface. The conductive portion 6 is formed on the dielectric layer 5 so as to close the pores 7 a. The pores 7 a are filled with the material forming the conductive portion 6 and are formed in the high-void portion 7 along the seed electrode layer 11. on. Furthermore, in this embodiment, the electrostatic capacitance is obtained from the high-void portion 7, the dielectric layer 5, and the conductive portion 6. In addition, the dielectric layer 5 is deposited in atomic layer units, thereby forming a dense film, which is different from the case of forming a dielectric layer by anodic oxidation like a solid electrolytic capacitor, with fewer defects and good insulation. In addition, since no polarity is provided, a capacitor having good usability can be obtained. FIG. 4 is an enlarged sectional view showing details of part B of FIG. 1. A low void portion 8 is formed on the conductive substrate 1 so as to surround the high void portion 7, and a protective layer 9, a dielectric layer 5, and a conductive portion 6 are also formed on the low void portion 8 so as to surround the high void portion 7. 、和 Seed electrode layer 11. A via-hole conductor (first via-hole conductor) 12 is formed near one end surface of the element body 2 so that the second terminal electrode 3b and the low-void portion 8 can be electrically connected to each other. The through-hole conductor 12 is formed in a through-hole that penetrates the conductive portion 6, the dielectric layer 5, and the protective layer 9. That is, the seed electrode layer 11 is formed on the inner surface of the through hole, and the conductive material 14 forming the second terminal electrode 3 b is filled on the inner surface of the seed electrode layer 11, and the seed electrode layer 11 and the conductive material 14 are filled. Forming a through-hole conductor 12. Further, a groove portion 15 is formed in the low-void portion 8 so as to fit into at least a part of the protective layer 9. In addition, the terminal electrode, the seed electrode layer 11, the conductive portion 6, and the dielectric layer 5 are divided into two regions of the first region 31 and the second region 32 by the groove portion 15, and thereby, the first region The second terminal electrodes 3a and 3b are formed by being electrically insulated. Further, in this embodiment, the first terminal electrode 3a on the high-void portion 7 and the first terminal electrode 3a on the low-void portion 8 are formed so as to have a step d. Here, the porosity of the high void portion 7 is not particularly limited, but from the viewpoint of obtaining a desired capacitance, it is preferably 30 to 80%, and more preferably 35 to 65%. On the other hand, the porosity of the low void portion 8 is preferably 25% or less, more preferably 10% or less from the viewpoint of ensuring desired mechanical strength, and may be 0% without voids. In addition, the manufacturing method of the high void portion 7 is not particularly limited. For example, it can be manufactured by an etching method, a sintering method, a dealloying method, or the like as described below, and a metal manufactured by these manufacturing methods can be used. An etched foil, a sintered body, a porous metal body, or the like is used as the high-void portion 7. The thickness of the high void portion 7 is not particularly limited, but from the viewpoint of ensuring mechanical strength while achieving desired miniaturization, it is preferably 10 to 300 μm, more preferably 30 to 150 μm, and still more preferably 30 to 80 μm. . In addition, as described below, the low void portion 8 can be used to break the pores 7a of the porous substrate 4 (high void portion 7) by subjecting the conductive substrate 1 on which the high void portion 7 is formed to punching or laser irradiation. And formed. The area ratio of the high-gap portion 7 to the low-gap portion 8 is set according to the electrostatic capacitance to be obtained. For example, in the case of obtaining a large-capacity capacitor, the area ratio of the high void portion 7 becomes large. On the other hand, when the electrostatic capacitance becomes small but the mechanical strength needs to be secured, the area ratio of the low void portion 8 becomes large. Furthermore, in this embodiment, by increasing the mechanical strength, the ratio of the length L to the height H of the element body 2 can be set to 3 or more, preferably 5 or more, so that a low-profile compact can be obtained. And large-capacity capacitors. The thickness of the conductive substrate 1 is not particularly limited, but is preferably 10 to 100 μm from the viewpoints of mechanical strength and low backing. The raw material of such a conductive substrate 1 is not particularly limited as long as it has conductivity. For example, metal materials such as Al, Ta, Ni, Cu, Ti, Nb, and Fe, or alloy materials such as stainless steel and Dura aluminum can be used. However, the conductive substrate 1 is preferably formed of a highly conductive material, particularly a metal material having a specific resistance of 10 μΩ · cm or less, and a semiconductor material such as Si is inferior from the viewpoint of reducing ESR more effectively. Further, as a material for forming the dielectric layer 5 of, if a material having insulation property is not particularly limited, for example, Al ₂ O ₃ may be used like AlO _x, SiO ₂ and the like _{_{_{SiO x, AlTiO x, SiTiO x}}} , HfO _{_{_{x, TaO x, ZrO x,}}} HfSiO x, ZrSiO x, TiZrO x, TiZrWO x, TiO x, SrTiO x, PbTiO x, BaTiO x, BaSrTiO x, BaCaTiO x, SiAlO x metal oxide, AlN _{_x,} SiN _x , Metal nitrides such as AlScN _x , or metal oxynitrides such as AlO _x N _y , SiO _x N _y , HfSiO _x N _y , SiC _x O _y N _z . From the viewpoint of forming a dense film, it is preferable that the dielectric layer 5 does not need to have crystallinity, and an amorphous film is used. The thickness of the dielectric layer 5 is also not particularly limited, but from the viewpoint of improving insulation and suppressing leakage current and ensuring a large electrostatic capacitance, it is preferably 3 to 100 nm, and more preferably 10 to 50 nm. The unevenness of the film thickness of the dielectric layer 5 is not particularly limited, but from the viewpoint of obtaining a stable desired electrostatic capacitance, it is preferable that the film thickness be uniform. In this embodiment, by using the following atomic layer deposition method, variations in film thickness based on the average film thickness can be suppressed to 10% or less in absolute value. The material for forming the conductive portion 6 is not particularly limited as long as it has conductivity, and Ni, Cu, AI, W, Ti, Ag, Au, Pt, Zn, Sn, Pb, Fe, Cr, Mo, Ru, Pd, Ta, and alloys thereof (e.g. CuNi, AuNi, AuSn), further metal nitrides such as TiN, TiAlN, TaN, metal oxynitrides such as TiN, TiAlON, PEDOT / PSS (poly (3 , 4-Ethylenedioxythiophene) / polystyrenesulfonic acid), polyaniline, polypyrrole and other conductive polymers, etc., but considering the filling or film-forming properties of pores 7a, metal nitrogen is preferred Compounds or metal oxynitrides. When such a metal nitride, a metal oxynitride, or a conductive polymer is used, in order to further reduce the resistance, it is preferable to use a plating method or the like on the surface of the conductive portion 6 Metal films such as Cu film and Ni film are formed. The thickness of the conductive portion 6 is also not particularly limited, but in order to obtain the conductive portion 6 with lower resistance, it is preferably 3 nm or more, and more preferably 10 nm or more. The material for forming the protective layer 9 is not particularly limited as long as it has insulation properties. The same material as the above-mentioned dielectric layer 5 can be used, such as SiN _x , SiO _x , AlTiO _x , AlO _x, etc. It is preferably SiO _x , and resin materials such as epoxy resins and polyimide resins or glass materials can also be used. The material and thickness of the first and second terminal electrodes 3a and 3b are not particularly limited as long as they have desired conductivity. For example, metals such as Cu, Ni, Sn, Au, Ag, and Pb can be used. Materials or alloys of these. The thickness is formed to be 0.5 to 50 μm, and preferably 1 to 20 μm. In this way, the capacitor forms an element body 2 on one of the main surfaces of the foil-shaped conductive substrate 1, and the element body 2 includes a porous substrate 4 (high void portion 7 and low void portion 8) including fine pores. 7a is a conductive material; a dielectric layer 5 is formed on a specific area of the surface of the porous substrate 4 containing the inner surface of the pores 7a; and a conductive portion 6 is formed on the dielectric layer 5; The first and second terminal electrodes 3a and 3b are electrically insulated from each other, and the first terminal electrode 3a is electrically connected to the conductive portion 6. On the other hand, the second terminal electrode 3b passes through the through-hole conductor 12 and the low gap. Since the portion 8 is electrically connected to the conductive substrate 1, it is possible to mount the substrate using the first and second terminal electrodes 3 a and 3 b formed on one main surface of the element body 2. Furthermore, since the element body 2 can be formed only on one main surface of the conductive substrate 1, a capacitor having a large capacity which can be further reduced in size and reduced in size can be obtained. Next, the method for manufacturing the capacitor will be described in detail based on FIGS. 5 to 11. FIG. 5 (a ₁ ) is a perspective view of a foil-like aggregate base which becomes a base material, and FIG. 5 (a ₂ ) is a cross-sectional view of FIG. 5 (a ₁ ) viewed in the direction of the XX arrow. As shown in FIGS. 5 (a ₁ ) and (a ₂ ), a large-sized aggregate substrate 16 having a porous substrate 4 having minute pores 7 a formed on one main surface of the conductive substrate 1 is prepared. Here, as the aggregate base 16, a metal etched foil, a metal sintered body, a porous metal body, or the like, which has been subjected to an expansion treatment on one main surface of the conductive substrate 1 can be used. The metal etching foil can be produced by applying a specific current to a metal foil such as Al in an arbitrary direction and etching the metal foil. The metal sintered body can be produced by forming and processing a metal powder such as Ta or Ni into a sheet shape, and then heating and firing at a temperature lower than the melting point of the metal. The porous metal body can be produced by using a dealloying method. That is, only a two-dimensional alloy of a noble metal and a base metal is electrochemically dissolved and removed in an electrolytic solution such as an acid. In addition, when the base metal is dissolved and removed, the noble metal that remains undissolved forms nano-scale open pores, thereby making a porous metal body. In this way, the aggregate base 16 having the porous base 4 formed on the conductive substrate 1 is prepared. Next, as shown in (b ₁ ) to (b ₃ ) of FIG. 6, the collective base 16 is subjected to a barrier treatment to block the porous base 4 into a high void portion 7 and a groove-like low void portion 8. The method of the barrier treatment is not particularly limited, and it can be formed by cracking a part of the pores 7a of the porous substrate 4 (high void portion 7) by using stamping, laser irradiation, or the like. For example, in the case of using a stamping process for the barrier treatment, a mold having a specific width dimension may be used to press the aggregate base 16 from the upper surface to block the high-void portion 7 and the low-void portion 8. In this case, the area ratio of the high-gap portion 7 to the low-gap portion 8 can be adjusted by adjusting the width dimension of a mold or the like, so that the electrostatic capacitance of the capacitor can be controlled as described above. In the case of using laser irradiation for blocking treatment, YVO ₄ laser, CO ₂ laser, YAG (yttrium aluminum garnet) laser, excimer laser, fiber laser, and All-solid pulse lasers such as a second laser, a picosecond laser, and a nanosecond laser are irradiated to a specific position of the porous substrate 4 to cause a part of the pores 7a to be cracked, thereby forming a low void portion 8. In addition, in the case where the low-void portion 8 is formed by such laser irradiation, in order to control the shape or porosity more accurately, it is preferable to use the all-solid pulse laser described above. Next, as shown in FIG. 7 (c), a protective layer 9 including an insulating material is formed on the surface of the low-void portion 8. The method for forming the protective layer 9 is not particularly limited, and an air type dispenser, a jet type dispenser, an inkjet method, a screen printing method, and an electrostatic coating method can be used to fill or coat the surface of the low void portion 8 Sexual material to form a protective layer 9. The insulating material for such a protective layer is not particularly limited as long as it has insulating properties. For example, polyimide resin, epoxy resin, and the like can be used. Next, as shown in FIG. 8 (d ₁ ), a dielectric layer 5 is formed on the surfaces of the high void portion 7 and the protective layer 9. FIG. 8 (d ₂ ) is an enlarged sectional view of a main part of FIG. 8 (d ₁ ). Specifically, the dielectric layer 5 is formed on the inner surface of the pores 7 a of the high-void portion 7 and the surface of the protective layer 9 on the low-void portion 8 as shown in FIG. 8 (d ₂ ). The method for forming the dielectric layer 5 is not particularly limited, and a chemical vapor phase growth (Chemical Vapor Deposition; hereinafter referred to as "CVD") method and a physical vapor phase growth (Physical Vapor Deposition; hereinafter referred to as "PVD") can also be used. ), Etc., but from the viewpoint of obtaining a thin film that is dense and has a small leakage current and good insulation, it is preferably formed by an atomic layer deposition (hereinafter referred to as "ALD") method. That is, in the CVD method, a reaction gas such as an organometallic compound or water as a precursor is simultaneously supplied to a reaction chamber for reaction to form a film. Therefore, it is difficult to form the dielectric layer 5 having a uniform film thickness to a high level. The inner side of the inner surface of the minute pores 9a of the meter class. The same applies to the case of the PVD method using a solid raw material. In contrast, in the ALD method, after the organometallic precursor is supplied to the reaction chamber and chemically adsorbed, the organometallic precursor that is excessively present in the gas phase is rinsed and removed. Thereafter, the reaction chamber is exposed to water vapor in the reaction chamber. The reaction gas is allowed to react, whereby a thin film of atomic layer units can be deposited on a specific area of the surface of the protective layer 9 on the high void portion 7 and the low void portion 8 including the inner surface of the pores 7a. Therefore, by repeating the above process and laminating the film in atomic layer units, as a result, a dense, high-quality dielectric layer 5 having a uniform and specific film thickness can be formed deeper to the inner surface of the pores 7a. Inside. By using the ALD method to make the dielectric layer 5 in this manner, a thin film, a dense dielectric layer 5 with a small leakage current and good insulation can be obtained, so that a large capacity having a stable capacity and a good reliability can be obtained.之 Capacitors. Next, as shown in FIG. 9 (e ₁ ), a conductive portion 6 is formed on the surface of the dielectric layer 5. FIG. 9 (e ₂ ) is an enlarged sectional view of a main part of FIG. 9 (e ₁ ). Specifically, as shown in FIG. 9 (e ₂ ), the conductive portion 6 is filled in the pore 7 a so as to be in contact with the dielectric layer 5, and is formed in a specific area of the surface of the high-void portion 7 and a low-void. The surface of the dielectric layer 5 on the portion 8. The method of forming the conductive portion 6 is also not particularly limited. For example, a CVD method, a plating method, a bias sputtering method, a sol-gel method, a conductive polymer filling method, or the like can be used, but in order to obtain a dense and highly accurate conductive As for the part 6, it is preferable to use the ALD method which is excellent in film-forming property similarly to the dielectric layer 5. Alternatively, for example, a conductive layer may be formed on the surface of the dielectric layer 5 formed inside the fine hole 7a by an ALD method, and a conductive material may be filled on the dielectric 5 by a method such as a CVD method or a plating method. Forming the conductive portion 6. As shown in FIG. 10 (f ₁ ) and FIG. 10 (f ₂ ), for a specific part, laser irradiation is performed at equal intervals in parallel with the end face to form, for example, penetration of the protective layer 9, the conductive portion 6, and the dielectric layer 5. The plurality of through-holes 17 which do not penetrate the low-void portion 8. The pore diameter of the through hole 17 is not particularly limited, and is formed to be about 25 μm, for example. There are also no particular restrictions on the location of the formation of the through hole 17, for example, about five locations are formed parallel to the end surface at a position of about 0.15 mm from the boundary between the high void portion 7 and the low void portion 8 toward the inside of the low void portion 8. Next, after performing Ar plasma treatment, etc., to remove the residue of the protective layer 9 of the through hole 17, as shown in FIG. 11 (g), a seed electrode layer 11 is formed on the surface of the conductive portion 6 and the inner surface of the through hole 17. . In addition, in FIG. 11 (g), the seed electrode layer on the inner surface of the through hole 17 is omitted. The method for forming the seed electrode layer 11 is not particularly limited, and it can be formed by a sputtering method, a non-electrolytic plating method, or the like. The material and film thickness of the seed electrode layer 11 are not particularly limited, and may be a two-layer structure of, for example, a Ti film and a Cu film. In this case, the film thickness of the Ti film is preferably, for example, 0.1 to 0.3 μm, and the film thickness of the Cu film is, for example, 0.5 to 2.0 μm. Next, as shown in FIG. 11 (h), the conductive portion 6 and the seed electrode layer 11 are separated. That is, laser irradiation or the like is performed at a specific position of the low-gap portion 8 in the direction of the high-gap portion 7 more than the position where the through-hole 17 is formed to penetrate the dielectric layer 5, the conductive portion 6, and the seed electrode layer 11 without penetrating. The protective layer 9 is subjected to a breaking process to form a groove portion 15. In this manner, the conductive portion 6 is divided into the first region 31 including the high-void portion 7 and the second region 32 including the through-hole conductor 12 by not including the via-hole conductor 12 by the groove portion 15. Next, as shown in FIG. 11 (i), plating is performed to form a first terminal electrode 3 a in the first region 31 and a second terminal electrode 3 b in the second region 32. At this time, the same conductive material as the second terminal electrode 3 b is also filled in the through hole 17 by plating, thereby forming the through hole conductor 12. Then, the assembly base body 16 is finally cut vertically and horizontally, as shown by a broken line C, to form a single chip, thereby manufacturing a capacitor. In addition, the cutting method of the aggregate base 16 is not particularly limited, and for example, cutting by laser irradiation, die processing of a mold, a cutting machine, a super-hard knife, a slitter, a tapered tapered knife, and the like can be used. It is easily cut by cutting tools. As such, according to this manufacturing method, only one main surface side of the conductive substrate 1 may be processed in the state where the base body 16 is assembled, thereby simplifying the manufacturing process. That is, it is possible to obtain a low-profile, small-sized, large-capacity capacitor from the large-sized collection base 16 with a high efficiency in a so-called multi-chip method, thereby achieving good productivity. Fig. 12 is a sectional view schematically showing a second embodiment of the capacitor of the present invention. In the second embodiment, an insulating layer 18 is interposed between the conductive portion 6 and the seed electrode layer 11 on the low-void portion 8, and the first terminal electrode is formed on the element body 2 so as to be the same plane. 3a and the second terminal electrode 3b. In addition, by this, the step d between the terminal electrodes between the high-gap portion 7 and the low-gap portion 8 can be eliminated as in the first embodiment, and the capacitor can be prevented from being installed obliquely, that is, even in the first embodiment. In the embodiment, the step d can be avoided by adjusting the thickness of the protective layer 9. However, when the dielectric layer 5 or the conductive portion 6 is produced by the ALD method, according to the viewpoint of production technology, there is a film formation. The temperature or the environment of the source gas (ammonia gas, chlorine gas, etc.) makes it difficult to increase the thickness of the protective layer 9. In contrast, as in the second embodiment, the first terminal electrode 3 a can be placed on the element body 2 by the insulating layer 18 being interposed between the conductive portion 6 and the seed electrode layer 11 because of the low void portion 8. The second terminal electrode 3b is formed so as to be the same plane. The capacitor of the second embodiment can be easily manufactured by the following method. That is, after forming the high void portion 7, the low void portion 8, the dielectric layer 5, and the conductive portion 6 by the same method and procedure as the first embodiment, the entire surface of the conductive portion 6 is coated by a spin coating method or the like. The photosensitive epoxy resin is subjected to the processes of exposure, development, and hardening in order on the low-void portion 7 by using a well-known photolithography technique, and an insulating layer 18 is formed on the low-void portion 7. Further, as in the first embodiment, the seed electrode layer 11, the via-hole conductor 12, and the first and second terminal electrodes 3 a and 3 b can be easily manufactured by singulation. FIG. 13 is a cross-sectional view schematically showing a third embodiment of the capacitor according to the present invention, and in this third embodiment, on each of the conductive portions 6 divided into two regions of the first region 31 and the second region 32 An intermediate electrode layer 19 is formed. That is, in this third embodiment, the conductive portion 6 is divided into two regions of the first region 31 and the second region 32 via the groove portion 15 on the low-void portion 8 in the same manner as the first embodiment. An intermediate electrode layer 19 is formed on each of the conductive portions 6 obtained by the division, and the intermediate electrode layer 19 also serves as a seed electrode layer. Specifically, an intermediate electrode layer 19 is formed on the main surface of the conductive portion 6 via the second insulating layer 20 on the low-void portion 8, and an intermediate electrode layer is directly formed on the surface of the conductive portion 6 on the high-void portion 7. 19. A first insulating layer 21 is formed on the surface of the intermediate electrode layer 19 including the conductive portions 6 and the intermediate electrode layer 19 obtained by the division, and a first electrically insulating first layer is formed on the surface of the first insulating layer 21. And second terminal electrodes 22a, 22b. The first terminal electrode 22 a is connected to the intermediate electrode layer 19 through a second via-hole conductor 23 penetrating the first insulating layer 21, and the second terminal electrode 22 b is connected to a third via-hole conductor 24 penetrating the first insulating layer 21. The intermediate electrode layer 19 is formed on the inner surface of the through-hole connected to the low-void portion 8 to form a film-shaped first through-hole conductor 25, and the second terminal electrode 22 b passes through the third through-hole conductor 24. The intermediate electrode layer 19 and the first via-hole conductor 25 are electrically connected to the low-void portion 8. In this third embodiment, the first and second terminal electrodes 22a and 22b having a high degree of freedom in shape can be formed by providing the intermediate electrode layer 19 for rewiring. In addition, the entire first high-void portion 7 can be covered with the first insulating layer 21, so that physical impact can be reduced, and mechanical durability can be improved. This third embodiment can be easily manufactured by the following method. That is, the middle electrode layer 19 is formed after forming the high void portion 7, the low void portion 8, the dielectric layer 5, the conductive portion 6, the second insulating layer 20, and the through hole by the same method and procedure as the first embodiment. A thin film-shaped first via-hole conductor 25 is formed on the inner surface of the via-hole. Next, as in the first embodiment, laser irradiation is performed to divide the intermediate electrode layer 19, the second insulating layer 20, the conductive portion 6, and the dielectric layer 5 to form a groove portion 26. Next, a first insulating layer 21 is formed on the surface of the intermediate electrode layer 19 including the groove portion 26, and the insulating material forming the first insulating layer 21 is filled in the inner surface of the film-shaped first via-hole conductor 25 and the groove portion 26. . Next, in order to electrically connect the first terminal electrode 22 a and the intermediate electrode layer 19, a second via-hole conductor 23 penetrating the first insulating layer 21 is formed at a specific location, and further, the second terminal electrode 22 b and the intermediate electrode layer 19 are formed. The third via-hole conductor 24 penetrating the first insulating layer 21 is electrically connected to a specific portion. Next, a seed electrode layer (not shown) including a two-layer structure such as Ti / Cu is formed on the first insulating layer 21 by a sputtering method or the like. Next, electroplating is performed to form first and second terminal electrodes 22a and 22b on the surface of the seed electrode layer. Finally, the aggregate substrate is cut to a specific size and singulated to obtain a capacitor. As in the third embodiment, even when the step of forming the intermediate connection layer 19 is included, it is substantially the same as the first embodiment in the state where the base substrate 16 is assembled only on one main surface side of the conductive substrate 1. The processing may be performed, so that the processing process can be simplified, and capacitors having terminal electrodes with a free shape by rewiring can be easily manufactured. Fig. 14 is a cross-sectional view schematically showing a fourth embodiment of the capacitor of the present invention. The fourth embodiment is based on the third embodiment described above, and the second insulating layer 20 interposed between the intermediate electrode layer 19 and the conductive portion 6 on the low-void portion 8 is omitted, and is also formed on the low-void portion 8. An intermediate electrode layer 19 is formed on the conductive portion 6. In the fourth embodiment, although the second insulating layer 20 is not provided, the thickness of the first insulating layer 21 can be reduced to form the first terminal electrode 22a and the second terminal electrode 22b on the same plane. In addition, since the second insulating layer 20 is not provided and the first insulating layer 21 is made thin, the mechanical durability is slightly inferior, but further reduction in backing can be achieved. That is, the third embodiment and the fourth embodiment can be appropriately used separately according to the application and the like, thereby increasing the freedom of application. FIG. 15 is a cross-sectional view schematically showing a fifth embodiment of the capacitor of the present invention. In addition to the first embodiment, the fifth embodiment is a main surface of the conductive substrate 1 opposite to the surface on which the porous substrate 4 is formed. A protective member 27 made of a glass material, a ceramic material, or the like is provided on one surface, that is, the other main surface. By providing the protective member 27 on the other main surface of the conductive substrate 1 as described above, it is possible to further improve mechanical durability against physical damage such as a drop or impact. The present invention is not limited to the embodiments described above. For example, in each of the above embodiments, the conductive portion 6 is filled in the dielectric layer 5 formed in the fine hole 7 a, but the film thickness may be approximately the same as that of the dielectric layer 5 so as to follow the dielectric layer 5. form. Moreover, in the above-mentioned embodiment, a low-void portion is provided around the high-void portion, but it may be provided only at both ends of the high-void portion, or a part of the porous substrate 4 may be removed by laser irradiation or the like, and conductive Only the high-void portion 7 is provided on the flexible substrate 1. The groove portions 15 and 26 are formed so as to fit into a part of the protective layer 9. However, the groove portions 15 and 26 may be formed so as to fit into a portion of the low-void portion 8. In addition, the manufacturing order shown in the said embodiment is an example, and as long as the manufacturing steps are included, the order of steps may be changed suitably as needed. [Industrial availability] A small, large-capacity capacitor with a low profile and easy handling as a single component is realized.

1‧‧‧導電性基板
2‧‧‧元件本體
3a‧‧‧第1端子電極
3b‧‧‧第2端子電極
4‧‧‧多孔基體
5‧‧‧介電層
6‧‧‧導電部
7‧‧‧高空隙部
7a‧‧‧細孔
8‧‧‧低空隙部
9‧‧‧保護層
11‧‧‧籽晶電極層
12‧‧‧通孔導體(第1通孔導體)
14‧‧‧導電性材料
15‧‧‧槽部
16‧‧‧集合基體
17‧‧‧通孔
18‧‧‧絕緣層
19‧‧‧中間電極層
20‧‧‧第2絕緣層
21‧‧‧第1絕緣層
22a‧‧‧第1端子電極
22b‧‧‧第2端子電極
23‧‧‧第2導通通孔導體
24‧‧‧第3導通通孔導體
25‧‧‧第1導通通孔導體
26‧‧‧槽部
27‧‧‧保護構件
31‧‧‧第1區域
32‧‧‧第2區域
101‧‧‧高空隙部
102‧‧‧低空隙部
103‧‧‧多孔金屬基體
104‧‧‧導電部
105‧‧‧保護膜
106a‧‧‧第1端子電極
106b‧‧‧第2端子電極
C‧‧‧虛線
d‧‧‧階差1‧‧‧ conductive substrate
2‧‧‧ component body
3a‧‧‧The first terminal electrode
3b‧‧‧ 2nd terminal electrode
4‧‧‧ porous substrate
5‧‧‧ Dielectric layer
6‧‧‧ conductive section
7‧‧‧ high clearance
7a‧‧‧pore
8‧‧‧low clearance
9‧‧‧ protective layer
11‧‧‧seed electrode layer
12‧‧‧through-hole conductor (1st through-hole conductor)
14‧‧‧ conductive material
15‧‧‧Slot
16‧‧‧ Collection base
17‧‧‧through hole
18‧‧‧ Insulation
19‧‧‧ intermediate electrode layer
20‧‧‧Second insulation layer
21‧‧‧The first insulation layer
22a‧‧‧The first terminal electrode
22b‧‧‧ 2nd terminal electrode
23‧‧‧ 2nd via hole conductor
24‧‧‧ 3rd via hole conductor
25‧‧‧ 1st via hole conductor
26‧‧‧Slot
27‧‧‧Protective member
31‧‧‧ Zone 1
32‧‧‧Zone 2
101‧‧‧High clearance
102‧‧‧Low clearance
103‧‧‧ porous metal substrate
104‧‧‧Conductive section
105‧‧‧ protective film
106a‧‧‧The first terminal electrode
106b‧‧‧ 2nd terminal electrode
C‧‧‧ dotted line
d‧‧‧step difference

圖1係模式性表示本發明之電容器之一實施形態之剖視圖。圖2係圖1之俯視圖。圖3係表示圖1之A部詳情之放大剖視圖。圖4係表示圖1之B部詳情之放大剖視圖。圖5(a₁ )、(a₂ )係模式性表示本發明之電容器之製造方法之製造步驟圖(1/7)。圖6(b₁ )～(b₃ )係模式性表示本發明之電容器之製造方法之製造步驟圖(2/7)。圖7(c)係模式性表示本發明之電容器之製造方法之製造步驟圖(3/7)。圖8(d₁ )、(d₂ )係模式性表示本發明之電容器之製造方法之製造步驟圖(4/7)。圖9(e₁ )、(e₂ )係模式性表示本發明之電容器之製造方法之製造步驟圖(5/7)。圖10(f₁ )、(f₂ )係模式性表示本發明之電容器之製造方法之製造步驟圖(6/7)。圖11(g)～(i)係模式性表示本發明之電容器之製造方法之製造步驟圖(7/7)。圖12係模式性表示本發明之電容器之第2實施形態之剖視圖。圖13係模式性表示本發明之電容器之第3實施形態之剖視圖。圖14係模式性表示本發明之電容器之第4實施形態之剖視圖。圖15係模式性表示本發明之電容器之第5實施形態之主要部分剖視圖。圖16係模式性表示專利文獻1中記載之電容器之剖視圖。FIG. 1 is a cross-sectional view schematically showing an embodiment of a capacitor of the present invention. FIG. 2 is a top view of FIG. 1. FIG. 3 is an enlarged sectional view showing details of part A of FIG. 1. FIG. 4 is an enlarged sectional view showing details of part B of FIG. 1. 5 (a ₁ ) and (a ₂ ) are diagrams (1/7) schematically showing manufacturing steps of a method for manufacturing a capacitor of the present invention. 6 (b ₁ ) to (b ₃ ) are schematic diagrams (2/7) showing manufacturing steps of a method for manufacturing a capacitor of the present invention. FIG. 7 (c) is a manufacturing process diagram (3/7) schematically showing the manufacturing method of the capacitor of the present invention. 8 (d ₁ ) and (d ₂ ) are schematic diagrams (4/7) showing manufacturing steps of a method for manufacturing a capacitor of the present invention. FIG _{9 (e 1), (e} 2) based schematically showing manufacturing steps of FIG (5/7) of the method of manufacturing a capacitor according to the present invention. FIG. 10 (f ₁ ) and (f ₂ ) are schematic diagrams (6/7) showing manufacturing steps of a method for manufacturing a capacitor of the present invention. 11 (g) to (i) are diagrams (7/7) schematically showing manufacturing steps of a method for manufacturing a capacitor of the present invention. Fig. 12 is a sectional view schematically showing a second embodiment of the capacitor of the present invention. FIG. 13 is a sectional view schematically showing a third embodiment of the capacitor of the present invention. Fig. 14 is a cross-sectional view schematically showing a fourth embodiment of the capacitor of the present invention. Fig. 15 is a cross-sectional view schematically showing a main part of a fifth embodiment of the capacitor of the present invention. FIG. 16 is a cross-sectional view schematically showing a capacitor described in Patent Document 1. FIG.

1‧‧‧導電性基板 1‧‧‧ conductive substrate

2‧‧‧元件本體 2‧‧‧ component body

3a‧‧‧第1端子電極 3a‧‧‧The first terminal electrode

3b‧‧‧第2端子電極 3b‧‧‧ 2nd terminal electrode

4‧‧‧多孔基體 4‧‧‧ porous substrate

5‧‧‧介電層 5‧‧‧ Dielectric layer

6‧‧‧導電部 6‧‧‧ conductive part

7‧‧‧高空隙部 7‧‧‧ high clearance

8‧‧‧低空隙部 8‧‧‧low clearance

9‧‧‧保護層 9‧‧‧ protective layer

11‧‧‧籽晶電極層 11‧‧‧seed electrode layer

12‧‧‧通孔導體(第1通孔導體) 12‧‧‧through-hole conductor (1st through-hole conductor)

Claims

A capacitor is characterized in that an element body is formed on one main surface of a foil-shaped conductive substrate, and the element body is provided with: a porous substrate containing a conductive material having minute pores; and a dielectric layer formed on the A specific area of the surface of the porous substrate on the inner surface of the pores; and a conductive portion formed on the dielectric layer; on the main surface of the element body, a pair of terminal electrodes for electrical insulation is formed, and the pair of terminals One of the terminal electrodes is electrically connected to the conductive portion, and the other terminal electrode is electrically connected to the conductive substrate.

The capacitor according to claim 1, wherein the porous substrate has: a high void portion, which facilitates the acquisition of electrostatic capacitance; and a low void portion, which is formed on at least both end portions of the high void portion and has a void ratio lower than the above-mentioned high Void portion; the low void portion is formed at least at both end portions of the element body.

The capacitor according to claim 2, wherein the high void portion is surrounded by the low void portion.

The capacitor according to any one of claims 1 to 3, wherein a protective layer including an insulating material is interposed between the one terminal electrode and the conductive substrate.

The capacitor according to any one of claims 1 to 3, wherein the other terminal electrode is electrically connected to the conductive substrate through a first via-hole conductor.

The capacitor according to any one of claims 1 to 3, wherein the pair of terminal electrodes are formed in the same plane on the main surface of the element body.

The capacitor according to any one of claims 1 to 3, wherein the conductive portion is divided into two, and an intermediate electrode layer is formed on the surface of each conductive portion obtained by the division, and the intermediate electrode layer and the pair A first insulating layer is interposed between the terminal electrodes, the one terminal electrode system is electrically connected to one of the intermediate electrode layers, and the other terminal electrode system is electrically conductive with the other intermediate electrode layer. The substrate is electrically connected.

The capacitor according to claim 7, wherein the one terminal electrode is electrically connected to the one intermediate electrode layer through a second through-hole conductor penetrating the first insulating layer, and the other terminal electrode is through the first insulation. The third via conductor of the layer is electrically connected to the other intermediate electrode layer.

The capacitor according to claim 7, wherein a second insulating layer is interposed between a conductive portion of the conductive portions obtained by the above division and an intermediate electrode layer formed on the conductive portion.

The capacitor according to any one of claims 1 to 3, wherein a protective member is provided on the other main surface of the conductive substrate.

The capacitor according to any one of claims 1 to 3, wherein the dielectric layer is deposited in an atomic layer unit.

The capacitor according to any one of claims 1 to 3, wherein the conductive portion is formed by filling the inside of the pore.

The capacitor according to any one of claims 1 to 3, wherein the conductive portion is formed along the dielectric layer inside the pores.

The capacitor according to any one of claims 1 to 3, wherein the conductive substrate and the porous base system include a metal material and are integrally formed.

The capacitor according to any one of claims 1 to 3, wherein the conductive portion is formed of any one of a metal material and a conductive compound.

The capacitor according to claim 15, wherein the conductive compound includes a metal nitride and a metal oxynitride.

A method for manufacturing a capacitor is characterized in that it comprises the following steps: an aggregated substrate prepared on one of the main surfaces of a foil-shaped conductive substrate and comprising a porous conductive material formed with fine pores; and processing the aggregated substrate, and A high void portion is formed in a specific region of the collective substrate; a protective layer including an insulating material is formed on the conductive substrate; a dielectric layer is formed in a specific region of the surface of the collective substrate including the inner surface of the pores; A conductive portion is formed on the surface of the dielectric layer; a through hole penetrating the conductive portion and the protective layer is formed, and a conductive material is filled in the through hole to form a first through-hole conductor; the conductive portion is broken to not include the first through-hole. A first region including the high void portion and a second region including the first through-hole conductor; a terminal electrode connected to one of the conductive portions is formed on a main surface of the first region, and the second region is formed on the main surface of the first region; The main surface is formed with another terminal electrode connected to the conductive substrate via the first through-hole conductor to make a pair of terminal electrodes for electrical insulation; and After applying the above-described series of steps, the monolithic matrix of said set.

A method for manufacturing a capacitor is characterized in that it comprises the following steps: preparing a collective base body containing a porous conductive material having minute pores formed on one main surface of a conductive substrate; and processing the collective base body on the collective base body. A high void portion is formed in a specific region; a protective layer including an insulating material is formed on the conductive substrate; a dielectric layer is formed on a specific region of the surface of the aggregate substrate including the inner surface of the fine hole; and the dielectric layer is formed A conductive portion is formed on the surface; an intermediate electrode layer is formed on the conductive portion; a through hole penetrating through the intermediate electrode layer, the conductive portion, and the protective layer is formed, and a conductive film is formed at least on the inner surface of the through hole to produce A first via-hole conductor; dividing the conductive portion and the intermediate electrode layer into a first region that does not include the first via-hole conductor but includes the high-void portion, and a second region that includes the first via-hole conductor; A first insulating layer is formed on a surface of the intermediate electrode layer including a gap between the first region and the second region; one pair of terminal electrodes is electrically insulated. On the first insulating layer; fabricating a second via-hole conductor that electrically connects one of the terminal electrodes of the pair of terminal electrodes and the intermediate electrode layer in the first region to the other, and fabricating the other terminal electrode with the second electrode The third via hole conductor which is electrically conductive in the middle electrode layer of the region; and after performing the above-mentioned series of steps, the above-mentioned aggregate substrate is singulated.

The method for manufacturing a capacitor according to claim 18, comprising the step of forming a second insulating layer between the conductive portion and the intermediate electrode layer in the second region.

The method for manufacturing a capacitor according to any one of claims 17 to 19, wherein the thickness of the protective layer is adjusted, and the pair of terminal electrodes are formed in a same plane.

The method for manufacturing a capacitor according to any one of claims 17 to 19, wherein the dielectric layer is formed by an atomic layer deposition method.

The method for manufacturing a capacitor according to any one of claims 17 to 19, wherein the conductive portion is formed by an atomic layer deposition method.