TW201805913A - Display device and control method thereof - Google Patents

Abstract

A control method for a display device includes the steps of: obtaining a first characteristic value corresponding to a plurality of first pixel driving signals corresponding to a first scan line when the plurality of first pixel driving signals are received, obtaining a second characteristic value corresponding to a plurality of second pixel driving signals corresponding to a second scan line when the plurality of second pixel driving signals are received, and selectively disabling a first preset mechanism or enabling a second preset mechanism in a second timing period later than and next to a first timing period according to the first characteristic value and the second characteristic value. The first scan line is driven in the first timing period and the second scan line is driven in the second timing period.

Description

Display device and control method thereof

The present invention relates to a display device and a control method thereof, and more particularly to a display device and a control method thereof using column pixel feature values.

The display device, as the output periphery of the electronic device, is a necessary peripheral device for most electronic devices. For consumers' visual enjoyment, the number of pixels of today's display devices is increasing. Some display devices have a built-in mechanism to shorten the time for each pixel to write data to support high-pixel display devices. Such a mechanism consumes extra power to shorten the pixel writing time. However, in some cases, this mechanism not only consumes energy, but also fails to actually shorten the pixel writing time.

However, another consideration of electronic devices is power consumption. For mobile electronic devices, power consumption is even more important. As a relatively high power consumption component of an electronic device, a display device is more important to reduce the power consumption of the display device.

The invention is to provide a display device and a control method thereof, so as to reduce the power consumption of the display device.

A method for controlling a display device according to an embodiment of the present invention is applicable to a display device. The method includes the following steps: when receiving a plurality of first pixel driving signals corresponding to a first scan line of the display device, obtaining information about The first characteristic value of the first pixel driving signal of the first scanning line, wherein the first scanning line is driven in a first time interval. When receiving a plurality of second pixel driving signals corresponding to the second scanning line of the display device, a second characteristic value of the second pixel driving signal regarding the second scanning line is obtained, and the second scanning line is at a second time The interval is driven, and the second time interval is later in time and adjacent to the first time interval. According to the first feature value and the second feature value, the first preset mechanism is selectively stopped or the second preset mechanism is started in the second time interval.

A display device according to an embodiment of the present invention includes a plurality of first pixels, a plurality of second pixels, a first scanning line, a second scanning line, a plurality of data lines, a voltage presetting circuit, and a feature judging circuit. The first scan line is electrically coupled to the plurality of first pixels, and is configured to drive the plurality of first pixels in a first time zone. The second scanning line is electrically coupled to the plurality of second pixels to drive the plurality of second pixels in a second time interval. The second time interval is later in time and adjacent to the first time interval. Each of the plurality of data lines is electrically coupled to one of the plurality of first pixels and one of the plurality of second pixels. The voltage pre-regulation circuit is electrically coupled to the plurality of data lines for pre-charging or charge sharing. When receiving a plurality of first pixel driving signals corresponding to the plurality of first pixels, the feature determination circuit obtains a corresponding first characteristic value accordingly, and when receiving a plurality of second pixels corresponding to the plurality of first pixels When a plurality of second pixel driving signals are generated, the feature judgment circuit obtains a corresponding second feature value, and the feature judgment circuit selectively stops the energy in the second time interval according to the first feature value and the second feature value. Voltage preset circuit.

In summary, according to the display device and the control method thereof disclosed by the present invention, the pixel feature values corresponding to two scanning lines (gate driving lines) driven in two adjacent time intervals are selectively activated. The preset mechanism disables some circuits in the display device to achieve the purpose of reducing power consumption.

The above description of the contents of this disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical content of the present invention, and according to the content disclosed in this specification, the scope of patent applications and the drawings. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1, which is a display device control method according to an embodiment of the present invention. The method of FIG. 1 is suitable for a display device, and the method includes the following steps. As described in step S110, when a plurality of first pixel driving signals corresponding to the first scanning line of the display device is received, a first characteristic value of the first pixel driving signal corresponding to the first scanning line is obtained. A scan line is driven in the first time interval. As described in step S120, when a plurality of second pixel driving signals corresponding to the second scanning line of the display device are received, a second characteristic value of the second pixel driving signal regarding the second scanning line is obtained. The scan line is driven in a second time interval, and the second time interval is later in time and adjacent to the first time interval. As described in step S130, according to the first characteristic value and the second characteristic value, the first preset mechanism is selectively stopped or the second preset mechanism is started in the second time interval.

To help understand the method of FIG. 1, please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a schematic diagram of a display device architecture according to an embodiment of the present invention, and FIG. 3 is a signal timing diagram corresponding to FIG. 2. As shown in FIG. 2, a display device 1000 according to an embodiment of the present invention has M first pixels P _1,1 to P _{1, M} and M second pixels P _2,1 to P _{2, M} , and a scan line GD1, the second scan line GD2, a plurality of data lines SD ₁ to SD _M, preset circuit 1100 and voltage characteristic determination circuit 1200. The first scan line GD1 is electrically coupled to the first pixels P _1,1 to P _{1, M} for driving the foregoing first pixels P _1,1 to P _{1, M} in the first time interval TP1. The second scanning line GD2 is electrically coupled to the plurality of second pixels P _2,1 to P _{2, M} for driving the plurality of second pixels P _2,1 to P ₂ in the second time interval TP2. _M , the second time interval TP2 is later in time and is adjacent to the first time interval TP1. Each of the plurality of data lines SD ₁ to SD _M is electrically coupled to one of the first pixels P _1,1 to P _{1, M} and one of the second pixels P _2,1 to P _{2, M} One. The voltage presetting circuit 1100 is electrically coupled to the data lines SD ₁ to SD _M , and the characteristic determination circuit 1200 is electrically coupled to the voltage presetting circuit 1100. That is, as shown in FIG. 3, the voltage VG1 of the first scanning line GD1 is high voltage in the first time interval TP1, and the voltage VG2 of the second scanning line GD2 is low voltage in the first time interval. TP1 is a low voltage, and TP2 is a high voltage in the second time interval.

For presetting the voltage on the data line circuit 1100 SD ₁ to SD _M or precharged charge sharing. In an embodiment, please refer to FIG. 4A and FIG. 4B, wherein FIG. 4A is a schematic diagram of a circuit architecture of a voltage pre-adjustment circuit and a data line according to an embodiment of the present invention, and FIG. 4B is a schematic diagram of the signal timing corresponding to FIG. 4A. The voltage presetting circuit 1100 shown in FIG. 4A is actually a source driving line precharge circuit. The voltage presetting circuit 1100 includes an amplifier OP1, an amplifier OP2, and a bridge circuit MUX. MUX bridge circuit are electrically coupled to the output terminal of the amplifier OP1, and an output terminal of each amplifier OP2 data line SD ₁ to SD _M. An output terminal of the amplifier OP1 outputs a first precharge voltage V _p1 and an output terminal of the amplifier OP2 outputs a second precharge voltage V _p2 . Referring to FIG. 4B, each of the first time interval TP1 and the second time interval TP2 is divided into a precharge time interval TPC and a display time interval TD. The signal STB has a high potential during the precharge time interval TPC and a low potential during the display time interval TD.

In one embodiment, when the voltage pre-adjustment circuit 1100 is enabled, the bridge circuit MUX sends the first pre-charge voltage V _p1 to the data line SD _(2k-1) in the pre-charge time interval TPC of the first time interval TP1. And sends the second pre-charging voltage V _p2 to the data line SD _2k , where k is a positive integer. And the bridge circuit MUX sends the first precharge voltage V _p1 to the data line SD _{2k in the} precharge time interval TPC of the second time interval TP2, and sends the second precharge voltage V _p2 to the data line SD _(2k-1) . And during each display time interval TD, the bridge circuit MUX cuts off the current path between the amplifier OP1 and the amplifier OP2 and each data line. Therefore, as shown and, at each of the TPC precharge time interval, the voltage VS1 and the data line data line SD ₁ SD of the voltage VS2 of ₂ would each be assigned a first pre-charge voltage V _p1 or the second pre-charge voltage V _p2 4D . In one embodiment, when the voltage presetting circuit 1100 is not enabled, the bridge circuit MUX cuts off the current paths between the amplifier OP1 and the amplifier OP2 and the data lines. In a further embodiment, when the voltage presetting circuit 1100 is not enabled, the amplifiers OP1 and OP2 are disabled to reduce power consumption.

In another embodiment, please refer to FIG. 4C and FIG. 4D, wherein FIG. 4C is a schematic diagram of a circuit architecture of a voltage pre-adjustment circuit and a data line according to another embodiment of the present invention, and FIG. 4D is a schematic diagram of the signal timing corresponding to FIG. . The voltage presetting circuit 1100 shown in FIG. 4C is actually a source driving line charge sharing circuit. In this embodiment, the voltage presetting circuit 1100 has a plurality of switches SW ₁ to SW _{(M / 2)} . The switch SW _{1 is} electrically coupled to the data line SD ₁ and the data line SD ₂ respectively, and the switch SW _{k is} electrically coupled to each other. Connect data line SD _(2k-1) and data line SD _2k , where k is a positive integer. Referring to FIG. 4D, each of the first time interval TP1 and the second time interval TP2 is divided into a precharge time interval TPC and a display time interval TD. The signal STB has a high potential during the precharge time interval TPC and a low potential during the display time interval TD.

In one embodiment, when the voltage pre-regulation circuit 1100 is enabled, the switches SW ₁ to SW _{(M / 2)} are turned on during each pre-charge time interval TPC, so that adjacent data lines are shorted in pairs. To average its voltage. In each display time interval TD, each of the switches SW ₁ to SW _{(M / 2)} is opened. Therefore, as shown in each of the TPC precharge time interval, data line voltage VS1 ₁ SD (solid line) and the data line voltage VS2 ₂ SD (broken line) will be the same 4D, while the display time interval TD, the voltage VS1 and voltage VS2 are each charged to the corresponding voltage by the source driving circuit. In one embodiment, when the voltage pre-regulation circuit 1100 is not enabled, the switches SW ₁ to SW _{(M / 2)} continue to be disconnected regardless of the time interval.

The characteristic judgment circuit 1200 is used to selectively disable or enable the voltage preset circuit 1100 in the second time interval TP2. Specifically, when the feature judgment circuit 1200 receives the first pixel driving signals V _1,1 to V _{1, M} corresponding to the first pixels P _1,1 to P _{1, M} before the first time interval TP1, The feature judgment circuit 1200 obtains the first feature values CV1 of the first pixels P _1,1 to P _{1, M} corresponding to the first scan line GD1 according to the first pixel driving signals V _1,1 to V _{1, M.} . The first pixel driving signal V _1,1 is provided by the data line SD ₁ , and the first pixel driving signal V _1,2 is provided by the data line SD _2. The first pixel driving signal V _{1, M} Provided by the data line SD _M. Then, when the feature judgment circuit 1200 receives the second pixel driving signals V _2,1 to V _{2, M} corresponding to the second pixels P _2,1 to P _{2, M} before the second time interval TP2, the characteristics The judging circuit 1200 obtains the second characteristic values CV2 of the second pixels P _2,1 to P _{2, M} corresponding to the second scanning line GD2 according to the second pixel driving signals V _2,1 to V _{2, M.} The characteristic judgment circuit 1200 selectively disables the voltage pre-adjustment circuit 1100 in the second time interval TP2 according to the first characteristic value CV1 and the second characteristic value CV2. More specifically, the display device 1000 has a plurality of pixels P _1,1 to P _{N, M} arranged in an array, in which the pixels P _{h, k} are driven by the h-th scanning line and by the k-th data. The lines provide pixel drive signals. In addition, although only the first scan line GD1 and the second scan line GD2 are mentioned in the embodiments of the present invention, the first scan line GD1 and the second scan line GD2 are two scan lines that are sequentially enabled in time. , Does not correspond to the first scan line and the second scan of the display device 1000.

In an embodiment, for a method of calculating the first eigenvalue CV1 and the second eigenvalue CV2, please refer to FIG. 5, which is a flowchart of a eigenvalue calculation method according to an embodiment of the present invention. The process of calculating the first feature value is explained below. As shown in step S510, the first pixel driving signal is divided into N groups of pixel driving signals, where N is a positive integer greater than 1, and each group of pixel driving signals Contains a plurality of first pixel driving signals. As shown in step S520, according to the first brightness threshold value and the second brightness threshold value, a brightness characteristic value corresponding to each first pixel driving signal is given. As shown in step S530, according to the obtained luminance feature values, a cumulative feature value corresponding to each group of pixel driving signals is calculated. As shown in step S540, a first feature value is obtained according to the foregoing N accumulated feature values.

For this step flow, N is equal to 6 as an example for illustration, but N may also be 2 or other appropriate numbers, for example. In step S510, the first pixel driving signals V ₁₁ to V _1M are divided into six groups of pixel driving signals S ₁ to S ₆ , and the manner of differentiation is as follows in the following equation (1):

(1)

(1)

Therefore, the pixel driving signals used to drive the first pixel are grouped according to the remainder divided by 6. That is, the first pixel driving signal and the seventh pixel driving signal are grouped into the same group. The second Each pixel driving signal and the eighth pixel driving signal will be grouped into the same group, and the third pixel driving signal and the ninth pixel driving signal will be grouped into the same group. And so on. More specifically, the first group of pixel driving signals has a first pixel driving signal, a seventh pixel driving signal, a thirteenth pixel driving signal, and the like. The second group of pixel driving signals includes a second pixel driving signal, an eighth pixel driving signal, a fourteenth pixel driving signal, and the like.

The above-mentioned m is a positive integer, and n is a non-negative integer. Then, for each pixel driving signal with the same sequence of pixel driving signals, it is calculated whether the accumulation is needed. For example, the pixel driving signals V _1,1 to V _1,6 of the first order of the pixel driving signals of each group are based on the pixel driving signals V _1,1 to V _1,6 . Step value to determine whether to add the pixel driving signals V _1,1 to V _1,6 . The pixel driving signals V _1,7 to V _1,12 in the second order of the pixel driving signals of each group are based on the grayscale values corresponding to each of the pixel driving signals V _1,7 to V _1,12 . To determine whether to add the pixel driving signals V _1,7 to V _1,12 . The pixel driving signal V _{1, n} refers to a driving signal provided to the n-th pixel corresponding to the first scanning line GD1. Assume that the provided pixel driving signals V _1,1 to V _{1, M} and V _2,1 to V _{2, M are} each an eight-bit signal, that is, the mean value of the pixel driving signal Between 0 and 255, the first brightness threshold and the second brightness threshold are given to perform the foregoing determination. For example, if the first brightness threshold is 200 and the second brightness threshold is 50, if the pixel drive signals V _1,1 to V _{1,6 have} a grayscale value between 50 and 200, , The pixel driving signals V _1,1 to V _{1,6 are} not included in the accumulation. If all the grayscale values in the pixel driving signals V _1,1 to V _1,6 are not between 50 and 200, then when the grayscale value is greater than 200, the corresponding pixel driving signal is given a brightness characteristic value 1. Conversely, when the grayscale value is less than 50, the corresponding pixel driving signal is given a brightness characteristic value of 0. For example, the following table. Table I

As described above, by accumulating the luminance characteristic values of all the pixel driving signals to be added in each group of pixel driving signals, the cumulative characteristic values of the six groups of pixel driving signals can be obtained in sequence. As shown in Table 2, the cumulative characteristic values of the six pixel driving signals corresponding to the plurality of first pixel driving signals obtained at a certain point in time on a 1920 × 1280 screen. For example, the cumulative eigenvalue of the first pixel driving signal group is 951, which means that among the 960 pixel driving signals belonging to the first group of pixel driving signals, 951 pixel driving signals have a luminance characteristic value of 1. The cumulative characteristic value of the second pixel driving signal group is 551, which means that out of a total of 960 pixel driving signals belonging to the second group of pixel driving signals, the luminance characteristic value of 551 pixel driving signals is 1, and so on analogy. In step S540, according to the six accumulated feature values corresponding to the six pixel drive signals and a feature threshold value, the first feature value results corresponding to the foregoing plurality of first pixel drive signals are also shown in Table 2. Specifically, each cumulative feature value is compared with a feature threshold value. If the cumulative feature value is greater than the feature threshold value, the flag value corresponding to the set of pixel driving signals is 1, otherwise it is 0. The characteristic threshold in Table 2 is set to half of 960, which is 480. The six flag values (1,1,0,0,0,1) constitute the first eigenvalue. The flag value corresponding to the first pixel driving signal group is the flag CV11, the flag value corresponding to the second pixel driving signal group is the flag CV12, and the flag value corresponding to the third pixel driving signal group Is the flag CV13, the flag value corresponding to the fourth pixel driving signal group is the flag CV14, the flag value corresponding to the fifth pixel driving signal group is the flag CV15, and the sixth pixel driving signal group The corresponding flag value is the flag CV16. The flags CV11 to CV16 constitute the first characteristic value CV1. Table II

The method for obtaining the first eigenvalue has been described above, and the method for obtaining the second eigenvalue is the same, so it will not be described again. Similarly, the second characteristic value corresponding to the second pixel driving signal can be obtained as shown in Table 3. In other words, the second eigenvalue CV2 is (0,1,1,0,1,1). Table three

After obtaining the first eigenvalue CV1 and the second eigenvalue CV2 according to the methods corresponding to Tables 1 and 2, the operation in step S130 is as follows. In one embodiment, the characteristic judgment circuit 1200 calculates the difference between the first characteristic value CV1 and the second characteristic value CV2, and when the difference value is less than the difference threshold value, the first preset mechanism is stopped, that is, the energy pre-adjustment is stopped. Circuit 1100. In practice, please refer to FIG. 6, which is a schematic circuit diagram of a part of a feature judgment circuit according to an embodiment of the present invention. As shown in FIG. 6, the feature determination circuit 1200 includes six exclusive or gate (XOR) XOR1 to XOR6, an addition circuit ADD, and a comparison circuit COMP. The two inputs of the mutex OR gate XOR1 are respectively used to receive the first flag CV11 of the first characteristic value CV1 and the first flag CV21 of the second characteristic value CV2. The two inputs of the mutex OR gate XOR2 are respectively used to receive the second flag CV12 of the aforementioned first characteristic value CV1 and the second flag CV22 of the aforementioned second characteristic value CV2. The two inputs of the mutex OR gate XOR3 are respectively used to receive the third flag CV13 of the aforementioned first characteristic value CV1 and the third flag CV23 of the aforementioned second characteristic value CV2. The two inputs of the mutex OR gate XOR4 are respectively used to receive the fourth flag CV14 of the first characteristic value CV1 and the fourth flag CV24 of the second characteristic value CV2. The two inputs of the mutex OR gate XOR5 are respectively used to receive the fifth flag CV15 of the aforementioned first characteristic value CV1 and the fifth flag CV25 of the aforementioned second characteristic value CV2. The two inputs of the mutually exclusive OR gate XOR6 are respectively used to receive the sixth flag CV16 of the aforementioned first characteristic value CV1 and the sixth flag CV26 of the aforementioned second characteristic value CV2. The input terminals of the addition circuit ADD are respectively electrically coupled to the output terminals of the aforementioned mutually exclusive OR gates XOR1 to XOR6. Therefore, the output value of the addition circuit ADD indicates the difference between the first eigenvalue and the second eigenvalue. The comparison circuit COMP compares the difference value with a difference threshold value TDIFF to selectively stop the first preset mechanism, that is, the energy pre-adjustment circuit 1100, with the comparison result R. The mutually exclusive OR gates XOR1 to XOR6 and the addition circuit ADD in this embodiment can be regarded as one operation circuit.

The first feature value and the second feature value are used to describe a way of arranging features of multiple pixels on a scanning line in a frame. More specifically, in the embodiment described above, each cumulative feature value describes whether the grayscale value of the corresponding plurality of pixels as a whole is lighter or darker. By comparing the first eigenvalue with the second eigenvalue, it is possible to understand the brightness change of the pixels corresponding to the two scanning lines sequentially enabled in time. If the brightness change of the pixels corresponding to the two scanning lines is greater than a certain degree, the difference value is greater than the difference threshold value TDIFF; otherwise, if the brightness change of the pixels corresponding to the two scanning lines is less than a certain degree, the difference value is less than Difference threshold TDIFF. When the pixel brightness changes corresponding to the two scanning lines are so large that the difference value is smaller than the difference threshold value TDIFF, it means that the pixel brightness distribution corresponding to the two scanning lines should not have too much difference. Therefore, it is not necessary to enable the voltage pre-adjustment circuit 1100 to not cause the picture to be updated badly, so the first preset mechanism is stopped at this time, that is, the voltage pre-adjustment circuit 1100 is stopped.

According to the method described above, it is possible to use six registers to record the characteristic value of a scanning line, and greatly reduce the use of storage medium circuits. More specifically, according to the above-mentioned architecture, only a small number of addition circuits and digital comparators are required to obtain the feature values and the two feature values corresponding to the two scan lines are compared to obtain a judgment result.

In another embodiment, the feature determining circuit 1200 determines whether the first feature value and / or the second feature value is a preset feature value. When it is determined that the first feature value and / or the second feature value are preset feature values, the first preset mechanism is stopped or the second preset mechanism is started. Specifically, to determine whether the first feature value is a preset feature value, please refer to FIG. 2 and FIG. 7, where FIG. 7 is a schematic circuit diagram of a part of a feature determination circuit according to another embodiment of the present invention. As shown in FIG. 2, the display device 1000 further has a storage medium MEM for storing one or more preset characteristic value storage media, which can be implemented by a semiconductor device having a storage function, such as a non-volatile memory. As shown in FIG. 7, the characteristic judgment circuit 1200 includes mutually exclusive OR gates XOR1 to XOR6 and an inverse OR gate NOR. The two inputs of the mutex OR gate XOR1 are respectively used to receive the first flag CV11 of the first characteristic value CV1 and the first flag of the predetermined characteristic value. The two inputs of the mutex OR gate XOR2 are respectively used to receive the second flag CV12 of the first characteristic value CV1 and the second flag of the predetermined characteristic value. The two inputs of the mutex OR gate XOR3 are respectively used to receive the third flag CV13 of the first characteristic value CV1 and the third flag of the predetermined characteristic value. The two inputs of the mutex OR gate XOR4 are respectively used to receive the fourth flag CV14 of the first characteristic value CV1 and the fourth flag of the predetermined characteristic value. The two inputs of the mutex OR gate XOR5 are respectively used to receive the fifth flag CV15 of the first characteristic value CV1 and the fifth flag of the predetermined characteristic value. The two inputs of the mutually exclusive OR gate XOR6 are respectively used to receive the sixth flag CV16 of the first characteristic value CV1 and the sixth flag of the predetermined characteristic value. The six input terminals of the NOR gate NOR respectively receive the output values of the aforementioned mutually exclusive NOR gates XOR1 to XOR6. Therefore, when the output value of one of the exclusive OR gates XOR1 to XOR6 is logic true, the output of the inverse OR gate NOR is logic false, that is, at least one flag of the first characteristic value CV1 does not correspond Based on preset characteristic values. In other words, the output of the inverse OR gate NOR is true only when the first characteristic value CV1 completely corresponds to the preset characteristic value. If the first feature value CV1 and / or the second feature value CV2 are determined to be preset feature values according to the above circuit, the first preset mechanism is stopped or the second preset mechanism is started. Regardless of whether the voltage presetting circuit 1100 is in the state of FIG. 4A or the state of FIG. 4C, the feature judgment circuit does not need to rely on the polarity of each data line to perform the feature value comparison. In addition, the storage medium MEM in each embodiment of the present invention is, for example, a volatile storage medium or a non-volatile storage medium, which is not limited in the present invention.

In an embodiment, when the first feature value CV1 and the second feature value CV2 are obtained, the feature determination circuit 1200 further obtains the first feature value CV1 and the second feature value CV2 according to a pixel correspondence table. Specifically, please refer to FIG. 2 and FIG. 8, which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 2, the display device 1000 further has a storage medium MEM for storing a pixel correspondence table. The pixel correspondence table is used to describe the connection relationship between each pixel and each data line. As shown in FIG. 2, in an embodiment, the first pixel P _1,1 and the second pixel P _2,1 are electrically coupled to the data line SD ₁ , and the first pixel P _1,2 and the first pixel The two pixels P _2,2 are electrically coupled to the data line SD ₂ , and the first pixels P _{1, M} and the second pixel P _{2, M} are electrically coupled to the data line SD _M. As shown in FIG. 8, in another embodiment, the first pixel P _{1,1 is} electrically coupled to the data line SD ₁ , and the first pixel P _1,2 and the second pixel P ₂₁ are electrically coupled. Connected to the data line SD ₂ , the first pixel P _{1, M} and the second pixel P _{2, (M-1)} are electrically coupled to the data line SD _M , and the second pixel P _{2, M is} electrically Coupled to the data line SD _{M + 1} .

In an embodiment, the first scan line GD1 is the i-th scan line of the display device 1000, and the second scan line GD2 is the (i + 1) -th scan line of the display device 1000, where i is a positive integer. In another embodiment, the first scan line GD1 is the i-th scan line of the display device 1000, and the second scan line GD2 is the (i + 2) -th scan line of the display device 1000. In other words, the relationship between the first scan line GD1 and the second scan line GD2 is different according to the different screen update modes of the display device 1000, and the corresponding relationships between pixels may also be different. The pixel correspondence table stores the electrical coupling relationship between each data line and each pixel. More specifically, the pixel correspondence table may store a variety of electrical coupling relationships between the data lines and the pixels, so that when the screen update mode of the display device 1000 is adjusted, the feature determination circuit 1200 can correspondingly retrieve from the pixel correspondence table To get the correct pixel correspondence.

In another embodiment, please return to FIG. 2. The display device 1000 further includes a pixel mapping unit PREMAPPING which is electrically coupled to each data line and the feature determination circuit 1200. The pixel mapping unit PREMAPPING is also a circuit implementation of the aforementioned pixel mapping table, and is used to transmit the driving signals of each pixel input to the display device 1000 to the corresponding data lines to drive the corresponding first pixels and / or second pixels. Vegetarian. The feature determination circuit 1200 directly obtains the first feature and the second feature according to each of the first pixel driving signals and each of the second pixel driving signals output by the pixel mapping unit PREMAPPING. The pixel mapping unit PREMAPPING can be implemented by a circuit, or by a program (such as a programmable logic circuit) carried on the circuit.

Specifically, please refer to FIG. 2 and FIG. 9A, where FIG. 9A is a timing chart corresponding to the pixel driving signal of FIG. 2. As shown in FIG. 9A, in each group of pixel driving signals corresponding to the scanning line GD1, for example, the first group of pixel driving signals will have a signal R1 (corresponding to pixels P _1,1 ), a signal R3 (corresponding to pixels) P _1,7 ) and other signals. The second group of pixel driving signals will include signals G1 (corresponding to pixels P _1,2 ), and signals G3 (corresponding to pixels P _1,8 ). The third group of pixel driving signals will have signals such as signal B1 (corresponding to pixel P _1,3 ), signal R3 (corresponding to pixel P _1,9 ), and so on. The fourth group of pixel driving signals will have signals such as signal R2 (corresponding to pixel P _1,4 ), signal R4 (corresponding to pixel P _1,10 ), and so on. The fifth group of pixel driving signals will have signals such as signal G2 (corresponding to pixel P _1,5 ), signal G4 (corresponding to pixel P _1,11 ), and so on. The sixth group of pixel driving signals will have signals such as signal B2 (corresponding to pixels P _1,6 ), signal B4 (corresponding to pixels P _1,12 ), and the like. The pixel driving signals corresponding to the scanning lines GD2 correspond to the pixel driving signals corresponding to the scanning lines GD1.

On the other hand, please refer to FIG. 8 and FIG. 9B, where FIG. 9B is a timing chart corresponding to the pixel driving signal of FIG. 8. As shown in FIG. 9B, the pixel driving signals of each group corresponding to the scanning line GD1 are the same as the example in FIG. 9A. However, the pixel driving signals corresponding to the scanning lines GD2 are different from the pixel driving signals corresponding to the scanning lines GD1. Therefore, it is necessary to use the pixel mapping unit PREMAPPING or the storage medium MEM to enable the feature determination circuit 1200 to obtain the correct pixel signal correspondence relationship.

In another embodiment, please return to FIG. 2. The display device 1000 further includes a gray-scale control circuit 1300. The gray-scale control circuit 1300 is electrically coupled to the feature determination circuit 1200. The control circuit 1300 is enabled to adjust the grayscale values of some of the aforementioned first pixels P _1,1 to P _{1, M} and the second pixels P _2,1 to P _{2, M.} Specifically, please refer to FIG. 9, which is a gray scale control curve diagram according to an embodiment of the present invention. The horizontal axis of FIG. 9 is the grayscale value given by the pixel driving signal, and the vertical axis is the grayscale value of the pixel. It can be seen from FIG. 9 that in an embodiment, the grayscale value G _{o of the} actual pixel emission and the grayscale value G _i given by the pixel driving signal can be described by the following equation (2):

(2)

Wherein G ₁ is, for example 100, G _2, for example 190, α, for example, 0.5, β is, for example 0.5. Therefore, when the grayscale value given by the pixel driving signal is 200, the grayscale value of the pixel is only 195. Therefore, G ₁ and G _{2 are} two gray-scale thresholds. The above-mentioned values of G ₁ , G ₂ , α, and β are merely examples, and the present invention is not limited thereto. The number of gray-level thresholds and the gray-level control curve can be set freely by those with ordinary knowledge in the technical field, which is not limited in the present invention.

In another embodiment, the display device 1000 further includes a temperature controller 1400. The characteristic determination circuit 1200 controls the grayscale control circuit 1300 through the temperature controller 1400. The temperature controller 1400 determines whether to enable the grayscale control circuit 1300 according to the operating temperature of the display device 1000 and whether the second preset mechanism is activated. For example, when the operating temperature of the display device 1000 is lower than 40 degrees Celsius, even if the second preset mechanism is activated, the grayscale control circuit 1300 will not be activated. When the temperature of the display device 1000 reaches more than 40 degrees Celsius, once the second preset mechanism is activated, the grayscale control circuit 1300 is enabled by the temperature controller 1400.

In an embodiment, the above-mentioned circuits such as the feature determination circuit 1200, the grayscale control circuit 1300, and the temperature controller 1400 are disposed in a control chip of the display device 1000. In another embodiment, the circuits are integrated in a timing controller of the display device 1000. In one embodiment, the circuits are integrated as part of a transistor circuit on the panel. Those with ordinary knowledge in the art can appropriately change and configure the structure of the display device according to the technical ideas described in the description of the present invention. The above embodiments are not intended to limit the circuit configuration of the disclosed display device.

In summary, according to the display device and the control method thereof disclosed by the present invention, the pixel characteristic values corresponding to two scanning lines (gate driving lines) driven in two adjacent time intervals are selectively stopped. The first preset mechanism or the preset mechanism is activated to disable part of the circuits in the display device or enable another part of the circuits to achieve the purpose of reducing power consumption.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the patent protection scope of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

1000‧‧‧ display device
1100‧‧‧Voltage preset circuit
1200‧‧‧Feature judgment circuit
1300‧‧‧Grayscale control circuit
1400‧‧‧Temperature Controller
ADD‧‧‧ Addition circuit
COMP‧‧‧Comparison circuit
CV11 ~ CV16, CV21 ~ CV26‧‧‧flag value
GD1, GD2 ‧‧‧scan line
MEM‧‧‧Storage medium
MUX‧‧‧Bridge Circuit
NOR‧‧‧Anti-OR gate
OP1, OP2‧‧‧amplifier
P _1,1 ~ P _{1, M} , P _2,1 ~ P _{2, M} ‧‧‧pixels
PREMAPPING‧‧‧Pixel Mapping Unit
R‧‧‧ comparison result
SD ₁ ~ SD _{M + 1} ‧‧‧Data cable
STB ‧‧‧Signal
SW ₁ ~ SW _{(M / 2)} ‧‧‧Switch
TDIFF‧‧‧Threshold
TP1, TP2, TPC, TD‧‧‧
V _p1 , V _p2 , VS1, VS2, VG1, VG2‧‧‧Voltage
XOR1 ~ XOR6‧‧‧mutual exclusion or gate

FIG. 1 illustrates a display device control method according to an embodiment of the invention. FIG. 2 is a schematic structural diagram of a display device according to an embodiment of the invention. FIG. 3 is a signal timing diagram corresponding to FIG. 2. 4A is a schematic diagram of a circuit architecture of a voltage pre-adjustment circuit and a data line according to an embodiment of the present invention. FIG. 4B is a signal timing diagram corresponding to FIG. 4A. FIG. 4C is a schematic diagram of a circuit architecture of a voltage preset circuit and a data line according to another embodiment of the present invention. FIG. 4D is a signal timing diagram corresponding to FIG. 4C. FIG. 5 is a flowchart of a method for calculating a characteristic value according to an embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a part of a feature judgment circuit according to an embodiment of the present invention. FIG. 7 is a schematic circuit diagram of a feature determination circuit according to another embodiment of the present invention. FIG. 8 is a schematic circuit diagram of a display device according to another embodiment of the invention. FIG. 9A is a corresponding timing diagram of the pixel driving signal corresponding to FIG. 2. FIG. 9B is a timing chart corresponding to the pixel driving signal of FIG. 8. FIG. 10 is a grayscale control curve diagram according to an embodiment of the present invention.

Claims (17)

A display device control method is applicable to a display device. The method includes: when receiving a plurality of first pixel driving signals of a plurality of first pixels driven by a first scanning line of the display device, obtaining Regarding a first characteristic value of the first pixel driving signals of the first scanning line, the first scanning line is driven in a first time interval; when it is driven by a second scanning line of the display device A plurality of second pixel driving signals of a plurality of second pixels, a second characteristic value of the second pixel driving signals related to the second scanning line is obtained, and the second scanning line is at a second The time interval is driven, and the second time interval is later in time and adjacent to the first time interval; and according to the first eigenvalue and the second eigenvalue, selectively stopping a time interval in the second time interval The first preset mechanism or a second preset mechanism is activated. The method according to item 1 of the scope of patent application, wherein the step of selectively stopping the first preset mechanism in the second time interval according to the first characteristic value and the second characteristic value includes: calculating A difference between the first eigenvalue and the second eigenvalue; and when the difference is less than a difference threshold, stopping the first preset mechanism. The method according to item 1 of the scope of patent application, wherein the step of selectively stopping the first preset mechanism in the second time interval according to the first characteristic value and the second characteristic value includes: judging Whether the first feature value or the second feature value is a preset feature value; and when one of the first feature value and the second feature value is the preset feature value, stopping the first preset mechanism . The method according to item 1 of the scope of patent application, wherein the step of obtaining the first characteristic value includes: dividing the first pixel driving signals into N groups of pixel driving signals, where N is a positive value greater than 1. An integer, and each group of pixel driving signals includes a plurality of first pixel driving signals; according to a first brightness threshold value and a second brightness threshold value, a brightness characteristic corresponding to each of the first pixel driving signals is given Value; calculating a cumulative feature value corresponding to each group of pixel driving signals according to the brightness feature values; and obtaining the first feature value according to the N cumulative feature values. The method according to item 1 of the scope of patent application, wherein the steps of obtaining the first feature value and obtaining the second feature value further include obtaining a first feature value and the first feature value according to a pixel correspondence table. Two characteristic values. The display device includes a plurality of data lines. The pixel correspondence table is used to describe the electrical coupling relationship between the first pixels, the second pixels, and the data lines. The method according to item 1 of the scope of patent application, wherein when the first preset mechanism is stopped, a source driving line precharging circuit in the display device is disabled, and the source driving line precharging circuit is used for When enabled, the data lines corresponding to the first pixels and the second pixels are respectively charged to a corresponding first voltage. The method according to item 1 of the scope of patent application, wherein when the first preset mechanism is stopped, a source driving line charge sharing circuit in the display device is disabled, and the source driving line charge sharing circuit is used for When enabled, some of the plurality of data lines corresponding to the first pixels and the second pixels are shared with each other. The method according to item 1 of the scope of patent application, wherein when the second preset mechanism is activated, a grayscale control circuit in the display device is selectively enabled, and the grayscale control circuit is used to be enabled. , The grayscale values of at least some of the first pixels and the second pixels are adjusted. The method described in item 8 of the scope of patent application further includes determining whether to enable a gray-scale control circuit for adjusting when the display device is enabled based on an operating temperature of the display device and whether the preset mechanism is activated. Grayscale values of at least some of the first pixels and the second pixels. A display device includes: a plurality of first pixels; a plurality of second pixels; a first scanning line electrically coupled to the first pixels for driving the first pixels in a first time interval; A pixel; a second scanning line electrically coupled to the second pixels for driving the second pixels in a second time interval, the second time interval being later than and adjacent to each other in time During the first time interval; a plurality of data lines, each of which is electrically coupled to one of the first pixels and one of the second pixels; a voltage preset circuit, electrically coupled Connect the data lines for pre-charging or charge sharing of the data lines; and a feature judgment circuit, when receiving a plurality of first pixel driving signals corresponding to the first pixels, the feature The judging circuit obtains a first characteristic value of the first pixel driving signals, and when receiving a plurality of second pixel driving signals corresponding to the second pixels, the characteristic judging circuit is based on A second characteristic value of the second pixel driving signals is obtained, and the characteristic judgment circuit and According to the first characteristic value and the second characteristic value, the voltage pre-adjusting circuit is selectively disabled in the second time interval. The display device according to item 10 of the scope of patent application, wherein the characteristic judgment circuit comprises: an arithmetic circuit for calculating a difference between the first characteristic value and the second characteristic value; and a comparison circuit, electrically Coupled to the operation circuit to compare the difference value with a difference threshold value to generate a stop signal. The display device according to item 10 of the scope of patent application, wherein the display device further includes a storage medium electrically coupled to the feature judgment circuit for storing at least one preset feature value, and the feature judgment circuit judges the first feature value. Whether a feature value or the second feature value is a preset feature value, and when one of the first feature value and the second feature value is the preset feature value, the feature judgment circuit stops the voltage presetting Circuit. The display device according to item 10 of the scope of patent application, wherein the feature judgment circuit divides the first pixel driving signals into N groups of pixel driving signals, where N is a positive integer greater than 1, and each group of images is The pixel driving signal includes a plurality of first pixel driving signals, and the characteristic judging circuit gives a brightness characteristic value corresponding to each of the first pixel driving signals according to a first brightness threshold and a second brightness threshold. Then, based on the brightness feature values, a cumulative feature value corresponding to each group of pixel driving signals is calculated, so as to obtain the first feature value according to the N cumulative feature values. The display device described in item 10 of the scope of patent application, further includes a storage medium electrically coupled to the feature judgment circuit for storing a pixel correspondence table, and the feature judgment circuit is based on the first pixels. The driving signal and the pixel correspondence table are used to obtain the first feature value, and the second pixel driving signal and the pixel correspondence table are used to obtain the second feature value. The pixel correspondence table is used to describe the pixels. The electrical coupling relationship between the first pixel, the second pixels, and the data lines. The display device according to item 10 of the patent application scope, wherein the voltage pre-regulation circuit is a source driving line pre-charging circuit or a source driving line charge sharing circuit, and the source driving line charge sharing circuit is used for When enabled, some of the plurality of data lines corresponding to the first pixels and the second pixels share charge with each other, and the source driving line precharge circuit is used when being enabled , Respectively charging the plurality of data lines corresponding to the first pixels and the second pixels to a corresponding first voltage. The display device according to item 10 of the patent application scope further includes a grayscale control circuit, which is used to adjust the first pixels and the second pixels when the grayscale control circuit is enabled. The grayscale value of at least a part of the pixels. The grayscale control circuit is selectively enabled when the feature judgment circuit determines that the first feature value matches a preset feature or the second feature value matches the preset feature. . The display device according to item 16 of the scope of patent application, further comprising a temperature controller. When the feature judging circuit determines that the first feature value meets a preset feature or the second feature value meets the preset feature, the display The temperature controller determines whether to enable the grayscale control circuit according to an operating temperature of the display device.