TW201802574A - Method of simultaneous lithography and etch correction flow - Google Patents

Abstract

A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Description

Simultaneous lithography and etching correction process

The present disclosure relates to semiconductor fabrication, and more particularly to systems and methods for performing simultaneous lithography and etch process calibration processes.

In one embodiment, the "tape out" process is a process of implementing a data processing method and simulation to construct a single mask and/or correcting the lithographic error of the semiconductor layer design. In a specific embodiment, the method The individual mask polygons can be moved (eg, shifted) to account for, for example, any predicted overlay error during or during the optical proximity correction (OPC) step. OPC is used to correct lithographic nonlinearity by performing simulation, lithography process modeling, and, for example, calibration modeling for optimizing mask size (eg, changing mask size). The OPC process is performed to produce a mask "shape", and the mask data is used to form (print) a mask and a printed mask for forming semiconductor features in the lithography process.

The critical dimensions continue to shrink at technology nodes that exceed 22nm, and the process window for each process step is reduced. As a result, after the lithographic printing process is performed using the OPC design mask, it is seen that if an etching process is used after lithography such as reactive ion etching (RIE), the resulting etching step The crash will significantly fail in a variety of critical design configurations.

Thus, OPC provides the shape of the mask used to create the mask, and the use of the corrected lithography will print the feature. However, due to the RIE etching stage processing, the printed features on the substrate are gradually failing.

In the ideal case, there is a set of process conditions where no fault is found. This set of conditions is the process window (PW), which also prints the focus of the trouble-free wafer and the range of dose variation. The masks created must have tolerance for these process variations. For example, as is known, the focus exposure matrix masters the wafer process, with some variations added to account for manufacturing process variables. When lithography is performed, the main variables in the lithography are the focus and the exposure dose (i.e., how well the focus is maintained, and the amount of light (exposure dose)). Focus and exposure and dose variation are produced in a matrix, and the wafer is exposed through a pattern of focus and dose variations to produce the matrix. These patterns are measured under all process and exposure conditions.

When patterning, in the "Process Window" (PW), the boundaries of lithography and etching always collide with each other and lead to optimization, each of which will independently cause another boundary to hard fail. This is especially true as technology moves toward 22nm and more advanced nodes.

In one particular embodiment, an over-determined failure type is a resist top loss induced failure when etching in a hard mask opening (HMO) (HMO etch process) step.

Figure 1 shows an exemplary photo-resist material top-loss phenomenon and pattern transfer through failure of the etch. The top view shows a pair of mask edges 12A, 12B that define a gap 15 for depositing a resist layer 18 on the wafer, as the picture shows. As shown in Figure 1, Scheme 13 shows the normalized resist thickness as a function of the light (exposure) of the resist layer. As shown, low dose exposure has no material loss. As shown in the accompanying diagram 13, after exposure, in the ideal case, the photoresist layer does not lose any material until such a large dose (e.g., critical dose) is applied with the desired amount of exposure. However, due to this resistive property, when scattered photons hit the unexposed areas, the thickness/volume begins to deplete from the original level 11, i.e., the resist top loss (resistance level is lowered). This causes the pattern to be pinched and cannot be transferred by etching. Different design configurations result in different levels of concealment (resistance) strength 19, while the degree of resist height generation is illustrated as shown, possibly changing the same critical dimension (CD) resist feature 18A, 18B or 18C. That is, only the height of the resist is affected, and the CD is not affected, that is, the bottom size is not affected (due to focus and/or dose variation (process variation), mask design shape, etc.).

In the lithographic modeling used, SEM measurements were taken on the bottom critical dimension (CD) to measure the width and/or space of the bottom end of the resist. Because only the resist height is changed, the lithography model does not know the resist height change.

Due to the relationship of the resist properties (scheme 13 of Figure 1), when the scattered photons hit the unexposed areas, the exposed resist loses its thickness/volume. This causes the pattern to be pinched and cannot be transferred by etching, causing the etch to fail due to HMO failure.

2 shows a resulting wafer image 10 showing electron beam inspection (EBI) tool results showing multiple post RIE etch process failures 25 on multiple mask exposures/dies 30 of wafer 20 (in a specific set of Under the dosage process conditions). In particular, Figure 2 shows an exemplary 22 nm process with errors in the "Mx" metal steps. Here, the EBI test at the post HMO shows no PW. Both lithography modeling and ORC (optical rule inspection) are unpredictable for wafer failure due to FBI25. This ORC is a simulation of the mask and inspection (measurement) of finding a problem point (potential failure) during application to the wafer. The etch after the wafer failure 25 is not predicted, that is, the normal lithography model cannot predict this type of failure mechanism.

In the case, the conventional OPC correction process does not capture the correction failure mechanism and does not drive the mask size to an optimized common process center between lithography and etching.

Furthermore, the lack of a good etch model can result in patterning failure. For example, the bottom CD of the photoresist may be within specifications, but as noted, post-etching may fail. These failures are related to the top damage of the photoresist, but the top loss or 3D resist profile is difficult to measure directly and accurately model. Moreover, any applied etch model tends to be inaccurate and has resulted in unmanufactured lithography conditions. For example, the etch model lacks the "process window" simulation capability: 1) the reason is that the etch bias is only dependent on the pattern density condition; and 2) it has nothing to do with the lithography pattern fidelity or the 3D resist profile.

Furthermore, while 3D resist simulations are expensive and not suitable for full wafer analysis, this resist simulation can still be used to build more physically and accurately etched models.

In addition, in the modeling process, different models are usually established for the optical photolithography process and the etching process. This photolithography model involves describing an optical model of light formation in an exposure tool and exposing the exposure of the photoresist A photoresist model with development. These models are typically calibrated to a single set of measurements taken in a post-developed photoresist using a CD-SEM. CD-SEM measurements are typically applied at the bottom end of the photoresist, while measurement artifacts are removed by SEM-to-physical bias correction applied to the bottom CD measurement. This etch process is typically modeled as a variable deviation between post-development and post-etch measurements. This variable deviation was found to be a function of the parameters related to the pattern density of the post-developing pattern. If the quality of the photolithography is appropriate, the pattern density of the lithographic design target can be used as a proxy for the patterned photoresist, resulting in an increase in simulation efficiency.

However, this method does not fully take into account the complex interaction between the 3-dimensional photoresist profile, the CD-SEM measurement function, and the photoresist pattern transfer through the etching process to the film stack. Since the etch transfer may depend on the 3-dimensional profile of the photoresist, and depending on other factors of conventional considerations such as local pattern density in the etch model, it is reasonable to consider the full resist profile when creating a solid etch model.

However, 3D resist profile simulations are expensive and time consuming, and therefore are not suitable for full wafer etch modeling.

Since the conventional OPC correction process cannot capture the correction failure mechanism and cannot drive the mask size into the optimized common process center between lithography and etching, it provides a way to drive the mask size to A system and method for co-optimizing lithography and etching (eg, hard mask opening (HMO)) processes in an OPC calibration process centered between lithography/etching processes.

Accordingly, a method of optimizing a common process window between lithography and etching processes is provided. For example, a robust lithography model coupled with an HMO model will prevent defects and improve lithography process control/metering.

Furthermore, a method for rapidly approximating the 3D resist profile characteristics to facilitate the transferred etch pattern is provided.

Thus, in accordance with a first aspect, a system and method for etching mask correction is provided. The method includes: performing a first lithography process model simulation on a computer system, resulting in a line or space feature of the mask in the first process window; performing a second hard mask opening etching process model simulation on the computer system, Resulting in generating a line or space feature of the mask in the second process window; determining whether performing line features or spatial features generated by each of the first process model simulation and the second process model simulation are within respective target specifications; and modifying The mask design in a single iteration of the loopback procedure causes the line feature specification or spatial feature specification to be within each individual target specification and results in a common process window (PW) optimized between lithography and etching, wherein The lithography and etch mask process models are simultaneously optimized during the repeated loop processing.

In a further aspect, a calibration system and method for a hard mask open etch process is provided. The calibration method includes: obtaining an etched model form that takes into account an etched pattern due to a three-dimensional photoresist shape variation, the model form including two optical and density parameters directly related to the optical image, the calibration method comprising: performing an optical imaging model to mask The cover design specification produces the optical and density parameters; and in the reverse processing loop, the optical image parameters are entered in each of the first lithography process model simulations, and The optical image parameters in the second hard mask opening etch process model simulation are used as a proxy for the 3D resist profile, which produces an efficient and accurate simulation of the etched pattern.

10‧‧‧ wafer imagery

11‧‧‧ original level

12A‧‧‧mask edge

12B‧‧‧mask edge

13‧‧‧Illustration

15‧‧‧ gap

18‧‧‧Resist layer

18A‧‧‧Resistance characteristics

18B‧‧‧Resistance characteristics

18C‧‧‧Resistance characteristics

19‧‧‧Concealed (resistance) strength

20‧‧‧ wafer

25‧‧‧ wafer failure

30‧‧‧mask exposure/grain

50‧‧‧Process window range

53‧‧‧ lithography CD variation

55‧‧‧HMO/etching processing window

56‧‧‧After lithography key size CD variation

57‧‧‧HMO etching CD variation

60‧‧‧Resistive feature printing

63‧‧‧CD features

64‧‧‧CD features

65‧‧‧Resist feature printing

66‧‧‧CD features

70‧‧‧Conceptual superposition

80‧‧‧Process window range

83‧‧‧ HMO CD variation across process windows

85‧‧‧ lithography processing window

86‧‧‧ center line

87‧‧‧ lithography CD variation

88‧‧‧ Target

90‧‧‧Resistive feature printing

93‧‧‧Highly accurate printed features

96‧‧‧The line features are pinched

100‧‧‧OPC process simulation

110‧‧‧Process window

200‧‧‧ Process

204‧‧‧Steps

210‧‧‧Steps

250‧‧‧ steps

275‧‧‧Steps

300‧‧‧Steps

302‧‧‧Steps

305‧‧‧Steps

310‧‧‧Steps

325‧‧‧OPC mask making method

327~353‧‧‧Steps

350‧‧‧ Wafer

360‧‧‧Executive Form

362‧‧‧ first line

364‧‧‧ second line

366‧‧‧ third line

368‧‧‧ fourth line

370‧‧‧5rd line

375‧‧‧ wafer

377‧‧‧Executive relationship diagram

380‧‧‧Executive relationship diagram

383‧‧‧Executive relationship diagram

390‧‧‧Executive relationship diagram

392‧‧‧ difference in calculation

394‧‧‧HMO deviation

400‧‧‧ computing system

411‧‧‧Central Processing Unit

412‧‧‧System Bus

414‧‧‧ random access memory

416‧‧‧Read-only memory

418‧‧‧Input/Output (I/O) Adapter

421‧‧‧ disc unit

422‧‧‧User Interface Adapter

424‧‧‧ keyboard

426‧‧‧ Mouse

428‧‧‧Speaker

432‧‧‧ microphone

434‧‧‧Communication adapter

436‧‧‧Display adapter

438‧‧‧ display device

439‧‧‧Printer

440‧‧‧ tape drive

The features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments. The features of the drawings are not to scale unless the description of the disclosure In the drawings: Figure 1 shows an example of the top-loss phenomenon of the photoresist material and the pattern transfer failure that results in the transmission of the etch; Figure 2 shows the resulting wafer image, which shows the results of the electron beam inspection (EBI) tool. Multiple post RIE etch process failures (under a specific set of focus and dose process conditions) are exhibited on multiple mask exposures of the wafer; Figure 3A shows the convention for positioning anchors for a given dose and mask, The lithography process window optical proximity correction (PWOPC) process is used to optimize the mask size to amplify the lithography PW, but does not need to know or perceive any potential HMO etch bias problems; Figure 3B shows the use of Figure 3A. Optimize the resistive feature printing of the key feature size of the photoresist mask designed by the lithography PWOPC process window; Figure 3C shows the dose and mask positioning anchor and lithography process window OPC (PWOPC) given in Figure 3A ) HMO / etching generated by the process Processing window; FIG. 3D shows resistive feature printing using the optimized feature size of the photoresist mask designed for the HMO/etch process window generated according to the optimized PWOPC process window of FIG. 3A and FIG. 3C; 3E illustrates a conceptual superposition of the designed lithography process window (PWOPC) and conditions of FIG. 3A and the CD features produced by, for example, printing in an exemplary PWOPC lithography window, independent of the HMO/etch process; A conceptual superposition of the designed lithography process window (PWOPC) and conditions and the CD features produced by the printing under the conditions of an exemplary PWOPC lithography window after the HMO/etch process, for example, is shown; The figure shows the convention for a given dose and mask positioning anchor, where the HMO (hard mask opening) / etch process window HMOPWOPC process is used to optimize the mask size to amplify the HMO PW, however, without knowing or perceiving Any potential lithography processing problem; Figure 4B shows the use of resistive features for the generation of key feature sizes for photoresist masks designed according to the optimized HMO PWOPC process for optimal use according to Figure 4A Jiahua PWOPC The resist feature printing of the key feature size of the photoresist mask designed in the process window; Figure 4C shows the lithography produced by the dose and mask positioning anchor and the HMO OPC process window (PWOPC) process given in Figure 4A. Processing window, for example, is used to optimize the HMO etch processing window for printed metal lines; Figure 4D shows the use of optimized HMO according to Figure 4A The resist feature printing of the key feature size of the photoresist mask designed by the PWOPC process window; Figure 5 illustrates, in one embodiment, by displacing the mask size in the lithography/etching process. A method for optimizing both lithography and etching (HMO) in the OPC correction process. Figure 6 shows the flow of the method for co-optimizing both lithography and etching (HMO) in OPC; Figure 7 shows the HMO etch correction resulting from the optimized loop processing of Figure 6. Wafer production; Figure 8A shows an exemplary relationship between HMO etch bias (Y-axis) and developed resist critical dimension (X-axis); Figure 8B shows an exemplary relationship between HMO etch bias (Y-axis) and pitch Figure 8C shows an exemplary relationship between the HMO etch bias (Y-axis) and the duty cycle; Figure 9 shows an exemplary relationship between the HMO deviation etch and the resist slope of each physical wafer position; The figure shows a method for performing a total optimization of the mask size using both lithography and HMO models for a given specified lithography and HMO critical dimensions on a computer system; Figure 11 shows a particular embodiment , an exemplary table specifying how to modify the mask size or design when the resulting simulated output PW lithography/HMO profile is not within its target specification; and FIG. 12 depicts An exemplary hardware configuration of the method as described in Figures 6 and 10.

The disclosure will now be described in more detail with reference to the following description and drawings accompanying this application. The drawings of the present application are provided for illustrative purposes and are described in greater detail below.

Figure 3A shows a convention for positioning anchors for a given dose and mask, in which a photolithography ("lithography") process window OPC (PWOPC) process 50 is used to optimize the mask size to magnify the lithography PW, But you don't need to know or be aware of any potential problems in the HMO process. Here, dashed line 53 represents, for example, the lithography CD variation of the focus and dose through a given metal space target. As shown in Figure 3A, one goal is to ensure that the largest lithography process window for critical dimension features can be printed, for example, without worrying about what is happening in the HMO (hard mask opening) process window. In one embodiment, processing conditions near the centerline 56 of the process window range 50 result in more accurate features that meet the CD requirements.

Figure 3B shows resist feature printing 60 using the resulting feature size of the photoresist mask designed in accordance with the optimized lithography PWOPC process window 50 of Figure 3A. As shown, in the illustrated embodiment, process variations in the PWOPC process window 50 result in a printed lithography feature 60 that includes highly accurate printed with maximized lithography CD printability as shown. And spaced apart features 63.

FIG. 3E illustrates a conceptual overlay 70 of the designed lithography process window (PWOPC) 50 and condition 53 of FIG. 3A and the resulting CD feature 60 printed in, for example, the exemplary PWOPC lithography window 50, with HMO/ The etching process is irrelevant.

Figure 3C shows an HMO/etch processing window 55 produced for a given dose and mask positioning anchor and lithography process window OPC (PWOPC) process 50 of Figure 3A, for example, for optimizing printed metal lines The lithography processing window. Here, an attempt to magnify the lithography PW results in a non-optimized HMO etch window condition. That is, dashed line 57 represents the HMO etched CD variation across a given target of the process window condition during which a lithography process is performed to obtain a printed mask of the key feature lithography process window. However, because driven by the lithography PWOPC process 50, the target is printed on the largest lithography PW, but the same target 58 is not patterned at the center of its HMO process window. In fact, it is pushed to or near the edge of the HMO process window 55 of Figure 3C, resulting in a very small chance of this pattern remaining in the HMO step.

Figure 3D shows the resist feature print 65 produced using the key feature sizes of the mask designed in accordance with the optimized PWOPC process window 50 of Figure 3A, and the feature print 65 to cause key feature sizes in the HMO step. The HMO/etch process window 55 produced by Figure 3C. However, as shown in this embodiment of FIG. 3D, the process variation in the PMOOPC process window 55 for HMO/etching combines the printed and etched features at 64 with (especially) line features. The hard failure fault printing at 66 results in a tighter boundary, but the printed lithography feature 63 is more accurate, near the edge of the process window under the processing conditions of line 58 near the process window range 55 of Figure 3C. The CD features shown are the largest. Here, the RIE etching process is already under the condition corresponding to the line 58, Pushed to the position just outside its ideal processing window.

FIG. 3F is a diagram showing the CD features 63 of the designed HMO process window (PWOPC) 55 and condition 57 of FIG. 3C and the conditions of the exemplary PWOPC HMO window 55 after performing the HMO/etch process, for example. The conceptual superposition of 64, 66 is 75.

Figure 4A shows a convention for positioning anchors for a given dose and mask, where the HMO (hard mask opening) / etch process window HMO PWOPC process 80 is used to optimize the mask size to magnify the HMO PW, however, Know or detect any potential lithography issues. Here, dashed line 83 represents the HMO CD variation across the process window, where, for example, various levels of mask key feature sizes will be printed for the metal space. As shown in Figure 4A, one goal is to ensure that critical dimension features (hard mask openings) can be etched in the maximum process window. In one embodiment, processing conditions near the centerline 86 of the process window range 80 result in more accurate etched features that meet the CD requirements.

Figure 4B shows a resist feature print 90 using the generation of key feature sizes of the photoresist mask designed according to the optimized HMO PWOPC process 80 for optimizing the use of the optimized PWOPC process window according to Figure 4A. The resist feature print 90 produced by the key feature size of the 80-designed photoresist mask. As shown, in the illustrated embodiment, process variations in the PWOPC process window 80 result in lithographically printed and etched features 90, including highly accurate having the maximized CD process window shown. Print feature 93.

Figure 4C shows the dose and mask positioning given in Figure 4A The lithography processing window 85 produced by the anchor and HMO OPC Process Window (PWOPC) process 80, for example, is an HMO etch process window for optimizing the printed metal space. Here, when attempting to optimize the HMO etch window conditions alone, it leads to a non-optimized lithography PW. That is, dashed line 87 represents the lithographic CD variation produced by a given target across the process window condition during which an HMO etch process is performed to obtain a printed mask of the key feature HMO CD process window. However, because of the HMO PWOPC process 80 drive, the target 88 is patterned at the maximum HMO PW, but the same target is not printed at the center of its lithography process window. In fact, it is pushed to or near the edge of the lithography process window 85 of Figure 4C, causing the pattern to not be printed in the lithography step.

Figure 4D shows the resist feature print 95 produced using the key feature sizes of the photoresist mask designed in accordance with the optimized HMO PWOPC process window 80 of Figure 4A, and to cause key feature sizes in the post-lithography The lithography process window 85 is produced by the fourth feature of the resist feature printing 95. However, as shown in this embodiment of FIG. 4D, the process variation in the HMO PWOPC process window 85 for lithography causes a hard failure failure at 96 where the line features are pinched, but the printed micro The shadow feature 93 is more accurate, with the CD feature shown near the edge of the process window being the largest under the processing conditions of line 88 near the process window range 85 of Figure 4C. Here, the RIE etch process is already centered in the process window; however, the lithography process has been pushed to the position just outside the ideal lithography processing window under conditions corresponding to line 88.

Figure 5 conceptually illustrates a mode by which the size of the mask is driven Between the lithography and etching processes, a method for optimizing both lithography and etching (HMO) in the OPC correction process. In Figure 5, the OPC process flow simulation 100 achieves a common process window (PW) 110 optimized between lithography and etching. In the method 100 of FIG. 5, the analog processing for achieving the etch/HMO PWOPC process window 80 corresponding to the optimization of the PW optimized for the HMO PWOPC condition as set forth in FIG. 4A is the same. The processing optimization optimization loop is combined with the analog processing for achieving the optimized HMO PWOPC lithography process window 85 corresponding to the HMO PWOPC condition for optimizing the PW as proposed in FIG. 4C. A lithography/HMO co-optimization is provided to produce a co-optimized lithography/HMO common window 110. As shown, the co-optimized lithography/HMO common window 110 provides a centered range of lithographic critical dimension CD variations 56 after optimization including post HMO etched CD variations 86. Here, the mask size is driven to the best position for lithography and HMO/etch two processes. These simulations can be performed on a full wafer.

Figure 6 illustrates a flow 200 for co-optimizing both lithography and etching (e.g., hard mask openings or HMOs) in an OPC. Although the methods herein are described in relation to a hard mask opening etch process, it should be understood that the methods herein are applicable to any type of material being etched, such as nitride etch, oxide etch processes, and the like. In a first design step 204, a circuit design is generated using techniques known in the art. The design can be divided into sub-design areas or chiplet designs, for example, to avoid processing the entire reticle field at once. This process continues at 210 for the next dummy fill, which is a topographic fill, This adds shape to provide a uniform pattern layout or to avoid topography issues. This dummy fill step can be implemented on a localized basis for each wafer (ie, a sub-wafer followed by a sub-wafer) or for a full wafer. For example, these designs that take into account the topographical correction are further processed in a typical retargeting step 210 based on localization (ie, sub-wafer followed by sub-wafer) or full wafer. Subsequent steps perform a lithography/HMO co-optimization technique 300 to obtain an optimized process window for both lithography and HMO etch. Here, at 302, the model-based secondary analysis auxiliary feature step is first performed according to the known technique of optimizing the PWOPC lithography of the 305, and the output contour 56 shown in FIG. 5 is generated. Yes, in conjunction with the optimized PWHMO etch 310 to produce the output profile 86 shown in FIG. The output 250 is the optimal feature size computed for the mask based on the processing loop 300 and is subject to a further optical rule checking procedure 275. In the processing loop 300, two optimization processes of lithography PWOPC and HMO PWOPC are performed in each iteration, that is, in the simultaneous manner, by driving the outline of the mask design (for example, mask size) to be immersed in the lithography/ Between the two processes of etching, the lithography and etching (HMO) in the OPC correction process is optimized. For example, when the OPC code is generated in the loop 300, the lithography PWOPC model and the HMO PWOPC model data are input, and the MBSRAF data can also be selected, so that the calculations in the same processing loop 300 can be used to adjust the two models to set whether the indication is It is desirable to increase or decrease the specifications of the lithography CD as determined; and use the same processing loop 300 calculations to determine if it is necessary to increase or decrease the HMO etched CD specifications as determined. Next, use the combination of the two-process CD simulation to guide the mask size change, so that it will At the end of the optimization, the two specifications of the lithography CD and HMO CD are met.

Thus, in method 200, mask correction for simultaneous analysis and co-optimization of two independent process models is achieved. The lithography PWOPC and HMO PWOPC two-process models are executed simultaneously in each iteration (in the same loop), resulting in a mask solution that avoids independent failure of each model. This optimized mask size will drive the process to stay in the path of the independent process in the optimized specification. For example, in one embodiment, through lithography and HMO simulation modeling, the processing steps include: determining a first specification of a minimum lithography CD that ensures lithographic CD features are successful; and, similarly, determining to ensure etching of the CD The second specification of the minimum HMO etched CD with feature success. These first and second specifications are input to the loop processing 300 and are used to determine the mask size to try to meet the limits of each specification. Depending on whether the two specifications are met, the weighting between the two HMOs (Process Window RIE) and the lithography CD process causes the mask size to be changed in order to accelerate convergence to obtain the first and second specifications. Mask size solution.

Accordingly, process 200 of FIG. 6, FIG. 7, and optimized loop process 300 demonstrate the production of wafer 375 with HMO etch correction. Compared to the prior art mask and wafer processing of FIG. 2, the wafer 350 produced according to the optimized architecture 200 of FIG. 2 does not actually exhibit a resist top loss.

Therefore, it is a mask correction method that can simultaneously analyze and jointly optimize two independent process models. The two-process model is executed simultaneously in each iteration, resulting in a masking solution that avoids the independent failure of each model. (ie, the case where mask optimization is performed individually or sequentially.) This optimization The size of the mask will drive the process to stay in the path of the independent process in the optimized specification.

In further embodiments, the systems and methods herein use optical images as a proxy for 3D resist profiles and methods for creating efficient and accurate models of etched patterns using such images. Just as this optical image can be used as an input to accurately predict the edge exposure of the photoresist and the development model in the photoresist, an optical image is used as an etch process model that will accurately predict the edge placement of the etched pattern. Input. In establishing an efficient and accurate model of the etched pattern: 1) only the optics and etch models that result in faster processing are used; and 2) the final etched edge simulation is more accurate due to the approximate 3D resist effect.

Thus, in one embodiment, a more accurate etch model form for the PWHMO process 330 of FIG. 6 is provided which takes 3D resist information as an image. The optical imaging conditions were combined with the "resistance" model conditions as a proxy for the 3D resist profile. The process 330 of Figure 6 requires a calibration experience model for etching the data, including: modeling the etched CD, non-etching bias, to result in an easier measurement method with cleaner data.

Here, in view of Figs. 8A to 8C, an embodiment of various relationship diagrams relating to HMO deviation, that is, a relationship between a change from post-development to post-etching and various parameters related to the density of a partially printed pattern, is plotted. In each of Figures 8A through 8C, the HMO deviation is calculated as the measured dimensions of the photoresist are changed to hard mask measurements (caused by the etching process). For example, Figure 8A shows HMO etch bias (Y-axis) versus developed resist An exemplary relationship diagram 377 of the critical dimension (X-axis) (ie, the resist feature size), and FIG. 8B shows an exemplary relationship of the HMO etch bias (Y-axis) and the pitch (ie, the periodicity of the characteristic photoresist CD pattern). 380, and 8C show an exemplary relationship 383 of the HMO etch bias (Y-axis) versus the duty cycle of the patterned features. These graphs 377, 380, and 383 each exhibit significant system variations that are not captured by the pattern density conditions. That is to say, the pattern density is not properly taken out of the HMO etching deviation, that is, the correlation between the post-developing characteristic measurement and the local printed pattern density of the operation is not strong.

In a specific embodiment, as described herein with respect to FIG. 10, a method is implemented that includes obtaining and using an optical image as a proxy for a 3D resist profile, and implementing the method in processing loop 300 To use optical image parameters to create an efficient and accurate model of the etched pattern. That is, by obtaining an optical image and using this image as an input to the model of the etch process, the predicted edge placement of the etched pattern will be accurate. The advantages of this method are: 1) fast using only optics and etching models; and 2) final etch simulations are more accurate due to the approximate 3D resist effect.

Here, an efficient resistive shape-aware etching model form and a calibration method that takes into account differences in the etched pattern due to variations in the three-dimensional resist shape are provided. Thus, for example, the model form includes conditions directly related to the optical image; and the calibration method relies on the CD measurement of the etched image. Furthermore, the calibration method includes an empirical fit of the CD measurement results to the model form conditions.

In a specific embodiment, the model form includes optics Two conditions with density.

FIG. 9 shows an exemplary relationship diagram 390 showing the dependence of the HMO deviation etch 392 and the resist slope for each physical wafer location. In one embodiment, the resist slope is the difference between the top and bottom CD SEM measurements, that is, measured as the contact angle formed between the resist and the substrate. In Figure 9, it is seen that there is a better correlation between HMO bias and resist slope. For example, the various positions of the resist pattern formed and developed on the wafer are shown, and a plot of the difference 392 (difference in resist slope) calculated in nanometers from the HMO deviation 394 is plotted.

Accordingly, there is provided an efficient model for simulating an etched pattern, which includes both optical and density conditions; and a calibration method shown in FIG. 10 that takes into account differences in the etched pattern due to variations in the three-dimensional resistive profile. In a specific embodiment: the model form includes conditions directly related to the optical image; and the calibration method relies on CD measurements of the etched image. In addition, the calibration method includes an empirical fit of the CD measurements to the model form conditions. The etch model then uses optical information to guide the etch CD prediction.

Figure 10 shows an OPC masking method 325 for performing an optimized mask design using optical model parameters based on printed feature image simulation on a computer system. Using optical model parameters (eg, intensity distribution) is provided in the full wafer design space for placing lithography and RIE processes in the center of each process window (ie, lithography and HMO (eg, RIE) etch critical dimensions (CD) Common "knobs" within specifications.

As the method is shown at 327, the first step includes lithography Resistor coating and HMO (Reactive Ion Etching) two-stage process control range limits input to the computer system. These range limitations include photolithographic models and target mask size errors, (optical) focus errors, and (light) dose errors used in HMO (etching) processes. For light lithography models and HMO (etching) model processes, these values do not have to be the same.

In the method, at 329, the next step includes inputting a critical dimension (CD) for the feature(s) of the lithography model process to the computer system, and at 330, for the HMO (eg, reactive ion) Etching) The critical dimension (CD) of a particular feature(s) of the model process is input to the computer system.

At 331, the initial mask design specification is entered into the system.

Still further, at 332, the input to the computing system includes a secondary analytical auxiliary feature CD specification for the associated initial mask design.

In a preferred embodiment, the HMO (etched) model is based on optical simulation. That is to say, in the method, there are an analog lithography process (typically an optical process) and an analog etch process. At 335, the method uses an optical model to simulate an optical image from the simulated printing process (exposure and development of features on the wafer) that will be created by the initial mask. The result of the optical image simulation is the optical image parameters used in both the lithography (resistance model) and the HMO etch. In a specific embodiment, the optical image parameters include an intensity distribution of the generated optical image. Next, at 340, a lithography (resist coating) model is built based on optical image parameters, wherein the model performs a characteristic analysis of the photoresist response mode. However, now at 343, the HMO etch model is applied to the production site. Optical image parameters of the simulated image. That is, the HMO etch model is also built using the simulated optical image. Since the HMO etch model is built based on the simulated optical model, the solid model of light is represented by the mask and the exposure system. Thus, in a preferred embodiment, both the lithography process and the etch simulation process are co-optimized between the lithography in the loop 300 of FIG. 6 and the HMO etch using the same optical model. That is, the optical model parameters obtained from the optical simulation are common components between the lithography model and the HMO etch model.

Next, at 346, the method outputs the generated PW lithography/HMO profiles 56, 86 based on the PW lithography/etching simulation.

Next, at 350, the total optimization processing loop determines whether the PW lithography/HMO contour generated by the output is in the center position of the lithography and etching process window. That is, it is determined whether the mask design (eg, the mask segment or segment) is optimized in the analog processing loop 300 (FIG. 6) to conform to the CD specifications, that is, the corresponding in FIG. The contours 56, 86 are in the optimized process window.

In the correction algorithm 300, the calculated optical parameters are used simultaneously for co-optimization of both lithography and etching to improve the efficiency of optimization, thus producing an optimal mask design within the process window limits.

If it is determined in step 350 that the resulting PW lithography/HMO profile is in the center of the lithography and etching process window (ie, in accordance with its target specification), the mask design is ended (eg, mask segmentation) ) processing. Otherwise, at 350, if it is determined that the output PW lithography/HMO contour is not in the center position of the lithography and etching process window (ie, no In accordance with its target specification, then at step 335, the mask design (eg, size) is changed, and the process returns to step 335 to perform the optical model simulation again based on the mask design or the change in the mask segment.

Thus, the method repeats between steps 335 and 353 until an optimized mask design is determined.

11 shows that in one embodiment, the illustrative table 360 specifies how to modify the mask when the PW lithography/HMO profile produced by the output in the lithography and etch two process windows is not within the target specification (step 350). Fragment or segment) size or design.

As shown in FIG. 11, the table 360 includes a series of lines for judging, the first line 362 shows that the simulated lithography line CD is inside or outside the target specification; the second line 364 shows that the simulated lithography space CD feature is Within or outside the target specification; a third row 366 depicts the simulated HMO etched line CD being within or outside the target specification; and a fourth row 368 indicating that the simulated lithographic space CD feature is within or outside the target specification. In a specific embodiment, the fifth row 370 shows how to modify the mask design (or mask design segment) based on a comparison of lithography lines, lithography spaces, HMO lines, and HMO spatial features with their respective target specifications. Table rows 362 through 370 are used to inform how to modify the mask design based on any combination of key features outside of the specification as indicated by the decision in the co-optimization simulation.

For example, if the lithography line, lithography space, HMO line, and HMO space CD features are each within the target specification, then no moving mask is needed. However, looking closely at Table 360, any permutation of out-of-spec errors will motivate the modification of the mask design. In the table, the movement of the mask design can involve One or more of the following parameters: LLE is the lithographic line error, which represents the difference between the analog line CD of the mask or mask segment and its target specification; LSE is the lithographic space error, which represents the simulated CD and phase The difference distance between adjacent features compared to the target specification; HLE is the HMO line error, which represents the difference between the simulated line CD of the mask or mask segment and its target specification; HSE is the HMO etching space error, which represents The difference distance between the simulated CD and the adjacent features compared to the target specification; FB is the feedback factor, which can be combined for OPC recipe optimization in a manner that will be known to those of ordinary skill in the art. Adjustment parameter; LithoW is an adjustment or "weighting" factor that will be applied in the next OPC mask design iteration based on the determined lithography parameter error; and similarly, HMOW is based on the determined HMO etch process parameter error The adjustment or "weighting" factor that will be applied in the next OPC mask design iteration. Thus, based on any particular combination of the simulated errors in processing loop 300 (Fig. 6) and method 325 (Fig. 10), the mask/fragment design can be modified by table 360 of Fig. 11, for example, in the positive direction, The negative direction, and according to the size determined as in table 360, moves.

Figure 12 illustrates a specific embodiment of an exemplary hardware configuration of computer system 400 programmed to perform method steps for simultaneously performing two simulation (lithography and etching) process models in each iteration. A mask solution that avoids independent failure of each process model, such as those described in Figures 5, 6 and 10 herein. The computing system 400 is further programmed to perform a method step of forming an etch bias model that uses a resist form (ie, a resist angle) that is associated with a pattern etch bias value. Optical image, such as those described herein in relation to Figures 8A, 8B, 8C, and 9.

The hardware configuration preferably has at least one processor or central processing unit (CPU) 411. The CPU 411 is interconnected via a system bus 412 to a random access memory (RAM) 414, a read only memory (ROM) 416, and an input/output (I/O) adapter 418 (for use in a disk unit). Peripheral devices such as 421 and tape drive 440 are coupled to bus bar 412), user interface adapter 422 (for connecting keyboard 424, mouse 426, speaker 428, microphone 432, and/or other user interface devices to the confluence) Row 412), communication adapter 434 for connecting system 400 to a data processing network, internet, internal network, local area network (LAN), etc., and for connecting bus bar 412 to display device 438 And/or display adapter 436 of printer 439 (eg, such a digital printer).

The invention can be a system, method, and/or computer program product. The computer program product can include a computer readable storage medium(s) having computer readable program instructions for causing the processor to carry out the aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. Computer-readable storage media A non-exhaustive list of specific embodiments includes the following: portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable Programmable read-only Recall (EPROM or flash memory), static random access memory (SRAM), portable CD-ROM (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, groove A mechanical encoding device such as a punch-card or embossed structure having instructions recorded thereon, as well as any suitable combination of the foregoing. When used in a computer-readable storage medium, it is not intended to be interpreted as a temporary signal that is itself a radio wave or other free-propagating electromagnetic wave, or an electromagnetic wave that propagates through a waveguide or other transmission medium (eg, a light pulse through a fiber optic cable). Or an electrical signal transmitted through a wire.

The computer readable program instructions described herein can be downloaded from a computer readable storage medium to a respective computing/processing device or downloaded to a network such as the Internet, a local area network, a wide area network, and/or a wireless network. External computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for computer readable storage media in the respective computing/processing device Storage in the middle.

The computer readable program instructions for performing the operations of the present invention may be an interpreter command, an instruction set architecture (ISA) instruction, a machine instruction, a machine dependent instruction, a microcode, a firmware instruction, a status setting material, or a write Or source code or object code of any combination of a plurality of programming languages, such as object oriented programming languages such as Smalltalk, C++ or the like, and procedural programming languages such as "C" programming languages or similar programming languages. Computer readable program instructions are completely available on the user's computer Execution, partial execution on the user's computer (eg, stand-alone software package), partial on the user's computer and partly on the remote computer, or entirely on the remote computer or server. In the latter case, the remote computer can connect to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can connect to an external computer (for example, using Internet services). Suppliers through the Internet). In some embodiments, for the purposes of the present invention, an electronic circuit system includes, by way of example, a programmable logic circuit system, a field programmable gate array (FPGA), or a programmable logic array (PLA), The computer readable program instructions can be executed by the state information of the computer readable program instructions to personalize the electronic circuit system.

The present invention is described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present invention. It will be understood that the block diagrams and/or blocks of the block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams can be implemented by computer readable program instructions. The computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing device to produce a machine such that instructions executed by a processor of a computer or other programmable data processing device are used to create The functions/acts specified in the flowchart and/or block diagram one or more blocks are implemented. The computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing device, and/or other device to function in a particular manner such that the computer readable storage medium having stored instructions thereon Including an article containing instructions, such instructions implementing a flow chart and/or block diagram one or more blocks The function/action specified in .

Computer readable program instructions can also be loaded into a computer, other programmable data processing device, or other device to enable a series of operational steps to be performed on a computer, other programmable device, or other device to produce a computer-implemented program that causes the computer, other The instructions executed on the programmable device, or other device, implement the flowcharts and/or functions/acts specified in one or more of the blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of a system, method, and computer program product in accordance with various embodiments of the present invention. In this regard, the blocks of the flowcharts or block diagrams can represent a module, a segment, or a portion of an instruction comprising one or more executable instructions for implementing the (or) specified logical function. In some alternative implementations, the functions noted in the blocks may not function in the order shown. For example, two blocks shown in succession may in fact be executed substantially in parallel, or such blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that blocks of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations can be implemented by a special purpose hardware-based system that specifies A function or action, or a combination of special-purpose hardware and computer instructions.

The description of the specific embodiments of the invention has been described for purposes of illustration Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terminology used herein is for the purpose of best explanation of the embodiments. The practical application or technical improvements made to the technology appearing in the market, or those of ordinary skill in the art can understand the specific embodiments disclosed herein.

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Claims (21)

A method of modifying a reticle design, comprising: performing a first lithography process model simulation on a computer system, resulting in a line or space feature of the mask being generated in the first process window; performing a second etch process on the computer system Model simulation, resulting in generating a line or space feature of the mask in the second process window; determining whether performing line features or spatial features caused by each of the first process model simulation and the second process model simulation conform to individual line feature specifications And spatial feature specifications; and modifying the mask design in a single iteration of the repeated loop program such that the simulated line features or spatial features of the simulation are within each of the smallest critical dimension (CD) specifications; A common process window (PW) optimized between lithography and etching, wherein the lithography and etching processes are simultaneously optimized during the rewind process. The method of claim 1, wherein the first and second process models are performed simultaneously in each iteration, resulting in an optimized mask size solution that avoids independent failure of the models. The method of claim 1, further comprising: designating a minimum lithographic critical dimension (CD) to ensure successful lithographic CD feature printing; designating a minimum etched CD that ensures successful etched CD feature printing, and simulating each single The first lithography process model in the reverse loop and the second etch process model are used to determine that each has the most A mask design with a small lithography CD and a minimum etched CD specification. The method of claim 3, further comprising: applying a weight between the first lithography CD process window and the second etch process window to accelerate convergence, resulting in having the minimum lithography CD and minimum etching simultaneously Optimized mask size solution for features of the CD specification. The method of claim 3, wherein the common process window (PW) of the co-optimized lithography process and the etch process is optimized for use in lithographic critical dimension CDs including post-etching CDs. Centered range. The method of claim 3, further comprising: when the OPC code is generated in the repeated processing loop, using the calculation in the same processing loop to adjust both the lithography process model and the etching process model. The value of the minimum lithography CD specification and the value of the minimum etched CD specification are set. The method of claim 6, wherein the adjusting comprises: indicating whether the mask segment of the mask design needs to be modified in a positive or negative direction; and using the calculation in the single iteration, based on causing the minimum The mask segment setting movement is set by simulating the lithography or etched CD feature within the lithography CD specification or the minimum etched CD specification. The method of claim 1, further comprising: performing an optical imaging model to generate an optical parameter based on the mask design; and in the single iteration, The optical image parameters in each of the first lithography process model simulations are used and the optical image parameters in the second etch process model simulation are used as a proxy for the 3D resist profile. A system for modifying a reticle design, comprising: a memory storage device; a hardware processor connected to the memory storage device, configured to perform: performing a first lithography process model simulation, resulting in a first process window Generating a line or space feature of the mask; performing a second etching process model simulation, resulting in generating a line or space feature of the mask in the second process window; determining to perform each of the first process model simulation and the second process model simulation Whether the resulting line feature or spatial feature conforms to the individual line specification and spatial feature specification; and the modification of the mask or mask segment design in a single iteration of the repeated loop program, such that the simulated line feature or the simulated space Characterizing within each of the respective minimum critical dimension (CD) specifications; and resulting in a common process window (PW) optimized between lithography and etching, wherein the lithography and etching processes are tied to the repeating loop The process is optimized at the same time. The system of claim 9, wherein the first and second process models are performed simultaneously in each iteration, resulting in an optimized mask size solution that avoids independent failure of the models. The system of claim 9, wherein the hardware processor Further configured to: specify the minimum lithographic critical dimension (CD) to ensure successful lithographic CD feature printing; specify the minimum etched CD to ensure successful etched CD feature printing, and simulate the same in each single repeat loop A lithography process model and the second etch process model are used to determine a mask design having features that conform to each of the respective minimum lithography CD and minimum etched CD specifications. The system of claim 11, wherein the hardware processor is further configured to apply a weight between the first lithography CD process window and the second etch process window to accelerate convergence, resulting in simultaneous compliance Optimized mask size solutions for these minimum lithography CDs with minimal etched CD specifications. The system of claim 11, wherein the common process window (PW) of the co-optimized lithography process and the etch process is optimized for use in lithographic critical dimension CDs including post-etching CDs. Centered range. The system of claim 11, wherein the hardware processor is further configured to: generate an OPC code in the repeated processing loop, and adjust the first using a calculation in the same processing loop Both the lithography process model and the second etch process model set a value of the minimum lithography CD specification and a value of the minimum etched CD specification. For example, the system described in claim 14 of the patent scope, in which The hardware processor is further configured to: indicate whether the mask segment of the mask design needs to be modified in a positive or negative direction; and use the calculation in the single iteration based on causing the minimum lithography CD specification or The simulation of the lithographic or etched CD features within the minimum etched CD specification sets the mask segment design movement. The system of claim 9, wherein the hardware processor is further configured to: perform an optical imaging model to generate optical parameters based on the mask design; and in the single iteration, use each of the The optical image parameters in a lithography process model simulation and the use of the optical image parameters in the second etch process model simulation as a proxy for the 3D resist profile. A method for simulating an etch process, comprising: evaluating an optical imaging model to generate optical parameters based on a mask design; inputting the optical parameters in an etch process model, and using the etch process model to simulate an etch process, wherein It is an efficient and accurate simulation of the etched pattern. A calibration method for an etch process model, comprising: obtaining an etch process model form that takes into account a difference in an etched pattern due to variations in a three-dimensional photoresist profile, the model form including optical parameters directly related to the optical image and having one or Multiple calibration coefficients; one or more etched patterns to obtain one or more CD measurement junctions And fitting the one or more of the calibration coefficients in the form of the etch process model to one or more CD measurements. The calibration method of claim 18, wherein the optical parameters include optical intensity, image density, slope of the intensity, and measurement of minimum or maximum intensity. A system for simulating an etching process, comprising: a memory storage device; a hardware processor coupled to the memory storage device, configured to: evaluate an optical imaging model to generate optical parameters based on a mask design; The optical parameters are entered in an etch process model and the etch process model is used to simulate the etch process. A system for calibrating an etching process, comprising: a memory storage device; a hardware processor connected to the memory storage device, configured to: obtain an etched pattern due to variation of a three-dimensional photoresist shape a different form of etching process model comprising optical parameters directly related to the optical image and having one or more calibration coefficients; obtaining one or more CD measurements of one or more etched patterns, and The one or more of the calibration coefficients in the form of the etch process model are fitted to one or more CD measurements.