TW201801255A - Package carrier and manufacturing method of package carrier - Google Patents

Package carrier and manufacturing method of package carrier Download PDF

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Publication number
TW201801255A
TW201801255A TW105120846A TW105120846A TW201801255A TW 201801255 A TW201801255 A TW 201801255A TW 105120846 A TW105120846 A TW 105120846A TW 105120846 A TW105120846 A TW 105120846A TW 201801255 A TW201801255 A TW 201801255A
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Taiwan
Prior art keywords
build
flexible substrate
package carrier
opening
block
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TW105120846A
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Chinese (zh)
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TWI595607B (en
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林永清
劉珍君
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欣興電子股份有限公司
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Priority to TW105120846A priority Critical patent/TWI595607B/en
Priority to US15/259,011 priority patent/US10103104B2/en
Application granted granted Critical
Publication of TWI595607B publication Critical patent/TWI595607B/en
Publication of TW201801255A publication Critical patent/TW201801255A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Abstract

A package carrier including a flexible substrate, a first build-up structure and a second build-up structure is provided. The flexible substrate has a first surface and a second surface opposite to each other, and has a first opening connected between the first surface and the second surface. The first build-up structure is disposed on the first surface and covers the first opening. The second build-up structure is disposed on the second surface and has a second opening, and the first opening and the second opening are connected to each other to form a chip accommodating cavity together. In addition, a manufacturing method of the package carrier and a chip package structure having the package carrier are also provided.

Description

封裝載板及封裝載板的製造方法Package carrier board and method for manufacturing package carrier board

本發明是有關於一種封裝載板、封裝載板的製造方法及晶片封裝結構，且特別是有關於一種具有晶片容置槽的封裝載板、此封裝載板的製造方法及具有此封裝載板的晶片封裝結構。The invention relates to a packaging carrier board, a manufacturing method of the packaging carrier board and a chip packaging structure, and in particular to a packaging carrier board with a wafer accommodating groove, a manufacturing method of the packaging carrier board and a packaging carrier board having the same Chip packaging structure.

近年來，隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路元件高密度化，半導體相關產業也日漸發展。半導體積體電路(IC)產業包含積體電路製造及積體電路封裝。積體電路製造是將積體電路製作在晶圓上。積體電路封裝則可提供結構保護、電性傳遞及良好散熱給已製作有積體電路的晶片(即晶圓於切割後的一部分)。In recent years, with the demand for electronic products toward higher functionality, higher speed signal transmission, and higher density of circuit components, semiconductor-related industries have also grown. The semiconductor integrated circuit (IC) industry includes integrated circuit manufacturing and integrated circuit packaging. Integrated circuit manufacturing is to manufacture integrated circuits on a wafer. The integrated circuit package can provide structural protection, electrical transmission and good heat dissipation to the chip (that is, a part of the wafer after dicing) where the integrated circuit has been fabricated.

現行系統級封裝(System in package，SiP)及疊層封裝(Package on Package，PoP)受限於封裝面積與疊層封裝之接墊間距(pad pitch)等限制，封裝體內之晶片配置空間無法有效提升。Current system-in-package (SiP) and package-on-package (PoP) are limited by package area and pad pitch of the package-on-package, and the chip layout space in the package cannot be effective Promote.

本發明提供一種封裝載板，可增加晶片的配置空間。The invention provides a package carrier board, which can increase the arrangement space of the chip.

本發明提供一種封裝載板的製造方法，其所製造出的封裝載板可增加晶片的配置空間。The invention provides a method for manufacturing a package carrier board, the package carrier board manufactured thereby can increase the arrangement space of the wafer.

本發明提供一種晶片封裝結構，其封裝載板可增加晶片的配置空間。The present invention provides a chip packaging structure, the package carrier of which can increase the configuration space of the chip.

本發明的封裝載板包括一可撓性基板、一第一增層結構及一第二增層結構。可撓性基板具有相對的一第一表面及一第二表面，且具有連接於第一表面與第二表面之間的一第一開口。第一增層結構配置於第一表面且覆蓋第一開口。第二增層結構配置於第二表面且具有一第二開口，第一開口與第二開口相連接而共同構成一晶片容置槽。The package carrier of the present invention includes a flexible substrate, a first build-up structure and a second build-up structure. The flexible substrate has a first surface and a second surface opposite to each other, and has a first opening connected between the first surface and the second surface. The first build-up structure is disposed on the first surface and covers the first opening. The second build-up structure is disposed on the second surface and has a second opening. The first opening and the second opening are connected to form a chip accommodating groove.

在本發明的一實施例中，上述的封裝載板更包括一圖案化阻障層，其中圖案化阻障層配置於第一表面且延伸至晶片容置槽的一底面。In an embodiment of the invention, the package carrier described above further includes a patterned barrier layer, wherein the patterned barrier layer is disposed on the first surface and extends to a bottom surface of the chip receiving groove.

在本發明的一實施例中，上述的圖案化阻障層沿第一開口的內緣延伸。In an embodiment of the invention, the above-mentioned patterned barrier layer extends along the inner edge of the first opening.

在本發明的一實施例中，上述的第二開口的輪廓吻合於第一開口的輪廓。In an embodiment of the present invention, the outline of the second opening matches the outline of the first opening.

在本發明的一實施例中，上述的封裝載板更包括一圖案化導電層，其中圖案化導電層配置於第一表面且延伸至晶片容置槽的一底面。In an embodiment of the invention, the above-mentioned package carrier further includes a patterned conductive layer, wherein the patterned conductive layer is disposed on the first surface and extends to a bottom surface of the chip receiving groove.

在本發明的一實施例中，上述的封裝載板與另一封裝載板共用可撓性基板，可撓性基板在兩封裝載板之間的區段適於彎折。In an embodiment of the invention, the above-mentioned package carrier and another package carrier share a flexible substrate, and the section of the flexible substrate between the two package carriers is suitable for bending.

本發明的封裝載板的製造方法包括以下步驟。提供一可撓性基板，其中可撓性基板具有相對的一第一表面及一第二表面。形成一第一增層結構於第一表面。形成一第二增層結構於第二表面。裁切可撓性基板及第二增層結構，以使可撓性基板的一第一待移除區塊分離於可撓性基板的其他區塊，且使第二增層結構的一第二待移除區塊分離於第二增層結構的其他區塊，其中第一待移除區塊連接於第二待移除區塊。將第一待移除區塊分離於第一增層結構，以同時移除第一待移除區塊及第二待移除區塊而形成一晶片容置槽。The manufacturing method of the package carrier of the present invention includes the following steps. A flexible substrate is provided, wherein the flexible substrate has a first surface and a second surface opposite to each other. A first build-up structure is formed on the first surface. A second build-up structure is formed on the second surface. Cutting the flexible substrate and the second build-up structure, so that a first block to be removed of the flexible substrate is separated from other sections of the flexible substrate, and making a second of the second build-up structure The block to be removed is separated from other blocks of the second build-up structure, wherein the first block to be removed is connected to the second block to be removed. The first block to be removed is separated from the first build-up structure to remove the first block to be removed and the second block to be removed simultaneously to form a chip receiving groove.

在本發明的一實施例中，上述的封裝載板的製造方法更包括：在形成第一增層結構於第一表面之前，形成一圖案化阻障層於第一表面，其中圖案化阻障層延伸至第一待移除區塊。In an embodiment of the invention, the method for manufacturing a package carrier described above further includes: before forming the first build-up layer structure on the first surface, forming a patterned barrier layer on the first surface, wherein the patterned barrier The layer extends to the first block to be removed.

在本發明的一實施例中，上述的形成圖案化阻障層於第一表面的步驟包括：使圖案化阻障層沿第一待移除區塊的邊緣延伸。In an embodiment of the invention, the step of forming the patterned barrier layer on the first surface includes: extending the patterned barrier layer along the edge of the first block to be removed.

在本發明的一實施例中，上述的裁切可撓性基板及第二增層結構的步驟包括：藉由雷射製程同時裁切可撓性基板及第二增層結構。In an embodiment of the invention, the step of cutting the flexible substrate and the second build-up structure includes: simultaneously cutting the flexible substrate and the second build-up structure through a laser process.

在本發明的一實施例中，上述的封裝載板的製造方法更包括：在形成第一增層結構於第一表面之前，形成一圖案化導電層於第一表面，其中圖案化導電層延伸至第一待移除區塊。In an embodiment of the invention, the method for manufacturing a package carrier described above further includes: before forming the first build-up layer structure on the first surface, forming a patterned conductive layer on the first surface, wherein the patterned conductive layer extends To the first block to be removed.

在本發明的一實施例中，上述的封裝載板的製造方法更包括使封裝載板與另一封裝載板共用可撓性基板，其中可撓性基板在兩封裝載板之間的區段適於彎折。In an embodiment of the present invention, the above-mentioned method for manufacturing a package carrier further includes the package carrier and another package carrier sharing a flexible substrate, wherein the flexible substrate is between the two package carriers Suitable for bending.

基於上述，本發明的封裝載板藉其可撓性基板的第一開口與第二增層結構的第二開口共同構成晶片容置槽，使晶片能夠埋設於晶片容置槽內，藉以增加晶片的配置空間。此外，由於封裝載板以可撓性基板作為心層，故在製造封裝載板的過程中，可利用可撓性基板的部分區塊作為離形層來移除部分可撓性基板及部分第二增層結構，從而形成所述晶片容置槽，使封裝載板的製程較為簡便。Based on the above, the first opening of the flexible substrate and the second opening of the second build-up structure of the package carrier of the present invention together form a wafer accommodating groove, so that the chip can be buried in the wafer accommodating groove, thereby increasing the chip Configuration space. In addition, since the package carrier uses the flexible substrate as the core layer, in the process of manufacturing the package carrier, part of the flexible substrate can be used as a release layer to remove part of the flexible substrate and part of the first substrate The second build-up structure is used to form the chip accommodating groove, so that the process of packaging the carrier board is relatively simple.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

圖1A至圖1D是本發明一實施例的封裝載板的製造方法流程圖。首先，請參考圖1A，提供一可撓性基板110，可撓性基板110例如是聚亞醯胺(Polyimide，PI)軟板且具有相對的一第一表面110a及一第二表面110b。此外，更形成一圖案化阻障層112及一圖案化導電層114於可撓性基板110的第一表面110a，其中圖案化阻障層112及圖案化導電層114延伸至可撓性基板110的一第一待移除區塊R1，且圖案化阻障層112沿第一待移除區塊R1的邊緣延伸。圖案化阻障層112及圖案化導電層114例如是藉由對可撓性基板110上的一金屬層(如銅層)進行圖案化而同時被形成。1A to 1D are flowcharts of a method for manufacturing a package carrier according to an embodiment of the invention. First, referring to FIG. 1A, a flexible substrate 110 is provided. The flexible substrate 110 is, for example, a polyimide (PI) flexible board and has a first surface 110a and a second surface 110b opposite to each other. In addition, a patterned barrier layer 112 and a patterned conductive layer 114 are formed on the first surface 110a of the flexible substrate 110, wherein the patterned barrier layer 112 and the patterned conductive layer 114 extend to the flexible substrate 110 A first block R1 to be removed, and the patterned barrier layer 112 extends along the edge of the first block R1 to be removed. The patterned barrier layer 112 and the patterned conductive layer 114 are formed simultaneously by patterning a metal layer (such as a copper layer) on the flexible substrate 110, for example.

接著，請參考圖1B，形成一第一增層結構120於可撓性基板110的第一表面110a，並形成一第二增層結構130於可撓性基板110的第二表面110b。第一增層結構120例如包含介電層122、配置於介電層122的線路層124、連接線路層124的導電通孔126、配置於介電層122表面並覆蓋線路層124的防銲層128。第二增層結構130例如包含介電層132、配置於介電層132的線路層134、連接線路層134的導電通孔136、配置於介電層132表面並覆蓋線路層134的防銲層138。Next, please refer to FIG. 1B, a first build-up structure 120 is formed on the first surface 110 a of the flexible substrate 110, and a second build-up structure 130 is formed on the second surface 110 b of the flexible substrate 110. The first build-up structure 120 includes, for example, a dielectric layer 122, a circuit layer 124 disposed on the dielectric layer 122, a conductive via 126 connected to the circuit layer 124, and a solder mask layer disposed on the surface of the dielectric layer 122 and covering the circuit layer 124 128. The second build-up structure 130 includes, for example, a dielectric layer 132, a circuit layer 134 disposed on the dielectric layer 132, a conductive via 136 connecting the circuit layer 134, and a solder mask layer disposed on the surface of the dielectric layer 132 and covering the circuit layer 134 138.

請參考圖1C，裁切可撓性基板110及第二增層結構130，以使可撓性基板110的第一待移除區塊R1分離於可撓性基板110的其他區塊，且使第二增層結構130的第二待移除區塊R2分離於第二增層結構130的其他區塊，所述第一待移除區塊R1連接於所述第二待移除區塊R2。在本實施例中，例如是藉由雷射製程同時裁切可撓性基板110及第二增層結構130，其中延伸至第一待移除區塊R1的圖案化阻障層112可避免雷射非預期地裁切到第一增層結構120。Referring to FIG. 1C, the flexible substrate 110 and the second build-up structure 130 are cut to separate the first block R1 of the flexible substrate 110 from other blocks of the flexible substrate 110, and to make The second block R2 of the second build-up structure 130 is separated from other blocks of the second build-up structure 130, and the first block R1 is connected to the second block R2 . In this embodiment, for example, the flexible substrate 110 and the second build-up structure 130 are simultaneously cut by a laser process, in which the patterned barrier layer 112 extending to the first block R1 to be removed can avoid the laser The shot is cut to the first build-up structure 120 unexpectedly.

接著，將可撓性基板110的第一待移除區塊R1分離於第一增層結構120，以同時移除第一待移除區塊R1及第二待移除區塊R2而如圖1D所示形成一晶片容置槽C，從而完成封裝載板100之製作。詳細而言，在上述製程中，係藉可撓性基板110易於被剝離的特性，而使第一待移除區塊R1能夠作為離形層而順利地分離於第一增層結構120。Next, the first to-be-removed block R1 of the flexible substrate 110 is separated from the first build-up structure 120 to simultaneously remove the first to-be-removed block R1 and the second to-be-removed block R2 as shown in FIG. As shown in FIG. 1D, a chip accommodating groove C is formed, thereby completing the fabrication of the package carrier 100. In detail, in the above process, the flexible substrate 110 is easily peeled off, so that the first block R1 to be removed can be smoothly separated from the first build-up structure 120 as a release layer.

圖2是圖1D的封裝載板的俯視圖，圖1D所示剖面對應於圖2中的I-I線。為使圖式較為清楚，圖1D中的圖案化導電層114未在圖2示出。請參考圖1D及圖2，藉由上述製程所製作出的封裝載板100包括可撓性基板110、第一增層結構120及第二增層結構130。可撓性基板110具有相對的第一表面110a及第二表面110b，且具有連接於第一表面110a與第二表面110b之間的一第一開口110c，此第一開口110c係上述製程中移除第一待移除區塊R1所形成。第一增層結構120配置於可撓性基板110的第一表面110a且覆蓋第一開口110c。第二增層結構130配置於可撓性基板110的第二表面110b且具有一第二開口130a，此第二開口130a係上述製程中移除第二待移除區塊R2所形成，第二開口130a的輪廓例如吻合於第一開口110c的輪廓。可撓性基板110的第一開口110c與第二增層結構130的第二開口130a相連接而共同構成晶片容置槽C。封裝載板100更包括圖案化阻障層112及圖案化導電層114，圖案化阻障層112及圖案化導電層114配置於可撓性基板110的第一表面110a且延伸至晶片容置槽C的底面，且圖案化阻障層112沿第一開口110c的內緣延伸。FIG. 2 is a top view of the package carrier of FIG. 1D, and the cross section shown in FIG. 1D corresponds to line I-I in FIG. To make the drawing clearer, the patterned conductive layer 114 in FIG. 1D is not shown in FIG. 2. Please refer to FIGS. 1D and 2. The package carrier 100 manufactured by the above process includes a flexible substrate 110, a first build-up structure 120 and a second build-up structure 130. The flexible substrate 110 has a first surface 110a and a second surface 110b opposite to each other, and has a first opening 110c connected between the first surface 110a and the second surface 110b. The first opening 110c is a middle shift of the above process Except for the first block R1 to be removed. The first build-up structure 120 is disposed on the first surface 110a of the flexible substrate 110 and covers the first opening 110c. The second build-up structure 130 is disposed on the second surface 110b of the flexible substrate 110 and has a second opening 130a. The second opening 130a is formed by removing the second to-be-removed region R2 in the above process. The outline of the opening 130a matches, for example, the outline of the first opening 110c. The first opening 110c of the flexible substrate 110 and the second opening 130a of the second build-up structure 130 are connected to form a wafer accommodating groove C together. The package carrier 100 further includes a patterned barrier layer 112 and a patterned conductive layer 114. The patterned barrier layer 112 and the patterned conductive layer 114 are disposed on the first surface 110a of the flexible substrate 110 and extend to the chip receiving groove The bottom surface of C, and the patterned barrier layer 112 extends along the inner edge of the first opening 110c.

本實施例的封裝載板100如上述般藉其可撓性基板110的第一開口110c與第二增層結構130的第二開口130a共同構成晶片容置槽C，使晶片能夠埋設於晶片容置槽C內，藉以增加晶片的配置空間。此外，由於封裝載板100以可撓性基板110作為心層，故在製造封裝載板100的過程中，可利用可撓性基板110的部分區塊(即所述第一待移除區塊R1)作為離形層來移除部分可撓性基板110及部分第二增層結構130，從而形成所述晶片容置槽C，使封裝載板100的製程較為簡便。以下具體說明由所述封裝載板與晶片構成的晶片封裝結構。The package carrier 100 of this embodiment uses the first opening 110c of the flexible substrate 110 and the second opening 130a of the second build-up structure 130 to form a chip accommodating groove C as described above, so that the chip can be buried in the chip container Placed in the slot C to increase the space for the wafer. In addition, since the package carrier 100 uses the flexible substrate 110 as a core layer, in the process of manufacturing the package carrier 100, a portion of the flexible substrate 110 (ie, the first block to be removed) may be used R1) As a release layer, part of the flexible substrate 110 and part of the second build-up structure 130 are removed to form the chip accommodating groove C, so that the manufacturing process of the package carrier 100 is relatively simple. The following is a detailed description of a chip package structure composed of the package carrier and the chip.

圖3是本發明一實施例的晶片封裝結構的示意圖。在圖3的晶片封裝結構50中，第一封裝載板200、可撓性基板210、第一表面210a、第二表面210b、第一開口210c、圖案化阻障層212、圖案化導電層214、第一增層結構220、介電層222、線路層224、導電通孔226、防銲層228、第二增層結構230、介電層232、線路層234、導電通孔236、防銲層238、第二開口230a、晶片容置槽C’的配置與作用方式相同於圖1D的第一封裝載板100、可撓性基板110、第一表面110a、第二表面110b、第一開口110c、圖案化阻障層112、圖案化導電層114、第一增層結構120、介電層122、線路層124、導電通孔126、防銲層128、第二增層結構130、介電層132、線路層134、導電通孔136、防銲層138、第二開口130a、晶片容置槽C’的配置與作用方式，於此不再贅述。3 is a schematic diagram of a chip package structure according to an embodiment of the invention. In the chip package structure 50 of FIG. 3, the first package carrier 200, the flexible substrate 210, the first surface 210a, the second surface 210b, the first opening 210c, the patterned barrier layer 212, and the patterned conductive layer 214 , First build-up structure 220, dielectric layer 222, circuit layer 224, conductive via 226, solder mask layer 228, second build-up structure 230, dielectric layer 232, circuit layer 234, conductive via 236, solder mask The configuration and functioning of the layer 238, the second opening 230a, and the chip receiving groove C'are the same as those of the first package carrier 100, the flexible substrate 110, the first surface 110a, the second surface 110b, and the first opening of FIG. 1D 110c, patterned barrier layer 112, patterned conductive layer 114, first build-up layer structure 120, dielectric layer 122, circuit layer 124, conductive via 126, solder mask layer 128, second build-up layer structure 130, dielectric The configuration and functioning of the layer 132, the circuit layer 134, the conductive via 136, the solder mask layer 138, the second opening 130a, and the wafer accommodating groove C'will not be repeated here.

晶片封裝結構50更包括一第一晶片52、一第二封裝載板54、一第二晶片56及一封裝膠體58。第一晶片52配置於晶片容置槽C’內，第二封裝載板54具有相對的一第三表面54a及一第四表面54b，第二封裝載54板藉由第三表面54a而疊設於第二增層結構230及第一晶片52，第二晶片56則配置於第四表面54b。第二封裝載板54例如包含介電層54c、配置於介電層54c的線路層54d、連接線路層54d的導電通孔54e、配置於介電層54c表面並覆蓋線路層54d的防銲層54f。第一晶片52及第二封裝載板54例如是藉由銲球(solder ball)52a而連接於第一封裝載板200，第二晶片56可藉由銲線56a而連接於線路層54d。封裝膠體58用以覆蓋第一晶片52、第二晶片56、至少部分第一封裝載板200及至少部分第二封裝載板54。所述第一晶片52及第二晶片54可為應用處理器(application processor，AP)晶片、記憶體晶片或其他適當種類的主動、被動元件，本發明不對其種類加以限制。The chip package structure 50 further includes a first chip 52, a second package carrier 54, a second chip 56, and a encapsulant 58. The first chip 52 is disposed in the chip accommodating slot C', the second package carrier 54 has a third surface 54a and a fourth surface 54b opposite to each other, and the second package carrier 54 is stacked by the third surface 54a In the second build-up structure 230 and the first wafer 52, the second wafer 56 is disposed on the fourth surface 54b. The second package carrier 54 includes, for example, a dielectric layer 54c, a circuit layer 54d disposed on the dielectric layer 54c, a conductive via 54e connected to the circuit layer 54d, and a solder resist layer disposed on the surface of the dielectric layer 54c and covering the circuit layer 54d 54f. The first chip 52 and the second package carrier 54 are connected to the first package carrier 200 by solder balls 52a, for example, and the second chip 56 can be connected to the circuit layer 54d by bonding wires 56a. The encapsulant 58 is used to cover the first chip 52, the second chip 56, at least part of the first package carrier 200 and at least part of the second package carrier 54. The first chip 52 and the second chip 54 may be application processor (AP) chips, memory chips, or other suitable types of active and passive components, and the present invention does not limit the types.

圖4是本發明另一實施例的晶片封裝結構的示意圖。圖4的晶片封裝結構60及晶片封裝結構70及其具體結構類似圖3的晶片封裝結構50，於此不再贅述。圖4所示實施例與前述實施例的不同處在於，晶片封裝結構60及其封裝載板與晶片封裝結構70及其封裝載板共用可撓性基板310，使晶片封裝結構60與晶片封裝結構70能夠透過可撓性基板310而彼此電性連接。此外，可撓性基板310在兩晶片封裝結構60、70之間的區段適於彎折，使兩晶片封裝結構60、70能夠因應不同配置環境而配置為具有不同相對位置。在其他實施例中，可撓性基板可被更多數量的晶片封裝結構共用，本發明不對此加以限制。4 is a schematic diagram of a chip packaging structure according to another embodiment of the invention. The chip package structure 60 and the chip package structure 70 of FIG. 4 and their specific structures are similar to the chip package structure 50 of FIG. 3 and will not be repeated here. The difference between the embodiment shown in FIG. 4 and the previous embodiment is that the chip package structure 60 and its package carrier and the chip package structure 70 and its package carrier share the flexible substrate 310, so that the chip package structure 60 and the chip package structure 70 can be electrically connected to each other through the flexible substrate 310. In addition, the section of the flexible substrate 310 between the two chip packaging structures 60 and 70 is suitable for bending, so that the two chip packaging structures 60 and 70 can be configured to have different relative positions according to different configuration environments. In other embodiments, the flexible substrate can be shared by a larger number of chip packaging structures, which is not limited by the present invention.

綜上所述，本發明的封裝載板藉其可撓性基板的第一開口與第二增層結構的第二開口共同構成晶片容置槽，使晶片能夠埋設於晶片容置槽內，藉以增加晶片的配置空間。此外，由於封裝載板以可撓性基板作為心層，故在製造封裝載板的過程中，可利用可撓性基板的部分區塊作為離形層來移除部分可撓性基板及部分第二增層結構，從而形成所述晶片容置槽，使封裝載板的製程較為簡便。另外，複數晶片封裝結構可共用單一可撓性基板，所述可撓性基板在兩晶片封裝結構之間的區段適於彎折，使複數晶片封裝結構能夠因應不同配置環境而配置為具有不同相對位置，以增加晶片封裝結構在配置上的自由性。In summary, the first opening of the flexible substrate and the second opening of the second build-up structure of the package carrier of the present invention together form a wafer receiving groove, so that the chip can be buried in the wafer receiving groove, thereby Increase the configuration space of the wafer. In addition, since the package carrier uses the flexible substrate as the core layer, in the process of manufacturing the package carrier, part of the flexible substrate can be used as a release layer to remove part of the flexible substrate and part of the first substrate The second build-up structure is used to form the chip accommodating groove, so that the process of packaging the carrier board is relatively simple. In addition, the multiple chip package structure can share a single flexible substrate, and the section of the flexible substrate between the two chip package structures is suitable for bending, so that the multiple chip package structure can be configured to have different configurations according to different configuration environments Relative position to increase the freedom of configuration of the chip package structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

50、60、70‧‧‧晶片封裝結構
52‧‧‧第一晶片
52a‧‧‧銲球
54‧‧‧第二封裝載板
54a‧‧‧第三表面
54b‧‧‧第四表面
54c、122、132、222、232‧‧‧介電層
54d、124、134、224、234‧‧‧線路層
54e、126、136、226、236‧‧‧導電通孔
54f、128、138、228、238‧‧‧防銲層
56‧‧‧第二晶片
56a‧‧‧銲線
58‧‧‧封裝膠體
100‧‧‧封裝載板
110、210、310‧‧‧可撓性基板
110a、210a‧‧‧第一表面
110b、210b‧‧‧第二表面
110c、210c‧‧‧第一開口
112、212‧‧‧圖案化阻障層
114、214‧‧‧圖案化導電層
120、220‧‧‧第一增層結構
130、230‧‧‧第二增層結構
130a、230a‧‧‧第二開口
200‧‧‧第一封裝載板
C、C’‧‧‧晶片容置槽
R1‧‧‧第一待移除區塊
R2‧‧‧第二待移除區塊50, 60, 70 ‧‧‧ chip packaging structure
52‧‧‧ First chip
52a‧‧‧solder ball
54‧‧‧Second package carrier board
54a‧‧‧The third surface
54b‧‧‧Fourth surface
54c, 122, 132, 222, 232 ‧‧‧ dielectric layer
54d, 124, 134, 224, 234‧‧‧ circuit layer
54e, 126, 136, 226, 236
54f, 128, 138, 228, 238‧‧‧‧ solder mask
56‧‧‧ Second chip
56a‧‧‧bond wire
58‧‧‧Packing colloid
100‧‧‧Package carrier board
110, 210, 310 ‧‧‧ flexible substrate
110a, 210a‧‧‧First surface
110b, 210b‧‧‧Second surface
110c, 210c‧‧‧First opening
112, 212‧‧‧ Patterned barrier layer
114, 214‧‧‧ patterned conductive layer
120、220‧‧‧The first multi-layer structure
130、230‧‧‧Second build-up structure
130a, 230a‧‧‧Second opening
200‧‧‧The first package carrier board
C, C'‧‧‧Chip accommodating slot
R1‧‧‧The first block to be removed
R2‧‧‧The second block to be removed

圖1A至圖1D是本發明一實施例的封裝載板的製造方法流程圖。 圖2是圖1D的封裝載板的俯視圖。 圖3是本發明一實施例的晶片封裝結構的示意圖。 圖4是本發明另一實施例的晶片封裝結構的示意圖。1A to 1D are flowcharts of a method for manufacturing a package carrier according to an embodiment of the invention. 2 is a top view of the package carrier of FIG. 1D. 3 is a schematic diagram of a chip package structure according to an embodiment of the invention. 4 is a schematic diagram of a chip packaging structure according to another embodiment of the invention.

100‧‧‧封裝載板 100‧‧‧Package carrier board

110‧‧‧可撓性基板 110‧‧‧Flexible substrate

110a‧‧‧第一表面 110a‧‧‧First surface

110b‧‧‧第二表面 110b‧‧‧Second surface

110c‧‧‧第一開口 110c‧‧‧First opening

112‧‧‧圖案化阻障層 112‧‧‧ Patterned barrier layer

114‧‧‧圖案化導電層 114‧‧‧patterned conductive layer

120‧‧‧第一增層結構 120‧‧‧The first multi-layer structure

122、132‧‧‧介電層 122, 132‧‧‧ dielectric layer

124、134‧‧‧線路層 124, 134‧‧‧ line layer

126、136‧‧‧導電通孔 126, 136‧‧‧ conductive via

128、138‧‧‧防銲層 128, 138‧‧‧ solder mask

130‧‧‧第二增層結構 130‧‧‧The second build-up structure

130a‧‧‧第二開口 130a‧‧‧Second opening

C‧‧‧晶片容置槽 C‧‧‧chip receiving slot

Claims (12)

一種封裝載板，包括： 一可撓性基板，具有相對的一第一表面及一第二表面，且具有連接於該第一表面與該第二表面之間的一第一開口； 一第一增層結構，配置於該第一表面且覆蓋該第一開口；以及 一第二增層結構，配置於該第二表面且具有一第二開口，其中該第一開口與該第二開口相連接而共同構成一晶片容置槽。A package carrier includes: a flexible substrate having a first surface and a second surface opposite, and having a first opening connected between the first surface and the second surface; a first A build-up structure, configured on the first surface and covering the first opening; and a second build-up structure, configured on the second surface and having a second opening, wherein the first opening is connected to the second opening Together, they form a chip containing groove. 如申請專利範圍第1項所述的封裝載板，更包括一圖案化阻障層，其中該圖案化阻障層配置於該第一表面且延伸至該晶片容置槽的一底面。The package carrier as described in item 1 of the patent application scope further includes a patterned barrier layer, wherein the patterned barrier layer is disposed on the first surface and extends to a bottom surface of the chip receiving groove. 如申請專利範圍第2項所述的封裝載板，其中該圖案化阻障層沿該第一開口的內緣延伸。The package carrier as described in item 2 of the patent application scope, wherein the patterned barrier layer extends along the inner edge of the first opening. 如申請專利範圍第1項所述的封裝載板，其中該第二開口的輪廓吻合於該第一開口的輪廓。The package carrier as described in item 1 of the patent application scope, wherein the outline of the second opening matches the outline of the first opening. 如申請專利範圍第1項所述的封裝載板，更包括一圖案化導電層，其中該圖案化導電層配置於該第一表面且延伸至該晶片容置槽的一底面。The package carrier as described in item 1 of the patent application scope further includes a patterned conductive layer, wherein the patterned conductive layer is disposed on the first surface and extends to a bottom surface of the chip receiving groove. 如申請專利範圍第1項所述的封裝載板，其中該封裝載板與另一該封裝載板共用該可撓性基板，該可撓性基板在該兩封裝載板之間的區段適於彎折。The package carrier of claim 1, wherein the package carrier and the other package carrier share the flexible substrate, and the section of the flexible substrate between the two package carriers is suitable Yu bending. 一種封裝載板的製造方法，包括： 提供一可撓性基板，其中該可撓性基板具有相對的一第一表面及一第二表面； 形成一第一增層結構於該第一表面； 形成一第二增層結構於該第二表面； 裁切該可撓性基板及該第二增層結構，以使該可撓性基板的一第一待移除區塊分離於該可撓性基板的其他區塊，且使該第二增層結構的一第二待移除區塊分離於該第二增層結構的其他區塊，其中該第一待移除區塊連接於該第二待移除區塊；以及 將該第一待移除區塊分離於該第一增層結構，以同時移除該第一待移除區塊及該第二待移除區塊而形成一晶片容置槽。A method for manufacturing a package carrier includes: providing a flexible substrate, wherein the flexible substrate has a first surface and a second surface opposite to each other; forming a first build-up structure on the first surface; forming A second build-up structure on the second surface; cut the flexible substrate and the second build-up structure to separate a first block to be removed from the flexible substrate from the flexible substrate Other blocks of the second build-up structure, and separate a second block to be removed of the second build-up structure from other blocks of the second build-up structure, wherein the first block to be removed is connected to the second Removing the block; and separating the first block to be removed from the first build-up structure to simultaneously remove the first block to be removed and the second block to be removed to form a chip container Set slot. 如申請專利範圍第7項所述的封裝載板的製造方法，更包括： 在形成該第一增層結構於該第一表面之前，形成一圖案化阻障層於該第一表面，其中該圖案化阻障層延伸至該第一待移除區塊。The method for manufacturing a package carrier as described in item 7 of the patent application scope further includes: before forming the first build-up layer structure on the first surface, forming a patterned barrier layer on the first surface, wherein the The patterned barrier layer extends to the first block to be removed. 如申請專利範圍第8項所述的封裝載板的製造方法，其中形成該圖案化阻障層於該第一表面的步驟包括： 使該圖案化阻障層沿該第一待移除區塊的邊緣延伸。The method for manufacturing a package carrier as recited in item 8 of the patent application range, wherein the step of forming the patterned barrier layer on the first surface includes: causing the patterned barrier layer to move along the first block to be removed Of the edge. 如申請專利範圍第7項所述的封裝載板的製造方法，其中裁切該可撓性基板及該第二增層結構的步驟包括： 藉由雷射製程同時裁切該可撓性基板及該第二增層結構。The method for manufacturing a package carrier as described in item 7 of the patent application scope, wherein the steps of cutting the flexible substrate and the second build-up structure include: simultaneously cutting the flexible substrate and the flexible substrate by a laser process The second build-up structure. 如申請專利範圍第7項所述的封裝載板的製造方法，更包括： 在形成該第一增層結構於該第一表面之前，形成一圖案化導電層於該第一表面，其中該圖案化導電層延伸至該第一待移除區塊。The method for manufacturing a package carrier as described in item 7 of the patent application scope further includes: before forming the first build-up structure on the first surface, forming a patterned conductive layer on the first surface, wherein the pattern The conductive layer extends to the first block to be removed. 如申請專利範圍第7項所述的封裝載板的製造方法，更包括使該封裝載板與另一該封裝載板共用該可撓性基板，其中該可撓性基板在該兩封裝載板之間的區段適於彎折。The method for manufacturing a package carrier as described in item 7 of the patent application scope further includes the package carrier and the other package carrier sharing the flexible substrate, wherein the flexible substrate is on the two package carriers The section in between is suitable for bending.
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