TW201739004A - Semiconductor module and method of manufacturing the same - Google Patents

Abstract

A semiconductor module and a method of manufacturing the same are provided. In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the module substrate. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connecting the first electrical connector to the module substrate.

Description

Semiconductor module and method of manufacturing same

The present invention relates to a semiconductor module, and in particular to a module substrate and a semiconductor module having the module substrate.

Recently, there is an increasing demand for lightweight and small-sized electronic devices such as cellular phones and notebook computers. The size and weight of the semiconductor module to be placed in the electronic device are reduced to meet such requirements. The semiconductor module can be inserted into a connector of the electronic device. Therefore, the semiconductor module is fabricated to meet international standards in terms of shape and size (e.g., thickness or width).

Certain embodiments of the inventive concept provide a small-sized semiconductor module and a module substrate including the small-sized semiconductor module.

At least one embodiment is directed to a semiconductor module.

In one embodiment, the semiconductor module includes: a module substrate; and a first substrate mounted on the first surface of the module substrate and electrically connected to the first surface. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connects the first electrical connector to the module substrate.

In one embodiment, the semiconductor module includes a main substrate. The connection substrate and the at least one wafer are mounted on the first surface of the main substrate. The connection substrate is electrically connected to the wafer via the main substrate, and the connection substrate includes one or more taps for electrically connecting the semiconductor module to an external device.

At least one embodiment is related to a system.

In one embodiment, the system includes a module substrate having a connection region and a system region. The module substrate has a first surface and a second surface, and the second surface is opposite to the first surface. The first substrate is mounted on the first surface of the module substrate in the connection region and electrically connected to the first surface. The first substrate has one or more first electrical connectors, and the first substrate electrically connects the first electrical connector to the module substrate. At least one first system structure is mounted on the first surface of the module substrate in the system area.

One embodiment relates to a method of fabricating a semiconductor module.

In one embodiment, the method includes mounting a first substrate on a first surface of the module substrate in a first region of the module substrate. The first substrate includes at least one first electrical connector for the semiconductor module on an outer surface of the first substrate. The method further includes mounting a first device structure on the first surface of the module substrate in a second region of the module substrate. The module substrate electrically connects the first substrate to the first device structure. The module further includes forming a first mold layer over the first surface of the module substrate to cover the first device structure and cover a portion of the first substrate to enable the first The electrical connector remains exposed.

It will be understood that when an element is "connected" or "coupled" to another element, the element can be directly connected or directly coupled to the other element or the intermediate element can be present.

It should be understood that, although the terms "first", "second", and the like may be used herein to describe various elements, these elements are not limited by the terms. These terms are only used to distinguish the individual components. The first element may be referred to as a second element, and the second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and/or" as used herein includes any and all combinations of one or more of the items listed.

FIG. 1A is a plan view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. Fig. 1B is a cross-sectional view taken along line I-I' shown in Fig. 1A. Fig. 1C is an enlarged cross-sectional view showing a portion 'II' shown in Fig. 1B.

Referring to FIGS. 1A and 1B , the semiconductor module 1 may include a module substrate 100 , a first substrate 210 , a second substrate 220 , a first electronic component 410 , a second electronic component 420 , and one or more first semiconductor wafers 510 . One or more second semiconductor wafers 520, a first mold layer 610, and a second mold layer 620. The module substrate 100 may include a first region R1 and a second region R2. The first region R1 of the module substrate 100 may be adjacent to the side 100c of the module substrate 100. The module substrate 100 can have a first surface 100a and a second surface 100b that are opposite each other (eg, opposite each other). As shown in FIG. 1B, the side 100c of the module substrate 100 may be perpendicular to the first surface 100a and the second surface 100b. As shown in FIG. 1A, the side 100c of the module substrate 100 may extend parallel to the second direction D2 when viewed in a plan view. In the present specification, the first direction D1 and the second direction D2 may be parallel to the first surface 100a of the module substrate 100 and may not be parallel to each other. The module substrate 100 may be a printed circuit board (PCB) provided with a circuit pattern. The module substrate 100 can have a substantially uniform thickness A2. Here, the thickness A2 of the module substrate 100 may refer to the distance between the first surface 100a and the second surface 100b. As shown in FIG. 1B, one or more first connection pads 131 and one or more second connection pads 132 may be disposed on the second region R2 of the module substrate 100. The first connection pad 131 and the second connection pad 132 may be disposed on the first surface 100a and the second surface 100b, respectively.

The first substrate 210 may be mounted on the first region R1 of the first surface 100a of the module substrate 100. The first substrate 210 may have a longitudinal axis parallel to the second direction D2 when viewed in a plan view. The first substrate 210 can be a printed circuit board (PCB). One or more first connecting portions 250 may be disposed between the module substrate 100 and the first substrate 210. The first connection portion 250 can be coupled to the upper pad 115 on the module substrate 100 and the pad on the first substrate 210. The first connection portion 250 may be provided in the form of a bump or a solder ball. The first substrate 210 can have two opposing surfaces (eg, a bottom surface 210b and a top surface 210a). Here, the first substrate 210 may be disposed such that the bottom surface 210b faces the module substrate 100. The top surface 210a of the first substrate 210 may be positioned at a higher level than the first surface 100a of the second region R2 of the module substrate 100.

A first tap 310 may be disposed on the top surface 210a of the first substrate 210. The first tap 310 can be adjacent to the side 100c of the module substrate 100. In some embodiments, as shown in FIG. 1A, a plurality of first taps 310 may be disposed on the top surface 210a of the first substrate 210. Each of the first taps 310 may be arranged in the second direction D2 to form a row parallel to the second direction D2. Each of the first taps 310 can have a longitudinal axis that is parallel to the first direction D1 when viewed in plan view. The first tap 310 can be formed of or comprise at least one metal, such as copper or aluminum. In some embodiments, each of the first taps 310 can be a portion of the circuit pattern of the first substrate 210 that is exposed by the first protective layer 213.

The first electronic component 410 can be mounted on the first surface 100a of the second region R2 of the module substrate 100. The first electronic component 410 can be spaced apart from the first substrate 210 in the first direction D1. The first electronic component 410 can include a capacitor, a resistor, or an inductor. The first interposer 415 can be interposed before the module substrate 100 and the first electronic component 410, and the first interposer 415 can be coupled to the connection pads of the first connection pad 131 and the first electronic component 410. The first interposer 415 may be provided in the form of a solder, a solder ball or a bump, but the inventive concept is not limited thereto.

The first semiconductor wafer 510 may be mounted on the first surface 100a of the second region R2 of the module substrate 100 and may be spaced apart from the first substrate 210 in the first direction D1. In some embodiments, the first semiconductor wafer 510 can include a memory device (eg, a dynamic random access memory (DRAM) device, a NAND Flash device, a reverse or a flash ( NOR Flash device, OneNAND device, phase-change random access memory (PRAM) device, resistive random access memory (ReRAM) device or At least one of magnetic random access memory (MRAM) devices). In some embodiments, the first semiconductor wafer 510 can include logic devices (eg, photoelectronic devices, communication devices, digital signal processors, controllers, or system-on-chips). In some embodiments, the first semiconductor wafer 510 can include a memory device and a logic device. For the purpose of simplifying the description, the connection of a single first semiconductor wafer 510 will be explained. One or more first terminals 515 may be interposed between the module substrate 100 and the first semiconductor wafer 510 and the one or more first terminals 515 may be coupled to the corresponding first connection pads 131 and the first semiconductor wafer 510 The corresponding connection pad at the place. The first terminal 515 can be provided in the form of a solder or a bump. Although not shown in the drawings, the first terminal 515 may be a bonding wire disposed on a top surface of the first semiconductor wafer 510.

The first mold layer 610 can be disposed on the first surface 100a of the module substrate 100 to cover the first electronic component 410 and the first semiconductor wafer 510. For example, the first mold layer 610 can include an insulating polymer (eg, an epoxy molding compound). The first mold layer 610 may extend into a gap between the module substrate 100 and the first substrate 210 to hermetically cover the first connection portion 250. The first mold layer 610 can be configured to relieve or prevent the first connection portion 250 from being detached from the module substrate 100 or the first substrate 210. This can improve the reliability of the semiconductor module 1. The first mold layer 610 may extend into a gap region between the first electronic component 410 and the module substrate 100 and a gap region between the first semiconductor wafer 510 and the module substrate 100 to hermetically cover the first interposer 415 and the first terminal 515. The first mold layer 610 can be configured to expose the first tap 310. The first mold layer 610 can have a top surface that is substantially coplanar with the top surface of the first protective layer 213.

The second semiconductor wafer 520 and the second electronic component 420 can be mounted on the second surface 100b of the second region R2 of the module substrate 100. The second semiconductor wafer 520 can include at least one of a memory device or a logic device that is the same as or similar to the memory device or logic device of the first semiconductor wafer 510. The second electronic component 420 can include at least one of a capacitor, a resistor, or an inductor that is the same as or similar to a capacitor, resistor, or inductor of the first electronic component 410. The second electronic component 420 can be coupled to the second connection pad 132 via the second interposer 425 and a connection pad on the second interposer 425. The second semiconductor wafer 520 can be coupled to the second connection pad 132 via the second terminal 525 and a connection pad on the second terminal 525.

The second substrate 220 may be disposed on the second surface 100b of the first region R1 of the module substrate 100. The second substrate 220 may be disposed in parallel to the second direction D2. The second substrate 220 may overlap the first substrate 210 when viewed in a plan view. As an example, a printed circuit board can be used as the second substrate 220. One or more second connecting portions 260 may be interposed between the module substrate 100 and the second substrate 220 and the one or more second connecting portions 260 may be coupled to corresponding connecting pads and lower pads of the second substrate 220 125. The second connection portion 260 may be provided in the form of a bump or a solder. The second substrate 220 may have a top surface 220a facing the module substrate 100 and a bottom surface 220b opposite to the top surface 220a. The bottom surface 220b of the second substrate 220 may be positioned at a lower level than the second surface 100b of the second region R2 of the module substrate 100.

A second tap 320 may be disposed on the bottom surface 220b of the second substrate 220. The second tap 320 can be adjacent to the side 100c of the module substrate 100. As shown in FIG. 1A, each of the second taps 320 can be aligned in the second direction D2. Each of the second taps 320 may have a longitudinal axis that is parallel to the first direction D1 when viewed in plan view. The second tap 320 may be formed of or comprise at least one metal (eg, copper or aluminum). Each of the second taps 320 may be a portion of the circuit pattern of the second substrate 220 that is exposed by the second protective layer 223.

The second mold layer 620 can be disposed on the second surface 100b of the module substrate 100 to cover the second electronic component 420 and the second semiconductor wafer 520. The second mold layer 620 may be disposed to hermetically cover the second connection portion 260, the second interposer 425, and the second terminal 525. The second mold layer 620 may be formed of an epoxy molding compound or comprise an epoxy molding compound. The second mold layer 620 can have a bottom surface that is substantially coplanar with the bottom surface of the second protective layer 223. The second mold layer 620 can provide the same advantages as the first mold layer 610.

As an example, the first semiconductor wafer 510 and the second semiconductor wafer 520 may include a dynamic random access memory chip, and the semiconductor module 1 may be used as a dynamic random access memory module. However, the type of the semiconductor module 1 is not limited to this. The number, arrangement, and planar shape of the semiconductor wafers 510, 520 and electronic components 410, 420 can vary. In some embodiments, at least one of the first semiconductor wafer 510, the second semiconductor wafer 520, the first electronic component 410, and the second electronic component 420 can be omitted.

2 is a cross-sectional view showing how a semiconductor module is connected to an electronic device in accordance with an embodiment of the present invention. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 2, the electronic device 1000 may include a connector 1100. The electronic device 1000 can be an information device (such as a portable computer or a smart TV), a household appliance (such as a video player or a digital video disc player (DVD player)), or a mobile device (such as a portable multimedia device). Portable multimedia player (PMP), portable digital video disc player or cellular phone).

The first region R1 of the semiconductor module 1 can be inserted into the connector 1100 of the electronic device 1000. Here, the first region R1 of the semiconductor module 1 may refer to a portion of the semiconductor module 1 corresponding to the first region R1 of the module substrate 100. The connector 1100 can include a first conductive pad 1111 and a second conductive pad 1112. If the semiconductor module 1 is inserted into the connector 1100, the first tap 310 and the second tap 320 can be respectively coupled to the first conductive Pad 1111 and second conductive pad 1112. That is, the semiconductor module 1 can be electrically connected to the electronic device 1000 via the first tap 310 and the second tap 320 and the first conductive pad 1111 and the second conductive pad 1112 . In general, the semiconductor module 1 can be set to meet the standards of the connector 1100. For example, the semiconductor module 1 can be disposed such that the first region R1 can have a thickness A corresponding to the gap distance B of the connector 1100, wherein the thickness A1 refers to the top surface of the first tap 310 and the second tap The distance between the bottom surfaces of 320, and the gap distance B refers to the distance between the first conductive pad 1111 and the second conductive pad 1112. The thickness A1 of the first region R1 of the semiconductor module 1 may be substantially equal to or thicker than the sum of the thickness A2 of the second region R2 of the module substrate 100, the thickness A3 of the first substrate 210, and the thickness A4 of the second substrate 220. The first substrate 210 and the second substrate 220 may be mounted on the first region R1 of the module substrate 100 such that the thickness A1 of the first region R1 of the semiconductor module 1 can be within a range satisfying the standard of the semiconductor module 1.

In the case where the first tap 310 and the second tap 320 are directly disposed on the first surface 100a and the second surface 100b of the module substrate 100, the thickness A1 of the second region R2 of the module substrate 100 can be combined with the semiconductor. The thickness of the first region R1 of the module 1 is the same or similar. In some embodiments, the thickness A2 of the second region R2 of the module substrate 100 may be smaller than the thickness A1 of the first region R1 of the semiconductor module 1. For example, the first surface 100a of the module substrate 100 can be positioned at a lower level than the top surface 210a of the first substrate 210. The second surface 100b of the module substrate 100 can be positioned at a higher level than the bottom surface 220b of the second substrate 220. The semiconductor wafers 510, 520 and the electronic components 410, 420 can be mounted on the second region R2 of the module substrate 100. Therefore, the second region R2 of the semiconductor module 1 can have a thin thickness (for example, the thickness A5), and thus, the size of the semiconductor module 1 can be reduced.

1C is an enlarged cross-sectional view illustrating an electrical connection between a tap and a module substrate in accordance with an embodiment of the present invention. The cross-sectional view shown in Fig. 1C may correspond to the portion 'II' shown in Fig. 1B. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 1C in conjunction with FIG. 1B, the first substrate 210 may include a first base layer 211 and a first conductive pattern. The first base layer 211 may include an insulating material. The first conductive pattern may be or may include a first via 212 penetrating the first base layer 211. The first conductive pattern may also be disposed on the top surface and the bottom surface of the first base layer 211. The first protective layer 213 may be disposed to cover the top surface 210a of the first substrate 210. As an example, the first substrate 210 can be a printed circuit board. The circuit pattern in the first substrate 210 (eg, on the top surface 210a) may be exposed by the first protective layer 213, and such a circuit pattern may be used as the first tap 310. The first tap 310 can be electrically connected to the one or more metal patterns 109 of the module substrate 100 via the first via 212 of the first conductive pattern. The vias and conductive patterns in the present invention may be formed of any of the well-known conductive materials such as copper or aluminum.

The second substrate 220 may include a second base layer 221 and a second conductive pattern. The second conductive pattern may be or may include a second via 222 that penetrates through the second base layer 221. The second protective layer 223 may be disposed to cover the bottom surface 220b of the second substrate 220. The circuit pattern in the second substrate 220 (eg, on the bottom surface 220b) may be exposed by the first protective layer 213, and such a circuit pattern may be used as the second tap 320. The second tap 320 may be electrically connected to one or more of the metal patterns 109 of the module substrate 100 via the second via 222 of the second conductive pattern. Some examples of the insulating layer of the module substrate 100 and the metal pattern 109 are explained and explained above, but the inventive concept is not limited thereto.

1D is an enlarged cross-sectional view illustrating an electrical connection between a tap and a module substrate in accordance with an embodiment of the present invention. The cross-sectional view shown in Fig. 1D may correspond to the portion 'II' shown in Fig. 1B. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 1D, the first substrate 210 and the second substrate 220 may be mounted on the first region R1 of the module substrate 100. The module substrate 100 can be configured to have the same or substantially the same features as described above. A plurality of first base layers 211 may be disposed as the first substrate 210, and the first conductive patterns may include one or more first conductive layers 214 and a plurality of first through holes 212. Each of the first conductive layers 214 may be interposed between the respective pair of stacked first base layers 211. The circuit pattern in the first substrate 210 (eg, on the top surface 210a) may be exposed by the first protective layer 213, and such a circuit pattern may be used as the first tap 310. The first tap 310 can be electrically connected to the module substrate 100 via the first via 212 , the first conductive layer 214 , and the first connection portion 250 .

The second substrate 220 may be disposed to have the same or substantially the same structure as that shown in FIG. 1C. A plurality of second base layers 221 may be disposed, and the second conductive patterns may include one or more second conductive layers 224s and a plurality of second through holes 222. Each of the second conductive layers 224 may be interposed between the respective pair of stacked second base layers 221. The circuit pattern in the second substrate 220 may be exposed by the second protective layer 223, and such a circuit pattern may be used as the second tap 320. The second tap 320 can be electrically connected to the module substrate 100 via the second via 222 and the second conductive layer 224 .

1C and FIG. 1D, it will be further understood that the module substrate 100 can be a printed circuit board including a plurality of stacked layers, and the module substrate 100 provides an electrical connection using a conductive pattern including vias and conductive layers.

FIG. 3A is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. For example, Figure 3A illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A.

Referring to FIG. 3A, the semiconductor module 2 may include a module substrate 100, a first substrate 210, a first tap 310, a first electronic component 410, the one or more first semiconductor wafers 510, and a first Mold layer 610. Unlike the embodiment shown in FIG. 1B, the second substrate 220, the second semiconductor wafer 520, the second electronic component 420, the second mold layer 620, and the second tap 320 may not be disposed.

The first substrate 210 may be disposed such that the thickness A1 of the first region R1 of the semiconductor module 2 can be within a range satisfying the standard of the semiconductor module. The thickness A2 of the second region R2 of the module substrate 100 may be smaller than the thickness A1 of the first region R1 of the semiconductor module 2. The first surface 100a of the second region R2 of the module substrate 100 may be positioned at a lower level than the top surface 210a of the first substrate 210. The first electronic component 410 and the first semiconductor wafer 510 may be mounted on the first surface 100a of the second region R2 of the module substrate 100.

FIG. 3B is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. For example, Figure 3B illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A.

Referring to FIG. 3B , the semiconductor module 3 may include a module substrate 100 , a first tap 310 , a second tap 320 , one or more first semiconductor wafers 510 , and one or more second semiconductor wafers 520 . The first electronic component 410, the second electronic component 420, the first mold layer 610, and the second mold layer 620. The module substrate 100, the first tap 310 and the second tap 320, the electronic component 410 and the electronic component 420, the semiconductor wafer 510 and the semiconductor wafer 520, and the mold layer 610 and the mold layer 620 can be configured to have the same reference to FIG. 1A. Features of Figure 1B that are identical or substantially identical.

A third substrate 218 may be interposed between the module substrate 100 and the first substrate 210. One or more third connecting portions 258 may be disposed between the module substrate 100 and the third substrate 218. One or more first connecting portions 259 may be disposed between the third substrate 218 and the first substrate 210. The first tap 310 may be disposed on the top surface 210a of the first substrate 210. The first tap 310 can be electrically connected to the module substrate 100 via the first substrate 210 , the first connecting portion 259 , the third substrate 218 , and the third connecting portion 258 . The first connection portion 259 may be aligned to the third connection portion 258 in the third direction D3. The first connection portion 259 and the third connection portion 258 may be solder or solder balls.

A fourth substrate 228 is interposed between the module substrate 100 and the second substrate 220. The second tap 320 may be disposed on the bottom surface 220b of the second substrate 220. The second tap 320 is electrically connected to the module substrate 100 via the second substrate 220 , the second connecting portion 269 , the fourth substrate 228 , and the fourth connecting portion 268 . The second connection portion 269 may not be aligned to the fourth connection portion 268 in the third direction D3. For example, the second connecting portion 269 can be displaced relative to the fourth connecting portion 268 in the first direction D1 and can be electrically coupled to the fourth connecting portion via the through hole and the circuit pattern disposed in the fourth substrate 228 . 268. The vertical alignment between the first to fourth connection portions 259, 269, 258, 268 and the arrangement of the circuits and via patterns in the first to fourth substrates 210, 220, 218, 228 are variously variable. The second connection portion 269 and the fourth connection portion 268 may be solder or solder balls.

The first to fourth substrates 210, 220, 218, and 228 may be disposed on the first region R1 of the module substrate 100 such that the thickness A1 of the first region R1 of the semiconductor module 3 can meet the standard of the semiconductor module. Within the scope. The number of the first to fourth substrates 210, 220, 218, 228 stacked on the module substrate 100 may not be limited to those shown in FIG. 3B. The thickness A2 of the second region R2 of the module substrate 100 may be smaller than the thickness A1 of the first region R1 of the semiconductor module 3. Further, the thickness of the module substrate 100, the thickness of the first substrate 210, the thickness of the second substrate 220, the thickness of the third substrate 218, and/or the thickness of the fourth substrate 228 may be the same.

FIG. 3C is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. For example, Figure 3 illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 3C, the semiconductor module 4 may include a module substrate 100, a first substrate 210, a second substrate 220, a first electronic component 410, a second electronic component 420, a first semiconductor wafer 510, a second semiconductor wafer 520, and a A mold layer 610 and a second mold layer 620. The thickness A1 of the first region R1 of the semiconductor module 4 may be within a range that satisfies the standard of the semiconductor module. A first pad 215 may be disposed on the bottom surface 210b of the first substrate 210. A second pad 225 may be disposed on the top surface 220a of the second substrate 220.

A first connection portion 251 is interposed between the module substrate 100 and the first substrate 210. An anisotropic conductive film can be used as the first connecting portion 251. For example, the first connection portion 251 may include the first insulating polymer 251i and the first conductive particles 251c, and the first conductive particles 251c may be disposed in the insulating polymer 251i. The first conductive particles 251c may be coupled to the first pad 215 and the upper pad 115. The module substrate 100 can be electrically connected to the first tap 310 via the first conductive particles 251c.

A second connecting portion 261 may be interposed between the module substrate 100 and the second substrate 220. The second connection portion 261 may include an anisotropic conductive film. For example, the second connection portion 261 may include a second insulating polymer 261i and second conductive particles 261c. The second conductive particles 261c can be coupled to the second pad 225 and the lower pad 125, and thus, the second tap 320 can be electrically connected to the module substrate 100.

FIG. 3D is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. For example, Figure 3D illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 3D, the semiconductor module 5 may include a module substrate 100, a first substrate 210, a second substrate 220, a first electronic component 410, a second electronic component 420, a first semiconductor wafer 510, a second semiconductor wafer 520, and a second A mold layer 610 and a second mold layer 620.

The first connection portion 252 can be or can include a bond wire. The first pad 215 may be disposed on the top surface 210a of the first substrate 210. The first tap 310 can be coupled to the first pad 215 via a first substrate 210, shown in dashed lines. The first connecting portion 252 can be disposed on the top surface 210 a of the first substrate 210 and can be electrically coupled to the first pad 215 and the upper pad 115 . The first mold layer 610 can extend from the first surface 100a of the second region R2 of the module substrate 100 to cover at least a portion of the top surface 210a of the first substrate 210. The first mold layer 610 can be configured to hermetically cover or seal the first pad 215 and the first connection portion 252 and expose the first tap 310.

The second connection portion 262 can be or can include a bond wire. The second pad 225 may be disposed on the bottom surface 220b of the second substrate 220. The second tap 320 can be coupled to the second pad 225 via a second substrate 220, shown in dashed lines. The second connecting portion 262 can be disposed on the bottom surface 220b of the second substrate 220 and can be electrically coupled to the second pad 225 and the lower pad 125. The second mold layer 620 may extend to cover a portion of the bottom surface 220b of the second substrate 220 and hermetically cover or seal the second pad 225 and the second connection portion 262. The second tap 320 can be exposed by the second mold layer 620.

4A is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. For example, Figure 4A illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A. For the sake of brevity, the previously described elements may be identified by similar or identical reference numerals and will not be described again.

Referring to FIG. 4A, the semiconductor module 6 can be divided by the module substrate 100, the first substrate 210, the first tap 310, the second tap 320, the second substrate 220, the first electronic component 410, the second electronic component 420, and the A third semiconductor wafer 530 and a memory wafer 540 are also included in addition to the semiconductor wafer 510, the second semiconductor wafer 520, the first mold layer 610, and the second mold layer 620. The module substrate 100, the substrate 210 and the substrate 220, the tap 310 and the tap 320, the electronic component 410 and the electronic component 420, the semiconductor wafer 510 and the semiconductor wafer 520, and the mold layer 610 and the mold layer 620 may be configured to have a reference pattern. 1A and 1B have the same or substantially the same features.

The semiconductor module 6 can be a solid state drive (SSD) module. For example, the semiconductor module 6 can be configured to read data from or write data to the memory chip 540 in response to a read/write request from an external electronic device (eg, 1000 shown in FIG. 2). . The first tap 310 and the second tap 320 can be used as a signal path for electrically connecting the semiconductor module 6 to the electronic device 1000.

The memory chip 540 may be stacked on the first surface 100a of the second region R2 of the module substrate 100. As shown, the memory wafers 540 can be staggered in a stack such that the bond wires can be electrically connected to the respective memory wafers 540. Memory chip 540 can be a non-volatile memory chip. For example, memory chip 540 can include a reverse flash memory device. Alternatively, the memory chip 540 may include a PRAM memory device, an MRAM memory device, a ReRAM memory device, a ferroelectric random access memory (FRAM) memory device, or an anti-flash or flash Memory device. The number and arrangement of the memory chips 540 may not be limited to those shown in FIG. 4A.

One of the first semiconductor wafer 510, the second semiconductor wafer 520, and the third semiconductor wafer 530 may serve as an interface, the other may serve as a controller, and the other may serve as a buffer memory chip. For the sake of brevity, the following description will refer to the first semiconductor wafer 510, the second semiconductor wafer 520, and the third semiconductor wafer 530 as examples of interfaces, controllers, and buffer memory wafers, respectively; however, the inventive concept may not be limited to this.

The first semiconductor wafer 510 can include an input/output interface circuit. For example, the first semiconductor wafer 510 can be configured to perform an interface operation between the electronic device 1000 and the semiconductor module 6 in accordance with a bus bar format of a host.

The second semiconductor wafer 520 can be configured to control the operation of connecting the memory wafer 540 to an external device (eg, the electronic device 1000) via the first semiconductor wafer 510. The second semiconductor wafer 520 can read data from or write data to the memory wafer 540 in response to a command from the electronic device 1000. The third semiconductor wafer 530 can be used as a buffer memory wafer. For example, the third semiconductor wafer 530 can temporarily store material to be transferred between the second semiconductor wafer 520 and the memory wafer 540 and/or between the second semiconductor wafer 520 and the electronic device 1000. The third semiconductor wafer 530 can be comprised of or include at least one random access memory device (eg, DRAM or static random access memory (SRAM)).

As another example, at least one of the first to third semiconductor wafers 510, 520, 530 may be omitted. For example, the second semiconductor wafer 520 can be omitted. In this case, the first semiconductor wafer 510 or the third semiconductor wafer 530 may be configured to function as a controller. In some embodiments, the second semiconductor wafer 520 and the third semiconductor wafer 530 can be omitted, and the first semiconductor wafer 510 can be configured to function as an interface, a controller, and a buffer memory wafer.

4B is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. For example, Figure 4B illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in Figure 1A. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 4B, the semiconductor module 7 can be removed from the module substrate 100, the first substrate 210, the second substrate 220, the first tap 310, the second tap 320, the first electronic component 410, the second electronic component 420, and the A die layer 610 and a second die layer 620 further include a first package 550, a second package 560, and a third package 570.

The first package 550 may be disposed on the first surface 100a of the second region R2 of the module substrate 100. The first package 550 may include a first package substrate 551, a first wafer 552, and a first molding pattern 553. The first package 550 can be electrically connected to the module substrate 100 via the first connection terminal 555 . More specifically, the first wafer 552 can be electrically connected to the module substrate 100 via the first package substrate 551. The second package 560 can be disposed on the first surface 100a of the second region R2 of the module substrate 100. The second package 560 can include a second package substrate 561, a second wafer 562, and a second molding pattern 563. A plurality of second wafers 562 may be stacked on the second package substrate 561. The second package 560 can be coupled to the module substrate 100 via the second connection terminal 565. More specifically, each of the second wafers 562 can be electrically connected to each other and electrically connected to the module substrate 100 via the second package substrate 561 .

A first underfill layer 611 may be interposed between the module substrate 100 and the first substrate 210 to hermetically cover or seal the first connection portion 250. A first device underfill layer 612 may be interposed between the module substrate 100 and the first electronic component 410. A first package underfill layer 613 and a second package underfill layer 614 may be interposed between the module substrate 100 and the first package 550 and between the module substrate 100 and the second package 560, respectively. The underfill layer may be an underfill layer of the intercalation material in the present invention. The first mold layer 610 can be disposed on the first surface 100a of the module substrate 100 to cover the first electronic component 410, the first package 550, and the second package 560. Although not shown, the first underfill layer 611, the first device underfill layer 612, the first package underfill layer 613, and the second package underfill layer 614 may be omitted, and the first mold layer 610 may be disposed to be hermetically sealed. The first connecting portion 250, the first interposer 415, the first connecting terminal 555, and the second connecting terminal 565 are covered or sealed. In some embodiments, the first mold layer 610 can be omitted.

The third package 570 can be mounted on the first surface 100a of the second region R2 of the module substrate 100. The third package 570 can include a lower package 571 and an upper package 575 on the lower package 571. The lower package 571 may include a lower substrate 572, a lower wafer 573, and a lower molding pattern 574. The upper package 575 can include an upper substrate 576, an upper wafer 577, and an upper molding pattern 578. A connection bump 579 may be disposed between the lower substrate 572 and the upper substrate 576 and the connection bump 579 is coupled to the lower substrate 572 and the upper substrate 576. The third package 570 can be coupled to the module substrate 100 via the third connection terminal 585. The lower substrate 572 and the upper substrate 576 electrically connect the upper wafer 577 to the module substrate 100 , and the lower substrate 572 electrically connects the lower wafer 573 to the module substrate 100 .

A second underfill layer 621 may be interposed between the module substrate 100 and the second substrate 220 to hermetically cover or seal the second connection portion 260. A second device underfill layer 622 may be disposed between the module substrate 100 and the second electronic component 420. A third package underfill layer 623 may be disposed between the module substrate 100 and the third package 570. The second mold layer 620 can be disposed on the second surface 100b of the module substrate 100 to cover the second electronic component 420 and the third package 570. As an example, the second underfill layer 621, the second device underfill layer 622, and the third package underfill layer 623 may be omitted, and the second mold layer 620 may be disposed to hermetically cover or seal the first connection portion 250, The second interposer 425 and the third connection terminal 585. In some embodiments, the second mold layer 620 can be omitted.

In the above embodiment, the first package 550 can be a memory controller, the second package 560 can be a non-volatile memory device, and the third package 570 can be an application processor.

Hereinafter, a process for manufacturing a semiconductor module will be explained.

5A, 6A, and 7A are plan views illustrating a process of fabricating a semiconductor module in accordance with an embodiment of the present invention. 5B, 6B, and 7B are cross sections taken along lines III-III' shown in Figs. 5A, 6A, and 7A, respectively. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIGS. 5A and 5B, a module strip 101 including a plurality of module regions 102 may be provided. As shown in FIG. 5A, the module area 102 can be arranged in the first direction D1 and the second direction D2 when viewed in a plan view. The module area 102 can be defined by a scribe line 151 and a scribe line 152. As shown in FIG. 5B, the scribe line 151 and the scribe line 152 may be recessed regions formed on the first surface 100a and the second surface 100b of the module strip 101. Each of the module areas 102 can include a first zone R1 and a second zone R2. In some embodiments, the module strip 101 can be configured to include a plurality of first regions R1. The first zone R1 can be disposed adjacent to the side 101c of the module strip 101.

The first connection pad 131 and the second connection pad 132 may be disposed on the second region R2 of the module strip 101. The first connection pad 131 and the second connection pad 132 may be respectively disposed on the first surface 100a and the second surface 100b of the module strip 101. The module strip 101 can have a uniform thickness. For example, the thickness A2 of the second region R2 of the module strip 101 may be the same as or substantially the same as the thickness of the first region R1.

Referring to FIGS. 6A and 6B, the first substrate 210 and the second substrate 220 may be mounted on the module strip 101. In some embodiments, the first substrate 210 provided with the first tap 310 can be prepared. For example, a printed circuit board can be used as the first substrate 210, and the first tap 310 can be some of the circuit patterns disposed in the first substrate 210. The first substrate 210 may be disposed on the first surface 100a of the module strip 101. The first substrate 210 may be disposed on the first surface 100a of the module substrate 100 and may be disposed to extend in the second direction D2 and intersect the plurality of module regions 102. The first substrate 210 may overlap the plurality of first regions R1 when viewed in a plan view. The first substrate 210 may not cover the second region R2.

A second substrate 220 provided with a second tap 320 can be prepared. The second substrate 220 can be disposed on the second surface 100b of the module strip 101. As shown in FIG. 6A, the second substrate 220 may be disposed to extend in the second direction D2 and intersect the plurality of module regions 102. The second substrate 220 may overlap the first region R1 when viewed in a plan view.

The first zone R1 of the module strip 101 may have a thickness A1 defined as the distance between the top surface of the first tap 310 and the bottom surface of the second tap 320. The thickness A1 of the first region R1 of the module strip 101 may be substantially equal to or greater than the sum of the thickness A2 of the second region R2 of the module region 102, the thickness A3 of the first substrate 210, and the thickness A4 of the second substrate 220. The first substrate 210 and the second substrate 220 may be disposed such that the thickness A1 of the first region R1 of the module strip 101 can be within a range satisfying the standard of the semiconductor module. The thickness A2 of the second region R2 of the module strip 101 may be less than the thickness A1 of the first region R1 of the module strip 101.

Referring to FIGS. 7A and 7B, the first semiconductor wafer 510, the first electronic component 410, and the first mold layer 610 may be mounted on the first surface 100a of the module strip 101. The second semiconductor wafer 520, the second electronic component 420, and the second mold layer 620 can be mounted on the second surface 100b of the module strip 101. Referring to FIGS. 7A and 1B in conjunction with FIGS. 1A and 1B, a sawing process can be performed along the dicing streets 151 and 152 on the module strip 101, and thus, the module strip 101 can be divided into many Module area 102. After the sawing process, each of the module areas 102 of the module strip 101 can be used as the module substrate 100 shown in FIGS. 1A and 1B. In some embodiments, the first substrate 210, the second substrate 220, and the mold layer 610 and the mold layer 620 can be divided together with the module strip 101 by a sawing process. The resultant structure may have the same structure as the semiconductor module 1 described with reference to FIGS. 1A and 1B.

8A, 8B, and 8C are cross-sectional views illustrating a process of forming a semiconductor module, in accordance with an embodiment of the present invention. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 8A, the first substrate 210 and the module substrate 100 can be prepared. For example, the first substrate 210 and the module substrate 100 may be formed of or comprise a semiconductor material such as germanium. The first substrate 210 may be disposed on the first region R1 of the module substrate 100 such that the first pad 215 of the first substrate 210 is aligned to the upper pad 115 of the module substrate 100. Before the deposition of the first substrate 210, a plasma etching process and a treatment using a chemical solution may be performed on the bottom surface 210b of the first substrate 210 and the first region R1 of the first surface 100a of the module substrate 100. Treatment process. The plasma etching process can be performed using at least one of oxygen, argon, nitrogen, CF ₄ or NH ₃ . The treatment process can be performed using ammonium hydroxide, NH ₄ F or HF as a chemical solution. The plasma etching process and processing process may be performed to form an activated functional group on the bottom surface 210b of the first substrate 210 and the first surface 100a of the first region R1 of the module substrate 100. The reactive functional group can be Si-NH ₂ or Si-F.

Referring to FIG. 8B, the first substrate 210 may be directly bonded to the module substrate 100. For example, the reactive functional groups on the bottom surface 210b of the first substrate 210 can react with the reactive functional groups on the first surface 100a of the module substrate 100, and thus, the first substrate 210 can be attached to the module substrate 100. . The first pad 215 can be coupled to the upper pad 115, and thus, the first substrate 210 can be electrically connected to the module substrate 100. Direct bonding to the first substrate 210 can be performed at room temperature (for example, about 25 ° C). As another example, during the process of attaching the first substrate 210 to the module substrate 100, an annealing process may be further performed on the first substrate 210. The annealing process can be performed at a temperature of 200 ° C or less.

Referring to FIG. 8C, the second substrate 220 may be directly bonded to the second surface 100b of the module substrate 100. The second substrate 220 may be formed of or comprise a semiconductor material such as germanium. Direct bonding can be performed on the second substrate 220 using the same method as that used for the first substrate 210 shown in FIGS. 8A and 8B. The first electronic component 410, the first semiconductor wafer 510 and the first mold layer 610, the second electronic component 420, the second semiconductor wafer 520, and the second mold layer 620 may be mounted on the module substrate 100. As a result of the above process, the semiconductor module 8 can be fabricated.

9A and 9B are cross-sectional views illustrating a process of forming a semiconductor module in accordance with an embodiment of the present invention. For example, each of FIGS. 9A and 9B illustrates a vertical cross section of the semiconductor module taken along line I-I' shown in FIG. 1A. For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be described again.

Referring to FIG. 9A, a module substrate 100 including a first substrate 210 and a second substrate 220 can be fabricated. For example, the module substrate 100 having the first tap 310 and the second tap 320 can be prepared. Here, the module substrate 100 may be a printed circuit board. Thereafter, certain portions of the module substrate 100 may be removed (eg, by etching, grinding, etc.) to form a first recessed region on the top and bottom surfaces of the module substrate 100 as indicated by dashed lines, respectively. 121 and the second recessed area 122. The first recessed region 121 may be formed to define the first substrate 210. The first surface 100a of the second region R2 of the module substrate 100 may correspond to a bottom surface of the first recess region 121 and may be positioned at a lower level than the top surface 210a of the first substrate 210. The second recessed region 122 may be formed to define the second substrate 220. The second surface 100b of the second region R2 of the module substrate 100 may correspond to a bottom surface of the second recess region 122 and may be positioned at a lower level than the bottom surface 220b of the second substrate 220. Referring to FIG. 9A in conjunction with FIG. 1C and FIG. 1D, an electrical connection can be established between the first substrate 210 and the second substrate 220 and the module substrate 100 in a manner similar to that described with reference to FIG. 1C or FIG. In some embodiments, the connecting portion 250 and the connecting portion 260 shown in FIG. 1C and FIG. 1D may be omitted, and the first conductive pattern and the second conductive pattern of the first substrate 201 and the second substrate 220 may be directly coupled to the module. The metal pattern 109 of the group substrate 100.

Referring to FIG. 9B, the first electronic component 410, the first semiconductor wafer 510, and the first mold layer 610 may be mounted in the first recessed region 121, and the second electronic component 420 and the second semiconductor may be mounted in the second recessed region 122. Wafer 520 and second mold layer 620. The thickness A1 of the first region R1 of the semiconductor module 9 may be greater than the thickness A2 of the second region R2 of the module substrate 100. Therefore, the semiconductor module 9 can be manufactured.

According to some embodiments of the inventive concept, a first region of a semiconductor module can be inserted into an electronic device. The first substrate and the second substrate may be mounted on the first region of the module substrate. The first substrate and the second substrate may be disposed such that the thickness of the first region of the semiconductor module can be within a range that satisfies the standard of the thickness of the semiconductor module. The thickness of the second region of the module substrate may be less than the thickness of the first region of the semiconductor module. The semiconductor wafer can be mounted on the second region of the module substrate. Therefore, the size of the semiconductor package can be reduced.

While the exemplary embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that the form and details can be made without departing from the spirit and scope of the appended claims. The change on.

1, 2, 3, 4, 5, 6, 7, 8, 9‧‧‧ semiconductor modules
100‧‧‧Module substrate
100a‧‧‧ first surface
100b‧‧‧ second surface
100c, 101c‧‧‧ side
101‧‧‧Modular strips
102‧‧‧Modular area
109‧‧‧Metal pattern
115‧‧‧Upper mat
121‧‧‧First recessed area
122‧‧‧Second depression
125‧‧‧lower pad
131‧‧‧First connection pad
132‧‧‧Second connection pad
151, 152‧‧ ‧ cutting road
210‧‧‧Substrate/first substrate
210a, 220a‧‧‧ top surface
210b, 220b‧‧‧ bottom surface
211‧‧‧ first base layer
212‧‧‧First through hole
213‧‧‧ first protective layer
215‧‧‧First pad
218‧‧‧ third substrate
220‧‧‧Substrate/second substrate
221‧‧‧Second base layer
222‧‧‧Second through hole
223‧‧‧Second protective layer
224‧‧‧Second conductive layer
225‧‧‧second pad
228‧‧‧fourth substrate
250‧‧‧Connection/First Connection
251, 252, 259‧‧‧ first connection
251c‧‧‧First conductive particles
251i‧‧‧Insulating Polymer / First Insulation Polymer
258‧‧‧ Third connection
260‧‧‧Connection/Second Connection
261, 262, 269‧ ‧ second connection
261c‧‧‧Second conductive particles
261i‧‧‧Second insulating polymer
268‧‧‧fourth connection
310‧‧‧ tap/first tap
320‧‧‧ tap/second tap
410‧‧‧Electronic components/first electronic components
415‧‧‧First interposer
420‧‧‧Electronic components/second electronic components
425‧‧‧Second interpolator
510‧‧‧Semiconductor wafer/first semiconductor wafer
515‧‧‧First terminal
520‧‧‧Semiconductor wafer/second semiconductor wafer
525‧‧‧second terminal
530‧‧‧ Third semiconductor wafer
540‧‧‧ memory chip
550‧‧‧first package
551‧‧‧First package substrate
552‧‧‧First chip
553‧‧‧First molded pattern
555‧‧‧First connection terminal
560‧‧‧second package
561‧‧‧Second package substrate
562‧‧‧second chip
563‧‧‧Second molding pattern
565‧‧‧Second connection terminal
570‧‧‧ Third package
571‧‧‧Lower package
572‧‧‧lower substrate
573‧‧‧lower wafer
574‧‧‧Lower molding pattern
575‧‧‧Upper package
576‧‧‧Upper substrate
577‧‧‧Upper wafer
578‧‧‧Upper moulding pattern
579‧‧‧connection bumps
585‧‧‧third connection terminal
610‧‧‧Mold layer/first mold layer
611‧‧‧First underfill layer
612‧‧‧The bottom layer of the first device
613‧‧‧First package underfill
614‧‧‧Second package underfill
620‧‧‧Mold layer / second mold layer
621‧‧‧Second underfill layer
622‧‧‧Second device underfill
623‧‧‧ Third package underfill
1000‧‧‧Electronic devices
1100‧‧‧Connector
1111‧‧‧First conductive pad
1112‧‧‧Second conductive pad
A1, A2, A3, A4, A5‧‧ thickness
B‧‧‧ clearance distance
D1‧‧‧ first direction
D2‧‧‧ second direction
D3‧‧‧ third direction
I-I', III-III'‧‧‧ line
Section II‧‧‧
R1‧‧‧ first district
R2‧‧‧Second District

The exemplary embodiments will be more clearly understood from the following description of the appended claims. The drawings represent various non-limiting exemplary embodiments described herein. FIG. 1A is a plan view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. Fig. 1B is a cross-sectional view taken along line I-I' shown in Fig. 1A. 1C is an enlarged cross-sectional view showing a portion 'II' of FIG. 1B according to an embodiment of the present invention. FIG. 1D is an enlarged cross-sectional view showing a portion 'II' of FIG. 1B according to an embodiment of the present invention. 2 is a cross-sectional view showing how a semiconductor module is connected to an electronic device in accordance with an embodiment of the present invention. FIG. 3A is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. FIG. 3B is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. FIG. 3C is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. FIG. 3D is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the inventive concept. 4A is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. 4B is a cross-sectional view illustrating a semiconductor module in accordance with an embodiment of the present invention. 5A, 6A, and 7A are plan views illustrating a process of fabricating a semiconductor module in accordance with an embodiment of the present invention. 5B, 6B, and 7B are cross sections taken along lines III-III' shown in Figs. 5A, 6A, and 7A, respectively. 8A, 8B, and 8C are cross-sectional views illustrating a process of forming a semiconductor module in accordance with an embodiment of the present invention. 9A and 9B are cross-sectional views illustrating a process of forming a semiconductor module in accordance with an embodiment of the present invention.

1‧‧‧Semiconductor Module

100‧‧‧Module substrate

100c‧‧‧ side

210‧‧‧Substrate/first substrate

220‧‧‧Substrate/second substrate

310‧‧‧ tap/first tap

320‧‧‧ tap/second tap

410‧‧‧Electronic components/first electronic components

420‧‧‧Electronic components/second electronic components

510‧‧‧Semiconductor wafer/first semiconductor wafer

520‧‧‧Semiconductor wafer/second semiconductor wafer

D1‧‧‧ first direction

D2‧‧‧ second direction

I-I’‧‧‧ line

R1‧‧‧ first district

R2‧‧‧Second District

Claims (25)

A semiconductor module includes: a module substrate; and a first substrate mounted on the first surface of the module substrate and electrically connected to the first surface, the first substrate having the semiconductor module One or more first electrical connectors, the first substrate electrically connecting the first electrical connector to the module substrate. The semiconductor module of claim 1, wherein the module substrate has a first region and a second region, and the first substrate is mounted on the module substrate in the first region . The semiconductor module of claim 2, wherein an edge of the first substrate is aligned with an edge of the module substrate. The semiconductor module of claim 3, wherein the first electrical connector is a tap extending perpendicularly from the edge of the first substrate on an outer surface of the first substrate . The semiconductor module of claim 4, wherein the first substrate comprises a plurality of taps arranged in a row along the edge of the first substrate. The semiconductor module of claim 5, further comprising: a mold layer located above the first surface of the module substrate and partially covering the first substrate to make the plurality of points The joint remains exposed. The semiconductor module of claim 2, wherein the first electrical connector is a tap extending perpendicularly from the edge of the first substrate on an outer surface of the first substrate . The semiconductor module of claim 2, wherein an outer surface of the first substrate is at a different level from the first surface of the module substrate in the second region. The semiconductor module of claim 2, wherein the thickness of the semiconductor module at the first region satisfies a thickness requirement of a standardized connector. The semiconductor module of claim 2, further comprising: at least one wafer mounted to the module substrate in the second region. The semiconductor module of claim 2, further comprising: at least one package mounted to the module substrate in the second region. The semiconductor module of claim 1, wherein at least one solder ball electrically connects the first substrate to the module substrate. The semiconductor module of claim 1, further comprising: a second substrate mounted on the second surface of the module substrate and electrically connected to the second surface, the second surface and The first surface is opposite, the second substrate has one or more second electrical connectors for the semiconductor module, and the second substrate electrically connects the second electrical connector to The module substrate. The semiconductor module of claim 13, wherein the module substrate has a first region and a second region, and the first substrate and the second substrate are mounted in the first region On the module substrate. The semiconductor module of claim 14, wherein an edge of the first substrate is aligned with an edge of the module substrate, and an edge of the second substrate and the edge of the module substrate Align. A semiconductor module comprising: a main substrate; and a connection substrate and at least one wafer mounted on the first surface of the main substrate, the connection substrate being electrically connected to the wafer via the main substrate, and The connection substrate includes one or more taps for electrically connecting the semiconductor module to an external device. A system includes: a module substrate having a connection area and a system area, the module substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first substrate, The connection area is mounted on the first surface of the module substrate and electrically connected to the first surface, the first substrate has one or more first electrical connectors, the first substrate Electrically connecting the first electrical connector to the module substrate; and at least one first system structure mounted on the first surface of the module substrate in the system region. The system of claim 17, wherein the first system structure is a wafer. The system of claim 17, wherein the first system structure is a package. The system of claim 17, further comprising: a second substrate mounted on the second surface of the module substrate and electrically connected to the second surface in the connection region, The second substrate has one or more second electrical connectors, the second substrate electrically connects the second electrical connector to the module substrate; at least one second system structure The system area is mounted on the second surface of the module substrate. The system of claim 20, wherein the first system structure is one of a wafer and a package, and the second system structure is one of a wafer and a package. The system of claim 20, wherein the system is a solid state drive. The semiconductor module of claim 20, wherein an outer surface of the first substrate is at a different level from the first surface of the module substrate in the system region, and The outer surface of the second substrate is at another level different from the second surface of the module substrate in the system region. A method of manufacturing a semiconductor module, comprising: mounting a first substrate on a first surface of the module substrate in a first region of the module substrate, the first substrate being on an outer surface of the first substrate Having at least one first electrical connector for the semiconductor module; mounting a first device structure on the first surface of the module substrate in a second region of the module substrate, The module substrate electrically connects the first substrate to the first device structure; and forming a first mold layer over the first surface of the module substrate to cover the first device And covering a portion of the first substrate such that the first electrical connector remains exposed. The method of manufacturing a semiconductor module according to claim 24, further comprising: mounting a second substrate on the second surface of the module substrate in the first region of the module substrate, The second substrate includes at least one second electrical connector on an outer surface of the second substrate, the second surface is opposite to the first surface; and the second device is disposed on the module substrate The second area is mounted on the second surface of the module substrate, and the module substrate electrically connects the second substrate to the first device structure and the second device structure Forming at least one of the second mold layer over the second surface of the module substrate to cover the second device structure and covering a portion of the second substrate to enable the second The sexual connector remains exposed.