TW201738754A - Method, device, and system for dynamically allocating memory - Google Patents

Abstract

A method, device, and system for dynamically allocating memory. The method comprises: receiving a memory allocation request from a server; determining, according to the memory allocation request, and on the basis of a memory pool comprising a plurality of memory chips driven by a PCIE apparatus, whether a total available memory size of one or more memory chips satisfies a requested memory size; and if so, allocating to the server the requested memory size. The method, device, and system can realize dynamic memory allocation for a server.

Description

Method, device and system for dynamically allocating memory

The present invention relates to the field of computer technology, and in particular, to a method, device and system for dynamically allocating memory.

In computer systems, memory is one of the key factors determining the performance of the whole machine. In the server system, DIMMs (Dual-Inline-Memory-Modules) are often used as the memory. The granules in the DIMM memory are packaged in a DIP (Dual Inline Package). The early memory particles were soldered directly onto the motherboard so that if a piece of memory fails, the entire motherboard is scrapped. Later, a memory particle slot appeared on the motherboard, so that the memory particles could be replaced. The more commonly used memory particles are DRAM (Dynamic Random Access Memory) chips. DIMMs include one or more DRAM chips on a small integrated circuit board that can be directly connected to the motherboard using some of the pins on the board.

DIMMs are often used in server systems. Due to the large capacity limitation of DIMMs, from 8G, 16G, 32G, 64G to 128G, the single capacity is small. The lack of flexibility relative to rapid business changes. The current practice is to insert 16 DIMMs in a single server (single machine), or extend the DIMM through the RAZER card to achieve the purpose of expanding the memory capacity. However, since the DIMM is limited by the DIMM CHANNEL of the CPU, there is a limitation in capacity, which results in a server of different specifications due to the capacity requirement, which brings management inconvenience and overhead.

One of the technical problems solved by the present invention is to provide a method, device and system for dynamically allocating memory.

According to an embodiment of an aspect of the present invention, a method for dynamically allocating memory includes: receiving a memory allocation request of at least one server; and based on the memory allocation request, based on a plurality of bus interface interfaces a memory pool composed of standard device-driven memory particles, determining whether the memory pool has a memory sum of one or more free memory particles satisfying the requested memory size; if so, the requested memory Assigned to the server.

Preferably, the memory particles comprise DRAM particles, and the method further comprises: converting the DRAM interface of the DRAM particles into a PCIE interface.

Preferably, the converting the DRAM interface of the DRAM particles into the PCIE interface comprises: expanding the capacity of the DRAM interface through the memory buffer; connecting the input of the memory controller to the DRAM particles, and performing double rate on the memory controller. The conversion logic of the DDR memory process to the PCIE process causes the output of the memory controller to be the PCIE interface.

Preferably, driving the DRAM particles through the PCIE device comprises: enabling the SRIOV function of the PCIE device; installing the physical function PF driver and the virtual function VF driver; realizing mapping of the PCIE address, the server address and the memory address, and The address map is written to the PF driver and the VF driver.

Preferably, the method further includes: deploying the memory pool: controlling, by a management unit, the plurality of servers to share the memory space of the memory pool; operating the PF driver in the management unit, thereby The space corresponds to and matches the virtual function driving space ID; the virtual function driver is run on each server, so that the server finds its corresponding address space and operates.

Preferably, the method further comprises: determining whether the server uses the allocated memory space, and if so, releasing the memory space.

Preferably, if it is determined that the requested memory space is not available, the method further includes: waiting, and determining whether there is a newly released memory space; if the released memory space satisfies the requested memory requirement, The released memory space is allocated to the server.

According to an embodiment of an aspect of the present invention, an apparatus for dynamically allocating a memory includes: a request receiving unit configured to receive a memory allocation request to a server; and a determining unit configured to allocate a request according to the memory Determining whether the memory pool has a memory sum of one or more free memory particles satisfying the requested memory size based on a memory pool composed of a plurality of memory particles driven by the bus interface standard device An allocating unit for allocating the requested memory to the server.

Preferably, the memory particles comprise DRAM particles; the device further comprises: an interface conversion unit for expanding the capacity of the DRAM interface through the memory buffer; and connecting the input of the memory controller to the DRAM particles in the memory The body controller performs the conversion logic of the DDR memory process to the PCIE process, so that the output of the memory controller is the PCIE interface, so that the output of the memory controller is the PCIE interface.

Preferably, the device further comprises: a driving unit for enabling the SRIOV function of the PCIE device; installing the PF driver and the VF driver; and implementing mapping of the PCIE address, the server address and the memory address, and The address map is written to the PF driver and the VF driver.

Preferably, the device further includes: a memory pool deployment unit, configured to control a memory space shared by the plurality of servers in the memory pool; and running the PF driver in the management unit to thereby user space and VF The space IDs correspond to and match; and the VF driver is run on each server, so that the server finds its own corresponding address space and operates.

Preferably, the determining unit is further configured to: determine whether the server uses the allocated memory space; and the device further includes: a releasing unit, configured to release the used memory space.

Preferably, the determining unit is further configured to: if it is determined that the requested memory space is not available, wait, and determine whether there is a newly released memory space; if the released memory space satisfies the requested memory requirement And instructing the allocating unit to allocate the released memory space to the server.

According to an embodiment of an aspect of the present invention, a system for dynamically allocating memory is provided, the system comprising: being driven by a plurality of PCIE devices A memory pool composed of DRAM particles; one or more servers; and the device for dynamically allocating memory according to any of the above.

According to an embodiment of another aspect of the present invention, a memory is provided, the memory comprising a plurality of memory particles, wherein the memory particles are driven by a busbar interface standard device.

It can be seen that the present invention separates the server and the memory through the PCIE through a memory pool composed of a plurality of DRAM particles driven by the PCIE device, and can realize dynamic allocation and on-demand allocation of memory by different servers through PCIE exchange. . Preferably, the capacity expansion is performed by the memory buffer during the process of converting the interface of the DRAM particles into the PCIE interface. In addition, since the memory particles are expanded by the memory buffer, and the dynamic allocation and on-demand allocation of the memory pool, there is no need to increase the entire memory strip compared with the standard memory, so the cost has a lower advantage. . Moreover, compared to the existing standard memory, the PCIE device can be hot swapped, so the maintainability is enhanced.

Those skilled in the art will appreciate that although the following detailed description is made with reference to the illustrated embodiments and drawings, the invention is not limited to these embodiments. Rather, the scope of the invention is intended to be limited only by the scope of the appended claims.

501‧‧‧Request receiving unit

502‧‧‧judging unit

503‧‧‧Distribution unit

504‧‧‧Interface conversion unit

505‧‧‧ drive unit

506‧‧‧ memory pool deployment unit

507‧‧‧ release unit

Other features, objects, and advantages of the present invention will become more apparent from the Detailed Description of Description 1 is a flow chart of a method for dynamically allocating memory according to an embodiment of the present invention; FIG. 2 is a schematic diagram of converting a set of DRAM interfaces into a PCIE interface in a method for dynamically allocating memory according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a DRAM pool deployment based on a PCIE interface in a method for dynamically allocating memory according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a DRAM pool deployment based on a PCIE interface in a method for dynamically allocating memory according to an embodiment of the present invention; It is a schematic structural diagram of an apparatus for dynamically allocating memory according to an embodiment of the present invention.

Those skilled in the art will appreciate that although the following detailed description is made with reference to the illustrated embodiments and drawings, the invention is not limited to these embodiments. Rather, the scope of the invention is intended to be limited only by the scope of the appended claims.

Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as a process or method depicted as a flowchart. Although the flowcharts describe various operations as a sequential process, many of the operations can be implemented in parallel, concurrently or concurrently. In addition, the order of operations can be rearranged. The process may be terminated when its operation is completed, but may also have additional steps not included in the figures. The processing may correspond to methods, functions, procedures, sub-routines, sub-programs, and the like.

The computer device includes a user device and a network device. The user equipment includes, but is not limited to, a computer, a smart phone, a PDA, etc.; the network device includes but is not limited to a single network server, a server group composed of multiple network servers, or a cloud-based computing system ( Cloud Computing is a cloud of computers or web servers. Cloud computing is a kind of decentralized computing. It is a super virtual computer composed of a group of loosely coupled computers. Wherein, the computer device can be operated separately to implement the present invention, and can also access the network and implement the present invention by interacting with other computer devices in the network. The network where the computer device is located includes, but is not limited to, an internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.

It should be noted that the user equipment, the network equipment, the network, and the like are merely examples, and other existing or future computer equipment or networks may be applicable to the present invention, and should also be included in the scope of the present invention. Within, and by reference.

The methods discussed below, some of which are illustrated by flowcharts, can be implemented by hardware, software, firmware, mediation software, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, mediation software, or microcode, the code or code segments used to perform the necessary tasks can be stored in a machine or computer readable medium (such as a storage medium). The processor(s) can perform the necessary tasks.

The specific structural and functional details disclosed are merely representative and are for the purpose of describing exemplary embodiments of the invention. However, the invention may be embodied in many alternative forms and should not be construed The invention is limited only to the embodiments set forth herein.

It should be understood that although the terms "first," "second," etc. may be used herein to describe the various elements, these elements should not be limited by these terms. These terms are used only to distinguish one unit from another. For example, a first unit could be termed a second unit, and similarly a second unit could be termed a first unit, without departing from the scope of the exemplary embodiments. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that when a unit is referred to as "connected" or "coupled" to another unit, it can be directly connected or coupled to the other unit, or an intermediate unit can be present. In contrast, when a unit is referred to as being "directly connected" or "directly coupled" to another unit, there is no intermediate unit. Other words used to describe the relationship between the units should be interpreted in a similar manner (eg "between" and "directly between" and "adjacent to" Than "directly adjacent to", etc.).

The terminology used herein is for the purpose of describing the particular embodiments, The singular forms "a", "an", It is also to be understood that the terms "comprises" and / or "comprising", "the", "the" Other features, integers, steps, operations, units, elements, and/or combinations thereof.

It should also be mentioned that in some alternative implementations, the mentioned The functions/acts can occur in an order different from that indicated in the drawings. For example, two figures shown in succession may in fact be executed substantially concurrently or sometimes in the reverse order, depending on the function/acts involved.

The technical terms in the embodiments of the present invention are first explained as follows.

Memory particles: Also known as memory chips or memory chips, often referred to as memory cells of a memory strip.

DRAM particles: from DRAM wafers as memory particles.

The PCIE (Peripheral Component Interface Express) device refers to a device that supports the PCIE protocol.

The SRIOV feature allows efficient sharing of PCIE devices between devices/virtual machines.

VF (Virtual Function) driver is mainly used to discover PCIE devices.

The PF (Physical Function) driver is mainly used to manage the correspondence between the address of each user space of the memory and the ID of the VF.

The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a flow chart of a method of dynamically allocating memory in accordance with an embodiment of the present invention. The method of this embodiment mainly includes the following steps: S110: receiving a memory allocation request of a server; S120, determining, according to a memory allocation request, a memory pool based on a memory pool composed of a plurality of memory particles driven by a PCIE device Whether the pool One or more free memory particles satisfy the requested memory space; if there is a requested memory space, step S130 is performed; if there is no requested memory space, step S140 is performed.

S130, allocating the requested memory space to the server; S140, waiting; S150, determining whether there is a newly released memory space, and determining whether the released memory space satisfies the requested memory requirement; if the released memory The body space satisfies the requested memory requirement, and S160 is executed; if not, the process returns to S140 and continues to wait.

S160. Allocate the released memory space to the server.

The memory pool is composed of a plurality of memory particles driven by a PCIE device, wherein the memory particles may be DRAM particles. This means that interface conversion and protocol conversion of DRAM particles are required, and the interface-converted DRAM particles need to be driven by PCIE devices, and the PCIE interface-based DRAM pool needs to be deployed.

In order to further understand the present invention, the following aspects are further described in detail from the above aspects.

First, the implementation of the DRAM interface to PCIE interface is introduced.

2 is a schematic diagram of converting a set of DRAM interfaces into a PCIE interface in a method of dynamically allocating memory according to an embodiment of the invention.

In the specific implementation, the interface conversion and protocol conversion functions can be implemented by means of the FPGA.

The process of transferring the DRAM interface to the PCIE interface includes:

(Step 1) The DRAM interface is capacity-expanded by MEMORY BUFFER.

The memory referred to in the present invention refers to a server memory. Those skilled in the art understand that the server memory is also a memory, and it has no obvious substantive difference between the appearance and the structure of the ordinary PC memory. It mainly introduces some new technologies into the memory.

For example, server memory can be divided into Buffer memory with cache and Unbuffer memory without cache. Buffer is a scratchpad, which can also be understood as a cache memory. It has many applications in the memory of the server and the graphics workstation. The capacity is mostly 64K, but as the capacity of the memory increases, its capacity also increases. Memory with Buffer will greatly improve the read and write speed of the memory. Memory with Buffer almost always has ECC (Error Checking and Correcting) function.

Register is a register or a directory register. The role on the memory can be understood as a book directory. Through Register, when the memory is connected to the read and write instructions, the directory will be retrieved first, then read and write operations, which will greatly improve Server memory efficiency. Memory with Register (register or directory register) must have a Buffer, and the Register memory currently visible also has ECC functionality.

LRDIMMs (Load-Reduced DIMMs) achieve the goal of reducing server bus load and power consumption by using new technology and lower operating voltage, and allowing the server memory bus to be used. In order to achieve a higher operating frequency and significantly increase the memory support capacity.

For normal Unbuffered DIMMs, the Registered DIMM used by the server boosts the memory support capacity by buffering the signal on the memory bank and replaying the memory particles, while the LRDIMM memory changes the Register wafer on the current RDIMM memory to an iMB. (isolation Memory Buffer) The memory isolation buffer chip reduces the load on the memory bus and further increases the memory support capacity accordingly.

The DIMMs of the present invention are not limited in type, i.e., the DIMMs of the present invention cover current or future types of DIMMs. Also, the memory capacity is increased by the Memory Buffer function of the DIMM.

After the above step (1), by connecting the high-speed IO pin of the FPGA to the interface of the DIMM and then defining these pins, the internal logic implementation is to internally compare the signals of these high-speed pins to a MEMORY controller.

DRAM has the advantages of low power consumption, high integration (large single-chip capacity), and low price, but the control of DRAM is relatively complicated and requires timing refresh, so it is necessary to design a DRAM controller. The FPGA (Field Programmable Gate Array) provides high-capacity programmable logic to design a DRAM controller (MEMORY controller) that meets specific requirements. Since the FPGA is a CMOS process, its power consumption is very small, and at the same time, the FPGA can be rewritten to facilitate performance expansion. If necessary, simply change the internal logic of the FPGA to suit different design needs or environments. begging. In addition to using FPGA to implement the memory controller, other programmable logic devices can be implemented, such as CPLD (Complex Programmable Logic Device), PLD (Programmable Logic Device), etc. .

(Step 2) The input of the MEMORY controller is connected to the DRAM pellet, so the input of the MEMORY controller is a DDR unit supporting a DDR (double data rate) process.

(Step 3) The exit of the MEMORY controller is a high-speed SERDES (SERializer/DESerializer) supporting NVME (Non-Volatile Memory Express) and PCIE (Peripheral Component Interface Express). /Deserializer) to match the PCIE interface of the PCIE device.

In this example, the DDR memory is taken as an example, which has the advantage of a fast transmission rate.

NVMe is a logical device interface standard like AHCI. It is a specification of SSD using PCI-E channel. NVMe is designed to take full advantage of the low latency and parallelism of PCI-E SSD, as well as contemporary processors. Parallelism between platform and application. The parallelism of SSD can be fully utilized by the host hardware and software. Compared with the current AHCI standard, the NVMe standard can bring various performance improvements.

PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth, and the busbar bandwidth is not shared. Supports active power management, error reporting, end-to-end reliability transfer, hot swap and quality of service (QOS). The main advantage of PCIE is the high data transfer rate. For example, the current highest 16X 2.0 version can reach 10GB/s, and there is considerable potential for development.

Here, it is necessary to implement a complete set of logic for logical translation of DDR, PCIE and NVME processes/protocols in hardware language. In this example, it is implemented inside the FPGA. In order to convert the DRAM interface to PCIE interface conversion, the FPGA needs to identify DDR, PCIE and NVME and perform logic conversion. Referring to FIG. 2, the FPGA internally includes a DDR unit, an NVMe unit, and a PCIE unit. The DDR unit is used as an input to support the DDR Process and is connected to a unified interface of a group of DRAM particles. The NVMe unit supports the NVM protocol and connects the DDR unit and the PCIE unit. The PCIE unit supports the PCIE protocol, which acts as an FPGA output and provides a PCIE interface to the PCIe device.

In this way, a set of DRAM interfaces can be converted into a PCIE interface, for example, converted to a PCIE X8 interface.

3 is a schematic diagram of a single-particle DRAM interface converted into a PCIE interface in a method for dynamically allocating memory according to an embodiment of the invention. The difference between the mode of Figure 3 and the mode of Figure 2 is that instead of changing the interface of a group of DRAM particles, the interface of a single DRAM particle is changed, both of which can achieve the same purpose.

The process of transferring the DRAM interface to the PCIE interface includes:

(Step 1) The DRAM interface is capacity-expanded by MEMORY BUFFER.

(Step 2) The input of the MEMORY controller is connected to the DRAM pellet, so the input of the MEMORY controller is a DDR unit supporting DDR (double data rate) protocol.

(Step 3) The exit of the MEMORY controller is a PCIE unit supporting PCIE (Peripheral Component Interface Express) to match the PCIE interface of the PCIE device.

In a specific implementation, the above interface conversion can be implemented by means of a wafer. The conversion of the DRAM interface to the PCIE interface is completed in the DRAM chip package, that is, the interface of the DRAM secondary package is a PCIE interface chip.

Below, the implementation details of driving the converted DRAM particles using a PCIE device are described.

After the interface conversion shown in FIG. 2 or FIG. 3 above, the DRAM particles based on the PCIE interface have been obtained. Next, the DRAM based on the PCIE interface needs to be driven, thereby sharing the memory capacity or the single server for multiple servers. A plurality of virtual machines in the server share the memory capacity to prepare.

Those skilled in the art understand that SRIOV technology is a hardware-based virtualization solution that improves performance and scalability. The SRIOV standard allows for efficient sharing of PCIE devices between virtual machines, and it is implemented in hardware to achieve I/O performance comparable to native performance. The SRIOV specification defines a new standard by which new devices are created that allow virtual machines to be directly connected to I/O devices. A single I/O resource can be shared by many virtual machines. Shared devices will provide dedicated resources and also use shared common resources. In this way, each virtual machine is accessible The only resource. Therefore, a PCIE device with SRIOV enabled and with appropriate hardware and OS support can be displayed as multiple separate physical devices, each with its own PCIE configuration space.

The two main functions in SRIOV are: (1) Physical Function (PF): PCI function to support SRIOV function, as defined in the SRIOV specification. The PF contains the SRIOV functional structure for managing SRIOV functions. PF is a full-featured PCIE feature that can be discovered, managed, and processed just like any other PCIE device. PF has fully configured resources that can be used to configure or control PCIE devices. (2) Virtual Function (VF): A function associated with a physical function. VF is a featherweight PCIE function that shares one or more physical resources with physical functions and other VFs associated with the same physical function. VF only allows configuration resources for its own behavior.

In the present invention, driving the DRAM based on the PCIE interface mainly includes the following processes:

(1) First, enable the SRIOV function of the PCIE hardware.

This feature enable indicates that this PCIE device supports the SRIOV function and can be discovered at the OS level.

(2) PF drive

Installed in the server or a driver in the management machine. This driver is mainly used to manage the correspondence between the address of each user space of the memory and the ID of the VF. That is, the PF can see the ID of all the spaces of the PCIE device. The address can be managed.

(3) VF drive

A driver installed in a virtual machine, mainly used to discover PCIE devices.

(4) Address mapping

Mainly to achieve the mapping of PCIE address, server (virtual machine) address and memory address.

(5) Completing memory address mapping when loading the driver

These address mappings are done while the driver is loading to see this PCIE space in memory.

Finally, the implementation details of deploying a DRAM pool based on the PCIE interface are introduced.

After completing the above interface conversion and PCIE interface-based DRAM driving, a memory pool composed of a plurality of DRAM particles based on PCIE interface is obtained, and the following needs to properly deploy and manage the memory pool, thereby efficiently performing memory allocation. , to achieve the purpose of multiple servers sharing the same memory pool.

The deployment of the DRAM pool based on the PCIE interface mainly includes the following processes:

(1) Multiple physical machines share the memory space of the memory pool

Multiple hosts share the storage space in this memory pool.

(2) Management unit management PF driver operation

The PF driver is running in the management unit. The function is to match the user space with the space ID of the VF and perform flexible online matching.

(3) Run the VF driver on SERVER:

After the above preparation is completed, VF will run on each server, the server Find the address space you see and you can manipulate the space.

(4) The memory space allocation on each SERVER is managed by the management unit and distributed on the flexible line.

4 is a schematic diagram of a DRAM pool deployment based on a PCIE interface in a method for dynamically allocating memory according to an embodiment of the invention.

In FIG. 4, a plurality of servers, a memory pool composed of a plurality of DRAM particles driven by PCI devices, a management unit, and a PCIE switch are shown. The server includes a PCIE module. As described above, the VF driver is run on the server, so that the server finds its own address space and operates on the address space.

The management unit is responsible for managing the memory allocation of the server to the memory pool, including three aspects: managing the memory that is already in use; releasing the used memory; and using the memory allocation. Specifically, the management unit allocates the memory capacity required for the request to the server according to the memory allocation request of the server, and after the use is completed, releases and re-allocates the server to the server with the required request.

The PCIE switch can provide multiple turns to connect multiple memory particles, so the memory space of multiple memory particles can be allocated to a specific server at one time.

Compared with the prior art, each server accesses a fixed amount of memory through a slot, not only the memory capacity is expanded by the memory buffer, but also the memory allocation can be realized as needed. For example, a server has 16 slots. If the capacity of each memory bank is 16G, even if it is fully populated, it only has 256G capacity. Suppose now that 300G memory is needed, according to The existing method only adds one server, although this can meet the memory requirements, but the additional resources of the new server are wasted. In the manner of the present invention, the memory capacity is expanded by the memory buffer, and a certain number of DRAM particles driven by the PCIE device can be set according to requirements, and the memory size according to the request can be requested when the server requests the memory allocation. Dynamically selecting the number of memory particles that satisfy the size of the requested memory, and allocating the contents of the memory particles to the server. After the server is used, the memory space is dynamically released for other needs. The server is used.

It can be seen that the present invention converts the DRAM interface to the PCIE interface by converting the interface of the DRAM particles into a PCIE interface through a programmable logic chip (FPGA) or a chip, and then transfers the PCIE device through the driver of the PCIE device. After assigning to a specific compute node, the PCIE address of this part is mapped to the memory address, thereby achieving the purpose of driving the memory of the allocated portion; the server can be allocated and managed by the memory pool. A certain amount of memory space requested, and dynamic management of memory allocation and release.

Compared with the prior art, the solution of the invention has at least the following advantages:

(1) Allocating memory on demand

Through the memory pool composed of DRAM particles driven by PCIE devices, the dynamic allocation and on-demand allocation of memory by different servers can be realized through PCIE exchange.

(2) Separation of memory and server

PCIE extension can be achieved through PCIE interface conversion. The PCIE is connected to the PCIE SLOT of the standard server, which separates the server from the memory via PCIE.

(3) Achieve large-capacity memory

Through the expansion of the memory BUFFER, the capacity can be expanded many times compared to the standard memory.

(4) Cost savings

Since the memory particles are expanded by the memory buffer and the dynamic allocation and on-demand allocation of the memory pool, the cost is lower than that of the standard memory.

(5) Maintainability enhancement

Compared to the existing standard memory, the PCIE device can be hot swapped, so the maintainability is enhanced.

Embodiments of the present invention provide an apparatus for dynamically allocating memory corresponding to the above method. Referring to FIG. 5, the apparatus includes: a request receiving unit 501, configured to receive a memory allocation request of a server; and a determining unit 502, configured to: based on the memory particles driven by the plurality of PCIE devices according to the memory allocation request Forming a memory pool, determining whether the memory pool has a memory sum of one or more free memory particles satisfying the requested memory size; and an allocating unit 503 for allocating the requested memory to the servo Device.

Preferably, the device further includes: an interface conversion unit 504, configured to buffer the DRAM interface through the memory The capacity expansion is performed; and the input of the memory controller is connected to the DRAM particles, and the conversion logic of the DDR memory process to the PCIE process is performed in the memory controller, so that the output of the memory controller is the PCIE interface, so that the memory is controlled. The output of the device is the PCIE interface.

Preferably, the device further includes: a driving unit 505 for enabling the SRIOV function of the PCIE device; installing the PF driver and the VF driver; and implementing mapping of the PCIE address, the server address and the memory address, and The address map is written to the PF driver and the VF driver.

Preferably, the device further includes: a memory pool deployment unit 506, configured to control a plurality of servers to share a memory space of the memory pool; and the PF driver is operated in the management unit, thereby The VF space ID corresponds to and matches; and the VF driver is run on each server, so that the server finds its own corresponding address space and operates.

Preferably, the determining unit 502 is further configured to: determine whether the server uses the allocated memory space; and the device further includes: a releasing unit 507, configured to release the used memory space.

Preferably, the determining unit 502 is further configured to: if it is determined that the requested memory space is not available, wait, and determine whether there is a newly released memory space; if the released memory space satisfies the requested memory requirement, Indicating an allocation slip Element 503 allocates the released memory space to the server.

In addition, the present invention also provides a system for dynamically allocating memory, the system comprising: a memory pool composed of a plurality of memory particles driven by a PCIE device; one or more servers; and FIG. 5 as previously described The device for dynamically allocating memory as shown.

In addition, the present invention also provides a memory comprising a plurality of memory particles, wherein the memory particles are driven by a PCIE device.

It should be noted that the present invention can be implemented in a combination of software and/or software and hardware, for example, using a dedicated integrated circuit (ASIC), a general purpose computer, or any other similar hardware device. In one embodiment, the software program of the present invention may be executed by a processor to implement the steps or functions described above. Likewise, the software programs (including related material structures) of the present invention can be stored in a computer readable recording medium such as a RAM memory, a magnetic or optical drive or a floppy disk and the like. Additionally, some of the steps or functions of the present invention may be implemented in hardware, for example, as a circuit that cooperates with a processor to perform various steps or functions.

Additionally, a portion of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide a method and/or solution in accordance with the present invention. Program instructions for invoking the method of the present invention may be stored in a fixed or removable recording medium and/or transmitted via a data stream in a broadcast or other signal bearing medium, and/or stored in a The working memory of the computer device in which the program instructions are run. Here, an embodiment in accordance with the present invention includes a device including a computer program for storing A memory of instructions and a processor for executing program instructions, wherein when the computer program instructions are executed by the processor, the apparatus is triggered to operate based on the foregoing methods and/or technical solutions in accordance with various embodiments of the present invention .

It is apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments are to be considered as illustrative and not restrictive, and the scope of the invention is defined by the scope of the appended claims rather than the description All changes that come within the meaning and range of equivalents of the scope of the invention are included in the invention. Any reference signs in the scope of the patent application should not be construed as limiting the scope of the claimed patent. In addition, it is to be understood that the word "comprising" does not exclude other elements or steps. A plurality of units or devices recited in the scope of the system patent application may also be implemented by a unit or device by software or hardware. The first, second, etc. words are used to denote names and do not denote any particular order.

Claims (15)

A method for dynamically allocating memory, comprising: receiving a memory allocation request of a server; and determining, according to the memory allocation request, the memory based on a memory pool composed of a plurality of storage particles driven by a standard device of the bus interface interface Whether the body pool has a memory sum of one or more free storage particles satisfies the requested memory size; if so, the requested memory is allocated to the server. The method of claim 1, wherein the storage particles comprise DRAM particles, the method further comprising: converting the DRAM interface of the DRAM particles into a PCIE interface. The method of claim 2, wherein the converting the DRAM interface of the DRAM particles into the PCIE interface comprises: expanding the capacity of the DRAM interface through the memory buffer; and connecting the input of the memory controller to the DRAM particles. In the memory controller, the conversion logic of the double-rate DDR memory process to the PCIE process is performed, so that the output of the memory controller is the PCIE interface. The method of claim 1, wherein the driving the DRAM particles by the PCIE device comprises: enabling the SRIOV function of the PCIE device; installing the physical function PF driver and the virtual function VF driver; implementing the PCIE address and the server address Mapping to the memory address and writing the address map to the PF driver and VF driver. The method of claim 4, wherein Include: arranging the memory pool: a management unit controls a plurality of servers to share the memory space of the memory pool; running the PF driver in the management unit to associate the user space with the virtual function driving space ID and Matching is performed; the virtual function driver is run on each server, so that the server finds its corresponding address space and operates. The method of any one of claims 1 to 5, further comprising: determining whether the server uses the allocated memory space, and if so, releasing the memory space. The method of claim 6, wherein if it is determined that the requested memory space is not available, the method further comprises: waiting, and determining whether there is a newly released memory space; if the released memory space is satisfied The requested memory request allocates the freed memory space to the server. An apparatus for dynamically allocating memory, comprising: a request receiving unit, configured to receive a memory allocation request of a server; and a determining unit, configured to be driven by a plurality of bus interface standard devices according to the memory allocation request a memory pool composed of memory particles, determining whether the memory pool has a memory sum of one or more free memory particles satisfying the requested memory size; and an allocation unit for allocating the requested memory to The server. The device of claim 8, wherein the memory The body particles include DRAM particles; the device further includes: an interface conversion unit for expanding the capacity of the DRAM interface through the memory buffer; and connecting the input of the memory controller to the DRAM particles, and performing DDR memory on the memory controller The conversion logic of the process to the PCIE process causes the output of the memory controller to be a PCIE interface, so that the output of the memory controller is a PCIE interface. The device of claim 8, further comprising: a driving unit for enabling the SRIOV function of the PCIE device; installing the PF driver and the VF driver; and implementing the PCIE address, the server address and the memory The mapping of the body address and the address mapping is written to the PF driver and the VF driver. The device of claim 10, further comprising: a memory pool deployment unit, configured to control a memory space of the plurality of servers sharing the memory pool; and operating the PF driver in the management unit, thereby The user space is matched and matched with the VF space ID; and the VF driver is run on each server, so that the server finds its own corresponding address space and operates. The device of any one of claims 8 to 10, wherein the determining unit is further configured to: determine whether the server uses the allocated memory space; the device further includes: a releasing unit, configured to release Use completed memory Body space. The device of claim 12, wherein the determining unit is further configured to: if it is determined that the requested memory space is not present, wait, and determine whether there is a newly released memory space; if the released memory The body space satisfies the requested memory requirement, and the allocation unit is instructed to allocate the released memory space to the server. A system for dynamically allocating memory, comprising: a memory pool composed of a plurality of memory particles driven by a bus interface standard device; one or more servers; and, Patent Application Nos. 8-13 The device for dynamically allocating memory of any of the above. A memory, wherein the memory comprises a plurality of memory particles, wherein the memory particles are driven by a busbar interface standard device.