TW201737428A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

Description

Semiconductor package

Embodiments of the present invention relate to a semiconductor package and a method of fabricating the same, and, in particular, to a semiconductor package having a specific structure of through insulator via (TIV) and a method of fabricating the same.

An integrated circuit (IC) is incorporated into many electronic devices. The integrated circuit package is capable of vertically stacking a plurality of integrated circuits in a three-dimensional (3D) package to save a horizontal area on a printed circuit board (PCB). Alternative packaging techniques (referred to as 2.5D packaging) may use an interposer to couple one or more semiconductor dies to a printed circuit board. The interposer may be formed of a semiconductor material such as germanium. A plurality of integrated circuits or other semiconductor dies (which may be heterogeneous technologies) may be mounted on the interposer.

Many devices on one or more semiconductor dies may cause electrical noise and/or electromagnetic (EM) interference by emitting electromagnetic emissions (EM emission). RF devices and inductors are examples of devices that generate electrical noise and electromagnetic interference. A source with noise (eg, a radio frequency device) can generate electrical noise in a signal carried in a conductive structure (eg, a metal lead). Electrical noise in the conductive leads can affect various other signals and devices in the package. Electrical signals with noise can cause serious problems in semiconductor packaging.

According to some embodiments of the present invention, a semiconductor package includes a first semiconductor component, an insulating layer, and a second semiconductor component. The first semiconductor component includes at least one conductive layer and at least one via layer. An insulating layer is over the first semiconductor element and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. At least one of the through-holes has a conductive core, and the conductive core comprises a copper-containing material. The second semiconductor component is over the insulating layer and includes at least one conductive layer and at least one via layer. At least one through-hole of the insulating layer couples at least one via layer of the first semiconductor element to at least one via layer of the second semiconductor element.

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of elements and arrangements are set forth below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature "above" or "on" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include An embodiment may be formed between an feature and a second feature that may provide additional features, such that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. This re-use is for the purpose of brevity and clarity and is not a representation of the various embodiments and/or configurations discussed.

In addition, for ease of explanation, space such as "beneath", "below", "lower", "above", "upper" may be used herein. The relative terms are used to describe the relationship of one element or feature to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or steps in addition to the orientation illustrated. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly accordingly. Unless specifically stated otherwise, terms relating to fit, coupling, etc. (eg, "connected" and "interconnected") mean that each structure is directly or indirectly secured through an intermediate structure. To or fit to each other's relationship, as well as a movable or rigid fit or relationship. Also, terms relating to electrical coupling, etc. (eg, "coupled", "connected", and "interconnected") mean that each structure is directly through the intermediate structure, unless explicitly stated otherwise. Or indirectly connected to each other.

In various embodiments, the semiconductor package includes at least one through insulator via (TIV) that couples the first metal layer to the second metal layer. The semiconductor package includes a first semiconductor package component and a second semiconductor package component. Each semiconductor package includes a plurality of conductive metal layers and a plurality of via layers that couple respective conductive lines in each of the plurality of conductive metal layers. A plurality of semiconductor dies are disposed in the insulating layer between the first semiconductor package and the second semiconductor package. A plurality of through insulating layer holes extend through the insulating layer and couple the first metal layer of the first semiconductor package with the first metal layer of the second semiconductor package. In some embodiments, the through-holes include an inner conductive core, an insulating layer, and an outer conductive mask. The inner conductive core comprises copper and/or a copper alloy.

FIG. 1 depicts a side view of a semiconductor package 2 having an interposer 4 in accordance with some embodiments. The interposer 4 is disposed between the substrate and one or more semiconductor dies (referred to as 2.5-dimensional semiconductor packages). In the 2.5-dimensional semiconductor package shown in FIG. 1, the interposer 4 is disposed under the first semiconductor die 6 and the second semiconductor die 8 and disposed above the package substrate 16. In some embodiments, the interposer 4 includes a base substrate (eg, germanium) having one or more passive devices formed thereon and a plurality of through-silicon vias (TSVs). The interposer 4 couples the electrical connections of the first and second semiconductor dies 6, 8 to the package substrate 16 and/or the printed circuit board 10. In some embodiments, the interposer 4 does not contain any active devices. In some embodiments, the semiconductor package 2 can include an integrated fan-out wafer level packaging (InFO-WLP). The first and second semiconductor dies 6, 8 are coupled to the first surface 12 of the interposer 4. The second surface 14 of the interposer 4 opposite the first surface 12 is directly coupled to the package substrate 16.

In some embodiments, the first and second semiconductor dies 6, 8 comprise one or more active devices. For example, in some embodiments, the first and second semiconductor dies 6, 8 may comprise a GPS die, a GPS baseband die, a processor (eg, an Advanced RISC machine) , ARM) processor) and / or any other suitable active device. Package substrate 16 may comprise any suitable substrate (e.g., ceramic material) and support one or more electrical connections between interposer 4 and printed circuit board 10. The printed circuit board 10 mechanically supports two or more integrated circuit packages (semiconductor packages) 2 and utilizes one or more conductive tracks, conductive pads, and/or conductive layers formed on the non-conductive substrate. The other features formed by the layers electrically interconnect the two or more integrated circuit packages (semiconductor packages) 2.

The package substrate 16 is bonded to the printed circuit board 10 by the solder balls 18 and bonded to the interposer 4 by the solder balls 20. The solder balls 24 bond the interposer 4 to the first semiconductor die 6 and the second semiconductor die 8. The solder balls are broadly referred to as "solder balls," but are not necessarily "ball shaped" as in the illustrated embodiment. Solder balls are also alternatively referred to as solder bumps and in various shapes in various embodiments. The solder balls physically join the respective elements together and electrically couple the electronic features of the respective elements together. In some embodiments, one or more of the interposer 4, the first, second, semiconductor dies 6, 8, the printed circuit board 10, and/or the package substrate 16 include one or more of those discussed in further detail below. A ground shielded transmission path 26 is provided.

FIG. 2 illustrates a three dimensional (3D) semiconductor package 50 in accordance with some embodiments. In the three-dimensional semiconductor package 50 as shown in FIG. 2, a plurality of semiconductor dies are stacked on top of one another and include one or more turns of vias (TSV) 70 to enable one or more upper dies to be associated with one or more The lower grains are communicative. The three-dimensional semiconductor package 50 includes a plurality of semiconductor dies, such as a central processing unit (CPU) 52, a cache memory 54, a dynamic random-access memory (DRAM), and a non-volatile memory (Non-volatile). Memory, NVM) 56, analog device 58, radio frequency device 60, power source 62, one or more sensors 64, and/or one or more inputs/outputs (input/output, I) /O) Connection 66. A plurality of through insulating layer vias (TIV) layers 68a-68e having a plurality of through insulating vias 72 are coupled to the plurality of semiconductor dies. Each semiconductor die may include one or more through-substrate vias (TSVs) 74. In some embodiments, one or more substrate vias 74 couple a first through insulating layer aperture 72a formed under the semiconductor die 54 to a second through insulating via hole 72b formed over the semiconductor die 54. In other embodiments, one or more metal layers and/or vias inside the semiconductor die can couple the first through insulating layer aperture 72a to the second through insulating layer aperture 72b. Although a particular three-dimensional semiconductor package 50 is discussed herein, it is to be understood that one or more additional dies, one or more reduced numbers of dies, one or more alternative dies, and/or One or more 2.5-dimensional semiconductor arrangements or 2-dimensional semiconductor arrangements. In some embodiments, the grounded shield transmission path includes one or more through insulating layer holes and/or one or more turns perforation/substrate vias extending through the one or more semiconductor dies.

FIG. 3 illustrates a semiconductor package 100 including a grounded shield transmission path 102 in accordance with some embodiments. The ground shield transmission path 102 couples the first semiconductor package component 101a and the second semiconductor package component 101b. The first semiconductor package component 101a includes at least one metal layer 104a, at least one via layer 106a, and a cap layer 130. In some embodiments, the first semiconductor package component 101a can comprise any suitable material, such as germanium. The second semiconductor package component 101b includes a plurality of metal layers 104b-104d, a plurality of via layers 106b-106d, and a cap layer 130. For example, in some embodiments, the second semiconductor package component 101b can be a package substrate, such as package substrate 16 discussed in connection with FIG. In some embodiments, the second semiconductor package component 101b is coupled to at least one semiconductor die 132 that includes an active device (active semiconductor device) 128. An insulating region 126 is disposed between the active device 128 and the first semiconductor package component 101a. In some embodiments, the insulating region 126 comprises a germanium material. The insulating region 126 may be a portion of the interposer between the semiconductor die 132 and the first semiconductor package component 101a and/or an insulating layer 114 (eg, an encapsulation layer) located between the semiconductor die 132 and the first semiconductor package component 101a. The part between.

The ground shield transmission path 102 extends through the insulating region 126 between the first semiconductor package component 101a and the second semiconductor package 101b. In some embodiments, the grounded shield transmission path 102 extends through the interposer, for example, using a TSV formed in an interposer (not shown). Through-insulator hole (TIV) 108 extends through insulating layer 114 and couples first via 140a formed in first via layer 106a of first semiconductor package component 101a to second via second semiconductor package component 101b The second through hole 140b formed in the via layer 106b. The through-insulator hole 108 includes a conductive material for transmitting signals from the first via 140a to the second via 140b. In some embodiments, the through-holes 108 have a cylindrical shape that extends along the longitudinal axis. Although only a single through insulating via is shown, it is contemplated that the semiconductor package 100 can include any number of through insulating vias extending through the insulating layer 114, all falling within the scope of embodiments of the present invention.

In some embodiments, the ground shield transmission path 102 includes an insulating layer 110 that surrounds an outer surface of the through insulating layer hole 108 that extends from the first via layer 106a to the second via layer 106b. The insulating layer 110 does not extend over the top or bottom surface of the insulating layer hole 108. The insulating layer 110 comprises an insulating material such as a polyimide material. In some embodiments, the insulating layer 110 extends circumferentially about a longitudinal length through the insulating layer apertures 108.

In some embodiments, the ground shield transmission path 102 includes a first semiconductor package component disposed on the insulating layer 110 and through the insulating layer hole 108 and/or disposed around the insulating layer 110 and the outer surface of the insulating layer hole 108. The 101a extends to the ground shielding layer 112 of the second semiconductor package component 101b. The grounding shield layer 112 includes a conductive material coupled to ground. The grounding shielding layer 112 is electrically isolated from the through insulating layer holes 108 by the insulating layer 110. The ground masking layer 112 isolates the insulating layer apertures 108 from radiation signals generated by one or more active devices (active semiconductor devices) 128 and/or prevents radiation signals from passing through the insulating layer holes 108. For example, when a radiation signal is generated near the insulating layer aperture 108, the radiation signal encounters the grounded shielding layer 112 before reaching the insulating layer aperture 108. The grounded shielding layer 112 drives the radiated signal to ground, thereby diverging the energy in the radiated signal and preventing the signal from being induced throughout the insulating layer aperture 108 due to the radiated signal. The ground shielding layer 112 reduces or eliminates radiation induced noise in the insulating layer holes 108 by preventing the radiation signal from being transmitted into the through insulating layer holes 108. Similarly, by preventing radiation signals from escaping through the insulating layer apertures 108, the grounded shielding layer 112 reduces or eliminates radiation induced noise caused by the through insulating layer apertures 108 and is transmitted through the insulating layer apertures 108. signal. Ground shield layer 112 is coupled to ground, such as ground formed in printed circuit board 10 coupled to semiconductor package 100. In some embodiments, the insulating layer 114 insulates the grounded shielding layer 112 from surrounding package components and/or additional through-insulator layers formed in the insulating layer 114.

In some embodiments, the grounding shield layer 112 completely surrounds each side of the insulating layer aperture 108. In other embodiments, the ground masking layer 112 is located in a layer above or below the one or more metal layers 104b-104d to limit radiation transfer between the metal layers 104b-104d. For example, in the illustrated embodiment, a continuous grounded shielding layer 120 is formed in the second semiconductor package component 101b. The continuous ground shielding layer 120 includes a conductive metal material 122 disposed in each via layer 106b-106d and/or metal layers 104b-104d of the semiconductor package component 101b and located in each pass of the semiconductor package component 101b. Between the aperture layers 106b-106d and/or the metal layers 104b-104d. In some embodiments, the conductive metal material 122 extends through the metal layers 104b-104d of the second semiconductor package component 101b in a substantially vertical direction and extends through the via layers 106b-106d in a substantially horizontal direction, but should The conductive metal material 122 can extend in any direction in any of the various layers of the semiconductor package component 101b. In some embodiments, in addition to the locations at which the vias 140b-140d couple the metal layers 104b-104d, the continuous ground masking layer 120 and the conductive metal material 122 isolate each of the metal layers 104b-104d. The continuous ground masking layer 120 is coupled to ground through one or more package components, such as a printed circuit board (not shown). The continuous ground shielding layer 120 prevents the radiation signal from being transmitted between the metal layers 104b-104d of the second semiconductor package component 101b.

In some embodiments, the continuous grounded shielding layer 120 is coupled to the grounded shielding layer 112 of the grounded shielding transmission path 102 and/or to the grounded shielding layer 112a. The continuous grounding shield layer 120 and the grounding shielding layers 112, 112a are used to cause the following components and one or more of the radiation signals generated by the semiconductor package 100 within the semiconductor package 100 (eg, signals generated by the active semiconductor device 128 and/or Signal transmission via signal paths 146a-146d) insulation: transmission paths, such as transmission paths (signal paths) 146a-146d formed in metal layers 104b-104d and through insulating layer holes 108; active devices, such as active semiconductors Device 128; and/or other portions of semiconductor package 100. For example, in some embodiments, the ground conductive metal material (conductive metal material) 122 disposed in the second via layer 106b and the third via layer 106c of the second semiconductor package component 101b will be the first metal layer 104b and Radiation signal isolation. Similarly, the grounded conductive metal material (conductive metal material) 122 disposed in the third via layer 106c and the fourth via layer 106d isolates the second metal layer 104c from the radiation signal.

In some embodiments, the grounded shielding layer 112a is centered with the active semiconductor device 128 coupled to the semiconductor package component 101b. The grounded shielding layer 112a blocks the active semiconductor device 128 from transmitting and/or receiving radiation signals. For example, in some embodiments, active semiconductor device 128 is a RF emitting device. The grounding shield layer 112a is centered at the radio frequency emitting device to prevent radio frequency signal transmission from the device from interfering with other components of the semiconductor package 100 (e.g., through the insulating layer apertures 108). The grounding shield layer 112a can be coupled to ground through one or more package components, such as a printed circuit board (not shown). Active semiconductor device 128 can include any suitable active semiconductor device that can generate radiation transmission and/or be sensitive to received radiation transmission. Other embodiments of the semiconductor package for one or more through-holes can be referred to the novel high-isolation for the three-dimensional integrated circuit, filed on March 22, 2016, Serial No. 15/076,976. US Patent Application for COAXIAL THROUGH VIA WITH NOVEL HIGH ISOLATION CROSS COUPLING METHOD FOR 3D INTEGRATED CIRCUITS. The entire disclosure of the U.S. Patent Application is incorporated herein by reference.

In some embodiments, the through-insulation layer apertures 108 comprise a conductive material that has a relatively short interconnect length and time delay compared to conventional via connections. For example, the through-holes 108 may comprise copper (Cu) and/or a copper-based alloy. In some embodiments, a portion of the grounded shielding layer 112 that penetrates the insulating layer apertures 108 is formed from the same copper and/or copper-based alloy.

In some embodiments, a plurality of solder bumps 134 are coupled to metal contacts formed in an under bump metallurgy (UBM) layer 156. In some embodiments, the contacts of one or more surface mount devices (SMDs) are coupled to metal contacts (not shown) formed in the under bump metallurgy (UMB) layer 156. The contacts of the solder bumps 134 and/or surface mount devices are used to couple the semiconductor package 100 to one or more additional circuit components (eg, circuit boards) using surface-mount technology.

FIG. 4 illustrates a flow diagram of a method 300 of forming a semiconductor package 400 (FIGS. 5-24) in accordance with some embodiments. 5 through 23 illustrate various cross-sectional views of semiconductor package 400 during fabrication, in accordance with some embodiments. At step 302, a first buffer layer 402 is deposited on carrier 404 as shown in FIG. The first buffer layer 402 can comprise any suitable material, such as polyimine, polybenzoxazole (PBO), and/or any other suitable material. The carrier 404 is a rigid material to support the semiconductor package 400 during formation. For example, in some embodiments, carrier 404 includes glass and/or other inert material to support semiconductor package 400 during formation but does not interact with any of the components of semiconductor package 400.

In some embodiments, a photothermal conversion (LTHC) release layer 406 is formed between the carrier 404 and the first buffer layer 402. The photothermal conversion release layer 406 is used to release the semiconductor package 400 from the carrier 404 after the semiconductor package 400 is completely formed and/or partially formed. For example, in some embodiments, a laser and/or other concentrated light source is applied to the photothermal conversion release layer 406 to heat the photothermal conversion release layer 406 and separate the semiconductor package 400 from the carrier 404. .

At step 304, a first metal layer or copper redistribution layer 408 (Cu RDL, referred to herein as a first metal layer) is formed over at least a portion of the first buffer layer 402. As shown in FIG. 6, the first metal layer 408 can include a plurality of metal traces 408a, 408b separated by one or more gaps. For example, in some embodiments, the first metal layer 408 can be deposited by a reticle that defines the one or more metal traces 408a, 408b, although it is understood that the first metal layer 408 can also be deposited as a solid layer and used. One or more etching processes and/or one or more reticle to remove portions of the solid layer. The first metal layer 408 can be deposited to any suitable depth (eg, any other suitable depth of 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, and/or greater than 9 microns or less than 5 microns). In some embodiments, the first metal layer 408 is a backside (B/S) metal layer of the semiconductor package 400. The backside metal layer is used to couple the semiconductor package 400 to one or more circuit elements.

At step 306, as shown in FIG. 7, a through-insulation layer via photoresist patterning layer (TIV) is deposited over the first metal layer 408 to define one or more through-insulation layer forming holes 412a, 412b. The through-insulation layer forming holes 412a, 412b have a predetermined diameter and a predetermined depth (for example, depositing the through-insulation via-hole photoresist patterning layer 410 to a predetermined height). For example, in some embodiments, the through-insulation layer forming holes 412a, 412b each have a diameter of about 120 microns and a depth of about 200-250 microns, but it is understood that the through-insulation layer forming holes 412a, 412b can also have a larger / or smaller diameter and / or depth. In some embodiments, the through-silicon via photoresist patterning layer 410 is deposited by defining one or more reticle through the insulating layer forming apertures 412a, 412b.

At step 308, a seed layer 414 is conformally deposited over the insulating layer via photoresist pattern 410. In some embodiments, such as the embodiment shown in FIG. 8, seed layer 414 comprises a titanium-copper (Ti-Cu) material. The seed layer 414 is deposited to a thickness sufficient to produce a predetermined conductivity. For example, in some embodiments, the Ti/Cu seed layer 414 can be deposited to a predetermined thickness (e.g., a Ti thickness of 1000 Å and a Cu thickness of 5000 Å), although it is understood that any other suitable conductivity can be selected.

At step 310, a conductive metal layer 416 is deposited over the seed layer 414 as shown in FIG. In some embodiments, the conductive metal layer 416 is deposited using one or more electrochemical plating (ECP) processes. For example, the conductive metal layer 416 can be a copper layer deposited by electrochemical plating. The conductive metal layer 416 is deposited to a thickness sufficient to fill each of the through-insulation layer forming holes 412a, 412b defined in advance. For example, in some embodiments, conductive metal layer 416 can be deposited to a depth of about 120 microns. In some embodiments, a portion of conductive metal layer 416 extends over insulating layer forming apertures 412a, 412b and over insulating layer via photoresist patterning layer 410.

At step 312, semiconductor package 400 is planarized to remove a portion of conductive metal layer 416 that extends over insulating layer via photoresist pattern 410, as shown in FIG. The portion of conductive metal layer 416 can be removed using any suitable process, such as chemical mechanical planarization (CMP). In some embodiments, the semiconductor package 400 is planarized to expose conductive material deposited within the through insulating layer forming holes 412a, 412b formed through the insulating layer via photoresist patterning layer 410.

At step 314, the through-insulation via-resist patterning layer 410 is removed. As shown in FIG. 11, removing the through-via via photoresist pattern 410 leaves a plurality of conductive pillars 418a, 418b. The through insulation may be removed using any suitable process, such as an ozone plasma ashing process, wet acid cleaning, and/or any other suitable process, and/or combinations thereof. Layer via photoresist patterning layer 410. The conductive pillars 418a, 418b extend a predetermined distance above the first buffer layer 402. For example, the conductive pillars 418a, 418b may extend over the conductive layer (first metal layer) 408 by about 120 microns, although it is understood that the conductive pillars 418a, 418b may also have a larger and/or smaller height. In some embodiments, the height of the conductive pillars 418a, 418b corresponds to the depth of the through insulating layer forming holes 412a, 412b formed through the insulating layer via photoresist patterning layer 410.

At step 316, as shown in FIG. 12, an insulating layer 420 is conformally deposited over portions of the semiconductor package 400. The insulating layer 420 can be any suitable high-k insulating layer 420 deposited using any suitable process. In various embodiments, insulating layer 420 comprises one or more of the following: a ceramic material, a dielectric material, a polymeric material, any other suitable material, and/or any combination thereof. For example, in some embodiments, a low temperature (eg, 180 ° C) plasma enhanced chemical vapor deposition (PECVD) dielectric is deposited. Plasma assisted chemical vapor deposition of dielectrics may include but not limited to silicon-based dielectric _{(e.g., SiN x, SiO 2, SiO} x N y) and / or any other suitable dielectric. In other embodiments, the insulating layer 420 is a polymeric insulating material such as epoxy (Epoxy), polybenzoxazole, polyimine (PI), benzocyclobutene (BCB), and/or any other Suitable polymer insulation material.

At step 318, a coaxial ground seed layer 422 is conformally deposited over insulating layer 420 as shown in FIG. In some embodiments, the coaxial ground seed layer 422 can be deposited using any suitable deposition process, such as sputtering. The coaxial ground seed layer 422 comprises a conductive material such as copper (Cu), a copper alloy, and/or any other suitable conductive material. The coaxial ground seed layer 422 can comprise any suitable material, such as a material comprising Ti/Cu having a thickness of 1/3 KÅ.

At step 320, as shown in FIG. 14, a photoresist layer 424 is deposited over the first portion of the coaxial ground seed layer 422. The photoresist layer 424 may comprise any suitable photoresist material, such as poly(methyl methacrylate) (PMMA), poly(methyl glutarimide (PMGI)). A phenol formaldehyde resin, and/or any other suitable photoresist layer 424. The photoresist layer 424 is deposited and the photoresist layer 424 is exposed to a light source to solidify or develop the photoresist material. In some embodiments, A photoresist layer 424 is deposited over portions of the coaxial ground seed layer 422 that define ground shields for one or more coaxial through-insulator apertures. The photoresist layer 424 can be coated or deposited using any suitable process.

At step 322, as shown in FIG. 15, the second portion of the coaxial ground seed layer 422 that is not covered by the photoresist layer 424 is removed. The second portion of the coaxial ground seed layer 422 can be removed using any suitable method, such as a wet-etchant process as is well known in the art. Photoresist layer 424 protects the first portion of coaxial ground seed layer 422 during the wet etchant process.

At step 324, as shown in FIG. 16, the photoresist layer 424 is removed. The photoresist layer 424 can be removed using any suitable process, such as an ozone plasma ashing process, a wet acid cleaning process, and/or any other suitable process, and/or combinations thereof. After removing the photoresist layer 424, a portion of the semiconductor package 400 includes a plurality of coaxial connectors 426 having an inner conductive layer (conductive metal layer) 416, an insulating layer 420, and an outer conductive layer (coaxial Grounded seed layer) 422. In some embodiments, the outer conductive layer (coaxial ground seed layer) 422 includes a grounded shielding layer.

At step 326, a plurality of semiconductor dies (active semiconductor dies or devices) 428a, 428b are coupled to a portion of semiconductor package 400. The semiconductor die is pre-formed into a semiconductor die containing one or more active semiconductor components. As shown in FIG. 17, semiconductor die 428a, 428b are coupled or bonded to first metal layer 408. In some embodiments, the semiconductor die 428a, 428b each comprise a die attach film (DAF) layer 430, a germanium layer 432 comprising one or more active components, an aluminum contact pad 434, and a metal via 436, however, it is understood that the semiconductor die 428a, 428b can also have any suitable number and/or any suitable type of layer. In some embodiments, the upper portion of each semiconductor die 428a, 428b (eg, metal via 436) is substantially parallel to the top of the coaxial connector 426, although it is understood that the height of the semiconductor die 428a, 428b can also be extended. Up to and/or below the top of the coaxial connector 426.

At step 328, as shown in FIG. 18, an over molding layer 438 is deposited over portions of the semiconductor package 400. The overmold layer 438 is used to fill one or more gaps between each of the semiconductor die 428a, 428b and each of the plurality of coaxial connectors 426. In some embodiments, the overmold layer 438 comprises an insulating (or non-conductive) material. For example, in various embodiments, overmold layer 438 can comprise an insulating material, such as a polymeric material. In some embodiments, the overmold layer 438 is deposited to a depth sufficient to fill the gap between each of the semiconductor dies 428a, 428b and/or each of the coaxial connectors 426. For example, in some embodiments, overmold layer 438 is deposited to a thickness sufficient to extend over the top of semiconductor die 428a, 428b and/or coaxial connector 426 by about 50 microns.

At step 330, as shown in FIG. 19, a portion of the semiconductor package 400 is planarized to remove a portion of the overmold layer 438 disposed over the semiconductor die 428a, 428b. The portion of overmold layer 438 can be removed using any suitable process (eg, a polishing process performed prior to the chemical mechanical planarization process, and/or any other suitable process). In some embodiments, the upper portion of the insulating layer 420 of each of the coaxial connectors 426 and the upper portion of the outer conductive layer (coaxial ground seed layer) 422 are removed to expose the inner conductive layer (conductive metal layer) 416. A portion of each of the semiconductor dies 428a, 428b, such as a portion of the aluminum contact pads 434, may also be removed.

At step 332, a via insulating layer 440 is deposited over portions of the semiconductor package 400 as shown in FIG. The via insulating layer 440 includes an insulating material, such as polyimide, polybenzoxazole (PBO), and/or any other suitable material for isolating each of the semiconductor dies 428a, 428b and the coaxial connector 426. A plurality of linear vias 442 are formed in the via insulating layer 440 to provide electrical connection points for each of the semiconductor dies 428a, 428b and the coaxial connectors 426. The linear vias 442 can comprise any suitable electrically conductive material, such as copper and/or copper alloys. In some embodiments, the via insulating layer 440 includes an overhang 444 at each of the coaxial connectors 426 to isolate the inner conductive material (conductive metal layer) 416 and the outer conductive ground shielding layer (coaxial ground crystal Seed layer) 422. The via insulating layer 440 can be deposited to any suitable depth, such as a depth equal to or less than about 4.5 microns, although it is understood that the via insulating layer 440 can also have any suitable depth greater than or less than 4.5 microns.

At step 334, one or more additional layers (eg, one or more via layers and/or conductive layers) are formed on portions of semiconductor package 400. For example, as shown in FIGS. 21 and 22, via insulating layers 446, 448 and/or conductive layers 450a-450c are formed over via insulating layer 440. An additional via insulating layer (polybenzoxazole layer) 446 includes a plurality of vias 452a-452c that couple coaxial connector 426 and semiconductor die 428a, 428b to conductive layer 450a . In some embodiments, additional conductive layers (eg, conductive layers 450a-450c) are used to couple two or more elements of semiconductor package 400 together. For example, in the embodiment shown in FIG. 21, conductive layer 450a couples first semiconductor die 428a to second semiconductor die 428b. In some embodiments, conductive layers 450a-450c are used to couple one or more components of semiconductor package 400 to external connection points. For example, as shown in FIG. 23, first semiconductor die 428a and second semiconductor die 428b are coupled to connection pads 456 by a plurality of conductive lines 454a-454c formed in a plurality of conductive layers 450a-450c. It will be appreciated that any number of via layers 446, 448 and/or conductive layers 450a-450c may be deposited on portions of semiconductor package 400.

At step 336, as shown in FIG. 21, solder balls 458 are formed at one or more connection points of the semiconductor package. For example, in some embodiments, solder balls are formed on the connection pads 456. Solder balls 458 can comprise any suitable material, such as tin (Sn), silver (Ag), copper (Cu), lead (Pb), and/or combinations thereof.

At step 338, a light source is applied to the photothermal conversion release layer 406 to heat the photothermal conversion release layer 406, thereby separating the semiconductor package 400 from the carrier (glass carrier) 404. The light source can be any suitable light source, such as a laser or other directional light source. FIG. 24 illustrates the fabricated semiconductor package 400 after being removed from the glass carrier 404.

In various embodiments, a semiconductor package is disclosed. The semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor component includes at least one conductive layer and at least one via layer. The insulating layer is over the first semiconductor element and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one through insulating layer hole has a conductive core, and the conductive core includes a copper-containing material. The second semiconductor component is above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one through-hole layer couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

In some embodiments, the at least one through insulating layer aperture includes a first insulating layer disposed about the conductive core and a grounded shielding layer disposed about the first insulating layer.

In some embodiments, the ground shielding layer comprises a copper-containing material.

In some embodiments, the insulating layer comprises a low temperature plasma assisted chemical vapor deposition (PECVD) dielectric.

In some embodiments, the plasma assisted chemical vapor deposition dielectric comprises a lanthanide dielectric.

In some embodiments, the at least one through insulating layer aperture further includes a second insulating layer disposed about the grounded shielding layer.

In some embodiments, the second insulating layer comprises a polymeric insulating material selected from the group consisting of polybenzoxazole (PBO), polyimine (PI), and benzocyclobutene (BCB).

In some embodiments, the copper-containing material comprises a titanium/copper (Ti/Cu) material.

In some embodiments, the insulating layer includes an interposer that includes one or more active semiconductor devices.

In various embodiments, a method of forming a semiconductor package is disclosed. The method includes at least the following steps. A first conductive layer is formed on the substrate. An insulating layer is formed over the first conductive layer. A via layer is formed over the insulating layer. A second conductive layer is formed over the via layer. The first conductive layer includes at least one conductive trace. The insulating layer includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The through insulating layer aperture has a conductive core coupled to the at least one conductive trace of the first conductive layer. The via layer includes at least one conductive via extending from a first side to a second side of the via layer, and the via layer is coupled to the at least one through insulating via of the insulating layer. The second conductive layer includes at least one conductive trace coupled to the at least one conductive via of the via layer.

In some embodiments, forming the insulating layer includes at least the following steps. Depositing a through hole insulating photoresist layer (TIV hole photoresist layer) on the first via layer, wherein the through insulating via via photoresist layer defines at least one through via hole (TIV hole), the at least one through The insulating layer via is at least partially over the at least one conductive via of the first via layer. Depositing a first conductive copper-containing material on the through-insulation via-hole photoresist layer, wherein the first conductive copper-containing material is deposited to a depth sufficient to fill the at least one through-via via. The through-insulation via-hole photoresist layer is removed such that the pillars of the first conductive copper-containing material define the at least one conductive core penetrating through the holes of the insulating layer.

In some embodiments, forming the insulating layer further includes the following steps. Depositing a first insulating layer on the pillar of the first conductive copper-containing material. Depositing a second conductive copper-containing material on the first insulating layer, wherein the pillar, the first insulating layer, and the second conductive copper-containing material of the first conductive copper-containing material define the at least one Through the hole of the insulation layer.

In some embodiments, depositing the first insulating layer comprises depositing a low temperature plasma assisted chemical vapor deposition (PECVD) dielectric material.

In some embodiments, forming the insulating layer includes performing a planarizing step to expose the conductive core.

In some embodiments, further comprising forming a second insulating layer on the at least one through insulating layer via.

In some embodiments, the second insulating layer comprises a material selected from the group consisting of polybenzoxazole (PBO), polyimine (PI), and benzocyclobutene (BCB).

In some embodiments, further comprising coupling at least one active semiconductor die to the insulating layer.

In some embodiments, the following steps are also included. A connection pad is formed over the second conductive layer, wherein the connection pad is coupled to the at least one conductive trace formed in the second conductive layer. A solder ball is formed on the connection pad.

In various embodiments, a semiconductor package is disclosed. The semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor component includes a first conductive layer and a first via layer. The first conductive layer has at least one conductive trace. The first via layer has at least one conductive via, the at least one conductive via being coupled to the at least one conductive trace of the first conductive layer. The insulating layer is vertically above the first semiconductor element and includes an active semiconductor device, a through insulator via (TIV), and an insulating material. The through insulating layer aperture extends from a first side of the insulating layer to a second side of the insulating layer. The through insulating layer aperture includes a conductive core, an insulating layer at least partially surrounding the conductive core, and a grounded shielding layer surrounding at least the insulating layer. The conductive core is coupled to the at least one conductive via of the first via layer at a first end of the through-insulator hole. The conductive core and the ground shielding layer each comprise a copper-containing material. The insulating material is located between the active semiconductor device and the through insulating layer hole. The second semiconductor component is located above the insulating layer and includes a second via layer and a second conductive layer. The second via layer includes at least one conductive via that is coupled to the conductive core through the insulating via at a second end of the through insulating via. The second conductive layer includes at least one conductive trace coupled to the at least one conductive via of the second via layer.

In some embodiments, the first copper-containing material is a titanium-copper material.

The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the invention. It will be apparent to those skilled in the art that the present invention can be readily utilized as a basis for designing or modifying other processes and structures to perform the same objectives and/or implementations as those described herein. The same advantages are given. A person skilled in the art will recognize that the equivalents of the present invention are not to be construed as being limited to the spirit and scope of the invention. .

2‧‧‧Semiconductor package
4‧‧‧Intermediary
6‧‧‧First semiconductor die
8‧‧‧Second semiconductor die
10‧‧‧Printed circuit board
12‧‧‧ first surface
14‧‧‧ second surface
16‧‧‧Package substrate
18, 20, 24, 458‧‧‧ solder balls
26, 102‧‧‧ Grounding shield transmission path
50‧‧‧Three-dimensional semiconductor package
52‧‧‧Central Processing Unit
54‧‧‧ Cache memory
56‧‧‧Dynamic random access memory/non-volatile memory
58‧‧‧ analog device
60‧‧‧RF devices
62‧‧‧Power supply
64‧‧‧Sensor
66‧‧‧Input/output connections
68a, 68b, 68c, 68d, 68e‧‧‧ through the insulation hole
70‧‧‧矽 piercing
72‧‧‧through insulation hole
72a‧‧‧First through insulation hole
72b‧‧‧Second through insulation hole
74‧‧‧Substrate perforation
100‧‧‧Semiconductor package
101a‧‧‧First semiconductor package components
101b‧‧‧Second semiconductor package components
104a, 104d‧‧‧ metal layer
104b‧‧‧First metal layer
104c‧‧‧Second metal layer
106a‧‧‧First via layer
106b‧‧‧Second via layer
106c‧‧‧ third via layer
106d‧‧‧fourth via layer
108‧‧‧through insulation hole
110, 114‧‧‧ insulation
112, 112a‧‧‧ Grounding shield
120‧‧‧Continuous grounding shield
122‧‧‧ Conductive metal materials
126‧‧‧Insulated area
128‧‧‧Active device
130‧‧‧Top cover
132‧‧‧Semiconductor grains
134‧‧‧ solder bumps
140a‧‧‧first through hole
140b‧‧‧second through hole
146a, 146b, 146c, 146d‧‧‧ signal path
156‧‧‧Under bump metal layer
300‧‧‧ method
302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 334, 336 ‧ ‧ steps
400‧‧‧Semiconductor package
402‧‧‧First buffer layer
404‧‧‧ Carrier Board
406‧‧‧Photothermal conversion release layer
408‧‧‧First metal layer
408a, 408b‧‧‧metal trace
410‧‧‧through insulating layer through-hole photoresist patterned layer
412a, 412b‧‧‧through insulating layer forming holes
414‧‧‧ seed layer
416‧‧‧ Conductive metal layer
418a, 418b‧‧‧ conductive column
420‧‧‧Insulation
422‧‧‧ coaxial grounded seed layer
424‧‧‧Photoresist layer
426‧‧‧ coaxial connector
428a, 428b‧‧‧ semiconductor die
430‧‧‧ die bonding film
432‧‧‧矽
434‧‧‧Aluminum contact pads
436‧‧‧Metal through hole
438‧‧‧ overmolded layer
440, 446, 448‧‧‧ through-hole insulation
442‧‧‧With linear through holes
444‧‧‧Overhanging
450a, 450b, 450c‧‧‧ conductive layer
452a, 452b, 452c‧‧‧through holes
454a, 454b, 454c‧‧‧ conductive lines
456‧‧‧Connecting mat

1 depicts a side view of a 2.5 dimensional semiconductor package including an interposer, in accordance with some embodiments. 2 depicts a side view of a three-dimensional (3D) semiconductor package in accordance with some embodiments. 3 illustrates a 2.5 dimensional semiconductor package including an interposer having a grounded shielded transmission path, in accordance with some embodiments. 4 illustrates a flow chart of a method of forming a semiconductor package including one or more through-silicon via connections (TIV-Cu connections), in accordance with some embodiments. FIG. 5 illustrates a partial semiconductor package having a first buffer layer and a light-to-heat conversion (LTHC) layer formed on a carrier, in accordance with some embodiments. 6 illustrates a portion of a semiconductor package of FIG. 5 with a first metal layer deposited thereon, in accordance with some embodiments. FIG. 7 illustrates a portion of the semiconductor package of FIG. 6 with a through-insulation through-silicon via photoresist patterning layer (TIV hole photoresist patterning layer) deposited thereon, in accordance with some embodiments. 8 illustrates a portion of a semiconductor package of FIG. 7 with a titanium/copper (Ti/Cu) seed layer deposited thereon, in accordance with some embodiments. 9 illustrates a portion of a semiconductor package of FIG. 8 having a copper (Cu) layer deposited in one or more through-insulator vias (TIV holes), in accordance with some embodiments. FIG. 10 illustrates a portion of the semiconductor package of FIG. 9 after a chemical-mechanical planarization process, in accordance with some embodiments. 11 illustrates a portion of a semiconductor package of FIG. 10 after a photoresist removal process, in accordance with some embodiments. Figure 12 illustrates a portion of the semiconductor package of Figure 11 with an insulating layer deposited thereon, in accordance with some embodiments. Figure 13 illustrates a portion of the semiconductor package of Figure 12 with a ground shielding layer deposited thereon, in accordance with some embodiments. 14 illustrates a portion of a semiconductor package of FIG. 13 with a coaxial photoresist patterning layer deposited thereon, in accordance with some embodiments. Figure 15 illustrates a portion of the semiconductor package of Figure 14 after a wet etching process, in accordance with some embodiments. 16 illustrates a portion of the semiconductor package of FIG. 15 after a photoresist removal process, in accordance with some embodiments. 17 illustrates a portion of a semiconductor package of FIG. 16 coupled with a first semiconductor die and a second semiconductor die, in accordance with some embodiments. 18 illustrates a portion of the semiconductor package of FIG. 17 with an over molding layer deposited thereon, in accordance with some embodiments. 19 illustrates a portion of a semiconductor package of FIG. 18 after a chemical-mechanical planarization (CMP) process, in accordance with some embodiments. 20 depicts a portion of the semiconductor package of FIG. 19 with a layer of polybenzoxazole (PBO) deposited thereon, in accordance with some embodiments. 21 illustrates a portion of a semiconductor package of FIG. 20 having a plurality of conductive layers and a polybenzoxazole layer, in accordance with some embodiments. 22 illustrates a portion of a semiconductor package of FIG. 21 having a plurality of conductive layers and vias that couple a first semiconductor die and a second semiconductor die to a connection pad, in accordance with some embodiments. 23 illustrates a portion of a semiconductor package of FIG. 22 having solder bumps formed on a connection pad in accordance with some embodiments. 24 illustrates the semiconductor package of FIG. 23 separated from a glass carrier in accordance with some embodiments.

400‧‧‧Semiconductor package

402‧‧‧First buffer layer

408a, 408b‧‧‧metal trace

426‧‧‧ coaxial connector

428a, 428b‧‧‧ semiconductor die

440, 446, 448‧‧‧ through-hole insulation

442‧‧‧With linear through holes

450a, 450b, 450c‧‧‧ conductive layer

452a, 452b, 452c‧‧‧through holes

454a, 454b, 454c‧‧‧ conductive lines

456‧‧‧Connecting mat

458‧‧‧ solder balls

Claims (1)

A semiconductor package comprising: a first semiconductor component comprising at least one conductive layer and at least one via layer; an insulating layer over the first semiconductor component, the insulating layer comprising an extension from a first side of the insulating layer At least one through the insulating layer aperture to the second side of the insulating layer, wherein the through insulating layer aperture comprises a conductive core, the conductive core comprises a copper-containing material; and the second semiconductor component comprises at least one conductive layer and at least a via layer, wherein the second semiconductor component is over the insulating layer, and wherein the at least one through insulating via couples the at least one via layer of the first semiconductor component to the second The at least one via layer of the semiconductor component.