TW201735483A - High voltage transmit/receive switch with standard BCD process - Google Patents

Abstract

An analog transmit/receive switch and voltage detection circuit that do not require depletion mode devices are provided. The switch may be configured to operate in a receive mode and a protection mode. The voltage detection circuit may be coupled to the switch and may be configured to measure a potential difference between two terminals of the switch. The switch and the voltage detection circuit may not include any depletion mode devices.

Description

High voltage transmission/reception switcher with standard BCD process

The present invention generally relates to an analog switcher and voltage detection circuit that does not require a depletion mode device.

Related application cross-reference

The present application claims the benefit of U.S. Provisional Patent Application Serial No. 62/311,473, the entire disclosure of which is incorporated herein by reference.

According to the related prior art, a two-terminal transmit/receive switch can pass a small analog signal with a fixed low resistance and quickly turn itself off when the occurrence of a high voltage is detected. The switch can be connected between an ultrasonic sensor and an input of a low noise, low voltage receiving amplifier, and can protect the input from high voltage transmission signals in the ultrasonic device without any control signals and Help with high voltage power supplies.

A detailed block diagram of a transmit/receive switch in accordance with the related prior art is shown in FIG. The basic block of the switch is a 4-transistor butterfly (symmetric) switch and the voltage detection circuit.

The switch of the two-terminal high voltage transmission/reception protection has a fixed resistance characteristic when a small signal, for example, within about ±300 millivolts is applied. When high voltage, For example, an amplitude greater than 2 volts, when present, the voltage detection circuit will clamp one of the two depletion mode PMOS transistors to cut off the current path of the symmetrical switch. The current-voltage characteristics of the transmitting/receiving switch of Fig. 1 are shown in Fig. 2.

A switch according to the related prior art consists of a depletion mode high voltage NMOS transistor and a depletion mode PMOS transistor, which is nominally turned on to pass a small analog signal and detect the presence of a high voltage. Thus, while certain devices are capable of fabricating these related prior art switchers, these switches impose problems with other BCD process wafer foundries that do not provide any form of depletion device.

In an attempt to implement an analog switcher without high voltage supply, the bootstrap and translinear loop techniques are used in the exemplary embodiment of FIG. The translinear loop can adjust the VGS of the symmetrical switch, and given the M1, M2, and M5 system size matches, the conductance of the mate is matched to the transconductance of M5.

Thus, a transmit/receive switch in accordance with one or more exemplary embodiments of the present disclosure may be capable of passing a small analog signal and blocking ±90 volts without a high voltage supply, and without any depletion or thick oxide devices, and Therefore, it can be transferred to different BCD processes.

According to one aspect of the exemplary embodiment, there is provided an apparatus, comprising: a switch configured to operate in a receiving mode and a protection mode, and a voltage detecting circuit connected to the switch, The voltage detection circuit measures the potential difference between the two terminals of the switch. The switch and the voltage detection circuit may not include any depletion mode devices.

The switch can be constructed to automatically switch between the receiving mode and the protection mode without a control signal. The switch may also include a first NMOS transistor and a second NMOS device The crystals, whose sources are extremely coupled together. The switch may not contain any PMOS transistors.

The device may also include a third and further transistor that is configured to close the switch. The source terminals of the third transistor and the fourth transistor may be coupled to the source terminals of the first NMOS transistor and the second NMOS transistor, and the 汲 terminals of the third transistor and the fourth transistor may be coupled To the gate terminals of the first NMOS transistor and the second NMOS transistor.

The voltage detection circuit can include first and second variable resistors that are configured to measure a potential difference between the two terminals of the switch. The gate terminal of the third transistor may be coupled to the first variable resistor, and the gate terminal of the fourth transistor may be coupled to the second variable resistor. The switch can be configured to switch between the receiving mode and the protection mode according to a threshold voltage of the third transistor or a threshold voltage of the fourth transistor. The third and fourth transistors may be NMOS transistors. In the receiving mode, the resistance of the switch can be substantially fixed. In protection mode, the switch can operate as a fixed current source.

R1, R2‧‧‧Variable Resistors

M1B, M2B, M5B‧‧‧ current mirror

M6, M7‧‧‧ low voltage NMOS switcher

M1A, M2A‧‧ symmetrical switcher

1 shows a transmitting/receiving switch according to the related art; FIG. 2 shows a current-voltage characteristic of the transmitting/receiving switch shown in FIG. 1; FIG. 3 shows the use of a trans-linear circuit according to an exemplary embodiment. Analog converter circuit; Figure 4 shows a transmit/receive switch in accordance with an exemplary embodiment.

The following exemplary embodiments will be described in detail with reference to the accompanying drawings, in which Exemplary embodiments can be The form is embodied without being limited to the exemplary embodiments presented herein. For the sake of brevity, the description of the well-known parts is omitted.

Referring to Figure 4, an exemplary embodiment of the present disclosure is shown that includes an analog switch and a voltage detection circuit. Typically, this analog switch has two modes of operation: 1) receive mode and 2) protected mode. In the receive mode, the resistance of the analog switcher is quite fixed due to the cross-linear loop technique. Distortion is minimized and is limited only by stray capacitance for any AC ground path, which also attenuates the signal and introduces electrical noise. In the protection mode, the combined switcher protects the low-voltage, low-noise receive amplifier against positive and negative high-voltage pulses by converting itself into a high-impedance fixed current source. The DC current through the combined switch is defined by current mirrors M1B, M2B and M5B. The combined switch automatically switches between the receive mode and the protected mode without a control signal.

A pair of low voltage NMOS switches M6 and M7 are added to turn off the symmetrical switches M1A and M2A. Unlike the previous design, there is no need for a PMOS switch in series, so that the symmetric switches M1A and M2A can be much smaller than M1 and M2 of FIG. 1, and in the exemplary embodiment of FIG. 4, the stray capacitance is also much smaller. In addition to the way the symmetrical switcher is cut off, the voltage detection circuit consisting of M1B, M2B, R1 and R2 is similar to the voltage detection circuit of Figure 1, except for M1B and M2B, as shown in Figure 4. Other transistors are reinforced devices with low voltage gate oxides. The tip voltage between the receive mode and the protection mode is just the threshold voltage of M6 or M7 multiplied by the variable resistor ratio of R1 or R2. If the variable resistor is center tapped and the threshold voltage of M6 and M7 is 1 volt, the tip voltage will be approximately 4 volts.

The transmission/reception switch according to the above exemplary embodiment does not require a depletion mode device. Cross-linear loop and bootstrap operation to achieve fixed symmetry of the switch in receive mode On resistance. Thus, the exemplary embodiment shown in FIG. 4 can eliminate harmonic distortion due to signal-related on-resistance. The voltage detection circuit of the exemplary embodiment of FIG. 4 can measure the potential difference between the two switch terminals having a pair of resistors R1 and R2. The scaled-down voltage at the variable resistor taps of R1 and R2 adjusts the tip voltage between the receive mode and the protection mode, which is only one function of the M6 or M7 threshold voltage. The transmit/receive switch of the exemplary embodiment can be easily implemented in all nominal BCD processes by the flexibility of the tip voltage adjustment and without any depletion mode or thick oxide device.

The inventive concept of the present disclosure has been described and illustrated with respect to the exemplary embodiments thereof, and is not limited to the exemplary embodiments disclosed herein, and modifications may be made without departing from the scope of the invention. Was completed.

Claims (11)

An apparatus includes: a switch configured to operate in a receive mode and a protection mode; and a voltage detection circuit coupled to the switch, the voltage detection circuit measuring two end points of the switch The potential difference between the switch and the voltage detection circuit does not include any depletion mode device. The device of claim 1, wherein the switch is configured to automatically switch between the receiving mode and the protected mode without a control signal. The device of claim 1, wherein the switch comprises a first NMOS transistor and a second NMOS transistor, and the source terminals of the first NMOS transistor and the second NMOS transistor are coupled together. The device of claim 3, wherein the switch does not include any PMOS transistor. The apparatus of claim 3, further comprising a third transistor and a fourth transistor configured to close the switch. The device of claim 5, wherein a source terminal of the third transistor and the fourth transistor is coupled to a source terminal of the first NMOS transistor and the second NMOS transistor; and wherein The drain electrodes of the third transistor and the fourth transistor are coupled to the gate terminals of the first NMOS transistor and the second NMOS transistor. The device of claim 6, wherein the voltage detecting circuit comprises a first variable resistor and a second variable resistor, and the system is configured to measure the two end points of the switch. a potential difference between the two; and wherein a gate terminal of the third transistor is coupled to the first variable resistor, and a gate terminal of the fourth transistor is coupled to the second variable resistor. The device of claim 7, wherein the switch is configured to switch between the receiving mode and the protection mode according to a threshold voltage of the third transistor or a threshold voltage of the fourth transistor. The device of claim 5, wherein the third transistor and the fourth transistor system are NMOS transistors. The device of claim 1, wherein the resistance of the switch is substantially fixed in the receiving mode. The device of claim 1, wherein the switch operates as a fixed current source in the protection mode.