TW201735414A - RRAM based complementary switch for crosspoint memory applications - Google Patents

Abstract

An embodiment includes a resistive random access memory (RRAM) system comprising: a bi-polar complimentary resistive switch (CRS) comprising a top electrode, a bottom electrode, and an oxide layer between the top and bottom electrodes; wherein (a) a first plurality of oxygen vacancies are within the oxide layer and are adjacent the top electrode at a first concentration, (b) a second plurality of oxygen vacancies are within the oxide layer and are adjacent the bottom electrode at a second concentration, and (c) a third plurality of oxygen vacancies are within the oxide layer at a third concentration and between the first and second pluralities of oxygen vacancies. Other embodiments are described herein.

Description

Resistive random access memory-based complementary switch for cross-point memory applications

Embodiments of the invention are in the field of semiconductor devices, and in particular with respect to non-volatile memory.

Resistive random access memory (RRAM or ReRAM) relies on the type of material that switches from the initial insulation state to the low resistance state by "forming" events. In the event that is formed, the device undergoes a "soft breakdown" process in which the thinned lines are formed in a dielectric layer between the two electrodes. Such a thin line divides the current flowing through the thin wire to form a low resistance state. The RRAM switches states by applying voltages of different polarities to the electrodes, by eliminating the thin wires switching from the low resistance state to the high resistance state, and switching from the high resistance state to the low resistance state by re-forming the thin wires. Thus, conventional PRAM can be used as a memory.

100‧‧‧RRAM stacking

101‧‧‧Top electrode

101‧‧‧ electrodes

111‧‧‧Oxygen exchange layer (OEL)

131‧‧‧ bottom electrode

131‧‧‧electrode

141‧‧‧Area

142‧‧‧Area

144‧‧‧Oxygen vacancies

144‧‧‧ vacancies

200‧‧‧RRAM stacking

201‧‧‧ top electrode

221‧‧‧Oxide layer

223‧‧‧resistance

232‧‧‧ bottom electrode

241‧‧‧The first plurality of oxygen vacancies

242‧‧‧ second plural oxygen vacancies

244‧‧‧Oxygen vacancies

245‧‧‧ third plural oxygen vacancies

301‧‧‧Top electrode

321‧‧‧Oxide

331‧‧‧ bottom electrode

351‧‧‧Oxide resistance

900‧‧‧ system

905‧‧‧Baseband processor

910‧‧‧Application processing

915‧‧‧Power Management Integrated Circuit (PMIC)

920‧‧‧User Interface/Monitor

925‧‧‧ sensor

930‧‧‧Flash memory

932‧‧‧Safety parts

935‧‧‧DRAM

940‧‧‧General Integrated Circuit Card (UICC)

942‧‧‧Safe storage

945‧‧‧ Capture device

950‧‧‧Security Processor

960‧‧‧NFC contactless interface

965‧‧‧NFC antenna

970‧‧‧ Radio Frequency (RF) Transceiver

975‧‧‧Wireless Local Area Network (WLAN) transceiver

995‧‧‧ Identification device

1300‧‧‧Wearing module

1310‧‧‧ core

1320‧‧‧Sensor Hub

1330‧‧‧Power delivery circuit

1340‧‧‧Non-volatile storage

1350‧‧‧Input/Output (IO) interface

1390‧‧‧Wireless transceiver

Features and advantages of the embodiments of the invention will be apparent from the description of the appended claims. Where appropriate, component symbols are reused in different drawings to indicate corresponding or similar components.

Figure 1 (a) includes a conventional RRAM stack, Figure 1 (b) includes its corresponding current-voltage characteristics; Figure 2 (a) includes an RRAM stack of an embodiment of the present invention, and Figure 2 (b) includes its corresponding current - voltage characteristics; Figures 3(a)-3(e) include an RRAM stack forming an embodiment of the present invention; Figure 4 is a memory array in an embodiment; Figures 5-6 include systems, each of which includes an RRAM stack An embodiment.

SUMMARY OF THE INVENTION AND EMBODIMENT

The following description will refer to the drawings in which similar structures will be designated as similar suffix references. In order to more clearly show the structure of the different embodiments, the drawings contained herein are schematic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structure, such as that shown in the photomicrograph, will have a different appearance, and such differences will still be incorporated into the structures claimed in the illustrated embodiments. In addition, the drawings are only shown to facilitate an understanding of the structure of the illustrated embodiments. In order to maintain the clarity of the drawings, other structures known in the art are not intended to be included in the drawings. For example, it is not necessary to display each layer of the semiconductor device. "Embodiment", "different embodiment" and It is to be understood that the described embodiments may include specific features, structures or characteristics, but not all embodiments must include particular features, structures or characteristics. Some embodiments may or may not have some or all of the features to describe other embodiments. "First", "second", "third", and the like, recite common objects and indicate different examples to which the analogous elements are referred. Such an adjective does not mean that the recited object must have a given order, whether in time, space, grade, or any other form. "Connected" may mean direct physical or electrical contact with each other. "coupled" may mean mutual cooperation or interaction, but does not mean direct physical or electrical contact.

RRAMs can sometimes include complementary switches that include two reverse-direction bipolar resistance switches. In the "Complementary Resistive Switch" by Eike Cyrus Linn (see ***.publications.rwth-aachen.de/record/210058/files/4365.pdf), such a switch can be included in the balance type ( Also referred to as an "intersection" array, which is a matrix comprising n word lines, m-bit lines and n. m memory unit, which can be accessed individually or in column-to-column access. The array can be active or passive. For active implementations, each matrix element has its own active selectable transistor (1T), while for passive implementations only two terminal selector devices, such as diodes, are used. For resistive random access memory (ReRAM), a resistive switch (1R) and a transistor (1T) (1T1R configuration) are used. Each of the resistive switching units, whether monopolar or bipolar, can be used. In contrast to active arrays, no transistors are used in passive balance arrays. The passive balance array consists of only the bit lines and word lines and the storage elements of each intersection, forming a minimum feature size of 4F ² .

FIG. 1(a) includes a RRAM-based complementary switch 100. The switch 100 includes a top electrode 101, an oxygen exchange layer (OEL) 111, (eg, hafnium (Hf), titanium (Ti), and the like), an oxide 121 (eg, HfOx), and an intermediate metal layer 131. Oxygen vacancies 144 have a higher concentration in region 141 and a relatively lower concentration in region 142. The vacancy set forms a thin line as a memory. In response to the above, a "temporary collapse" occurs, for example, when annealing is generated such that oxygen is removed by the oxygen exchange layer 111 to create vacancies 144. Since the scavenging occurs near the oxygen exchange layer/oxide interface (the interface between layers 111 and 121), such a vacancy group occurs there. The stack 100 further includes a bottom electrode 101', an oxygen exchange layer 111' (e.g., hafnium (Hf), titanium (Ti), and the like), an oxide 121' (e.g., HfOx). Oxygen vacancies 144' have a higher concentration in region 141' and a relatively lower concentration in region 142'. Oxygen is removed by the oxygen exchange layer 111' thereby creating vacancies 144'. The vacancy group is adjacent to the oxygen exchange layer/oxide interface (the interface between layers 111' and 121').

The bias electrodes 101, 101' having a single polarity can intentionally remove the vacancies in the regions 143, 143' to release or break the filaments and construct a high resistance state (a memory state of "0"). The biasing of the electrodes 101, 101' can be reversed with the opposite polarity to re-form the vacancies in the regions 143, 143' to reform the filaments and build a low resistance state ("1" memory state). FIG. 1(b) shows an example of the current-voltage characteristics of the stack 100. When the voltage rises above the first threshold, both RRAM1 and RRAM2 are low. Pressure (point 1 - setting), when the second threshold is exceeded, one of the devices (RRAM1) is set to high resistance (point 2 - reset), resulting in "high resistance state" or HRS or memory state "0 ". When the voltage is lower than another threshold (point 3 - set), the two devices enter a low resistance, and one of the last devices (RRAM2) is reset to a high resistance (point 4 - reset), causing the device to enter a "low resistance state" "Or LRS or memory status "1".

Applicants have discovered the disadvantages of the complementary switch 100. For example, switch 100 requires two RRAM switches that result in processing complexity and loss of layout (eg, the relatively large area required for the switch). To address this shortcoming, Applicants provide embodiments of complementary switches (e.g., bipolar complementary resistive switches, sometimes referred to herein as "CRS"), using only one RRAM stack rather than two stacks. Having such a complementary switch embodiment using an RRAM stack has several advantages over conventional complementary RRAM switches. First, a complementary switch consisting of a single RRAM stack simplifies processing and reduces layout losses (eg, saves space compared to the conventional two switching devices). Second, limiting the switching current (eg, switching current <1 mA) according to an embodiment of the oxide resistance (described in more detail below) increases the reliability of the memory using such a device (ie, for the device due to overcurrent) The damage is protected). Third, embodiments provide a symmetric RRAM stack (because no oxygen exchange layer is present), which reduces processing complexity. Fourth, the embodiment includes thin line reset/setting occurring at two positions in the vacant thin line (for example, see areas 243' and 243 of Fig. 2(a)) (removal of the second RRAM switch is required) begging).

2(a) includes an RRAM stack 200 that includes a top electrode 201, an oxide 221 (eg, HfOx), and a bottom electrode 232. Oxygen vacancies 244 are distributed between regions 241, 242, 243 (when in a low resistance state). The vacancies are integrally formed as thin lines of memory. As described above, a "soft breakdown" occurs to create a gap 144. The vacancy group is close to the electrode/oxide interface (the interface between layers 201/221 and between layers 232/221). 2(b) is similar to the current-voltage characteristic diagram of FIG. 1(b), showing that although there is no oxygen exchange layer, the stack 200 operates in the HRS state (when the voltage exceeds _Vth2 , the memory state is "1"), and Operates in the LRS state (the memory state is "0" when V _th 4 is exceeded).

Returning to FIG. 2(a), the first plurality of oxygen vacancies 241 are adjacent to the electrode 201 at a first concentration, and the second plurality of oxygen vacancies 242 are adjacent to (not necessarily directly adjacent to) the electrode 232 at a second concentration, the third plurality Oxygen vacancies 245 are located between the first plurality of oxygen vacancies 241 and the second plurality of oxygen vacancies 242 at a third concentration. As used herein, "proximity" or "direct proximity" is a relative term. Thus, the vacancies 242 are adjacent to the layer 232 but not adjacent to the layer 201, and the vacancies 241 are adjacent to the layer 201 but not adjacent to the layer 232.

In the embodiment, there is no oxygen exchange layer between the electrodes 201 and 232, and the electrodes 201, 232 are separated from and away from the oxygen-free exchange layer.

In an embodiment, the oxide layer 221 includes at least one of the following: HfO ₂ , SiO ₂ , Al ₂ O ₃ , TiO ₂ , SrTiO ₃ , Cr-SrTiO ₃ , NiO, CuOx, ZrO ₂ , Nb ₂ O ₅ , MgO , Fe ₂ O ₃ , Ta ₂ O ₅ , ZnO, CoO, CuMnOx, CuMoOx, InZnO, Cr-SrZrO ₃ , PrCaMnO ₃ , SrLaTiO ₃ , LaSrFeO ₃ , (Pr, Ca) MnO ₃ , Nb-SrTiO ₃ , and LaSrCoO ₃ . EXAMPLES The top electrode 201 includes at least one of: hafnium (Hf), titanium (Ti), tantalum (Ta), palladium (Pd), tungsten (W), molybdenum (Mo), and platinum (Pt) (eg, TiN). And the bottom electrode 231 includes at least one of: hafnium (Hf), titanium (Ti), tantalum (Ta), palladium (Pd), tungsten (W), molybdenum (Mo), and platinum (Pt) (eg, TiN). . Additionally, the electrodes 201, 231 can comprise multiple layers of material having different qualities.

Embodiments include a resistor 233 adjacent one of the electrodes, such as electrode 232 (but in other embodiments adjacent to electrode 201). In some embodiments, the electrical resistance is adjacent to both of the electrodes. The resistor 233 can be an oxide or a nitride, such as TiON. Such resistance may be formed during the fabrication of the device 200 by exposing the electrode surface, for example, with oxygen (or a general atmospheric gas) (eg, on the upper surface of the electrode 232 of FIG. 3(b)).

In an embodiment, the oxide layer 221 directly contacts the electrodes 201, 232 (eg, no resistance 233 is present in the embodiment). In another embodiment, the oxide layer 221 directly contacts the resistor 233 and the electrode 201.

The RRAM stack 200 is a function as a non-volatile memory, wherein in a first state (when energy is applied to the top electrode at a first polarity and the first threshold voltage is satisfied), the first plurality, the second plurality, and the third a plurality of oxygen vacancies forming a first thin line having a first electrical resistance; and in a second state (when energy is applied to the top electrode at a first polarity and satisfying a second threshold voltage), the first plurality and the second plurality Third, plural The oxygen vacancies form a second thin line configuration, or a discontinuity, resulting in a higher resistivity.

For example, in Figure 2(b), the first state may occur at _Vth1 and the second state may occur at _Vth2 . In the first state, there is a continuous vacancy at 243, 243', 243", thus forming a relatively low resistance thin line. In the second state, there is a vacancy with discontinuity. For example, at 243' has a lower concentration ( Or discontinuity), thus forming a discontinuous thin line ("0" memory state) having a relatively high resistance.

In the RRAM stack 200, in a third state (when energy is applied to the top electrode in a second polarity opposite the first polarity and the third threshold voltage is met), the first plurality, the second plurality, and the third plurality The oxygen vacancies form a third thin line having a relatively low electrical resistance; and in a fourth state (when energy is applied to the top electrode at a second polarity and the fourth threshold voltage is satisfied), the first plurality and the second plurality The third and the plurality of oxygen vacancies form a fourth thin line configuration, or a discontinuity, resulting in a higher resistivity.

For example, in Figure 2(b), the third state occurs at _Vth3 and the fourth state occurs at _Vth4 . In the third state, there are continuous vacancies at 243, 243', 243", thus forming a thin line having a relatively low resistance. In the fourth state, there is a discontinuous vacancy. For example, at 243" has a relatively low concentration ( Or discontinuity), thus forming a discontinuous thin line ("1" memory state) with relatively high resistance.

3(a)-3(e) include methods of forming an RRAM stack in accordance with an embodiment of the present invention. In FIG. 3(a), a bottom electrode 331 is formed. In Figure 3 In (b), an oxide resistor 351 is deposited on the bottom electrode. Next, an oxide 321 is formed after the top electrode 301 (Fig. 3(d)) (Fig. 3(c)). Finally, a pattern is formed and etched to form an RRAM cell, which is annealed to produce a thin line 245 consisting of oxygen vacancies (Fig. 3(e)).

The different embodiments disclosed herein are directed to RRAM stacking. As shown in FIG. 4, any such RRAM stack 200 can be stacked by another node (eg, a diagram by coupling a portion or node of the stack (eg, the top electrode of FIG. 2(a)) to the row decoder. The bottom electrode of 2(a) is coupled to the array column decoder of the counterbalance/intersection, and is used in the memory unit (and the memory array).

Embodiments provide a smaller and more power efficient memory unit that can be scaled down to, for example, a 22 nm CD.

Referring now to Figure 5, a block diagram of an example system in which embodiments may be used is shown. As can be seen, system 900 can be a smart phone or other wireless communicator, or any other Internet of Things (IoT) device. The baseband processor 905 is configured to perform various signal processing associated with the communication signals transmitted or received by the system. In turn, the baseband processor 905 is coupled to the application processor 910, which is the main CPU of the system, for executing the operating system and other system software, in addition to the user application, for example, many are well known. Social media and multimedia applications. Application processor 910 can be configured to perform various other computing operations for the device.

In turn, the application processor 910 can be coupled to a user interface/display 920 (eg, a touch screen display). In addition, the application processor 910 can be coupled to a memory system, including non-volatile memory. That is, the flash memory 930 and the system memory, that is, the DRAM 935. In some embodiments, flash memory 930 can include a security component 932 in which secret and other sensitive information can be stored. As can be seen later, the application processor 910 is also coupled to the capture device 945, such as one or more image capture devices, which can record images and/or still images.

The Universal Integrated Circuit Card (UICC) 940 includes a subscriber identification module, and in some embodiments includes a secure storage 942 to store secure user information. System 900 can include a security processor 950 (eg, a Trusted Platform Module (TPM)) that can be coupled to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerations The device can be coupled to the application processor 910 to enable input of various sensing information, such as mobile or other environmental information. Additionally, one or more authentication devices 995 can be used to receive, for example, user biometric input for use. For the identification operation.

Further illustrated, a near field communication (NFC) contactless interface 960 provides NFC near field communication via the NFC antenna 965. Although individual antennas are shown, it will be appreciated that in some implementations, a single antenna or different combinations of antennas may be provided to enable various wireless functions.

A power management integrated circuit (PMIC) 915 is coupled to the application processor 910 to implement platform level power management. For this purpose, the PMIC 915 can perform power management requirements to the application processor 910 to enter the desired particular low power state. Additionally, the PMIC 915 can control the power level of other components of the system 900, depending on platform constraints.

In order to enable communication, such as transmission and reception in one or more IoT networks, different circuits may be coupled between the baseband processor 905 and the antenna 990. In particular, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 can be used. In general, the radio frequency transceiver 970 can be based on a given wireless communication, such as 3G or 4G wireless communication protocols, code division multiple access (CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), or other protocols. Agreement for receiving and transmitting wireless data and calls. Additionally, GPS sensor 980 can be presented with location information provided to secure processor 950 for use in the content information described herein for the pairing method. Other wireless communications may be provided, such as the reception or transmission of radio signals (eg, AM/FM) and other signals. Further, via the WLAN transceiver 975, wireless communication area may also be achieved, for example, standard Bluetooth (Bluetooth ^TM) or according to IEEE 802.11.

System 900 can include hundreds or thousands of the above described memory cells/stacks (e.g., stack 200 of Figure 2(a)) and is critical to the memory function of system 900. Memory 935, 932, 930, 942, 950 and other unlabeled memory can include the memory stacks and/or arrays described herein (see Figure 4).

Embodiments may be used in the context of an IoT device, including wearable devices or other small IoT devices. Referring to Figure 6, a block diagram of a wearable module 1300 in accordance with another embodiment is shown. In a particular embodiment, the module 1300 may be Intel® Curie ^TM module, which comprises a suitable solid or all of the plurality of components within a single module is part of a small wearable device. As shown, the module 1300 includes a core 1310 (of course, more cores may be displayed in other embodiments). This core can be a relatively low-order sequential core, such as the Intel Architecture® Quark ^TM design. In certain embodiments, core 1310 can implement the TEE described herein. The core 1310 is coupled to different components, including a sensor hub 1320 that is configurable to interact with a plurality of sensors 1380, such as one or more biological, mobile environments, or other sensors. A power delivery circuit 1330 having a non-volatile storage 1340 (which includes the RRAM stack 200 and/or other embodiments described herein) is presented. In an embodiment, the circuit can include a rechargeable battery and a rechargeable circuit that can receive the charging power wirelessly in an embodiment. One or more input/output (IO) interfaces 1350 may be presented as, for example, one or more interfaces that match one or more USB/SPI/I2C/GPIO protocols. Further, a wireless transceiver 1390, a wireless transceiver may be a Bluetooth ^TM or other low-energy short-distance wireless communication system so as to enable presentation of the as described herein. It can be appreciated that the wearable module can be in any other form in different implementations. Wearable and/or IoT devices have a smaller form factor, lower power requirements, limited command combinations, relatively low computational throughput, or any of the above, compared to a typical CPU or GPU. By.

The following examples are illustrative of further embodiments.

Example 1 includes a resistive random access memory (RRAM) system including a bipolar complementary resistive switch (CRS) comprising: a top electrode, a bottom electrode, an oxide layer between the top electrode and the bottom electrode; Wherein (a) the first plurality of oxygen vacancies are located in the oxide layer at a first concentration And adjacent to the top electrode, (b) the second plurality of oxygen vacancies are located in the oxide layer at a second concentration adjacent to the bottom electrode, and (c) the third plurality of oxygen vacancies are located in the oxide layer at a third concentration, and Between the first and second plurality of oxygen vacancies, and (d) the CRS does not include an oxygen exchange layer (OEL) between the top electrode and the bottom electrode.

"Top" and "Bottom" are relative terms that can vary depending on the orientation of the stack. The oxygen exchange layer is a term well known to those skilled in the art. The oxygen exchange layer can be referred to as a "metal cover layer". The oxygen exchange layer can include a metal such that when the oxygen exchange layer is adjacent to or in contact with an oxygen source stage (e.g., an oxide layer), the oxygen exchange layer facilitates "oxygen exchange" at the oxygen source level. Example 1 does not have such a metal layer between the top electrode and the bottom electrode.

Depending on the state of the CRS, the "first concentration" (as with the other concentrations mentioned above) can be extremely low (rare to no vacancies) or extremely high.

Another version of Example 1 includes a resistive random access memory (RRAM) system including: a bipolar complementary resistive switch (CRS) including a top electrode, a bottom electrode, between the top electrode and the bottom electrode An oxide layer; wherein (a) the first plurality of oxygen vacancies are located within the oxide layer at a first concentration and adjacent to the top electrode, and (b) the second plurality of oxygen vacancies are located within the oxide layer at a second concentration and adjacent The bottom electrode, and (c) the third plurality of oxygen vacancies are located in the oxide layer at a third concentration and between the first and second plurality of oxygen vacancies.

In Example 2, the body of Example 1 can optionally include wherein the oxide layer is a single piece and directly contacts both the top electrode and the bottom electrode.

Direct contact can eliminate the barrier layer and its like.

In Example 3, the body of Example 1-2 can optionally include a resistor having an additional oxide layer, wherein the additional oxide layer directly contacts both the bottom electrode and the oxide layer.

In Example 4, the body of Examples 1-3 can optionally include an oxide layer in which (a) the CRS does not include a metal layer between the additional oxide layer and the top electrode, and (b) directly contacts the upper electrode. (c) The oxide layer is monolithic.

In Example 5, the body of Examples 1-4 may optionally include wherein, in the first state, when energy is applied to the top electrode in a first polarity and the first threshold voltage is satisfied, the first plurality and the second plurality a third plurality of oxygen vacancies forming a first thin line having a first electrical resistance; and in the second state, when energy is applied to the top electrode in a first polarity and satisfying a second threshold voltage, the first plurality The second plurality and the third plurality of oxygen vacancies form a second thin line having a second electrical resistance higher than the first electrical resistance.

The second resistance can be very high, and when the path is incomplete due to the lack of vacancies in the region 243', the second thin line can constitute a broken or incomplete thin line. There may be some vacancies in area 243', but only a few are high resistance.

In Example 6, the body of Examples 1-5 can optionally include wherein in the second state, the first plurality of oxygen vacancies are at a first concentration, and in the first state, the first plurality of oxygen vacancies are additional concentrations , which is greater than the first concentration.

In Example 7, the subject of Examples 1-6 can optionally include In the second state, the first plurality of oxygen vacancies is the first concentration, and the second plurality of oxygen vacancies is the second concentration, and the second concentration is greater than the first concentration.

In Example 8, the body of Examples 1-7 can optionally include wherein both the first and second threshold voltages are positive and the second threshold voltage is greater than the first threshold voltage.

"Greater than" means that V _th 2 is greater than V _th 1 and V _th 4 is greater than V _th 3 .

In Example 9, the body of Examples 1-8 can optionally include wherein, in the third state, when energy is applied to the top electrode with a second polarity (as opposed to the first polarity) and the third threshold voltage is met, a plurality of, a second plurality, and a third plurality of oxygen vacancies forming a third thin line having a third electrical resistance; and in the fourth state, when energy is applied to the top electrode in a second polarity and satisfying the fourth critical At the voltage, the first plurality, the second plurality, and the third plurality of oxygen vacancies form a fourth thin line having a fourth electrical resistance higher than the third electrical resistance.

The so-called resistance "greater than" another resistor means having a "higher resistance" than the other resistor.

In Example 10, the subject of Examples 1-9 can optionally include wherein in the fourth state, the first plurality of oxygen vacancies is at a first concentration, the second plurality of oxygen vacancies is at a second concentration, and the second The concentration is less than the first concentration.

In Example 11, the body of Examples 1-10 can optionally include wherein both the third and fourth threshold voltages are negative and the fourth threshold voltage is greater than the third threshold voltage.

"Greater than" means that V _th 2 is greater than V _th 1 and V _th 4 is greater than V _th 3 .

In Example 12, the body of Examples 1-11 can optionally include wherein, in an initial formation state, when energy is applied to the top electrode in a first polarity, the first, second, and third plurality of oxygen vacancies form a first a thin line; wherein the initial formation state occurs before the first and second states.

In Example 13, the body of Examples 1-12 can optionally include wherein the oxide layer comprises at least one selected from the group consisting of: HfOx, SiOx, Al2Ox, TiOx, TaOx, GdOx, ErOx, NbOx, WOx, ZnOx, and InGaZnOx.

Another version of Example 13 provides a CRS that does not include an oxygen exchange layer (OEL) between the top electrode and the bottom electrode.

In Example 14, the body of Examples 1-13 can optionally include wherein the top electrode comprises at least one selected from the group consisting of TiN, TaN, tungsten (W), ruthenium (Ru), iridium (Ir), palladium. (Pd), platinum (Pt), molybdenum (Mo), TiAlN and TaAlN, and the bottom electrode also includes at least one of the above.

In Example 15, the body of Examples 1-14 can optionally include a memory array that includes a row decoder and a column decoder coupled to each other via a CRS.

Example 16 includes a resistive random access memory (RRAM) system including: a bipolar complementary resistive switch (CRS) including a top electrode, a bottom electrode, and an oxide layer between the top electrode and the bottom electrode Wherein in the first state, when energy is applied to the top electrode in a first polarity and the first threshold voltage is satisfied, the first complex in the oxide layer The plurality, the second plurality, and the third plurality of oxygen vacancies form a first path having a first electrical resistance; wherein in the second state, when energy is applied to the top electrode at the first polarity and the second threshold voltage is satisfied a first plurality, a second plurality, and a third plurality of oxygen vacancies forming a second path having a second electrical resistance between the top electrode and the bottom electrode, the second electrical resistance being greater than the first electrical resistance; wherein Two states: (a) the first oxygen vacancies are located in the third oxide layer above the first concentration, and (b) the second oxygen vacancies are located in the third oxide layer below the second concentration, The two concentrations are greater than the first concentration, and (c) the third oxygen vacancies are located in the intermediate third oxide layer at a third concentration.

The first concentration may have a small amount of vacancies or even no vacancies.

In Example 17, the body of Example 16 can optionally include an oxygen exchange layer (OEL) in which the CRS is not included between the top electrode and the bottom electrode.

In Example 18, the body of Examples 16-17 can optionally include a resistor having an additional oxide layer, wherein the additional oxide layer directly contacts both the bottom electrode and the oxide layer.

In Example 19, the body of Examples 16-18 can optionally include wherein the additional oxide layer comprises TiON.

Example 20 includes a method comprising: forming a bottom electrode; forming an oxide resistor on the bottom electrode; forming an oxide layer on the oxide resistor; forming a top electrode on the oxide layer; on the oxide resistor, the top electrode, the bottom The electrode and oxide layers are patterned to form a resistive random access memory (RRAM) cell that includes a complementary resistive switch (CRS); annealing the RRAM cell to produce a thin line consisting of oxygen vacancies in the oxide layer.

In Example 21, the body of Example 20 can optionally include a column decoder and a row decoder that couple the RRAM cells to the memory array.

The above description of the embodiments of the present invention has been presented by way of illustration and description. The disclosed forms are not intended to be exhaustive or to limit the invention, and the scope of the description and the accompanying claims includes the terms, such as left, right, top, bottom, top, bottom, above, below, above, below, The first, second, etc. are for illustrative purposes only and are not intended to be limiting. For example, the designation indicating the relative vertical position is that the device side (or main surface) of the reference substrate or the integrated circuit is the "top" surface of the substrate; the substrate may actually be in any orientation to make the substrate " The top "side" may be lower than the "bottom" side of the standard ground frame of the reference, while still falling within the meaning of the term "top." The term "on" (including the scope of the patent application) as used herein does not mean that the first layer "on" the second layer is directly on the second layer and is in direct contact with the second layer. Unless otherwise stated; there may be a third layer or other structure on the first layer between the first layer and the second layer. Embodiments of the devices or articles described herein can be manufactured, used, or shipped in a number of positions and orientations. It will be appreciated by those skilled in the relevant art that many modifications or variations are possible in the above teachings. Those skilled in the art will appreciate that the various components shown in the figures can have different equivalent combinations and substitutions. Therefore, the scope of the invention is not limited by the detailed description, but is defined by the scope of the appended claims.

245‧‧‧ third plural oxygen vacancies

301‧‧‧Top electrode

321‧‧‧Oxide

331‧‧‧ bottom electrode

351‧‧‧Oxide resistance

Claims (22)

A resistive random access memory (RRAM) system comprising: a bipolar complementary resistive switch (CRS) comprising a top electrode, a bottom electrode, an oxide layer between the top electrode and the bottom electrode; (a) a first plurality of oxygen vacancies located within the oxide layer at a first concentration adjacent to the top electrode, and (b) a second plurality of oxygen vacancies located within the oxide layer at a second concentration adjacent to and adjacent to the oxide layer a bottom electrode, (c) a third plurality of oxygen vacancies located in the oxide layer at a third concentration and between the first and second plurality of oxygen vacancies. The system of claim 1 wherein the oxide layer is monolithic and is in direct contact with both the top electrode and the bottom electrode. A system of claim 1 comprising a resistor having an additional oxide layer, wherein the additional oxide layer directly contacts both the bottom electrode and the oxide layer. The system of claim 3, wherein (a) the bipolar complementary resistive switch does not include a metal layer between the additional oxide layer and the top electrode, (b) the oxide layer directly contacts the upper electrode And (c) the oxide layer is monolithic. The system of claim 1, wherein: in the first state, when energy is applied to the top electrode in a first polarity and the first threshold voltage is satisfied, the first plurality, the second plurality, and the third plurality The oxygen vacancies form a first thin line having a first electrical resistance; In the second state, when energy is applied to the top electrode at the first polarity and the second threshold voltage is satisfied, the first plurality, the second plurality, and the third plurality of oxygen vacancies form a second thin line. It has a second electrical resistance that is higher than the first electrical resistance. The system of claim 5, wherein in the second state, the first plurality of oxygen vacancies is the first concentration, and in the first state, the first plurality of oxygen vacancies is an additional concentration, the additional concentration Greater than the first concentration. The system of claim 5, wherein in the second state, the first plurality of oxygen vacancies is the first concentration, and the second plurality of oxygen vacancies is the second concentration, the second concentration being greater than the first concentration. The system of claim 7, wherein the first threshold voltage and the second threshold voltage are both positive, and the second threshold voltage is greater than the first threshold voltage. The system of claim 5, wherein: in the third state, when energy is applied to the top electrode in a second polarity opposite to the first polarity, and the third threshold voltage is satisfied, the first plurality and the second plurality a third plurality of oxygen vacancies forming a third thin line having a third electrical resistance; and in the fourth state, when energy is applied to the top electrode at the second polarity and satisfying a fourth threshold voltage, the first A plurality of the second plurality, the third plurality of oxygen vacancies forming a fourth thin line having a fourth electrical resistance higher than the third electrical resistance. The system of claim 9, wherein in the fourth state, the first A plurality of oxygen vacancies are the first concentration, the second plurality of oxygen vacancies is the second concentration, and the second concentration is less than the first concentration. The system of claim 10, wherein the third threshold voltage and the fourth threshold voltage are both negative and the fourth threshold voltage is greater than the third threshold voltage. The system of claim 5, wherein in the initial formation state, when energy is applied to the top electrode in the first polarity, the first plurality of oxygen vacancies, the second plurality of oxygen vacancies, and the third plurality of oxygen The vacancy forms the first thin line; wherein the initial formation state occurs before the first state and the second state. The system of claim 5, wherein the bipolar complementary resistive switch does not include an oxygen exchange layer (OEL) between the top electrode and the bottom electrode. The system of claim 1, wherein the oxide layer comprises at least one selected from the group consisting of: HfOx, SiOx, Al ₂ Ox, TiOx, TaOx, GdOx, ErOx, NbOx, WOx, ZnOx, and InGaZnOx. The system of claim 14, wherein the top electrode comprises at least one selected from the group consisting of: TiN, TaN, tungsten (W), ruthenium (Ru), iridium (Ir), palladium (Pd) Platinum (Pt), molybdenum (Mo), TiAlN and TaAlN, the bottom electrode also includes the at least one. A system as claimed in claim 1, comprising a memory array comprising row decoders and columns coupled to each other via the bipolar complementary resistive switches decoder. A resistive random access memory (RRAM) system comprising: a bipolar complementary resistive switch (CRS) comprising a top electrode, a bottom electrode, an oxide layer between the top electrode and the bottom electrode; Wherein in the first state, when energy is applied to the top electrode in a first polarity and the first threshold voltage is satisfied, the first plurality, the second plurality, and the third plurality of oxygen vacancies are formed in the oxide layer a first path having a first electrical resistance; wherein in the second state, when energy is applied to the top electrode at the first polarity and the second threshold voltage is satisfied, the first plurality, the second plurality, the a third plurality of oxygen vacancies forming a second path having a second electrical resistance between the top electrode and the bottom electrode, the second electrical resistance being greater than the first electrical resistance; wherein in the second state: (a) the a first oxygen vacancy at a first concentration in a third upper portion of the oxide layer, (b) a second oxygen vacancy at a second concentration in a third lower portion of the oxide layer, the first Two concentrations greater than the first Concentration, and (c) a third oxygen vacancy concentration is within the middle third of the third oxide layers. The system of claim 17, wherein the bipolar complementary resistive switch does not include an oxygen exchange layer (OEL) between the top electrode and the bottom electrode. The system of claim 17, comprising a resistor having additional oxygen a layer of the oxide wherein the additional oxide layer directly contacts both the bottom electrode and the oxide layer. The system of claim 19, wherein the additional oxide layer comprises TiON. A method comprising: forming a bottom electrode; forming an oxide resistor on the bottom electrode; forming an oxide layer on the oxide resistor; forming a top electrode on the oxide layer; the oxide resistor, the top electrode, The bottom electrode and the oxide layer are patterned to form a resistive random access memory (RRAM) cell including a complementary resistive switch (CRS); and the RRAM cell is annealed to produce a thin line by which the oxidation The oxygen vacancies of the layer are composed. The method of claim 21, comprising coupling the RRAM unit to a column decoder and a row decoder of the memory array.