TW201735303A - Techniques for forming electrically conductive features with improved alignment and capacitance reduction - Google Patents

Abstract

Techniques are disclosed for forming electrically conductive features with improved alignment and capacitance reduction. In accordance with some embodiments, individual conductive features may be formed over a semiconductor substrate by a subtractive process (e.g., subtractive patterning). For a given feature, first and second barrier layers (conformal or otherwise) may be disposed along sidewalls thereof, and a helmet-like hardmask body may be disposed over a top surface thereof. Additional conductive features can be formed between existing features, using the barrier layers as alignment spacers, thereby halving (or otherwise reducing) feature pitch. A layer of another hardmask material may be disposed over the additionally formed features. That layer and the helmet-like hardmask bodies may be of different material composition, providing for etch selectivity with respect to one another. Additional layer(s) can be formed over the resultant topography, exploiting the hardmask etch selectivity in forming interconnects for adjacent integrated circuit layers.

Description

Technique for forming conductive features with improved alignment and reduced capacitance

The present invention relates to techniques for forming conductive features with improved alignment and capacitance reduction.

In the fabrication of integrated circuits, the interconnects can be formed over a semiconductor substrate using a copper-based damascene process. This process typically begins with a feature, such as a trench or via, that is etched into the insulator layer and filled with copper, resulting in a copper wire or through via (TBV). Additional layers of insulator material and copper fill features can be added, resulting in a multilayer integrated circuit. With proper alignment, adjacent integrated circuit layers can be electrically connected by such interconnect features.

100,101,102,104,105‧‧‧Integrated Circuit (IC)

102‧‧‧Semiconductor substrate

104‧‧‧ dielectric layer

104a‧‧‧Characteristics

106‧‧‧Electrical characteristics

106a‧‧‧Electrical characteristics

106b‧‧‧Electrical characteristics

108‧‧‧Baffle layer

110‧‧‧hard mask layer

112‧‧‧Baffle layer

114a‧‧‧Characteristics

114b‧‧‧Characteristics

116‧‧‧hard mask layer

118‧‧‧ dielectric layer

118a‧‧‧Characteristics

118b‧‧‧Characteristics

1000‧‧‧Computation System

1002‧‧‧ motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

1-6 are process flows for fabricating an integrated circuit (IC) in accordance with an embodiment of the present invention.

Figure 7 illustrates the cross-section of an IC configured in accordance with another embodiment of the present invention. Section view.

Figure 8 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

Figure 9 illustrates a cross-sectional view of the IC, after forming a hard mask layer, in accordance with an embodiment of the present invention.

Figure 10 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

Figure 11 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

Figure 11' illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

12-17, in conjunction with FIGS. 1-2, illustrate a process flow for fabricating an IC in accordance with another embodiment of the present invention.

Figure 18 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

Figure 19 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present invention.

20-28 illustrate a process flow for fabricating an IC in accordance with another embodiment of the present invention.

29 illustrates a computing system implemented in an integrated circuit structure or device that is formed using the disclosed techniques in accordance with an exemplary embodiment.

These and other features of this embodiment will be better understood by reading the following detailed description (in conjunction with the figures described herein). In the graphics, in each The same or nearly identical components shown in the figures may be represented by similar numbers. For the sake of brevity, not every component can be labeled in every figure. Further, as will be understood, the figures are not necessarily drawn to scale or are used to limit the particular embodiments shown. For example, while certain graphics generally indicate straight lines, right angles, and smooth surfaces, practical implementations of the present technology may have less perfect straight and right angles, and certain features may have surface topography or otherwise be fabricated. Non-smooth, given real world limits. In short, graphics are only provided to show the example structure.

SUMMARY OF THE INVENTION AND EMBODIMENT

Techniques for forming conductive features with improved alignment and capacitance reduction are disclosed. These techniques can be implemented with a damascene process or a erase process. In more detail, and in accordance with certain embodiments, a plurality of conductive features can be formed over the semiconductor substrate by a damascene process, wherein the individual features are formed directly within the dielectric layer (which is then recessed). In other embodiments, the plurality of conductive features can be formed over the semiconductor substrate by eliminating the patterning process, wherein the layer of conductive material is patterned into the individual features. In either case, for a given feature, the first and second barrier layers (which may be conformal or otherwise) may be configured along their sidewalls, while the helmet-like (or hat-like) hard mask may be Configured on top of its top surface. According to certain embodiments, additional conductive features may be formed between existing features, using a barrier layer as a trim spacer. In this way, the pitch of the features disposed over the substrate can be halved (or reduced). In some cases, another hard mask Layers of material can be placed over the additionally formed features. According to certain embodiments, the second hard mask layer and the helmet-like hard mask body may have different material compositions such that they exhibit etch selectivity with respect to each other. Additional layers can be formed over the resulting topography, using etching of the hard mask material to selectively form interconnections for adjacent integrated circuit layers, such as for a given target application or terminal use. Various configurations and variations will be apparent from this description.

General overview

Existing methods for handling short-circuit tolerances and capacitance suffer from challenges such as reducing defects, preserving pattern fidelity, and minimizing damage to metal structures during etching. As device sizes continue to shrink, interconnect features become narrower and more closely formed, which exacerbates these and other important issues.

Thus, and in accordance with certain embodiments of the present invention, techniques for forming conductive features with improved alignment and capacitance reduction are disclosed. In accordance with certain embodiments, the plurality of conductive features can be formed over the semiconductor substrate by any of the following: a damascene process in which individual features are formed directly into the dielectric layer that is subsequently recessed; or the pattern is eliminated A process in which a layer of conductive material is patterned into individual features. In either case, for a given feature, the first and second barrier layers (which may be conformal or otherwise) may be disposed along their sidewalls, and the helmet-like or hat-like hard mask may be configured Above its top surface. According to certain embodiments, additional conductive features may be formed between existing features, using a barrier layer as a trim spacer. With this In this way, the pitch of the features placed on the substrate can be halved (or reduced). In some cases, another layer of hard mask material can be disposed over the additionally formed features. According to certain embodiments, the second hard mask layer and the helmet-like hard mask body may have different material compositions such that they exhibit etch selectivity with respect to each other. Additional layers can be formed over the resulting topography, using etching of the hard mask material to selectively form interconnections for adjacent integrated circuit layers, such as for a given target application or terminal use.

In accordance with certain embodiments, the disclosed techniques can be used, for example, to form a first complex number (eg, a first half or other subset) of conductive features at a time, and then to form a second complex number (eg, second) Semi or other subset) conductive features. Between the patterning of the individual complex numbers, the spacer and hard mask deposition processes described herein can be utilized to provide an architecture with high etch selectivity, preferential alignment (or both) characteristics. As will be understood in light of this disclosure, the disclosed techniques can be utilized for any broad range of conductive feature configurations, including, for example, interconnects, trenches, vias, and plug cuts, to name a few.

In some cases, the disclosed techniques can provide improved pattern fidelity that can result in improved short circuit tolerance by reducing the risk of shorting to the wrong conductor. In some cases, patterning alternating conductive features (eg, pitches of 2 x instead of x ), as described herein, may reduce the risk of shorting to erroneous conductive features. Moreover, in some examples, a hard mask layer configured as described herein may be retained over the top surface of the conductive features to increase conductive features for the overlying layer (eg, vias in the upper layer) Short circuit tolerance for or other interconnects. In some cases, the disclosed techniques can be utilized, for example, to pattern interconnects with a tight pitch with improved etch layout error (EPE). In some cases, the disclosed techniques can be used to reduce the aspect ratio for metal (or other conductive material) deposition because additional hard masks can be patterned after the first set of conductive features. In some cases, the disclosed techniques can be provided at the height of staggered conductive features (eg, alternating lines or trenches) that can be used to reduce the capacitance of the host IC, as compared to conventional architectures.

According to certain embodiments, the use of the disclosed techniques can be detected, for example, by any of the following (or combinations): scanning electron microscopy (SEM), transmission electron microscopy (TEM), or established integrators Other suitable inspections of the circuit or other semiconductor structures having any of the following (or combinations): (1) the presence of a plurality of spacer materials whose spacers may be oriented vertically and/or horizontally, in the final interconnect stack And (2) alternating conductive features of different heights (eg, lines or trenches).

Metal mosaic technology and structure

1-6 illustrate a process flow for fabricating an integrated circuit (IC) 100 in accordance with an embodiment of the present invention. This process can begin as in Figure 1, which illustrates a cross-sectional view of an IC 100 configured in accordance with an embodiment of the present invention. As shown, the IC 100 includes a semiconductor substrate 102 that can have any of a wide range of configurations. For example, the semiconductor substrate 102 can be configured as a bulk semiconductor substrate, a semiconductor-on-insulator (XOI, where X represents a semiconductor material) structure (such as a germanium insulator (SOI)), a semiconductor wafer, and a multilayer structure (or combination) ). According to some embodiments, the semiconductor substrate 102 can be shaped Any one (or combination) of semiconductor materials such as germanium (Si), germanium (Ge), and germanium (SiGe). In some cases, semiconductor substrate 102 can include one or more conductive features (eg, interconnects) disposed therein. It should be noted that the substrate 102 does not have to be formed from a semiconductor at all, in certain embodiments. Other suitable materials and configurations for the semiconductor substrate 102 will depend on the intended application and will be apparent from this disclosure.

The IC 100 also includes a dielectric layer 104 disposed over the semiconductor substrate 102. Dielectric layer 104 can be formed from any of a wide range of dielectric materials. For example, in some embodiments, dielectric layer 104 can be formed from an oxide or a carbon-doped (C) oxide such as yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ). Zirconium oxide (ZrO ₂ ), lanthanum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), or lanthanum oxide (La ₂ O ₃ ), and the like. In some embodiments, the dielectric layer 104 can be formed from a nitride such as tantalum nitride (Si ₃ N ₄ ), or an oxynitride such as yttrium oxynitride (SiON), a carbide such as tantalum carbide (SiC). Or an oxycarbonitride such as bismuth oxycarbonitride (SiOCN). In some embodiments, dielectric layer 104 can be formed from any combination of the foregoing. In some embodiments, the dielectric layer 104 can be a homogeneous dielectric structure (eg, comprising only a single dielectric material); while in other embodiments, the dielectric layer 102 can be a heterogeneous dielectric structure (eg, comprising portions of different dielectric materials) ). In some cases, dielectric layer 104 can be configured to (at least partially) function as an interlayer dielectric (ILD) of IC 100. In some examples, dielectric layer 104 can be configured to provide shallow trench isolation (STI) of IC 100.

Dielectric layer 104 can be via any suitable standard, custom, or proprietary Techniques are formed over the semiconductor substrate 102 as will be apparent from this description. According to certain embodiments, the dielectric layer 104 may be via a physical vapor deposition (PVD) process (such as sputter deposition), a spin-on deposition (SOD) process, and a chemical vapor deposition (CVD) process (such as plasma enhanced CVD). (PECVD)) is formed by any one (or combination). The dimensions of the dielectric layer 104 can be customized, such as for a given target application or terminal use. In some cases, dielectric layer 104 can have a thickness in the range of about 50-150 nm (eg, any other sub-range in the range of about 50-100 nm, about 100-150 nm, or about 50-150 nm). Other suitable materials, forming techniques, and configurations for the dielectric layer 104 will depend on the intended application and will be apparent from the description.

In accordance with certain embodiments, dielectric layer 104 can be patterned with one or more features 104a, which can be any of a wide range of configurations. For example, in some cases, the predetermined feature 104a can be a trench (single damascene or dual damascene), plug cut, or other opening or recess that extends only through portions of the entire thickness of the dielectric layer 104 (eg, It is thus landed above the lower semiconductor substrate 102 (instead of the underlying semiconductor substrate 102)). In other cases, the predetermined features 104a can be perforations or other openings or depressions that extend through the entire thickness of the dielectric layer 104 (eg, such that they land on the underlying semiconductor substrate 102). The established features 104a can be formed via any suitable standard, custom, or proprietary lithography and etching techniques, as will be apparent from this disclosure. According to certain embodiments, the predetermined features 104a may be formed via an etch and clean process, which may involve wet etching or dry etching (or both), the etch chemistry of which may be (at least in part) dependent on the dielectric The material composition of layer 104 and semiconductor substrate 102 is customized. The size and geometry of the established feature 104a can be customized, such as for a given target application or terminal use. In some cases, the predetermined feature 104a can have substantially vertical sidewalls (eg, within about 2° of vertical straightness). In other examples, the predetermined feature 104a can have a tapered sidewall (eg, about 2° perpendicular to the vertical). The pitch or other spacing of adjacent features 104a can be customized. As shown, features 104a can be patterned, for example, at a pitch of 2 x , in accordance with certain embodiments. Other suitable configurations and configurations for feature 104a will depend on the intended application and will be apparent from the description.

Conductive features 106 may be disposed within predetermined features 104a of dielectric layer 104, in accordance with certain embodiments. In some cases, a predetermined conductive feature 106 can be formed over the semiconductor substrate 102 such that it contacts the upper surface of the semiconductor substrate 102 or is disposed over the upper surface of the semiconductor substrate 102. In some other instances, the predetermined conductive features 106 can be formed at least partially within the semiconductor substrate 102 such that they extend at least partially under the upper surface of the semiconductor substrate 102. In some other instances, the predetermined conductive features 106 can be formed over the semiconductor substrate 102 and at least partially within the semiconductor substrate 102 such that they are at least partially in contact with or disposed on the upper surface of the semiconductor substrate 102. Above the upper surface of the semiconductor substrate 102 and at least partially extending under the upper surface of the semiconductor substrate 102. Various configurations and variations will be apparent from this description.

The predetermined conductive features 106 can be formed from a wide range of conductive materials. Either. For example, in some embodiments, the predetermined conductive features 106 can be formed from, for example, copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold ( Any one (or combination) of conductive metals such as Au), titanium (Ti), and tantalum (Ta). The predetermined conductive features 106 can be formed via any suitable standard, custom, or proprietary technique, as will be apparent from this disclosure. In accordance with certain embodiments, the predetermined conductive features 106 can be formed via any one (or combination) of electroplating processes, electroless deposition processes, atomic layer deposition (ALD) processes, PVD processes, and CVD processes, among others.

The size and geometry of a given conductive feature 106 can be customized, such as for a given target application or terminal use; and in some cases can depend, at least in part, on the size and geometry of a given host feature 104a. In some cases, the predetermined conductive features 106 can be generally rectangular or square cross-sectional geometries. In some other cases, the predetermined conductive features 106 can be generally trapezoidal cross-sectional geometries. In some examples, a given conductive feature 106 can have one or more curved surfaces (top, sidewall, or other). In some examples, the predetermined conductive features 106 can have beveled or tapered sidewalls; while in some other examples, the predetermined conductive features 106 can have substantially straight, vertical sidewalls. The pitch (P ₁ ) or other spacing of adjacent conductive features 106 can be customized and can depend, at least in part, on the pitch of other host features 104a. Other suitable materials, forming techniques, and configurations for the conductive features 106 will depend on the intended application and will be apparent from this disclosure.

This process can continue as shown in FIG. 2, which illustrates a cross-sectional view of the IC 100 of FIG. 1 after recessing the dielectric layer 104, in accordance with an embodiment of the present invention. Dielectric layer 104 can be via any suitable standard, custom, or proprietary technology It is recessed, as will be clear from this description. In some cases, the recess of the dielectric layer 104 can be performed via any one (or combination) of the isotropic etch process and the anisotropic etch process. A given etch process can involve wet etch or dry etch (or both), and the particular etch chemistry utilized by a given application etch process can be customized, such as for a given target application or end use. In an exemplary case, an air gap etch process can be utilized to recess dielectric layer 104. The depth and extent of the depressions of dielectric layer 104 can be controlled to provide both quantitative symmetry/asymmetry and isotropic/anisotropic, as desired.

Note that as generally shown in FIG. 2, at least one conductive feature 106 (eg, conductive feature 106 shown in the middle) has a dielectric material of dielectric layer 104 in contact with its sidewalls, and at least one other conductive feature 106 (eg, most The conductive features 106) shown on the left and/or rightmost sides do not have a dielectric material of the dielectric layer 104 in contact with their sidewalls. This may (at least in some cases) be caused by any two conductive features 106 that may be interleaved with each other over the underlying semiconductor substrate 102, in accordance with certain embodiments. Considering FIG. 1, at least one of the conductive features 106 is at a different height relative to the semiconductor substrate 102 than at least one other conductive feature 106. In accordance with certain embodiments, the recesses of the dielectric layer 104 can be optimized (or customized) for a given amount of interlacing between adjacent conductive features 106. According to certain embodiments, dielectric layer 104 may be recessed, for example, until the bottom of a given conductive feature 106 is reached, such as generally shown in FIG. According to an embodiment, the recess of the dielectric layer 104 can be implemented such that its predetermined feature 104a landed on the trench stop, which can improve the etch control. To this end, in some cases The dielectric layer 104 can be formed as a multilayer structure (eg, a double layer, a triple layer, or other number of component layers), wherein the component layers have different material compositions, one of which is configured to function as Etch stop layer.

This process can continue as shown in FIG. 3, which illustrates a cross-sectional view of the IC 100 of FIG. 2 after forming the barrier layer 108, in accordance with an embodiment of the present invention. The barrier layer 108 can be configured (according to certain embodiments) to be (at least partially) a spacer layer that functions as IC 100 (or other host IC). To this end, the material composition of the barrier layer 108 can be customized, such as for a given target application or terminal use. In some cases, the barrier layer 108 may be formed from any one (or combination) such as, for example, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), and titanium oxide (TiO ₂ ). . More generally, and in accordance with certain embodiments, barrier layer 108 can be formed (partially or wholly) from any suitable low-k metal oxide having a dielectric constant (k) of less than or equal to about 5.0.

The barrier layer 108 can be formed via any suitable standard, custom, or proprietary technique, as will be apparent from this disclosure. According to certain embodiments, the barrier layer 108 may be via any one (or combination) of a chemical vapor deposition (CVD) process, such as a plasma enhanced CVD (PECVD) process, and an atomic layer deposition (ALD) process, and the like. Was formed. Size and geometry of the barrier layer 108 may be customized, as desired by the use for a given application or target terminal; and (at least partially) depends on the pitch of the conductive features 106 of barrier layer ₁ and the size P of at least 112 One (discussed below). In some cases, barrier layer 108 may have a thickness (e.g.) at about 0.25 to 0.5 multiplied by the pitch P x ₁ (e.g., about 0.25-0.375 multiplied by x, multiplied by about 0.375-0.5 x, or about 0.25 -0.5 is multiplied by any other subrange within the range of x ). In some examples, the barrier layer 108 can have a substantially uniform thickness over the topography provided by the dielectric layer 104 and the conductive features 106; while in some other examples, the barrier layer 108 can have a non-uniform Alternatively, the varying thickness is above the topography (eg, the first portion of the barrier layer 108 can have a thickness within the first range and the second portion can have a thickness within the second, different range). In some examples, the barrier layer 108 can be substantially conformal to its lower square topography (eg, over the dielectric layer 104 and extending the upper sidewalls and over the top surface of the conductive features 106). Other suitable materials, forming techniques, and configurations for the barrier layer 108 will depend on the intended application and will be apparent from the description.

This process can continue as in FIG. 4, which illustrates a cross-sectional view of the IC 100 of FIG. 3 after forming the hard mask layer 110, in accordance with an embodiment of the present invention. The material composition of the hard mask layer 110 can be customized, such as for a given target application or terminal use. In some embodiments, the hard mask layer 110 can be formed from titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), hafnium oxide (SiO ₂ ), tantalum carbonitride (SiCN), and Any one (or combination) of yttrium oxynitride (SiO _x N _y ) or the like.

The hard mask layer 110 can be formed via any suitable standard, custom, or proprietary technique, as will be apparent from this disclosure. According to certain embodiments, the hard mask layer 110 may be formed via a non-conformal deposition process, such as, for example, a PVD process (such as a sputter deposition process), and a CVD process, or the like. As will be understood in light of this specification, the use of a non-conformal process can cause a hard mask material to be deposited substantially (eg, only, mostly, or predominantly) on top of the conductive features 106. Not between them. In some cases, a given hard mask may extend beyond (eg, extend) the top surface of the underlying conductive feature 106 to the full thickness (or less than full thickness) of the lower barrier layer 108 (eg, such as generally visible in the figure) 4, 13, and 23). In some cases, a given hard mask may extend beyond (eg, extend) the top surface of the lower conductive feature 106 (eg, less than about 25% of its width, less than about 20% of its width, less) It is about 15% of its width, less than about 10% of its width, less than about 5% of its width, or less than about 1% of its width. In some other instances, the predetermined hard mask may not extend beyond (eg, may not extend) the top surface of the underlying conductive feature 106. One or more etching and cleaning processes can be selectively utilized in forming the hard mask layer 110, in accordance with certain embodiments. In an exemplary case, the wet cleaning process can be used to ensure that no hard mask material remains on the bottom of the space between adjacent conductive features 106.

The size and geometry of the hard mask layer 110 can be customized, such as for a given target application or terminal use. In some cases, the hard mask layer 110 may have a thickness (e.g.) at about 0.25 to 0.5 multiplied by the pitch P x ₁ (e.g., about 0.25-0.375 multiplied by x, multiplied by about 0.375-0.5 x, or A range of approximately 0.25-0.5 times any other sub-range within the range of x ). In some cases, the hard mask layer 110 can have any thickness, for example, in the range of about 5-20 nm (eg, about 5-10 nm, about 10-15 nm, about 15-20 nm, or about 5-20 nm). Within the scope of other sub-ranges). In some examples, the hard mask layer 110 can have a substantially uniform thickness above its lower square top; in some other examples, the hard mask layer 110 can have a non-uniform or varying thickness Above the topography (eg, the first portion of the hard mask layer 110 can have a thickness in the first range and the second portion can have a thickness in the second, different range). As can be seen from Figure 4, in accordance with certain embodiments, the hard mask layer 110 can be formed such that it contains one or more component hard mask bodies. In some cases, a given hard mask may be configured as a generally helmet-like (or cap-like) portion that is disposed over the topography provided by the barrier layer 108 and the lower portion of the conductive features 106. In some cases, the predetermined component of the hard mask layer 110 can be a generally rectangular or square cross-sectional geometry. In some other instances, the predetermined component hard mask of the hard mask layer 110 can be generally trapezoidal cross-sectional geometry. In some examples, a given component of the hard mask layer 110 can have one or more curved surfaces (top, sidewall, or other). In some examples, the predetermined component hard mask of the hard mask layer 110 can have beveled or tapered sidewalls; in some other examples, the hard mask layer 110 has a predetermined composition of a hard mask. The body can have substantially straight, vertical sidewalls.

In some cases, a component hard mask (eg, a helmet-like hard mask) of the hard mask layer 110 can be formed to allow it to be electrically leaky. However, in other cases, such hard masks may be formed such that they are not (or only negligibly) leaking. Other suitable materials, forming techniques, and configurations for the hard mask layer 110 will depend on the intended application and will be apparent from the description.

This process can continue as shown in FIG. 5, which illustrates a cross-sectional view of the IC 100 of FIG. 4 after forming the barrier layer 112, in accordance with an embodiment of the present invention. The barrier layer 112 can be configured (according to certain embodiments) to be (at least partially) a spacer layer that functions as IC 100 (or other host IC). As will be understood from this description, the barrier layer 112 can be formed in any of the example materials, techniques, and configurations discussed above, for example, for the barrier layer 108. In some embodiments, the barrier layer 112 can be a different material composition than the barrier layer 108. In some embodiments, the barrier layer 112 may have a thickness (e.g.) at about 0.1 to 0.25 multiplied by the pitch P x ₁ (e.g., about 0.1 to 0.2 multiplied by x, from about 0.15 to 0.25 multiplied by x, or about 0.1-0.25 times the range of any other sub-range within the range of x ). In some examples, the barrier layer 112 can have a substantially uniform thickness over the topography provided by the hard mask layer 110 and the barrier layer 108; while in some other examples, the barrier layer 112 can have a non- The uniform or varying thickness is above this topography (eg, the first portion of barrier layer 112 can have a thickness within a first range and the second portion can have a thickness within a second, different range). In some examples, the barrier layer 112 can be substantially conformal to its lower square appearance.

When forming the barrier layer 112, it may be desirable to remove portions thereof deposited over the hard mask layer 110 to ensure that the upper surface of the component hard mask of the hard mask layer 110 remains exposed. At the same time, it may be desirable to remove portions of the barrier layer 112 that are deposited over portions of the barrier layer 108 between adjacent conductive features 106. To these ends, partial removal of the barrier layer 112 can be performed via any suitable standard, custom, or proprietary directional etching technique, as will be apparent from this description.

As can be seen from FIG. 5, for example, the barrier layer 112 can be formed (according to certain embodiments) to extend from the barrier layer 108, along the sidewalls of the conductive features 106, and along the components of the hard mask layer 110. The side wall of the body. In some examples, the barrier layer 112 can extend the barrier layer 108 and the hard mask layer upward. The full height of 110, while in some other examples, the barrier layer can extend up less than its full height. As further seen from FIG. 5, features 114a may exist between adjacent conductive features 106 due to the particular interface of barrier layers 112 and 108 between such conductive features 106. Other suitable materials, forming techniques, and configurations for the barrier layer 112 will depend on the intended application and will be apparent from the description.

This process can continue as in Figure 6, which illustrates a cross-sectional view of the IC 100 of Figure 5 after forming features 114b from a predetermined feature 114a, in accordance with an embodiment of the present invention. As can be seen, the predetermined features 114a can undergo additional patterning, for example, to provide features 114b. In some cases, complex features 114b can be formed to provide a second set of conductive features 106 (eg, the first set is formed as discussed above with respect to FIG. 1). To these ends, the established features 114b can be formed in any of the example techniques and configurations discussed above, for example, for feature 104a, in accordance with certain embodiments. In some cases, the predetermined features 114b can be formed to extend all the way down to the top surface of the underlying semiconductor substrate 102, through the global portion thickness of each of the barrier layer 108 and the dielectric layer 104, for example. The predetermined features 114b can be formed, for example, as grooves, perforations, plug cuts, through holes, or any other feature, such as intended for a given target application or terminal use. In accordance with certain embodiments, features 114b (and 114a, discussed above) can be patterned on alternating trenches such that their pitch P _{1 of} IC 100 is approximately halved (e.g., as generally discussed with reference to FIG. In the next one). The size and geometry of the predetermined features 114b (and 114a) may depend, at least in part, on the dimensions of the barrier layers 112 and 108, which may define the size limitations of the features 114b (and 114a). For example, a first portion of the barrier layer 112 adjacent the sidewalls of the first conductive features 106 and a second portion of the barrier layer 112 adjacent the sidewalls of the adjacent conductive features 106 can act to protect those portions of the IC 100 while providing the predetermined features 114b The directivity of (or 114a) is formed on top of IC 100.

At this point in the process flow, there are a wide range of options for how to proceed with manufacturing. For example, consider Figure 7, which illustrates a cross-sectional view of an IC 101 configured in accordance with an embodiment of the present invention. As can be seen herein, all (or a subset) of features 114a and 114b of IC 100 can be filled with a conductive material, in accordance with certain embodiments. Thus, the resulting IC 100 may have a pitch P ₂ of the conductive features 106, the pitch P ₂ may be a part of the IC 100 of the original pitch of _{P. 1.} In an exemplary case, the pitch P ₂ may be about half of the pitch P ₁ (eg, if P ₁ = 2 x , then P ₂ = x ). In some cases, the newly formed conductive features 106 can be of the same material composition as the original conductive features 106 previously formed. In other cases, different conductive materials may be utilized such that the IC 101 controls one or more conductive features 106 of the first material composition and one or more conductive features 106 of the second, different material composition.

In some cases, after filling all (or a subset) of features 114a and 114b, IC 101 may optionally undergo any of a chemical mechanism planarization (CMP) process and an etch and clean process (or combination). For example, to remove any unnecessary portions of the barrier layer 112, the hard mask layer 110, and the barrier layer 108, and any excess (eg, overload) conductive features 106 that may be present. However, in other cases, the hard mask layer 110 may be allowed to remain on top of the IC 101.

In other cases, after filling all (or a subset) of features 114a and 114b, IC 101 may optionally undergo a recess process in which conductive features 106 are recessed below barrier layer 112 and hard mask layer 110. height. For example, consider Figure 8, which illustrates a cross-sectional view of an IC 102 configured in accordance with an embodiment of the present invention. The depressions of the conductive features 106 can be performed via any suitable standard, customary, or proprietary etching and cleaning techniques, as will be apparent from this disclosure.

In some cases, after the recessed conductive features 106 are as in FIG. 8, the IC 102 can optionally undergo one or more additional processes. For example, consider Figure 9, which illustrates a cross-sectional view of IC 102 after formation of hard mask layer 116, in accordance with an embodiment of the present invention. As can be seen, the hard mask layer 116 can be formed in any one or more of the desired features 114a and 114b, over the conductive features 106, in accordance with certain embodiments. As will be understood from this description, the hard mask layer 116 can be formed in any of the example materials, techniques, and configurations discussed above, for example, for the hard mask layer 110, in accordance with certain embodiments. In some cases, the hard mask layer 116 and the hard mask layer 110 can have different material compositions, providing etch selectivity to each other.

According to certain embodiments, after forming the hard mask layer 116, the IC 102 may undergo selective removal of portions of the dielectric layer 118, portions (or both) of its hard mask layers 110 and 116, and The predetermined conductive features 106 are further formed. For example, consider Figure 10, which illustrates a cross-sectional view of an IC 102 configured in accordance with an embodiment of the present invention. As will be understood from this description, dielectric layer 118 can be formed in any of the example materials, techniques, and configurations discussed above, for example, for a dielectric layer 104, in accordance with certain embodiments. As can be seen herein, the dielectric layer 118 can be patterned with one or more features 118a, the size and geometry of which can be customized, such as intended for a given target application or terminal. In some cases, the predetermined features 118a can be formed to land (at least in part) over a portion of the hard mask layer 116 and under the conductive features 106. After patterning this feature 118a, a portion of the underlying hard mask layer 116 can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114b. In accordance with an embodiment, an additional conductive material can be deposited over the newly exposed conductive features 106 that allow the resulting conductive features 106a to extend upward through the patterned features 118a in the dielectric layer 118. In an exemplary case, the vias (or other conductive features) of the next overlying layer may be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106a across the two IC layers.

Figure 11 illustrates a cross-sectional view of an IC 102 configured in accordance with another embodiment of the present invention. Figure 11' illustrates a cross-sectional view of an IC 102 configured in accordance with another embodiment of the present invention. As will be understood from this description, FIG. 11' provides a demonstration of IC 100, which represents a more real-world structural feature and configuration, and the description provided herein with respect to FIG. 11 is equally applicable to FIG. 11'. As can be seen from these figures, dielectric layer 118 can additionally (or alternatively) be patterned with one or more features 118b, the size and geometry of which can be customized, such as for a given target application or terminal use. In some cases, the predetermined feature 118b can be formed to land (at least in part) over a portion of the hard mask layer 110 and below the conductive features 106. After patterning this feature 118b, the underlying hard mask layer 110 A portion can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114a. In accordance with an embodiment, an additional conductive material can be deposited over the newly exposed conductive features 106 that allow the resulting conductive features 106b to extend upward through the patterned features 118b in the dielectric layer 118. In an exemplary case, the vias (or other conductive features) of the next overlying layer can be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106b across the two IC layers. As shown in each of Figures 11 and 11 ', conductive features 106a may alternatively be present in IC 102, although IC 102 need not have such a configuration.

As can be seen generally in Figures 10-11', in some cases, the use of the disclosed techniques may allow for improved etch layout error (EPE) tolerance, in accordance with certain embodiments. As further seen in Figures 10-11', hard mask layer 110 (e.g., helmet-like hard mask) and hard mask layer 116 can exhibit etch selectivity, in accordance with certain embodiments.

Figures 1-2 and 12-17 illustrate the process flow for fabricating an IC 104 in accordance with another embodiment of the present invention. The process can begin as shown in Figures 1 and 2, as discussed above. This process can begin as shown in Figure 12, which illustrates a cross-sectional view of an IC 104 configured in accordance with another embodiment of the present invention. As seen herein, the IC 104 includes a barrier layer 108 that extends over the sidewalls (but not the top surface) of the conductive features 106 (eg, the barrier layer 108 extends over portions of the sidewalls above the dielectric layer 104). Therefore, the upper surface of the conductive feature 106 remains exposed. Comparing this with the barrier layer 108 of FIG. 3 (as discussed above), which instead conforms to the top surface of the conductive feature 106, and Side wall.

This process can continue as shown in FIG. 13, which illustrates a cross-sectional view of the IC 104 of FIG. 12 after forming the hard mask layer 110, in accordance with an embodiment of the present invention. As can be seen herein, a hard mask layer 110 (eg, one or more hard mask bodies, as discussed above) can be disposed (and directly in contact with) the top surface of the conductive features 106, along along the conductive features The end of the portion of the barrier layer 108 of 106, in accordance with an embodiment. Comparing this with the hard mask layer 110 of FIG. 4 (as discussed above), which instead resides (and directly contacts) a portion of the barrier layer 108 that conforms to the top surface of the conductive feature 106, According to an embodiment.

This process can continue as in FIG. 14, which illustrates a cross-sectional view of the IC 104 of FIG. 13 after forming the barrier layer 112, in accordance with an embodiment of the present invention. As can be seen herein, the barrier layer 112 can be disposed over portions of the barrier layer 108 and the hard mask layer 110 along the sidewalls of the conductive features 106. When forming the barrier layer 112, it may be desirable to remove portions thereof deposited over the hard mask layer 110 to ensure that the upper surface of the component hard mask of the hard mask layer 110 remains exposed. At the same time, it may be desirable to remove portions of the barrier layer 112 that are deposited over portions of the barrier layer 108 between adjacent conductive features 106. To these ends, partial removal of the barrier layer 112 can be performed via any suitable standard, custom, or proprietary directional etching technique, as will be apparent from this description.

As can be seen from FIG. 14, for example, barrier layer 112 can be formed (according to certain embodiments) to extend from barrier layer 104, along barrier layer 108 over the sidewalls of conductive features 106, and along hard mask layer 110. Component hard mask Side wall. In some examples, the barrier layer 112 can extend the full height of the barrier layer 108 and the hard mask layer 110 upward, while in some other examples, the barrier layer can extend upwardly less than its full height. As further seen from FIG. 4, features 114a may exist between adjacent conductive features 106 due to the particular interface of barrier layers 112 and 108 between such conductive features 106.

This process can continue as shown in FIG. 15, which illustrates a cross-sectional view of the IC 104 of FIG. 14 after forming features 114b from a predetermined feature 114a, in accordance with an embodiment of the present invention. As can be seen, the predetermined features 114a can undergo additional patterning, for example, to provide features 114b. In some cases, complex features 114b can be formed to provide a second set of conductive features 106 (eg, the first set is formed as discussed above with respect to FIG. 1). To these ends, the established features 114b can be formed in any of the example techniques and configurations discussed above, for example, for features 114b in the context of FIG. As discussed above, FIG. 6 is provided, 114b (and 114a, as discussed above) in feature 15 of FIG herein may be patterned on alternate grooves so that the pitch P of the IC 104 which is about ₁ Halve.

At this point in the process flow, there are a wide range of options for how to proceed with manufacturing. For example, all (or a subset) of features 114a and 114b of IC 104 can be filled with a conductive material, in accordance with certain embodiments. Thus, the resulting IC 104 may have a pitch P ₂ of the conductive features 106, the pitch P ₂ may be a part of the _{original. 1} pitch P of the IC 104. In an exemplary case, the pitch P ₂ may be about half of the pitch P ₁ (eg, if P ₁ = 2 x , then P ₂ = x ). In some cases, the newly formed conductive features 106 can be of the same material composition as the original conductive features 106 previously formed. In other cases, different conductive materials may be utilized such that the IC 104 controls one or more conductive features 106 of the first material composition and one or more conductive features 106 of the second, different material composition.

In some cases, after filling all (or a subset) of features 114a and 114b, IC 104 can optionally undergo any of the CMP processes and etch and clean processes (or combinations), for example, to In addition to the barrier layer 112, the hard mask layer 110, and any unwanted portions of the barrier layer 108, and any excess (e.g., overload) conductive features 106 that may be present. However, in other cases, the hard mask layer 110 can be allowed to remain on top of the IC 104.

In other cases, after filling all (or a subset) of features 114a and 114b, IC 104 may optionally undergo a recess process in which conductive features 106 are recessed below barrier layer 112 and hard mask layer 110. height. For example, consider Figure 16, which illustrates a cross-sectional view of an IC 104 configured in accordance with an embodiment of the present invention. The depressions of the conductive features 106 can be performed via any suitable standard, customary, or proprietary etching and cleaning techniques, as will be apparent from this disclosure.

In some cases, after the recessed conductive features 106 are as in FIG. 16, the IC 104 can optionally undergo one or more additional processes. For example, consider Figure 17, which illustrates a cross-sectional view of IC 104 after formation of hard mask layer 116, in accordance with an embodiment of the present invention. As can be seen, the hard mask layer 116 can be formed in any one or more of the desired features 114a and 114b, over the conductive features 106, in accordance with certain embodiments. As will be understood from this description, the hard mask layer 116 can be formed as an example material as discussed above Any of the materials, techniques, and configurations, for example, for the hard mask layer 110, in accordance with certain embodiments. In some cases, the hard mask layer 116 and the hard mask layer 110 can have different material compositions, providing etch selectivity to each other.

According to certain embodiments, after forming the hard mask layer 116, the IC 104 may undergo selective removal of the dielectric layer 118, at least a portion of any one or both of its hard mask layers 110 and 116, And further formation of the predetermined conductive features 106. For example, consider Figure 18, which illustrates a cross-sectional view of an IC 104 configured in accordance with an embodiment of the present invention. As can be seen herein, the dielectric layer 118 can be patterned with one or more features 118a, the size and geometry of which can be customized, such as intended for a given target application or terminal. In some cases, the predetermined features 118a can be formed to land (at least in part) over a portion of the hard mask layer 116 and under the conductive features 106. After patterning this feature 118a, a portion of the underlying hard mask layer 116 can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114b. In accordance with an embodiment, an additional conductive material can be deposited over the newly exposed conductive features 106 that allow the resulting conductive features 106a to extend upward through the patterned features 118a in the dielectric layer 118. In an exemplary case, the vias (or other conductive features) of the next overlying layer may be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106a across the two IC layers.

Figure 19 illustrates a cross-sectional view of an IC 104 configured in accordance with another embodiment of the present invention. As seen from FIG. 11, dielectric layer 118 Additionally (or alternatively) may be patterned with one or more features 118b, the size and geometry of which may be customized, such as for a given target application or terminal use. In some cases, the predetermined feature 118b can be formed to land (at least in part) over a portion of the hard mask layer 110 and below the conductive features 106. After patterning this feature 118b, a portion of the underlying hard mask layer 110 can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114a. In accordance with an embodiment, an additional conductive material can be deposited over the newly exposed conductive features 106 that allow the resulting conductive features 106a to extend upward through the patterned features 118b in the dielectric layer 118. In an exemplary case, the vias (or other conductive features) of the next overlying layer can be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106b across the two IC layers. As shown in FIG. 19, conductive features 106a may alternatively be present in IC 104, although IC 104 need not have such a configuration.

As can be seen generally in Figures 18-19, in some cases, the use of the disclosed techniques can tolerate improved EPE tolerance, in accordance with certain embodiments. As further seen in Figures 18-19, the hard mask layer 110 (e.g., the helmet-like hard mask) and the hard mask layer 116 can exhibit etch selectivity, in accordance with certain embodiments.

Eliminate the patterning technology and structure:

20-28 illustrate a process flow for fabricating an IC 105 in accordance with another embodiment of the present invention. This process can begin as shown in Figure 20, which illustrates a cross-sectional view of an IC 105 configured in accordance with an embodiment of the present invention. As here See, IC 105 includes a semiconductor substrate 102 and a conductive layer 106 disposed thereon, each as discussed above.

This process flow can continue as in FIG. 21, which illustrates a cross-sectional view of IC 105 of FIG. 20 after patterned conductive layer 106 is one or more conductive features 106, in accordance with an embodiment of the present invention. Patterning of conductive layer 106 can be performed by any suitable standard, custom, or proprietary lithography, etching, and cleaning (or other erasing patterning) techniques, as will be apparent from this disclosure. In some cases, conductive features 106 may be formed from conductive layer 106 via any one (or combination) of etching processes. The given etching process can be an anisotropic etch involving wet etching or dry etching (or both), and the specific etching chemistry utilized by the intended application etching process can be customized, such as for a given target application or terminal. Use what you want. Patterning of conductive layer 106 can be controlled to provide both quantitative symmetry/asymmetry and isotropic/anisotropic, as desired. According to certain embodiments, the patterning of the conductive layer 106 can be performed until the upper surface of the underlying semiconductor substrate 102 is reached, such as generally shown in FIG.

This process flow can continue as shown in FIG. 22, which illustrates a cross-sectional view of the IC 105 of FIG. 21 after forming the barrier layer 108, in accordance with an embodiment of the present invention. As can be seen herein, the IC 105 includes a barrier layer 108 that extends over the sidewalls (but not the top surface) of the conductive features 106. Therefore, the upper surface of the conductive feature 106 remains exposed. This is compared to the barrier layer 108 of FIG. 3 (as discussed above), which is instead conformal to the top surface of the conductive feature 106, as well as its sidewalls.

This process can continue as shown in FIG. 23, which illustrates the formation of the hard mask layer 110. A cross-sectional view of the IC 105 of Figure 22 follows, in accordance with an embodiment of the present invention. As can be seen herein, a hard mask layer 110 (eg, one or more hard mask bodies, as discussed above) can be disposed (and directly in contact with) the top surface of the conductive features 106, along along the conductive features The end of the portion of the barrier layer 108 of 106, in accordance with an embodiment. Comparing this with the hard mask layer 110 of FIG. 4 (as discussed above), which instead resides (and directly contacts) a portion of the barrier layer 108 that conforms to the top surface of the conductive feature 106, According to an embodiment.

This process can continue as shown in Figure 24, which illustrates a cross-sectional view of the IC 105 of Figure 23 after forming the barrier layer 112, in accordance with an embodiment of the present invention. As can be seen herein, the barrier layer 112 can be disposed over portions of the barrier layer 108 and the hard mask layer 110 along the sidewalls of the conductive features 106. As previously discussed, when forming the barrier layer 112, it may be desirable to remove portions thereof deposited over the hard mask layer 110 to ensure that the upper surface of the component hard mask of the hard mask layer 110 remains exposed. At the same time, it may be desirable to remove portions of the barrier layer 112 that are deposited over portions of the barrier layer 108 between adjacent conductive features 106.

As can be seen from FIG. 24, for example, barrier layer 112 can be formed (according to certain embodiments) to extend from semiconductor substrate 102, along barrier layer 108 over sidewalls of conductive features 106, and along hard mask layer 110. The component is a side wall of the hard mask. In some examples, the barrier layer 112 can extend the full height of the barrier layer 108 and the hard mask layer 110 upward, while in some other examples, the barrier layer can extend upwardly less than its full height. As further seen from FIG. 24, features 114a may exist between adjacent conductive features 106 due to this A particular interface of the barrier layers 112 and 108 between the electrically conductive features 106.

At this point in the process flow, there are a wide range of options for how to proceed with manufacturing. For example, all (or a subset) of features 114a of IC 105 can be filled with a conductive material, in accordance with certain embodiments. Thus, the resulting IC 105 may have a pitch P ₂ of the conductive features 106, the pitch P ₂ may be a part of the IC 105 of the original pitch of _{P. 1.} In an exemplary case, the pitch P ₂ may be about half of the pitch P ₁ (eg, if P ₁ = 2 x , then P ₂ = x ). In some cases, the newly formed conductive features 106 can be of the same material composition as the original conductive features 106 previously formed. In other cases, different conductive materials may be utilized such that the IC 105 controls one or more conductive features 106 of the first material composition and one or more conductive features 106 of the second, different material composition.

In some cases, after filling all (or a subset) of features 114a, IC 105 can optionally undergo any of the CMP processes and etch and clean processes (or combinations), for example, to remove barriers Any unwanted portions of layer 112, hard mask layer 110, and barrier layer 108, as well as any excess (e.g., overload) conductive features 106 that may be present. However, in other cases, the hard mask layer 110 may be allowed to remain on the IC 105.

In other cases, after filling all (or a subset) of features 114a, IC 105 may optionally undergo a recess process in which conductive features 106 are recessed below the height of barrier layer 112 and hard mask layer 110. For example, consider Figure 25, which illustrates a cross-sectional view of an IC 105 configured in accordance with an embodiment of the present invention. The recess of the conductive feature 106 can be performed via any suitable standard, custom, or proprietary etching and cleaning techniques, such as This description will be clear to the reader.

In some cases, after the recessed conductive features 106 are as in FIG. 25, the IC 105 can optionally undergo one or more additional processes. For example, consider Figure 26, which illustrates a cross-sectional view of IC 105 after formation of hard mask layer 116, in accordance with an embodiment of the present invention. As can be seen, the hard mask layer 116 can be formed in any one or more of the desired features 114a, over the conductive features 106, in accordance with certain embodiments. In some cases, the hard mask layer 116 and the hard mask layer 110 can have different material compositions, providing etch selectivity to each other.

According to certain embodiments, after forming the hard mask layer 116, the IC 105 may undergo selective removal of the dielectric layer 118, at least a portion of any one or both of its hard mask layers 110 and 116, And further formation of the predetermined conductive features 106. For example, consider Figure 27, which illustrates a cross-sectional view of an IC 105 configured in accordance with an embodiment of the present invention. As seen herein in Figure 27, the dielectric layer 118 can be patterned with one or more features 118a, the size and geometry of which can be customized, such as for a given target application or terminal use. In some cases, the predetermined features 118a can be formed to land (at least in part) over a portion of the hard mask layer 116 and under the conductive features 106. After patterning this feature 118a, a portion of the underlying hard mask layer 116 can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114a. In accordance with an embodiment, an additional conductive material can be deposited over the newly exposed conductive features 106 that allow the resulting conductive features 106a to extend upward through the patterned features 118a in the dielectric layer 118. Yu Yifan In one example, the vias (or other conductive features) of the next overlying layer can be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106a across the two IC layers.

Figure 28 illustrates a cross-sectional view of an IC 105 configured in accordance with another embodiment of the present invention. As can be seen from FIG. 28, the dielectric layer 118 can additionally (or alternatively) be patterned with one or more features 118b, the size and geometry of which can be customized, such as for a given target application or terminal. Those who want it. In some cases, the predetermined feature 118b can be formed to land (at least in part) over a portion of the hard mask layer 110 and below the conductive features 106. After patterning this feature 118b, a portion of the underlying hard mask layer 110 can be selectively removed (eg, selectively etched away) to expose, for example, the underlying conductive features 106 controlled by features 114a. In accordance with an embodiment, additional metal can be deposited over the newly exposed conductive features 106, which allows the resulting conductive features 106b to extend upward through the patterned features 118b in the dielectric layer 118. In an exemplary case, the vias (or other conductive features) of the next overlying layer can be landed (partially or integrally) over the conductive features 106, resulting in conductive features 106b across the two IC layers. As shown in FIG. 28, conductive features 106a may alternatively be present in IC 105, although IC 105 need not have such a configuration.

As can be seen generally in Figures 27-28, in some cases, the use of the disclosed techniques can tolerate improved EPE tolerance, in accordance with certain embodiments. As further seen in Figures 27-28, the hard mask layer 110 (e.g., helmet-like hard mask) and hard mask layer 116 can exhibit etch selectivity, in accordance with certain embodiments.

As will be understood from this description, the process flow of Figures 1-9 can be considered (in a general sense) for a tessellation-based patterning process having a dielectric (e.g., ILD) recess, in accordance with certain embodiments. However, the process flow of Figures 20-28 can be considered (in a general sense) to eliminate conductive material (e.g., metal) patterning processes, in accordance with certain embodiments. Various appropriate uses of the techniques disclosed herein will be apparent from the description.

Sample system

29 illustrates a computing system 1000 implemented in an integrated circuit structure or apparatus that is formed using the disclosed techniques in accordance with an exemplary embodiment. As can be seen, computing system 1000 includes a motherboard 1002. The motherboard 1002 can include a number of components including, but not limited to, the processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or integrated therein. As will be appreciated, the motherboard 1002 can be, for example, any printed circuit board, whether it be a motherboard, a daughter board mounted on a motherboard, or the only board of the system 1000, and the like. Computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to motherboard 1002, depending on its application. These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, Display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and A large number of storage devices (such as hard disk drives, compact discs (CDs), digital compact discs (DVDs), etc.). Any of the components included in computing system 1000 can include one or more integrated circuit structures or devices that are formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions may be integrated into one or more wafers (eg, note that communication chip 1006 may be part of processor 1004 or integrated into processor 1004).

The communication chip 1006 enables wireless communication for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like, which may convey data by using modulated electromagnetic radiation transmitted through a non-solid medium. The term does not imply that its associated device does not contain any wiring, although in some embodiments it may not. The communication chip 1006 can implement any of several wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing system 1000 can include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. , Ev-DO and others.

Processor 1004 of computing system 1000 includes integrated circuit dies that are packaged within processor 1004. In some embodiments, the processor product The bulk circuit die includes on-board circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as described in various places herein. The term "processor" may refer to any device or portion of a device that processes, for example, electronic data from a register and/or memory to convert the electronic data into a memory and/or memory that can be stored in a register. Other electronic materials in the body.

The communication chip 1006 can also include integrated circuit dies that are packaged in the communication chip 1006. In accordance with certain such exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be understood in light of this description, it is noted that multiple standard wireless capabilities can be directly integrated into processor 1004 (eg, where the functionality of any of the wafers 1006 is integrated into processor 1004, rather than having separate communication chips). It is further noted that the processor 1004 can be a chipset having such wireless capabilities. In short, any number of processors 1004 and/or communication chips 1006 can be used. Similarly, any wafer or wafer set can have multiple functions integrated into it.

In various embodiments, the computing system 1000 can be a laptop, a small notebook, a notebook, a smart phone, an input pad, a personal digital assistant (PDA), an ultra-light mobile PC, a mobile phone, a desktop computer. , server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or uses it One or more integrated circuit structures or devices formed by the techniques are disclosed, as described in various places herein.

Further example embodiments

The following examples are directed to further embodiments from which various variations and configurations will be apparent.

Example 1 is an integrated circuit comprising: a substrate; first and second conductive features disposed on the substrate; a first barrier layer disposed on the substrate, wherein the first barrier layer extends along the a sidewall of each of the first and second conductive features; a first hard mask layer disposed over the substrate, wherein the first hard mask layer comprises substantially individually disposed on the first and second conductive layers At least first and second hard masks over the top surface of the feature; and a second barrier layer disposed over the substrate, wherein the second barrier layer extends along the first barrier layer, Above the sidewalls of each of the first and second conductive features, and along the sidewalls of the first and second rigid masks.

Example 2 includes the request target of any of Examples 1 and 3-15 and further comprising a third conductive feature disposed on the substrate between the first and second conductive features.

Example 3 includes the request target of Example 2, wherein the pitches of the first and second conductive features are about one-half of the pitch of the first and third conductive features.

Example 4 includes the request target of Example 2, wherein the first, second, and third conductive features have substantially the same height.

Example 5 includes the request target of Example 2, wherein at least one of the first, second, and third conductive features comprises copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt ( At least one of Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta).

Example 6 includes the request target of Example 2, wherein the third conductive feature has a different material composition than the first and second conductive features.

Example 7 includes the request target of Example 2 and further comprising a second hard mask layer disposed over a top surface of the third conductive feature, wherein the first and second hard mask layers are from the second barrier layer Separated physically.

Example 8 includes the request of Example 7, wherein the first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other.

Example 9 includes the request target of Example 7 and further comprising a dielectric layer disposed over the topography, the topography being provided by at least the first and second hard mask layers and the second barrier layer.

Example 10 includes the request target of Example 9, wherein at least one of the first, second, and third conductive features extends into the dielectric layer.

Example 11 includes the subject matter of any of Examples 1-10 and 12-15, wherein: the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), cerium oxide ( At least one of SiO ₂ ), lanthanum carbonitride (SiCN), and yttrium oxynitride (SiO _x N _y ); and at least one of the first and second hard masks has a thickness of about 5-20 nm The thickness within the range.

The example 12 includes the request target of any of the examples 1-11 and 13-15, wherein at least one of the first and second hard masks is configured to prevent leakage therethrough.

Example 13 includes the subject matter of any of Examples 1-12 and 14-15, wherein at least one of the first and second barrier layers comprises yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), And at least one of titanium oxide (TiO ₂ ).

The example 14 includes the request target of any of the examples 1-13 and 15, wherein the substrate comprises at least one of bismuth (Si), germanium (Ge), and germanium (SiGe).

Example 15 includes the request target of any of Examples 1-14, wherein the substrate is configured as at least one of a bulk semiconductor substrate, a semiconductor-on-insulator structure, a semiconductor wafer, and a multilayer structure.

Example 16 is a method of fabricating an integrated circuit, the method comprising: forming first and second conductive features on a substrate; forming a first barrier layer over the substrate, wherein the first barrier layer extends along the a sidewall of each of the first and second conductive features; forming a first hard mask layer over the substrate, wherein the first hard mask layer comprises substantially individually disposed on the first and second conductive features At least first and second hard masks over the top surface; and forming a second barrier layer over the substrate, wherein the second barrier layer extends along the first barrier layer, Above the sidewalls of each of the second conductive features, and along the sidewalls of the first and second rigid masks.

Example 17 includes the request target of any of Examples 16 and 18-30, wherein forming the first hard mask layer involves at least one of a physical vapor deposition (PVD) process and a chemical vapor deposition (CVD) process.

Example 18 includes the request target of any of Examples 16-17 and 19-30 and further comprising forming a third conductive feature on the substrate between the first and second conductive features.

Example 19 includes the request target of Example 18, wherein the pitches of the first and second conductive features are approximately the pitch of the first and third conductive features half.

Example 20 includes the request target of Example 18, wherein the first, second, and third conductive features have substantially the same height.

Example 21 includes the request target of Example 18, wherein the third conductive feature has a different material composition than the first and second conductive features.

Example 22 includes the request target of Example 18 and further comprising forming a second hard mask layer over the top surface of the third conductive feature, wherein the first and second hard mask layers are comprised by the second barrier layer Physically separated.

Example 23 includes the request of Example 22, wherein the first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other.

Example 24 includes the request target of Example 22 and further includes forming a dielectric layer over the topography, the topography being provided by at least the first and second hard mask layers and the second barrier layer.

Example 25 includes the request target of Example 24 and further comprising: etching through a portion of the dielectric layer; selectively removing at least one of the first and second hard masks to reveal the first and second conductive The top surface of at least one of the features; and further forming the at least one of the first and second conductive features such that at least one of the first and second conductive features extend into the dielectric layer.

Example 26 includes the request target of Example 24 and further comprising: etching through a portion of the dielectric layer; selectively removing the second hard mask layer from the third conductive feature to reveal the top surface of the third conductive feature; And further forming the third conductive feature such that the third conductive characteristic is extended Extend into the dielectric layer.

Example 27 includes the subject matter of any of Examples 16-26 and 28-30, wherein: the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), cerium oxide ( At least one of SiO ₂ ), lanthanum carbonitride (SiCN), and yttrium oxynitride (SiO _x N _y ); and at least one of the first and second hard masks has a thickness of about 5-20 nm The thickness within the range.

The example 28 includes the request of any of the examples 16-27 and 29-30, wherein at least one of the first and second hard masks is configured to prevent leakage therethrough.

Example 29 includes the request target of any of Examples 16-28 and 30, wherein the substrate comprises at least one of germanium (Si), germanium (Ge), and germanium (SiGe).

The example 30 includes the request target of any of the examples 16-29, wherein the substrate is configured as at least one of a bulk semiconductor substrate, a semiconductor-on-insulator structure, a semiconductor wafer, and a multilayer structure.

Example 13 is an integrated circuit comprising: a substrate; a first plurality of conductive features disposed on the substrate; a second plurality of conductive features disposed on the substrate, wherein the components of the second plurality of conductive features are conductive a pitch of a characteristic conductive feature of the first plurality of conductive features and a pitch of about two consecutive component conductive features of the first plurality of conductive features; a first barrier disposed over the substrate a layer, wherein the first barrier layer extends along a sidewall of the at least one component conductive feature of the first plurality of conductive features; the first hard mask layer includes at least one of the first plurality of conductive features disposed At least the entire top surface of the component conductive features to a second hard mask layer disposed on the substrate, wherein the second barrier layer extends along the first hard mask layer, and the at least one set of the first plurality of conductive features And a sidewall of the at least one hard mask along the sidewall of the first hard mask layer.

The example 32 includes the request target of any one of the examples 31 and 33-43, wherein the at least one component conductive feature of the first plurality of conductive features and the at least one component conductive feature of the second plurality of conductive features have substantially The same height.

The example 33 includes the request of any one of the examples 31-32 and 34-43, wherein the at least one component conductive feature of the first plurality of conductive features has at least one component conductive characteristic with the second plurality of conductive features Different material composition.

The example 34 includes the request target of any of the examples 31-33 and 35-43 and further comprising a second hard mask layer including at least the entire top portion of the at least one component conductive feature disposed on the second plurality of conductive features At least one hard mask over the surface, wherein the at least one hard mask of the second hard mask layer and the at least one hard mask system of the first hard mask layer are Physically separated.

Example 35 includes the request of Example 34, wherein the first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other.

Example 36 includes the request target of Example 34 and further includes a dielectric layer disposed over the topography, the topography being provided by at least the first and second hard mask layers and the second barrier layer.

The example 37 includes the request target of example 36, wherein at least one component conductive characteristic of at least one of the first plurality of conductive features and the second plurality of conductive features extends into the dielectric layer.

The example 38 includes the request of any one of the examples 31-37 and 39-43, wherein the first barrier layer is further disposed on the at least one component conductive feature of the first plurality of conductive features and disposed thereon Between the at least one hard mask of the first hard mask layer.

Example 39 includes the subject matter of any of Examples 31-38 and 40-43, wherein: the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), cerium oxide ( At least one of SiO ₂ ), lanthanum carbonitride (SiCN), and yttrium oxynitride (SiO _x N _y ); and the at least one hard mask of the first hard mask layer has a thickness of about 5-20 nm The thickness within the range.

The example 40 includes the request of any of the examples 31-39 and 41-43, wherein the at least one hard mask system of the first hard mask layer is configured to prevent leakage therethrough.

The example 41 includes the subject matter of any of the examples 31-40 and 42-43, wherein at least one of the first and second barrier layers comprises cerium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), And at least one of titanium oxide (TiO ₂ ).

The example 42 includes the request target of any of the examples 31-41 and 43, wherein the substrate comprises at least one of germanium (Si), germanium (Ge), and germanium (SiGe).

The example 43 includes the request target of any of the examples 31-42, wherein the substrate is configured as at least one of a bulk semiconductor substrate, a semiconductor-on-insulator structure, a semiconductor wafer, and a multilayer structure.

The foregoing description of the example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many configurations and variations will be possible in accordance with this specification. The scope of the present invention is intended to be limited by the scope of the appended claims. Future applications that claim priority to this application may claim the claimed subject matter in various ways, and may generally include any collection of one or more limitations as variously disclosed or otherwise shown herein.

100‧‧‧Integrated Circuit (IC)

102‧‧‧Semiconductor substrate

104‧‧‧ dielectric layer

106‧‧‧Electrical characteristics

108‧‧‧Baffle layer

110‧‧‧hard mask layer

112‧‧‧Baffle layer

114a‧‧‧Characteristics

114b‧‧‧Characteristics

Claims (23)

An integrated circuit comprising: a substrate; first and second conductive features disposed on the substrate; a first barrier layer disposed on the substrate, wherein the first barrier layer is along the first sum a sidewall extending from each of the second conductive features; a first hard mask layer disposed on the substrate, wherein the first hard mask layer comprises a top surface disposed entirely on the first and second conductive features At least first and second hard mask bodies thereon; and a second barrier layer disposed on the substrate, wherein the second barrier layer is along the first barrier layer, the first and second conductive layers Over the sidewalls of each of the features, and along the sidewalls of the first and second rigid masks. The integrated circuit of claim 1, further comprising a third conductive feature disposed on the substrate between the first and second conductive features. The integrated circuit of claim 2, wherein the first and second conductive features have a pitch of about half of a pitch of the first and third conductive features. The integrated circuit of claim 2, wherein the first, second, and third conductive features have substantially the same height. The integrated circuit of claim 2, further comprising a second hard mask layer disposed on a top surface of the third conductive feature, wherein: the first and second hard mask layers are The second barrier layer is physically Separating; and the first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other. The integrated circuit of claim 1, wherein the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), cerium oxide (SiO ₂ ), carbonitriding. At least one of bismuth (SiCN) and bismuth oxynitride (SiO _x N _y ); and at least one of the first and second hard masks has a thickness in the range of about 5-20 nm. The integrated circuit of claim 1, wherein at least one of the first and second hard masks is configured to prevent leakage therethrough. A method of fabricating an integrated circuit, the method comprising: forming first and second conductive features on a substrate; forming a first barrier layer over the substrate, wherein the first barrier layer extends along the first sum a sidewall of each of the second conductive features; forming a first hard mask layer over the substrate, wherein the first hard mask layer comprises substantially individually disposed on top surfaces of the first and second conductive features At least first and second hard masks thereon; and forming a second barrier layer over the substrate, wherein the second barrier layer extends along the first barrier layer, the first and second conductive layers Above the sidewalls of each of the features, and along the sidewalls of the first and second rigid masks. The method of claim 8, wherein the forming the first hard mask layer involves a physical vapor deposition (PVD) process and chemical vapor deposition At least one of the (CVD) processes. The method of claim 8, further comprising: forming a third conductive feature on the substrate between the first and second conductive features. The method of claim 10, wherein the first and second conductive features have a pitch that is about one-half of a pitch of the first and third conductive features. The method of claim 10, wherein the first, second, and third conductive features have substantially the same height. The method of claim 10, wherein the third conductive feature has a different material composition than the first and second conductive features. The method of claim 10, further comprising: forming a second hard mask layer over the top surface of the third conductive feature, wherein: the first and second hard mask layers are The barrier layers are physically separated; and the first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other. The method of claim 14, further comprising: forming a dielectric layer over the topography, the topography being provided by at least the first and second hard mask layers and the second barrier layer. The method of claim 15, further comprising: etching through a portion of the dielectric layer; selectively removing at least one of the first and second hard masks, Exposing the top surface of at least one of the first and second conductive features; and further forming the at least one of the first and second conductive features such that the at least one of the first and second conductive features One extends into the dielectric layer. The method of claim 15, further comprising: etching through a portion of the dielectric layer; selectively removing the second hard mask layer from the third conductive feature to expose the top surface of the third conductive feature And further forming the third conductive feature such that the third conductive feature extends into the dielectric layer. The method of claim 8, wherein the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), hafnium oxide (SiO ₂ ), niobium carbonitride ( At least one of SiCN) and yttrium oxynitride (SiO _x N _y ); and at least one of the first and second hard masks has a thickness in the range of about 5-20 nm. An integrated circuit comprising: a substrate; a first plurality of conductive features disposed on the substrate; a second plurality of conductive features disposed on the substrate, wherein the conductive features of the second plurality of conductive features are The pitch of the conductive features of the first plurality of conductive features is about one-half the pitch of the conductive features of the two consecutive components of the first plurality of conductive features; a first barrier layer disposed on the substrate, wherein the first barrier layer extends along a sidewall of the at least one component conductive feature of the first plurality of conductive features; the first hard mask layer includes At least one hard mask over at least the entire top surface of the at least one component conductive feature of the first plurality of conductive features; and a second barrier layer disposed over the substrate, wherein the second barrier layer extends along the second barrier layer The first barrier layer is over the sidewalls of the at least one component conductive features of the first plurality of conductive features and along the sidewalls of the at least one hard mask of the first hard mask layer. The integrated circuit of claim 19, wherein the at least one component conductive feature of the first plurality of conductive features has substantially the same height as the at least one component conductive feature of the second plurality of conductive features. The integrated circuit of claim 19, further comprising a second hard mask layer comprising at least one hard surface disposed over at least the entire top surface of the at least one component conductive feature of the second plurality of conductive features a mask body, wherein: the at least one hard mask of the second hard mask layer and the at least one hard mask system of the first hard mask layer are physically separated by the second barrier layer; The first and second hard mask layers have different material compositions such that they exhibit etch selectivity with respect to each other. The integrated circuit of claim 19, wherein the first barrier layer is further disposed on the at least one of the first plurality of conductive features A plurality of electrically conductive features are disposed between the at least one rigid mask of the first hard mask layer disposed thereon. The integrated circuit of claim 19, wherein the first hard mask layer comprises titanium nitride (TiN), tantalum nitride (Si ₃ N ₄ ), cerium oxide (SiO ₂ ), carbonitriding. At least one of bismuth (SiCN) and bismuth oxynitride (SiO _x N _y ); and the at least one hard mask of the first hard mask layer has a thickness in a range of about 5-20 nm.