TW201734486A - Method, system for utilizing a probe card device, and the probe card device - Google Patents

Abstract

A method for utilizing a probe card device includes steps as follows. Providing a probe card device having three identified marks on a reference plane of a circuit board; moving the reference plane to face a wafer-loading plane of a wafer stage; determining whether a coplanar defined by the identified marks is parallel with the wafer-loading plane; and adjusting the planarity of the circuit board until the reference plane is parallel with the wafer-loading plane when the coplanar is not parallel with the wafer-loading plane.

Description

Method, system and probe card device using probe card

The present invention relates to a method, system and probe card device for using a probe card.

The conventional probe card device touches the electrical terminals of the Device Under Test (DUT) through a plurality of probes for accessing the test object. Generally, the probe card device must be installed horizontally before the probe card device is tested. In the conventional manner, the probe card device is based on the plane defined by the tip end of the probes as the level.

However, if the height difference of these probes is too large, the tip ends of these probes cannot define a distinct plane, and it is difficult to control the level of the probe card device itself, and it is impossible to ensure that these probes can be fully and surely contacted. All electrical terminals to the object under test, resulting in inaccurate test performance.

To this end, if we can provide a solution design that can solve the above requirements and let the industry stand out from the competition, it becomes an important issue to be solved urgently.

In view of the above, it is an object of the present invention to provide a method, system and probe card apparatus for using the probe card to solve the difficulties mentioned in the prior art.

According to an embodiment of the present invention, the method of using the probe card comprises the steps (a) to (e) as follows. In the step (a), a probe card device is provided. The probe card device has a circuit substrate and a plurality of probes. The reference plane of the circuit substrate has at least three first identification marks that are not collinear, and the first identification The mark is coplanar with the reference plane; in step (b), the probe card device is moved such that the reference plane faces one of the wafer carrier faces of a stage; in step (c), the first identification mark is determined Whether the first coplanar surface is parallel to the wafer bearing surface; in step (d), when the first coplanar non-parallel wafer bearing surface is determined, the level of the circuit substrate is adjusted; in step (e), These probes are touched and tested on one of the wafers carried on the wafer carrier.

Thus, the first common surface defined by the first identification marks is used as a probe in the present embodiment as compared with the virtual plane defined by the needle ends of the probes as the evaluation level of the probe card device. The evaluation criteria of the level of the card device makes it easier to ensure that the probe card device and the wafer carrying surface of the stage are parallel to each other, so that the probes can more fully and surely contact all the electrical terminals of the object to be tested, thereby maintaining Test performance accuracy.

In one or more embodiments of the present invention, the above step (c) further comprises the following steps. These first identification marks of the reference plane are respectively detected. The coordinate positions of these first identification marks are analyzed. According to these first identification marks The coordinate position calculates a first plane function of the first coplanar surface in a three-dimensional coordinate system. Determining whether the first plane function is parallel to a second plane function of the wafer carrying surface. When it is judged that the first plane function is not parallel to the second plane function, it is determined that the reference plane is not parallel to the wafer carrying surface.

In one or more embodiments of the present invention, before the step (c) determines whether the first plane function is parallel to the second plane function, the steps are further included as follows. Detecting at least three non-collinear second identification marks on the wafer carrying surface, the second identification marks being coplanar with the wafer carrying surface; analyzing the coordinate positions of the second identifying marks; and determining the second identifying marks according to the second identifying marks At the coordinate position, a second plane function of the wafer bearing surface in the three-dimensional coordinate system is calculated.

In one or more embodiments of the present invention, the above step (d) further comprises the following steps. Adjusting at least one of a plurality of fine adjustment screws provided on the circuit substrate to adjust the level of the reference plane of the circuit substrate.

In one or more embodiments of the present invention, the above step (a) further comprises the following steps. The reference plane of the circuit substrate is parallel to the tip end of the probes to define a virtual plane.

In one or more embodiments of the present invention, the step of making the reference plane parallel to the virtual plane further includes the following steps. Detecting the first identification marks respectively; analyzing the coordinate positions of the first identification marks; and calculating a first plane function of the first coplanar surface in a three-dimensional coordinate system according to the coordinate positions of the first identification marks Detecting the end of the needle of the probes together to define a virtual plane, and calculating a third plane function according to the virtual plane; determining whether the first plane function of the reference plane is parallel to the third plane function of the virtual plane; The first plane function is not parallel to the third plane function, adjust this For some needle positions, the third plane function of the virtual plane is again detected and calculated, the first plane function is determined to be parallel to the third plane function, and the step of adjusting the needle position is performed until the first plane function is parallel to the third plane function.

In one or more embodiments of the present invention, the step of making the reference plane parallel to the virtual plane further includes the following steps. Determining whether the probe needle ends are flush with each other and jointly defining a virtual plane; when it is judged that the probe needle ends cannot jointly define a virtual plane, adjusting the probe needle ends; and repeatedly determining whether the probe needle ends are commonly defined The virtual planes and the steps of adjusting the ends of the probe needles are made until the ends of the probe needles are flush with each other to define a virtual plane.

According to another embodiment of the present invention, such a system using a probe card includes a stage, a probe card device, a movable carrier, a level determining device, and a horizontal fine adjustment device. The stage has a wafer carrying surface for carrying one of the wafers. The probe card device has a circuit substrate and a plurality of probes. The circuit substrate has a reference plane, and the reference plane has at least three first identification marks that are not collinear, and the first identification marks are coplanar with the reference plane. The needle ends of these probes collectively define a virtual plane, and the virtual planes are parallel to the reference plane. The movable carrier is used to move the circuit substrate such that the reference plane faces the wafer carrying surface. The level determining device is configured to determine whether the first coplanar surface defined by the first identification marks is parallel to the wafer carrying surface. The horizontal fine adjustment device is used to adjust the level of the circuit substrate.

In one or more embodiments of the present invention, the level determining apparatus includes a first image capturing unit, an image processing unit, a computing unit, and a determining unit. The first image capturing unit is configured to include the first identification marks The reference plane captures a first image. The image processing unit is electrically connected to the first image capturing unit for analyzing the first image to obtain coordinate positions of the first identification marks. The computing unit is electrically connected to the first image capturing unit and the image processing unit for calculating a first plane function of the first coplanar surface according to the coordinate positions of the first identification marks. The determining unit is electrically connected to the calculating unit for determining whether the first plane function is parallel to a second plane function of the wafer carrying surface.

In one or more embodiments of the present invention, the horizontal fine adjustment module includes at least three fine adjustment screws, which are respectively screwed on the circuit substrate.

In one or more embodiments of the present invention, the wafer carrying surface has at least three second identifying marks that are not collinear, and the second identifying marks are coplanar with the wafer carrying surface.

In one or more embodiments of the present invention, the level determining device further includes a second image capturing unit. The second image capturing unit is configured to capture a second image of the wafer carrying surface including the second identification marks. The image processing unit analyzes the second image to obtain coordinate positions of the second identification marks, and the calculating unit calculates a second plane function of the wafer bearing surface according to the coordinate positions of the second identification marks.

In one or more embodiments of the invention, the first identification marks are arranged in a triangular manner.

In one or more embodiments of the invention, the probes are coupled to a reference plane.

In one or more embodiments of the present invention, the first identification marks are respectively located at outer edge positions of the reference plane.

According to still another embodiment of the present invention, the probe card device comprises a support frame, a circuit substrate, a plurality of probes and at least three fine adjustment screws. The support frame has a frame. The circuit board is framed on the support frame. One of the reference planes of the circuit substrate is exposed to the frame, and the reference plane has at least three identification marks that are not collinear with each other, and the reference plane and the identification mark are coplanar in the same plane. These probes are connected to the reference plane of the circuit substrate for contacting and testing a wafer. The fine adjustment screws are respectively screwed on the circuit board, and one end of each of the fine adjustment screws abuts against the support frame for adjusting the level of the circuit board relative to the support frame.

In one or more embodiments of the present invention, the first identification marks are respectively located at outer edge positions of the reference plane of the circuit substrate.

In one or more embodiments of the invention, the identification marks are arranged in a triangular manner.

In one or more embodiments of the invention, each identification mark is a planar layer or a solid object.

In one or more embodiments of the invention, the identification marks are X-shaped in appearance and are identical to one another.

The above description is only for explaining the problems to be solved by the present invention, the technical means for solving the problems, the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.

10‧‧‧ method

11~16‧‧‧Steps

21~27‧‧‧Steps

31~36‧‧‧Steps

41~43‧‧‧Steps

100‧‧‧ system

110‧‧‧Base

111‧‧‧ chamber

112‧‧‧ stage

112S‧‧‧ wafer bearing surface

112M‧‧‧Second identification mark

113‧‧‧Secondary coplanar

120‧‧‧ lifting device

200, 201‧‧‧ probe card device

210‧‧‧ circuit board

211‧‧‧ first main face

211E‧‧‧ outer edge

211M‧‧‧ first identification mark

212‧‧‧First common face

213‧‧‧Second main face

220‧‧‧scale

221‧‧‧ scale value

230‧‧‧ probe

230S‧‧‧ virtual plane

240‧‧‧Support frame

241‧‧‧ frame

250‧‧‧outer board

260‧‧‧ test head

261‧‧‧Electrical connector

300‧‧‧Event Vehicles

400‧‧‧Level Judging Device

410‧‧‧First image capture unit

420‧‧‧Second image capture unit

430‧‧‧Image Processing Unit

440‧‧‧Computation unit

450‧‧‧judging unit

500‧‧‧ horizontal fine adjustment device

510‧‧‧ fine adjustment screw

511‧‧‧ nuts

512‧‧‧ wire trough

513‧‧‧ screw

W‧‧‧ wafer

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. FIG. 2 is a flow chart of a step 11 of FIG. 1 in a detailed embodiment; FIG. 3 is a flow chart of a step 13 of FIG. 1 in a detailed embodiment; Step 34 of FIG. 3 is a flowchart of a detailed embodiment; FIG. 5 is a schematic diagram of a system using a probe card according to another embodiment of the present invention; FIG. 6A is a probe card of FIG. FIG. 6B is a top view of the probe card device of FIG. 5; FIG. 7 is a bottom view of the probe card device of another embodiment; FIG. 8 is a view showing still another embodiment. FIG. 9 is a schematic view of a probe card device and a stage according to still another embodiment of the present invention; and FIG. 10 is a front view of the wafer carrying surface of FIG.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some conventional structures and components are used to simplify the drawing. The drawings will be illustrated in a simple schematic manner.

1 is a flow chart showing a method of using a probe card in accordance with an embodiment of the present invention. As shown in Fig. 1, the method 10 for using the probe card includes steps 11 to 16 as follows. In step 11, a probe card device is provided. The probe card device has a circuit substrate and a plurality of probes. The circuit substrate has a reference plane and at least three first identification marks that are not collinear. The first identification mark is formed. On the reference plane, and the first identification mark is coplanar with the reference plane. In step 12, the probe card device is moved such that the reference plane faces one of the wafer carrier faces of a stage. In step 13, it is determined whether the first coplanar surface defined by the first identification marks is parallel to the wafer carrying surface. If yes, proceed to step 14, otherwise, proceed to step 16. In step 14, a wafer is placed on the wafer carrier surface of the stage. However, it should be understood that the order in which the steps 14 are not limited in other embodiments is not necessarily after step 13. In step 15, the probes are touched and tested on the wafer carrier surface. In step 16, the level of the circuit substrate is adjusted. In one embodiment, for example, one of the fine adjustment screws screwed on the circuit substrate is adjusted. However, it should be understood that the method of the present invention is not limited to any conventional tool or device that can adjust the level of the reference plane of the circuit substrate. .

In this way, compared with the prior art, in the method of the present embodiment, it is easier to ensure the probe card device by using the first coplanar and the wafer bearing surface defined by the first identification marks to be parallel to each other. The virtual plane of these probes is parallel to the wafer carrying surface of the stage, which not only reduces process complexity, lead time, but also reduces the chance of test performance misalignment.

Specifically, the probes are fabricated and calibrated in conjunction with a reference plane having a first identification mark to ensure the virtual plane and stage of the probes. The wafer carrying surfaces are parallel to each other. Therefore, in the embodiment of the method, the needle ends of the probes can be detected to jointly define a virtual plane, and the reference plane of the circuit substrate is pre-confirmed to be a virtual plane parallel to the needle ends of the probes. Thus, FIG. 2 is a flow chart showing the step 11 of FIG. 1 in a detailed embodiment. The step of making the reference plane parallel to the virtual plane further includes steps 21 - 27 as follows.

In step 21, the first identification marks of the reference plane are respectively detected. In step 22, the coordinate positions of the first identification marks are analyzed. In step 23, a first plane function of the reference plane in a three-dimensional coordinate system (eg, a rectangular coordinate system) is calculated based on the coordinate positions of the first identification marks. The first plane function is, for example, a plane vector function or a plane equation of the reference plane, or any other way that can indicate the position of the direction of the reference plane. In step 24, the probe ends of the probes are detected to jointly define a virtual plane, and a third plane function is calculated according to the virtual plane. The third plane function is, for example, a plane vector function or a plane equation of a virtual plane, or any other way that can indicate the position of the direction of the virtual plane. In addition, it is to be understood that the order of step 24 is not necessarily after step 23. In step 25, it is determined whether the first plane function is parallel to the third plane function, and if so, proceeding to step 26, that is, determining that the reference plane containing the first identification marks is parallel to the virtual plane defined by the needle ends of the probes, Otherwise, proceed to step 27. In step 27, the needle positions are adjusted, after which it is returned to step 24, step 25, and even step 27 until the first plane function is judged to have been parallel to the third plane function. It will be appreciated that the method of the present invention is not limited to any conventional tool or device that can detect the virtual plane of the tip end of the probe 230.

Further, in the above step 24, in another embodiment, a plurality of steps are further included as follows. After detecting the virtual planes defined by the needle ends of the probes, it is determined whether the probe needle ends are flush with each other and jointly define a virtual plane. When it is determined that the probe tip ends cannot collectively define a virtual plane, adjusting the probe tip ends and detecting and judging whether the probe tip ends together define a virtual plane, or even adjusting the probe tip ends again Until the ends of the probe needles are flush with each other and can be detected by the commonly defined virtual plane. It will be appreciated that the method of the present invention is not limited to any conventional tool or device that detects the virtual plane of the probe tip of the probe. It will be appreciated that the method of the present invention is not limited to any conventional tool or device that can determine if the ends of the probe needles are flush with one another.

Figure 3 is a flow chart showing the step 13 of Figure 1 in a detailed embodiment. As shown in FIG. 3, step 31 to step 36 are further included in step 13 of the present embodiment as follows. In step 31, the first identification marks of the reference plane are respectively detected. In step 32, the coordinate positions of the first identification marks are analyzed. In step 33, based on coordinate positions of the first identification marks, a first plane function of the first coplanar in a three-dimensional coordinate system (for example, a rectangular coordinate system) is calculated, and the first plane function is, for example, a reference. Planar vector function or plane equation, or any other way that can indicate the position of the reference plane. In step 34, it is determined whether the first plane function is parallel to a second plane function of the wafer carrying surface, and if so, proceeding to step 35, that is, determining that the reference plane containing the first identification marks is parallel to the wafer carrying surface; otherwise, proceeding In step 36, it is determined that the reference plane containing the first identification marks is still not parallel to the wafer carrying surface. It should be understood that the method of the present invention is not limited to any of these first discriminations. A known tool or device that identifies and analyzes the coordinate positions of the first identification marks and calculates a first plane function of the reference plane.

Figure 4 is a flow chart showing the step 34 of Figure 3 in a detailed embodiment. In the present embodiment, as shown in FIG. 4, step 34 of FIG. 3 further includes steps 41 to 43 as follows. In step 41, at least three non-collinear second identification marks of the wafer carrying surface are respectively detected, and the second identification mark is coplanar with the wafer carrying surface. In step 42, the coordinate positions of the second identification marks are analyzed. In step 43, according to the coordinate positions of the second identification marks, the second plane function defined by the second identification marks in the three-dimensional coordinate system is calculated, and the second plane function is the wafer bearing The plane function of the face. It should be understood that the plane function of the wafer carrying surface of the stage can also be prepared in advance.

FIG. 5 is a schematic diagram of a system 100 for using a probe card in accordance with another embodiment of the present invention. Fig. 6A is a bottom view of the probe card device 200 of Fig. 5. As shown in FIG. 5 and FIG. 6A, the system 100 using the probe card of the present embodiment includes a stage 112, a probe card device 200, a movable carrier 300, a level determining device 400, and a horizontal fine adjustment. Device 500. The stage 112 has a wafer carrying surface 112S for carrying one of the wafers W. The probe card device 200 has a circuit substrate 210, a plurality of probes 230, and at least three non-collinear first identification marks 211M. The circuit substrate 210 has a first main surface 211 and a second main surface 213 opposite to each other. The first identification mark 211M and the probes 230 are respectively arranged on the first main surface 211 of the circuit substrate 210, and the first identification mark 211M and the first main surface 211 are coplanar with each other. The needle ends of these probes 230 collectively define a virtual plane. The virtual plane 230S movable carrier 300 is used to move the circuit substrate 210 such that the first main surface 211 faces the wafer carrying surface. 112S. The level determining device 400 is configured to determine whether the first coplanar 212 defined by the first identifying marks 211M is parallel to the wafer carrying surface 112S. The horizontal fine adjustment device 500 is used to adjust the levelness of the circuit substrate 210.

Therefore, when the level determining device 400 determines that the first coplanar 212 is parallel to the wafer carrying surface 112S, the first main surface 211 is parallel to the virtual plane 230S and the wafer carrying surface 112S. In this way, the step of testing the wafer by the probe can be performed. On the other hand, when the level determining device 400 determines that the first coplanar 212 is not parallel to the wafer carrying surface 112S, the user can manually control the horizontal fine adjusting device 500 to adjust the level of the circuit substrate 210, in conjunction with the judgment of the level determining device 400. Until the first major surface 211 is parallel to the wafer carrying surface 112S.

In this manner, since the virtual plane 230S of the tip end of the probe 230 is changed due to the configuration error or deformation of the probe 230, the configuration of the first identification mark 211M on the circuit substrate 210 is relatively simple and less susceptible to variation. Compared with the prior art, the virtual plane of the probe tip is used as the evaluation standard of the probe card device level. The first identification mark 211M is used as the evaluation standard of the probe card device 200 in the present embodiment, and is more easily and stably. Controlling the probe card device 200 and the wafer carrying surface 112S of the stage 112 are parallel to each other, so that the probes 230 can more fully and surely contact all the electrical terminals of the object to be tested (ie, the wafer), thereby maintaining the test. Performance accuracy.

Specifically, the system 100 includes a test head 260, a base 110, and a lifting device 120. The base 110 contains a chamber 111 therein. The lifting device 120 is disposed in the chamber 111, and is connected to one end of the stage 112, and opposite to the wafer carrying surface 112S of the stage 112 for driving the wafer W to vertically move up and down. The movable carrier 300 pivots the test head 260 and the base 110 to each other. The movable carrier 300 is used to flip the probe card device 200 drives the first main surface 211 of the circuit substrate 210 to face the wafer carrying surface 112S. The test head 260 is electrically connected to the circuit substrate 210 through the electrical connector 261.

However, the present invention is not limited thereto. In other embodiments, the system can also be fully automated, with the central processor electronically controlling the level determining device and the horizontal fine-tuning device to achieve the effect of immediately determining and fine-tuning the level.

As shown in FIG. 5, in the embodiment, one end of each of the probes 230 is connected to the first main surface 211 of the circuit substrate 210, and the other end ends of each of the probes 230 are flush with each other to define the above. Virtual plane 230S.

It should be understood that when the first main surface 211 including the first coplanar surface 212 is parallel to the virtual plane 230S and the wafer carrying surface 112S, the virtual plane 230S is parallel to the wafer carrying surface 112S. Therefore, in this embodiment, the first main The face 211 is a reference plane for demonstrating that the virtual plane 230S is parallel to the wafer carrying surface 112S. However, the system 100 of the present invention is not limited thereto, as long as the reference plane faces one side of the stage 112. In other embodiments, the reference plane may also face any of the sub-elements of the probe card device (such as the frame) facing the stage. .

As shown in FIG. 5, the probe card device 200 includes a support frame 240 and an outer plate 250. The support frame 240 is located on the outer panel 250. The outer panel 250 is placed on the base 110. The support frame 240 has a frame opening 241. The circuit board 210 is framed on the support frame 240. The first main surface 211 (ie, the reference plane) of the circuit substrate 210 is exposed to the frame opening 241. However, the circuit substrate 210 is not limited to being bolted, clamped, or otherwise secured within the support frame 240. FIG. 6B is a top view of the probe card device 200 of FIG. 5. As shown in FIG. 5 and FIG. 6B , the horizontal fine adjustment module includes at least three fine adjustment screws 510 , which are respectively screwed on the circuit substrate 210 . Each fine adjustment screw 510 penetrates the first main surface 211 of the circuit substrate 210 and The second main surface 213, and the nut 511 of each fine adjustment screw 510 (for example, the one-word knob nut 511) is exposed on the second main surface 213, and the screw 513 of each fine adjustment screw 510 is exposed on the first main surface 211. When the user rotates the fine adjustment screw 510 of the specific position, the screw 513 of the fine adjustment screw 510 protrudes from the first main surface 211 and pushes against the support frame 240, the circuit substrate 210 is correspondingly lifted, thereby adjusting the circuit substrate 210. Level.

More specifically, the second main surface 213 of the circuit substrate 210 is further provided with a scale 220 in the area surrounding the nut 511. The scale 220 has a plurality of scale values 221, and the scale values 221 respectively extend from the first main surface of the screw 513. The length of 211, that is, represents the degree of tilt of the circuit substrate 210. For example, when the wire slot 512 of the nut 511 points to one of the scale values 221, it indicates that the circuit substrate 210 has been adjusted to its corresponding tilt level.

In the present embodiment, as shown in FIG. 6A, the first identification marks 211M are not collinear with each other on the first main surface 211, and the first identification marks 211M have an X-like appearance and are completely identical to each other. These first identification marks 211M are not necessarily formed in the form of the first main surface 211, such as a planar layer (such as a printed pattern or plating or coating) or a three-dimensional object (such as a bolt or a sticker). However, the present invention is not limited thereto, and as long as the first identification marks 211M can be detected (identified), the present invention is not limited to the appearance, size, and formation of the first identification marks 211M.

In addition, for example, as shown in FIG. 6A, the first identification marks 211M are arranged on the first main surface 211 according to an equilateral triangle. However, in other embodiments, the first identification marks may be based on a right triangle, etc. Waist triangles or other kinds of triangles are arranged.

FIG. 7 is a bottom view of the probe card device 201 of another embodiment. As shown in FIG. 7, the probe card device 201 of the present embodiment is substantially the same as the above-described probe card device 200, except that the first identification marks 211M of the present embodiment are respectively located on the first main surface 211 of the circuit substrate 210 ( That is, the reference plane) is located outside the edge 211E. For example, the circuit substrate 210 has a disk shape, and the first identification marks 211M are respectively located on the first main surface 211 (ie, the reference plane) of the circuit substrate 210 and are connected to the circumferential surface (outer edge 211E) of the circuit substrate 210.

FIG. 8 is a detailed functional block diagram of the level determining apparatus 400 of still another embodiment. As shown in FIG. 5 and FIG. 8 , the level determining apparatus 400 includes a first image capturing unit 410 , an image processing unit 430 , a computing unit 440 , and a determining unit 450 . The first image capturing unit 410 is, for example, a photographing device for extracting a first image from the first main surface 211 (ie, the reference plane) including the first identification marks 211M. For example, the first image capturing unit 410 is located in the base 110 and faces the first identification marks 211M of the circuit substrate 210. The image processing unit 430 is electrically connected to the first image capturing unit 410 for analyzing the first image to obtain coordinate positions of the first identification marks 211M. For example, the image processing unit 430 is a display processing chip, and the first identification mark 211M can be recognized from the first image, and the first identification mark 211M is calculated in the three-dimensional space according to the relative positions of the first identification marks 211M. The coordinate position of the coordinate system. The calculating unit 440 is electrically connected to the first image capturing unit 410 and the image processing unit 430 for calculating the first plane function of the first main surface 211 (ie, the reference plane) according to the coordinate positions of the first identification marks 211M. . For example, the computing unit 440 is a central processing chip or a computing wafer, and three coordinate positions can be calculated to represent these first identification marks. The first plane function of the first coplanar 212 defined by 211M. For example, the first plane function is a plane vector function or a plane equation of the first major surface 211 (ie, the reference plane), or any other manner that can indicate the position of the reference plane. The determining unit 450 is electrically connected to the calculating unit 440 for determining whether the first plane function of the first main surface 211 (ie, the reference plane) is parallel to a second plane function of the wafer carrying surface 112S. For example, the determining unit 450 is a central processing chip. The second planar function of the wafer plane 112S is determined by conventional mathematical techniques to determine whether the first plane function of the reference plane is parallel. For example, it is determined whether the slope of the first plane function is the same as the slope of the second plane function.

In addition, the image capturing unit and the image processing unit having the same function as described above can also detect the virtual planes defined by the needle ends of the probes, or determine whether the needle ends of the probes can form a single virtual plane. Similarly, the third plane function of the virtual plane can also be calculated by the calculation unit having the same function as described above. Please refer to the above, and therefore, no further details are provided herein.

FIG. 9 is a schematic diagram of a probe card device 200 and a stage 112 according to still another embodiment of the present invention. Figure 10 is a front elevational view of the wafer carrying surface 112S of Figure 9. As shown in FIGS. 9 and 10, since the stage 112 is movable up and down, the wafer carrying surface 112S of the stage 112 is variably ground. Therefore, preferably, the stage 112 does not need to be moved to a specific position, and the present embodiment can determine between the first main surface 211 (ie, the reference plane) of the probe card device 200 and the wafer carrying surface 112S of the stage 112. Whether it is parallel.

As shown in FIGS. 9 and 10, the wafer carrying surface 112S has at least three second identification marks 112M that are not collinear. Second identification mark 112M and crystal The circular bearing surface 112S is coplanar. The level determining device 400 further includes a second image capturing unit 420. The second image capturing unit 420 is, for example, a photographing device for extracting a second image from the wafer carrying surface 112S including the second identifying marks 112M. For example, the second image capturing unit 420 is located above the stage 112 and faces the wafer carrying surface 112S. The image processing unit 430 analyzes the second image to obtain coordinate positions of the second identification marks 112M. For example, the image processing unit 430 recognizes the second identification marks 112M from the second image, and calculates the coordinate position of the second identification mark 112M in the three-dimensional coordinate system according to the relative positions of the second identification marks 112M. The calculating unit 440 calculates a second plane function of the second common plane 113 defined by the second identification marks 112M according to the coordinate positions of the second identification marks 112M. For example, computing unit 440 calculates three coordinate positions representing a second planar function of second common face 113 defined by these second identification marks 112M. The second plane function is a plane vector function or plane equation of the wafer carrying surface 112S, or any other manner that can indicate the position of the wafer carrying surface 112S.

Although the second identification mark 112M is different from the first identification mark 211M (6A, 7), the feature of the second identification mark 112M may follow the features of all the first identification marks 211M. , will not repeat them here.

Finally, the various embodiments disclosed above are not intended to limit the invention, and those skilled in the art can be protected in various modifications and refinements without departing from the spirit and scope of the invention. In the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧ method

11~16‧‧‧Steps

Claims (20)

A method for using a probe card, comprising: (a) providing a probe card device having a circuit substrate and a plurality of probes, wherein one of the reference planes has three non-collinear lines An identification mark, the first identification marks being in the same plane as the reference plane; (b) moving the probe card device such that the reference plane faces a wafer carrying surface of a stage; (c) determining the Determining, by the first identification mark, whether the first coplanar is parallel to the wafer bearing surface; (d) adjusting the level of the circuit substrate when the first coplanar is not parallel to the wafer bearing surface, so that the The first coplanar surface is parallel to the wafer carrying surface; and (e) the probes are contacted and tested for one of the wafers carried on the wafer carrying surface. The method of using the probe card according to claim 1, wherein the step (c) further comprises: respectively detecting the first identification marks; analyzing the coordinate positions of the first identification marks; Identifying a coordinate position of the mark, calculating a first plane function of the first coplanar surface in a three-dimensional coordinate system; determining whether the first plane function is parallel to a second plane function of the wafer bearing surface; When it is determined that the first plane function is not parallel to the second plane function, it is determined that the reference plane is not parallel to the wafer carrying surface. The method of using the probe card according to claim 2, wherein the determining whether the first plane function is parallel to the second plane function in the step (c) further comprises: detecting at least three of the wafer bearing surfaces respectively. a second identification mark that is not collinear, wherein the second identification marks are coplanar with the wafer bearing surface; the coordinate positions of the second identification marks are analyzed; and the coordinate positions are calculated according to the coordinate positions of the second identification marks The second planar function defined by the second identification marks is second coplanar in the three-dimensional coordinate system. The method of using a probe card according to claim 1, wherein the step (d) further comprises: adjusting at least one of a plurality of fine adjustment screws screwed on the circuit substrate to adjust the reference of the circuit substrate The level of the plane. The method of using the probe card of claim 1, wherein the step (a) further comprises: defining the reference plane of the circuit substrate parallel to the needle ends of the probes to define a virtual plane. The method of using a probe card according to claim 5, wherein the step of making the reference plane parallel to the virtual plane further comprises: Detecting the first identification marks respectively; analyzing the coordinate positions of the first identification marks; and calculating, according to the coordinate positions of the first identification marks, a first common surface in a three-dimensional coordinate system a plane function; detecting the virtual plane by the end of the probe of the probes, and calculating a third plane function according to the virtual plane; determining whether the first plane function is parallel to the third plane function; And the first plane function is not parallel to the third plane function, adjusting the needle positions; and detecting and calculating the third plane function of the virtual plane again, determining whether the first plane function is parallel to the third plane function and The steps of adjusting the positions of the needles until the first plane function is parallel to the third plane function. The method of using a probe card according to claim 5, wherein the step of making the reference plane parallel to the virtual plane further comprises: determining whether the probe needle ends are flush with each other and jointly defining the virtual plane; The probe ends of the probes are not capable of jointly defining the virtual plane, adjusting the probe needle ends; and repeatedly determining whether the probe needle ends collectively define the virtual plane and adjusting the probe needle ends, The virtual planes are defined together until the ends of the probe needles are flush with one another. A system using a probe card, comprising: a carrier having a wafer carrying surface for carrying one wafer; a probe card device having a circuit substrate and a plurality of probes, the circuit substrate having a reference plane, the reference The plane has at least three first identification marks that are not collinear, the first identification marks are coplanar with the reference plane, and the needle ends of the probes jointly define a virtual plane, and the virtual plane is parallel to the reference plane; a movable carrier for moving the circuit substrate such that the reference plane faces the wafer carrying surface; a level determining device for determining whether the first common plane defined by the first identification marks is parallel to the crystal a circular bearing surface; and a horizontal fine adjustment device for adjusting the level of the circuit substrate. The system of claim 8, wherein the level determining device comprises: a first image capturing unit, configured to capture a first image of the reference plane including the first identifying marks; An image processing unit is electrically connected to the first image capturing unit for analyzing the first image to obtain coordinate positions of the first identification marks; and a computing unit electrically connected to the first image capturing unit And the image processing unit, configured to calculate a first plane function of the first coplanar surface according to the coordinate positions of the first identification marks; and a determining unit electrically connected to the calculating unit for determining Whether the first plane function is parallel to a second plane function of the wafer carrying surface. The system for using a probe card according to claim 8, wherein the horizontal fine adjustment module comprises at least three fine adjustment screws, and the fine adjustment screws are respectively screwed on the circuit substrate. A system for using a probe card according to claim 8, wherein the wafer carrying surface has at least three second identification marks that are not collinear, and the second identification marks are coplanar with the wafer carrying surface. The system of claim 11, wherein the level determining device further comprises: a second image capturing unit for extracting a surface of the wafer containing the second identifying marks a second image, wherein the image processing unit analyzes the second image to obtain a coordinate position of the second identification marks, and the calculating unit calculates the wafer bearing surface according to the coordinate positions of the second identification marks The second plane function. The system for using a probe card according to claim 8, wherein the first identification marks are arranged according to a triangle. A system for using a probe card as described in claim 8, wherein the probes are coupled to the reference plane. A system for using a probe card according to claim 8, wherein the first identification marks are respectively located at an outer edge position of the reference plane. A probe card device comprising: a support frame having a frame; a circuit substrate disposed on the support frame, the circuit substrate having a reference plane exposed to the frame, the reference plane having at least three a non-collinear identification mark, and the reference plane is co-located with the identification marks; a plurality of probes are connected to the reference plane of the circuit substrate for contacting and testing a wafer; and at least three fine adjustment screws Each of the fine adjustment screws is abutted against the support frame for adjusting the level of the circuit substrate relative to the support frame. The probe card device of claim 16, wherein the identification marks are respectively located at an outer edge position of the reference plane of the circuit substrate. The probe card device of claim 16, wherein the identification marks are arranged in a triangular manner. The probe card device of claim 16, wherein each of the identification marks is a planar layer or a solid object. The probe card device of claim 16, wherein the identification marks have an X-like appearance and are completely identical to each other.