TW201731059A - Methods and apparatuses to provide ordered porosity - Google Patents

Abstract

A directed self-assembly (DSA) layer is deposited on one or more conductive features on an insulating layer on a substrate. The DSA layer comprises one or more first structures that are deposited on the insulating layer. One or more openings in the insulating layer are formed using the DSA layer as a mask to provide porosity for the insulating material. The one or more openings are self-aligned to the one or more conductive features.

Description

Method and apparatus for providing ordered porosity

Embodiments as described herein relate to the field of electronic device fabrication, and in particular to integrated circuit fabrication.

Generally, an integrated circuit (IC) refers to a group of electronic devices, for example, a transistor formed on a small wafer of a semiconductor material (usually germanium). Typically, the interconnect structure incorporated into the IC includes one or more layers of metal lines to connect and connect the electronic devices of the IC to each other. An interlayer dielectric is placed between the metal layers of the IC for insulation. In general, the efficiency of an interconnect structure depends on the resistance of each metal line and the coupling capacitance created between the metal lines.

As the IC size decreases, the spacing between the metal lines decreases. Small structures are easier to use with a higher dielectric constant dielectric, which increases the coupling capacitance between the wires. The increase in coupling capacitance between the metal lines has a negative impact on signal transmission along the metal lines. In addition, the increase in coupling capacitance increases the energy consumption of the integrated circuit.

A tradition of reducing the capacitive coupling between adjacent metal lines The technique involves replacing the higher k dielectric material of the separate metal lines with a lower k dielectric material.

100‧‧‧ side view

900‧‧‧3D view

101‧‧‧Substrate

102‧‧‧Insulation

103‧‧‧Characteristics

104‧‧‧Characteristics

110‧‧‧ spacing

131‧‧‧through hole

200‧‧‧ view

105‧‧‧ brush layer

201‧‧‧ Section

Section 202‧‧‧

300‧‧‧ view

106‧‧‧DSA layer

107‧‧‧Component Block

111‧‧‧Component Block

Section 108‧‧‧

109‧‧‧Parts

112‧‧‧ structure

113‧‧‧structure

301‧‧‧ vertical axis

302‧‧‧Width

303‧‧‧Width

400‧‧‧ view

114‧‧‧ openings

115‧‧‧ openings

401‧‧‧Width

402‧‧‧Width

410‧‧‧ view

411‧‧‧ openings

500‧‧‧ view

1300‧‧‧3D view

Section 1303‧‧‧

1400‧‧‧Upper view

116‧‧‧ hole

117‧‧‧ hole

1301‧‧ hole

1302‧‧‧ hole

Section 503‧‧‧

Section 504‧‧‧

501‧‧‧Width

502‧‧‧Width

600‧‧‧ view

118‧‧‧ Coverage

119‧‧‧Insulation

121‧‧‧ patterned hard mask layer

601‧‧ depth

700‧‧‧ view

122‧‧‧ openings

701‧‧‧ Groove area

702‧‧‧through hole area

800‧‧‧ view

123‧‧‧ Conductive layer

1000‧‧‧3D view

1100‧‧‧3D view

1101‧‧‧ spacing

1200‧‧‧3D view

1304‧‧‧ spacing

1306‧‧‧ horizontal axis

Section 1307‧‧‧

Section 1308‧‧‧

1501‧‧ depth

1600‧‧‧ images

1601‧‧‧Metal wire

1602‧‧‧Metal wire

1603‧‧‧Metal wire

1605‧‧‧ILD layer

1604‧‧‧ openings

1606‧‧‧ openings

1607‧‧‧ openings

1700‧‧ view

1701‧‧‧ Figure

1702‧‧‧ Curve

1703‧‧‧ Curve

1704‧‧‧Information

1705‧‧‧Information

1706‧‧‧Information

1800‧‧ view

1801‧‧‧ Curve

1900‧‧‧Intermediary

1902‧‧‧First substrate

1904‧‧‧second substrate

1906‧‧‧ Ball grid array

1908‧‧‧Metal interconnection

1910‧‧‧through hole

1912‧‧‧through through hole

1914‧‧‧ embedded devices

2000‧‧‧ Computing device

2002‧‧‧Integrated circuit die

2004‧‧‧ Processor

2006‧‧‧On-die memory

2008‧‧‧Communication chip

2010‧‧‧Volatile memory

2012‧‧‧Non-volatile memory

2014‧‧‧Graphic Processing Unit

2016‧‧‧Digital Signal Processor

2042‧‧‧ cryptographic processor

2020‧‧‧ chipsets

2022‧‧‧Antenna

2024‧‧‧Touch screen display

2026‧‧‧Touch Screen Display Controller

2029‧‧‧Battery

2028‧‧‧Global Positioning System Installation

2032‧‧‧Sensor

2034‧‧‧Speakers

2036‧‧‧ camera

2038‧‧‧User input device

2040‧‧‧large capacity storage device

Embodiments of the present invention may be best understood by referring to the following description and the accompanying drawings. In the drawings: Figure 1 shows a side view of a portion of an electronic device in accordance with an embodiment.

2 is a view similar to FIG. 1 after modifying a top surface of one or more features on an insulating layer using a brush layer, in accordance with an embodiment.

Figure 3 is a view similar to Figure 2 after depositing a DSA layer on features on an insulating layer, in accordance with an embodiment.

4A is a view similar to FIG. 3 after the structure of the second element of the DSA layer is selectively removed to form an opening to expose some of the top portions of the insulating layer, in accordance with an embodiment.

Figure 4B is a view similar to Figure 4B after removing portions of the first element of the DSA layer to increase the width of the opening in the DSA layer, in accordance with an embodiment.

Figure 5 is a view similar to one of the 4A or 4B drawings after forming an opening in the insulating layer using the DSA layer as a mask, according to an embodiment.

Figure 6 is a diagram of a patterned hard mask layer on an insulating layer over a cap layer deposited on a conductive feature in an insulating layer, in accordance with an embodiment Similar to the view in Figure 5.

Fig. 7 is a view similar to Fig. 6 after removing an exposed portion of the insulating layer to form an opening, according to an embodiment.

Figure 8 is a view similar to Figure 7 after deposition of a conductive layer into the opening, in accordance with an embodiment.

Fig. 9 is a three-dimensional view of a portion of the electronic device shown in Fig. 1 according to an embodiment.

Fig. 10 is a three-dimensional view of a portion of the electronic device shown in Fig. 2 according to an embodiment.

Fig. 11 is a three-dimensional view of a portion of the electronic device shown in Fig. 3 according to an embodiment.

Figure 12 is a three-dimensional view of a portion of the electronic device shown in Figure 4A, in accordance with an embodiment.

Figure 13 is a three-dimensional view of a portion of the electronic device shown in Figure 5, according to an embodiment.

Figure 14 is a top plan view of a portion of the electronic device shown in Figure 13 according to an embodiment.

Fig. 15 is a cross-sectional view of a line A-A' along a portion according to an embodiment.

Figure 16 is a top down scanning electron microscope (SEM) image of a self-aligned DSA mask displayed on an insulating layer, in accordance with an embodiment.

Figure 17 is a view showing a graph of Young's modulus for the porosity of various ILD films according to an embodiment.

Figure 18 is a view showing the ratio of porosity to hole radius to hole distance according to an embodiment.

Figure 19 illustrates an interposer including one or more embodiments of the present invention.

Figure 20 illustrates a computing device in accordance with an embodiment of the present invention.

SUMMARY OF THE INVENTION AND EMBODIMENT

Methods and apparatus for providing ordered porosity for integrated circuit fabrication are described. In one embodiment, a directed self-assembly (DSA) layer is deposited over one or more conductive features on an insulating layer on the substrate. The DSA layer includes one or more first structures deposited on the insulating layer. The DSA layer is used as a mask to form one or more openings in the insulating layer to provide porosity to the insulating material. The one or more openings are self aligned to the one or more conductive features.

Generally, in order for the dielectric material to shrink to a low k value below 2.0, the dielectric material needs to have a porosity greater than 40%. Conventional techniques for making porous dielectric materials include randomly mixing a back bone precursor with a porogen material that selectively ablates or etches the substrate.

However, under high loading volume porogen materials, there is no longer a continuous interconnect network of back bone precursor molecules such that the dielectric material collapses when ablating or etching the porogen material.

Generally, the increased loading of the porogen results in a maximum achievable porosity of 50% (%) to 60%. At maximum porosity or near maximum porosity, the mechanical strength of the dielectric material becomes too low to be Can withstand typical processing conditions for wire processing and assembly ends.

In one embodiment, increasing the porosity of the interlayer dielectric (ILD) material involves etching the ILD material using a DSA material as an etch mask to form holes in the ILD material between the metal lines that are compatible with the current metallization architecture. Each of the holes formed between the metal wires has a shape extending along the vertical axis. In one embodiment, the DSA material is used as a vertical hole formed in the ILD to self-align the metal lines extending along the horizontal axis. After the layer metallization is completed, vertical holes are formed in the ILD. Forming a vertical hole in the ILD layer that self-aligns the metal lines along the horizontal axis increases the porosity of the ILD material while maximizing the mechanical strength of the ILD material along the vertical axis.

In one embodiment, the DSA mask protects the metal layer, the barrier layer, and the post-chemical mechanical polishing (CMP) top surface of the nearby ILD material layer. Embodiments of the DSA mask may provide three-point protection because the DSA mask may prevent degradation of metal features, barrier layers, and ILD during ILD etching. In one embodiment, the DSA material is used as an etch to mask the holes in the etched ILD layer such that a small volume of ILD material remains on the sidewalls of the barrier layer after etching.

Since the holes in the ILD layer are etched after the metallization of the layer is completed, metal patterning can be performed with a non-porous ILD that is substantially stronger than the porous ILD. Since some portions of the ILD between the metal lines are removed, the capacitance between the metal lines is reduced. Some portions of the ILD remain between the metal lines after the vertical holes are formed. The remainder of the ILD between the wires provides additional mechanical strength compared to conventional air gap or porous ILD technology. It increases the shear modulus and prevents through hole fatigue.

Some embodiments of methods and apparatus for forming ordered vertical apertures using a DSA layer as described herein may avoid the need for a mask plug region, such as some air gap techniques, as compared to techniques in which the plug region is masked. This can reduce manufacturing costs. Traditional air gap technology will require removal of all ILD material between the wires. The size of the removed portion of the ILD is limited to the size determined by the DSA material compared to conventional techniques, and does not require a size corresponding to the portion of the ILD such that only a portion of the ILD material between the metal lines is removed. The structural order in which the highly porous film is introduced not only allows the elongation of the porosity to exceed 50% to 60%, but also the mechanical properties obtained are significantly higher than those of the conventional material having an unstructured pore shape. In an embodiment, an ordered pore structure is formed in the ILD layer between the metal lines. In an embodiment, each of the aperture structures formed in the ILD layer has a cylindrical shape and extends toward the substrate along a vertical axis, as described in further detail below.

The vertical cylindrical porosity arrangement may deliver mechanical stiffness along the vertical axis (layer to layer) while also benefiting along the transverse (wire to wire) axis. Because current manufacturing methods result in maximum mechanical stress along the vertical axis (eg, stresses caused during subsequent chemical mechanical polishing (CMP), die/package assembly, and thermal changes), the ILD layer between the metal lines The formation of an ordered vertically oriented aperture in some embodiments may provide the benefit of mechanical stiffness in the vertical direction for a given porosity in some embodiments. In one embodiment, a self-aligned vertically oriented cylindrical aperture in the middle of the ILD between the metal lines allows for even greater porosity values than conventional techniques. In one embodiment, the self-aligned vertical in the middle of the ILD between the metal lines The oriented cylindrical aperture provides the option of maintaining the ILD wall to the right of the metal line, as described in further detail below.

In the following description, various aspects of the illustrative embodiments will be described using the terms commonly employed by those skilled in the art to convey the substance of their work to those skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced only by some of the aspects described. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it is apparent to those skilled in the art that the present invention may be practiced without specific details. In other instances, well-known features are omitted or simplified to avoid obscuring the illustrative.

Various operations will be described as a plurality of discrete operations in a manner that is most helpful in understanding the present invention; however, the order of description should not be construed as implying that the operations must be dependent on the order. In particular, these operations do not need to be performed in the order presented.

While the invention has been shown and described with reference to the exemplary embodiments embodiments The average artist in the field may make modifications.

A reference to "an embodiment", "an embodiment" or "an embodiment" or "an embodiment" or "an" Therefore, the appearances of the "a" and "an" Furthermore, specific features, knots The configurations, or characteristics, may be combined in any suitable manner in one or more embodiments.

Moreover, the present invention resides in less than all features of a single disclosed embodiment. Therefore, the scope of the patent application, which is hereby incorporated by reference in its entirety herein, Although the exemplary embodiments have been described herein, it will be understood by those skilled in the art that Accordingly, the description is to be regarded as illustrative rather than limiting.

Figure 1 shows a side view 100 of a portion of an electronic device in accordance with an embodiment. Figure 9 is a three-dimensional view 900 of a portion of an electronic device shown in Figure 1 of an embodiment. A plurality of features, such as features 103 and features 104, are formed on insulating layer 102 on substrate 101.

In an embodiment, substrate 101 comprises a semiconductor material, such as germanium (Si). In an embodiment, the substrate 101 is a single crystal Si substrate. In another embodiment, the substrate 101 is a polycrystalline germanium substrate. In another embodiment, substrate 101 represents a prior interconnect layer. In yet another embodiment, the substrate 101 is an amorphous germanium substrate. In an alternate embodiment, substrate 101 comprises germanium, germanium ("Ge"), germanium ("SiGe"), III-V material based materials such as gallium arsenide ("GaAs"), or any combination thereof. In an embodiment, substrate 101 includes a metallization interconnect layer for an integrated circuit. In at least some embodiments, substrate 101 includes electronic devices such as transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices separated by an electrically insulating layer, such as interlayer dielectrics A quality, trench insulating layer, or any other insulating layer known to those of ordinary skill in the art of electronic device fabrication. In at least some embodiments, substrate 101 includes interconnects configured to connect metallization layers, such as vias.

In an embodiment, the substrate 101 is a semiconductor-on-insulator (SOI) substrate including a bulk lower substrate, an intermediate insulating layer, and a top single crystal layer. The top single crystal layer may contain any of the materials listed above, such as germanium.

In various implementations, the substrate can be, for example, an organic, ceramic, glass, or semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a germanium or insulator germanium structure. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with germanium, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, arsenic. Indium gallium, gallium antimonide, or other combinations of III-V or Group IV materials. Although several examples of materials that may form a substrate are described herein, it may be used as a possible construction of passive and active electronic devices (eg, transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronics). Any material based on the device, or any other electronic device, is within the spirit and scope of the present invention.

In an embodiment, the insulating layer 102 is an interlayer dielectric (ILD) layer. In an embodiment, the insulating layer 102 is a non-porous insulating layer. In another embodiment, the insulating layer 102 has a porosity of less than 10%. In an embodiment, the insulating layer 102 is a solid high k dielectric having a k value greater than 3.9. In an embodiment, the insulating layer 102 is a solid low-k dielectric layer having a k value of less than or equal to 3.9. In an embodiment, the insulating layer 102 is an oxide layer, such as a hafnium oxide layer, hafnium oxide, carbon doped oxidation. ("CDO"), or any combination thereof. In another embodiment, the insulating layer 102 is a nitride layer, such as a tantalum nitride layer. In an alternate embodiment, the insulating layer 102 comprises a nitride, an oxide, a polymer, a phosphonium phosphate glass, a fluorosilicate ("SiOF") glass, an organic tellurite glass ("SiOCH"), and other metal oxides. , or any combination thereof. In an alternate embodiment, insulating layer 102 is aluminum oxide, hafnium oxynitride, other metal oxide/nitride layers, any combination thereof, or other electrically insulating layer as determined by electronic device design.

In an embodiment, the thickness of the insulating layer 102 is determined by design. In an embodiment, the insulating layer 102 is deposited to a thickness of from about 20 nanometers (nm) to about 2 micrometers (μm). In embodiments, such as, but not limited to, chemical vapor deposition ("CVD") (eg, plasma enhanced chemical vapor deposition ("PECVD")), physical vapor deposition ("PVD"), molecular beam epitaxy (" One of the deposition techniques of MBE"), metal organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin coating, or other deposition techniques known to those of ordinary skill in the art of microelectronic device fabrication is An insulating layer 102 is deposited on the substrate 101.

Features 103 and 104 are formed in insulating layer 102 as shown in FIGS. 1 and 9. In an embodiment, features 103 and 104 are electrically conductive features. In an alternate embodiment, the conductive features are conductive lines, conductive vias connected to elements in the 101 layer, trenches, or any combination thereof. In an embodiment, at least one of the conductive features (eg, conductive features 103) includes a via 131 that is coupled to substrate 101. In an embodiment, the conductive features The center-to-center distance between the distances is less than about 100 nm. In one embodiment, the spacing 110 between the conductive features is from about 10 nanometers (nm) to about 80 nm. In a more specific embodiment, the pitch 110 is from about 20 nm to about 50 nm. In an embodiment, the electrically conductive feature is part of an interconnect layer.

In one embodiment, one of the conductive feature forming techniques known to those of ordinary skill in the art of microelectronic device fabrication is used to form the conductive features. In one embodiment, the insulating layer 102 is patterned and etched to form openings (eg, trenches, or other openings) using patterning and etching techniques known to those of ordinary skill in the art of microelectronic device fabrication. One or more conductive layers, such as a conductive layer on the substrate layer, are deposited to fill the openings in the insulating layer 102. One of the chemical mechanical polishing (CMP) techniques is used to remove portions of one or more conductive layers that extend above the top of the insulating layer 102. Portions of one or more conductive layers deposited within the openings in insulating layer 102 are not removed and become patterned conductive features, such as conductive features 103 and 104. In an embodiment, the conductive features have a width of less than about 40 nm. In an embodiment, the width of the conductive features is in the range of from about 5 nm to about 40 nm. In an embodiment, the height of the conductive features is less than about 65 nm. In an embodiment, the thickness of the conductive features is in the approximate range of 8 nm to 65 nm.

In an embodiment, the substrate layer comprises a conductive seed layer deposited on the conductive barrier layer, one or more liner layers, or both. In an embodiment, the seed layer comprises copper (Cu). In another embodiment, the seed layer comprises tungsten (W). In an alternate embodiment, the seed layer is copper, titanium nitride, tantalum, nickel, cobalt, tungsten, or any combination thereof. In a more specific embodiment, the seed layer is copper. In an embodiment, the conductive barrier layer comprises aluminum, titanium, nitrogen Titanium, tantalum, tantalum nitride, tungsten, cobalt, rhenium, other metals, or any combination thereof. Typically, a conductive barrier layer serves to prevent diffusion of conductive material from the seed layer into the insulating layer 102 to provide adhesion to the seed layer, or both. In one embodiment, the substrate layer includes a seed layer deposited on the sidewalls of the openings in the insulating layer 102 and the barrier layer on the bottom. In another embodiment, the substrate layer includes a seed layer deposited directly on the sidewalls and bottom of the opening in the insulating layer 102. Each of the conductive barrier layer and the seed layer may be deposited using any thin film deposition technique known to those of ordinary skill in the art of semiconductor fabrication, such as by sputtering, blanket deposition, and the like. In one embodiment, each of the electrically conductive barrier layer and the seed layer has a thickness in the range of from about 0.5 nanometers (nm) to 100 nm. In an embodiment, the barrier layer may be a thin dielectric that has been etched to establish electrical conductivity to the underlying metal layer. In an embodiment, the barrier layer may be omitted altogether, and a suitable self-doping of the copper wire may be used to form a "self-forming barrier layer."

In one embodiment, a conductive layer of copper is deposited onto the copper seed layer by an electroplating process. In another embodiment, a conductive layer is deposited onto the seed layer using one of the selective deposition techniques known to those of ordinary skill in the art of semiconductor fabrication, such as electroplating, electroless plating, or the like. In one embodiment, the selection of the material for the conductive layer determines the choice of material for the seed layer. For example, if the material used for the conductive layer includes copper, the material used for the seed layer also includes copper. In an embodiment, the conductive layer includes, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), Aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), platinum (Pt), bismuth (Si), or any combination thereof.

In alternative embodiments, examples of conductive materials that may be used in the conductive layer to form conductive features include, but are not limited to, metals (eg, copper, tantalum, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead), Metal alloys, metal carbides (eg, tantalum carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide), other conductive materials, or any combination thereof.

In an embodiment, the conductive features are formed by removing portions of the conductive layer and the base layer other than the openings in the insulating layer 102. It may be chemically (e.g., using etching), mechanically (e.g., using polishing), or by a combination thereof (e.g., using chemical mechanical polishing ("CMP") techniques known to those of ordinary skill in the art of microelectronic device fabrication). Except for the part of the conductive layer.

In another embodiment, features 103 and 104 comprise a sacrificial material (eg, a carbon hard mask, oxide, nitride, or titanium nitride) that has been deposited in a trench in insulating layer 102 in place of a conductive material. Or tungsten sacrificial metal) to avoid damage to the conductive material in later procedures. In an alternate embodiment, one of the sacrificial layer deposition techniques (eg, sputtering, blanket deposition, spin coating, or other deposition techniques known to those of ordinary skill in the art of electronic device fabrication) is used to deposit the sacrificial layer to fill the insulating layer 102. The opening in the middle. In one embodiment, one of the chemical mechanical polishing (CMP) techniques is used to remove portions of the sacrificial layer that extend over the top of the insulating layer 102.

2 is a view 200 similar to FIG. 1 after modifying the top surface of one or more features on the insulating layer 102 using the brush layer 105, in accordance with an embodiment. Figure 10 is a three-dimensional view 1000 of a portion of an electronic device shown in Figure 2, in accordance with an embodiment. In some embodiments, the brush layer comprises a material that is bonded to the conductor and not bonded to the insulating layer under some programming conditions. In some embodiments, the brush layer comprises a material that chemically bonds to the conductor and does not bond to the insulating layer when annealed at a temperature greater than room temperature. As shown in Figures 2 and 10, portions of brush layer 105 (e.g., portion 201 and portion 202) are deposited on the top surface of features (e.g., features 103 and 104). The brush layer 105 is not deposited on the top surface of the insulating layer 102. In an embodiment, the material of the brush layer 105 is a DSA material. In an embodiment, the brush layer 105 includes a termination element that is coupled to the tail element. In a non-limiting, exemplary embodiment, the terminal element of brush layer 105 is a thiol, phosphonate, acid, or any combination thereof. In a non-limiting exemplary embodiment, the terminal elements of the brush layer 105 are thiol (-SH), phosphonic acid (-PO ₃ R ₂ , where R = H, CH ₃ , C ₂ H _{5 ,} etc.), hydroxyl groups ( -OH), a carboxyl (-COOH) group, an aldehyde (-COH), any derivative thereof, or any combination thereof. In one embodiment, the tail elements of the brush layer 105 correspond to elements of the DSA material that are later deposited on the conductive features in the program. In an embodiment, the tail element of brush layer 105 is a polymethyl methacrylate (PMMA) material. In an embodiment, the tail element of brush layer 105 is a polystyrene (PS) material. In other embodiments, other materials are used as the terminal and tail elements of the brush layer. In an embodiment, the brush layer 105 has a thickness of from about 0.5 nm to about 5 nm.

In one embodiment, a liquid solution comprising the brush layer 105 of the terminal element and the tail element is deposited on the conductive using one of the spin coating techniques. Features and top surface of insulating layer 102. After deposition, the brush layer 105 is baked at a temperature greater than room temperature to chemically bond to the conductive features. In one embodiment, the brush layer 105 is baked at a temperature ranging from about 60 degrees Celsius to about 200 degrees Celsius. In an embodiment, the brush layer 105 is bonded to features 103 and 104 by terminal elements. The brush layer 105 is not chemically bonded to the insulating layer 102. The portion of the brush layer 105 that is external to the feature is removed using one or more irrigation techniques. In an alternate embodiment, the brush layer 105 is deposited using one of a number of deposition techniques, such as, but not limited to, chemical vapor deposition ("CVD") (eg, plasma enhanced chemical vapor deposition ("PECVD")), physical gas Phase deposition ("PVD"), molecular beam epitaxy ("MBE"), metal organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or known to those of ordinary skill in the art of electronic device fabrication. Other deposition techniques.

FIG. 3 is a view 300 similar to FIG. 2 after deposition of the DSA layer 106 on features on the insulating layer 102, in accordance with an embodiment. Figure 11 is a three-dimensional view 1100 of a portion of an electronic device shown in Figure 3, in accordance with an embodiment. In an embodiment, the DSA layer 106 comprises a polymer chain. In one embodiment, the DSA layer 106 is a diblock copolymer. As shown in Figures 3 and 10, the DSA layer 106 includes a first component (e.g., component block 107) and a second component (e.g., component block 111). In an embodiment, the first component is PMMA and the second component is PS. In another embodiment, the first component is a PS and the second component is a PMMA. In other embodiments, other materials are used as the first and second components of the DSA layer.

As shown in Figures 3 and 11, some parts of the first component (e.g., portion 108) is deposited on portions of portion 201 of brush layer 105 as features 103 and 104. Portions of the first component, such as portion 109, are deposited on portions of insulating layer 102 that are external to features 103 and 104. Portions of the second element 111 are deposited on some other portion of the insulating layer 102 outside of features 103 and 104. Portions of the second element 111 comprise structures, such as structure 112 and structure 113. In an embodiment, the structure is a vertical cylinder extending from the top surface of the DSA layer 106 toward the substrate 101 along the vertical axis 301. In an embodiment, each of the structures 112 and 113 extending along the vertical axis 301 has a predetermined shape (eg, circular, elliptical, oval, triangular, in a plane parallel to the top surface of the DSA layer 106). Rectangular, hexagonal, or other shape). As shown in Figure 3, each of structures 112 and 113 has substantially parallel opposing side walls. As shown in FIG. 3, the width 302 at the top of the structure 113 is substantially similar to the width 303 at the bottom of the structure 113. In one non-limiting example, structure 113 has a width of less than about 100 nm. In one non-limiting example, the width of structure 113 is in the approximate range of from about 5 nm to about 50 nm. In a more specific, non-limiting example, the structure 113 has a width of from about 10 nm to about 30 nm.

In one embodiment, the DSA layer 106 is baked at a temperature greater than room temperature to self-organize the second component 111 into structures such as structures 112 and 113 such that the structure of the second component 111 is only insulated outside of the conductive features. On the portion of layer 102. In one embodiment, the DSA layer 106 is baked at a temperature ranging from about 100 °C to about 250 °C.

In an embodiment, the tail element of the brush layer 105 and the DSA The first element of layer 106 has the same material. That is, modifying the top surface of the conductive features by the DSA brush layer 105 forces the structure of the second component of the DSA layer 106 to self-align between features 103 and 104.

In an embodiment, the volume fraction of the first element, the second element, or any combination thereof is adjusted to provide a predetermined structure to form a self-aligned ordered hole in the insulating layer 102 between the conductive features. In an embodiment, the DSA layer 106 comprises from 20% to about 40% by volume of the second component and from about 60% to about 80% by volume of the first component. In a more specific embodiment, the DSA layer 106 includes about 30% by volume of the second element and about 70% by volume of the first element.

In an embodiment, the spacing 1101 between adjacent structures of the second element 111 of the DSA layer 106 is adjusted to correspond to the pitch 110 of the features 103 and 104 below. In one embodiment, the pitch of the DSA layer structure pattern is greater than the pitch of the features 103 and 104 below divided by a square root of about 2 divided by 3 (eg, 2 x (3) ^{- 0.5} 1.15). In one embodiment, the pitch 1101 is a function of the total length of the first component molecule and the second component molecule of the DSA material. In an embodiment, the total length of the first and second element molecules of the DSA material is adjusted based on the pitch of the underlying conductive pattern. In one embodiment, the molecular weight of at least one of the second component and the first component of the DSA material is adjusted to ensure that the structure of the second component of the DSA layer is created over portions of the insulating layer 102 between the conductive features.

In one embodiment, the thickness of the DSA layer 106 is such that the spacing between the structures of the second elements of the DSA layer corresponds to the spacing between the conductive features on the insulating layer 102. In an embodiment, the DSA layer is sufficiently thin to Substantially all of the structure of the second element of the DSA layer extends along the vertical axis 301. In an embodiment, the DSA layer 106 has a thickness of from about 10 nm to about 80 nm. In a more specific embodiment, the DSA layer 106 has a thickness of from about 30 nm to about 50 nm.

In one embodiment, a liquid solution comprising a DSA material is spin coated onto the top of insulating layer 102 and on brush layer 105. In an alternate embodiment, the DSA layer 106 is deposited using other deposition techniques such as, but not limited to, chemical vapor deposition ("CVD") (eg, plasma enhanced chemical vapor deposition ("PECVD")), physical vapor deposition (" PVD"), molecular beam epitaxy ("MBE"), metal organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or other deposition techniques known to those of ordinary skill in the art of electronic device fabrication.

4A is a view 400 similar to FIG. 3 after the structure of the second element of the DSA layer 106 is selectively removed to form openings 114 and 115 to expose some of the tops of the insulating layer 102, in accordance with an embodiment. Figure 12 is a three-dimensional view 1200 of a portion of an electronic device shown in Figure 4A, in accordance with an embodiment.

In an embodiment, the second component 111 of the DSA layer 106 has a relatively high etch selectivity to the first component 107 of the DSA layer 106. In an embodiment, the ratio between the etch rate of the second element 111 and the etch rate of the first element 107 is at least 8:1. As shown in Figures 4A and 12, portions of the first component of the DSA layer 106 remain on features 103 and 104 and some other tops of insulating layer 102. As shown in Figures 4A and 13, openings 114 and 115 extend through DSA layer 106 along vertical axis 301. thickness of. In an embodiment, the shapes of the openings 114 and 115 are similar to the shapes of the structures 112 and 113. In an embodiment, each of the openings 114 and 115 extending along the vertical axis 301 has a cylindrical shape. In an embodiment, each of the openings 114 and 115 extending along the vertical axis 301 has a predetermined shape in a plane parallel to the top surface of the DSA layer 106 (eg, circular, elliptical, oval, triangular, rectangular, Hexagon, or any other shape). As shown in Figure 4A, each of the openings 114 and 115 has substantially parallel opposing side walls. As shown in Figures 4A and 12, the width 401 at the top of the opening 115 is substantially similar to the width 402 at the bottom of the opening 115. In one embodiment, each of the openings 114 and 115 has a width of from about 5 nm to about 50 nm.

In one embodiment, one or more of wet etching, dry etching, or a combination thereof, known to those of ordinary skill in the art of electronic device fabrication, is used to selectively remove the structure of the second component of the DSA layer 106. In one embodiment, after selectively removing the structure of the second component of the DSA layer 106, the DSA layer 106 is cured at a temperature greater than room temperature.

In one embodiment, the second component of the DSA layer 106 is a PMMA material and the first component of the DSA layer 106 is a PS material. In one embodiment, deep ultraviolet (DUV) exposure (to cut PMMA) followed by selective wet etching (eg, using acetic acid, isopropanol, or other wet solution) to selectively remove PMMA of DSA layer 106 structure. The remaining PS elements of the DSA layer are used as an etch mask to etch into the ILD layer 102.

4B is a portion of the first component of the DSA layer 106 removed to increase the width of the opening in the DSA layer 106, in accordance with an embodiment. This is similar to view 410 of Figure 4B. As shown in FIG. 4B, the opening 411 is wider than the opening 115. The opening 415 is wider than the opening 114. The first element of the DSA layer 106 is isotropically etched using, for example, an ashing technique, or a wet etch technique to widen the opening in the DSA layer 106. In an embodiment, the first element of the DSA layer 106 is etched using a hydrogen based ashing technique. In another embodiment, the first element of the DSA layer 106 is etched using an oxygen based ashing technique.

As shown in Figure 4B, each of the openings 411 and 415 has substantially parallel opposing side walls. As shown in FIG. 4B, the width at the top of the opening 411 is substantially similar to the width at the bottom of the opening 411. In one embodiment, each of the openings 411 and 415 has a width of from about 5 nm to about 50. In some embodiments, the openings 411 and 415 have a taper toward the bottom, as described in further detail below.

Figure 5 is a view similar to Figure 4A or 4B after using a DSA layer as a mask and then removing the DSA mask to form an opening in the insulating layer 102 using an ashing, dry etching, or wet chemical etch, in accordance with an embodiment. A view 500 of one of them. Figure 13 is a three-dimensional view 1300 of a portion of an electronic device shown in Figure 5, in accordance with an embodiment. Figure 14 is a top view 1400 of a portion 1303 of an electronic device shown in Figure 13 in accordance with an embodiment. Figure 15 is a cross-sectional view of line A-A' along portion 1303, in accordance with an embodiment.

As shown in Figures 5, 13, 14 and 15, a plurality of openings (holes), such as holes 116 and 117, 1301 and 1302, are formed in the insulating layer 102 outside of the conductive features. As shown in Figures 5, 13 and 15, in conductive Holes are formed in the insulating layer 102 between the signs 103 and 104. No holes are formed in the insulating layer 102 under features 103 and 104. The apertures are separated from the conductive features by a small portion of the remaining insulating material 102 (eg, portions 503 and 504). In one embodiment, the portion of the remaining insulating material 102 has a size in the range of from about 0.1 nm to about 20 nm. In a more specific embodiment, the portion of the remaining insulating material 102 has a size in the range of from about 1 nm to about 5 nm. In one embodiment, the holes 116, 117, 1301, and 1302 are separated from one another by portions of the remaining insulating material 102 (eg, portions 1307 and 1308) in directions parallel to the conductive features, such as 13, 13, and 15 The figure shows. The first component and brush layers 201 and 202 of the DSA layer 106 are removed to expose features (e.g., features 103 and 104) and portions of the insulating layer 102 outside of the conductive features.

As shown in FIGS. 5, 13, and 15, each of the holes in the insulating layer 102 has a predetermined shape in a plane parallel to the top surface of the insulating layer 102 (for example, a circle, an ellipse, an oval, a triangle, a rectangle, A hexagon, or other shape) and extending along the vertical axis 301 through a predetermined depth of the thickness of the insulating layer 102. 14 and 15 illustrate an example of the orderly porosity for the insulating layer 102, the insulating layer 102 being in the shape of a vertical cylinder that is self-aligned with the metal lines. In one embodiment, the shape of the holes in the insulating layer 102 is similar to the shape of the openings 114 and 115 in the DSA layer. In another embodiment, the shapes of the holes 116 and 117 are similar to the shapes of the openings 415 and 411. In an embodiment, the holes in the insulating layer 102 have an elongated shape along the thickness of the insulating layer (eg, along the vertical axis 301). In one embodiment, the etching process creates some cones at the bottom of the aperture. In an embodiment, the insulating layer The holes in 102 have a slightly conical bottom shape. In at least some embodiments, the width of the elongated aperture varies with depth such that the width at the top of the aperture is different than the width at the bottom of the aperture. In an embodiment, the width at the top of the aperture is greater than the width at the bottom of the aperture. In another embodiment, the width at the top of the aperture is less than the width at the bottom of the aperture. In an embodiment, each of the holes in the insulating layer 102 has a shape similar to a vertically oriented cylinder. In an embodiment, each opening in the insulating layer 102 has substantially parallel opposing sidewalls. As shown in FIG. 5, the width 501 at the top of the opening 117 is substantially similar to the width 502 at the bottom of the opening 117. In an embodiment, each of the openings in the insulating layer 102 has a width of from about 5 nm to about 50 nm.

As shown in FIG. 13, openings (eg, openings 117 and openings 1302) in the insulating layer 102 are self-aligned to the conductive features 103 and 105, and the conductive features 103 and 105 are in a plane parallel to the top surface of the insulating layer 102. The horizontal axis 1306 extends.

In an embodiment, the spacing 1304 between the openings 1301 and 1302 in the insulating layer is adjusted based on the spacing 110 between the features 103 and 104. In one embodiment, the spacing 1304 of the opening layer is greater than the spacing 110 of the feature divided by about 2 divided by the square root of 3 (eg, 2 x (3) ^-0.5 1.15). As shown in Figures 15 and 13, the depth of the opening in the insulating layer 102 (e.g., depth 1501) is similar to the thickness of the conductive features. In another embodiment, the depth of the opening in the insulating layer 102 is greater than the thickness of the conductive features. In yet another embodiment, the depth of the opening in the insulating layer 102 is less than the thickness of the conductive features.

In one embodiment, the openings in the insulating layer 102 are etched through openings in the DSA layer 106 between features 103 and 104 using dry etch techniques (eg, plasma etch techniques or other dry etch techniques). In an embodiment, fluoride-based plasma etching is used to etch openings in the insulating layer 102 between features 103 and 104. In one embodiment, the openings in the insulating layer 102 between the features 103 and 104 are etched using a plasma based on fluorinated carbon (eg, CF ₄ , CH ₂ F ₂ , CH ₃ F, C ₄ F _{8 ,} etc.). .

In an embodiment, after the opening in the insulating layer 106 is formed, portions of the first element of the DSA layer 106 are removed. In one embodiment, a portion of the first component of the DSA layer 106 is removed using one of a dry etch technique (eg, a plasma etch technique), a wet etch technique, or any combination thereof.

Although the location of the holes in the insulating layer 102 is determined by the pattern of the DSA layer 106, the width of the holes and thus the porosity can be adjusted by additional etching of portions of the first component of the DSA layer 106, as shown in FIG. 4B. This etching also determines the width of the holes that enter the insulating layer 102. Both the width and depth of the holes contribute to porosity and thus contribute to the capacitance between the wires. Generally, as the width, depth or both of the holes increase, the porosity of the insulating layer increases. In an embodiment, the upper portion of the insulating layer 102 includes holes that extend through a portion of the thickness of the insulating layer 102 such that the underside of the insulating layer 102 is stronger and denser than the upper portion of the ILD layer.

In another embodiment, when features 103 and 104 comprise sacrificial material, vertical holes 116 and 117 in insulating layer 102 use one or more Filler material deposition techniques (eg, spin-on deposition, flowable chemical vapor deposition, or atomic layer deposition) with filler materials (eg, can be filled with carbon hard masks, oxides, nitrides, or such as titanium nitride or tungsten The sacrificial metal) to fill. The sacrificial material may be removed from the trenches in the insulating layer 102 using one or more sacrificial material removal techniques known to those of ordinary skill in the art of electronic device fabrication (eg, dry etching, wet etching, or both). In an embodiment, after the sacrificial material is removed, the trenches in the insulating layer 102 are filled with a conductive material to form conductive features, as described above with respect to FIG.

As shown in Figures 5, 13, 14, and 15, the periodic vertical holes 116, 117, 1301, and 1302 are separated by portions (walls) of the ILD between the metal lines 503 and 504, and by ILD materials 1307 and 1308. The parts (walls) are separated from each other. These portions of the remaining ILD material provide some benefits. First, this remaining ILD portion shunts some of the vertical stress away from the via (to minimize via fatigue). Second, these parts of the ILD provide additional lateral mechanical strength and reduce the risk of failure under shear stress. Third, in some embodiments, the remaining ILDs 503 and 504 can provide additional dielectric stability to the edges of the metal lines. Third, in at least some embodiments, the DSA mask provides metal and barrier protection during ILD etching. In at least some embodiments, the sacrificial material is added, the possibility of etching while protecting the metal, or both are used to create openings in the DSA mask that are larger than the spacing between the metal lines. In an embodiment, the ordered holes in the ILD are not significantly wider than the half pitch between the conductive features. In this case, the DSA mask provides protection against metal and blocking during the ILD etch. In other embodiments, such as when using a sacrificial metal or when using an ILD etch When a stable barrier/metal system is engraved, the ordered holes of the DSA mask can be larger than the half spacing between the conductive features. In this embodiment, the total porosity of the ILD between the metal lines can increase the porosity by more than 34%.

6 is a view 600 similar to FIG. 5 after the patterned hard mask layer 121 on the insulating layer 119 on the cap layer 118 is deposited on the conductive features 103 and 104 in the insulating layer 102, in accordance with an embodiment. As shown in FIG. 6, the cover layer 118 is bridged over the openings 116 and 117. In an embodiment, the cover layer 118 extends down into the openings 116 and 117 to a depth 601. In an alternate embodiment, the depth 601 is from about 0 nm to about 20 nm. In a more specific embodiment, the depth 601 is from about 3 nm to about 10 nm.

In an embodiment, the cover layer 118 has a thickness of from about 2 nm to about 20 nm. In an embodiment, the cap layer 118 is an etch stop layer. In an embodiment, the cap layer 118 is tantalum nitride, tantalum carbide, or any combination thereof. In an alternate embodiment, the cap layer 118 is an oxide layer (eg, a hafnium oxide layer), a carbon doped oxide layer (eg, a carbon doped hafnium oxide layer), a ceria (SiOC) layer, a fluorine doped ceria, Metal oxides (such as titanium oxide, aluminum oxide, cerium oxide, or any other metal oxide); hydrogenated sesquioxanes (HSQ), fluorinated amorphous carbon, methyl sesquiterpene oxide (MSQ), nitrogen a layer (such as tantalum nitride, hafnium oxynitride), tantalum carbide, or other cover layer.

As described above, in order to continue to build up the subsequent upper layer in the integrated structure, the vertical ordered holes in the lower ILD layer are covered with the cover layer 118. In an embodiment, the vertical holes (holes) in the ILD layer 102 are filled with sacrificial Material (not shown) (for example, may be filled with a carbon hard mask, an oxide, a nitride, or a sacrificial metal such as titanium nitride or tungsten). In an embodiment, the sacrificial material filling the holes is sagged below the metal features 103 and 104 using CMP, etching, or both. In one embodiment, a semi-porous screen layer (eg, tantalum nitride, tantalum carbide, tantalum carbon oxide, carbon doped oxide, or having a porosity between 5-30% by volume) is deposited on the recessed sacrificial material. The above combination). In one embodiment, the sacrificial material is removed through a semi-porous screen layer using one of the sacrificial material removal techniques known to those of ordinary skill in the art. In an embodiment, the semi-porous screen is converted to a non-porous cover layer, such as cover layer 118, using any hole filling strategy (such as PECVD deposition, ALD deposition, or spin coating) after removal of the sacrificial material.

In one embodiment, one of the deposition techniques is used to deposit a cap layer 118 such as, but not limited to, spin coating, chemical vapor deposition ("CVD") (eg, plasma enhanced chemical vapor deposition ("PECVD")), physics It is known to those skilled in the art of vapor deposition ("PVD"), molecular beam epitaxy ("MBE"), metal organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or electronic device fabrication. Other deposition techniques. As shown in FIG. 6, an insulating layer 119 is deposited on the cap layer 118. In one embodiment, the insulating layer 119 is one of the insulating layers as described above with respect to the insulating layer 102 shown in FIG. In one embodiment, insulating layer 119 is deposited using one or more insulating layer deposition techniques as described above with respect to insulating layer 102 shown in FIG. In an embodiment, the insulating layer 119 is part of the next interconnect layer. A patterned hard mask layer 121 is deposited on the insulating layer 119 to form The next interconnect layer. The patterned hard mask layer 121 exposes portions of the insulating layer 119. In an embodiment, the hard mask layer 121 is a nitride layer such as tantalum nitride, hafnium oxynitride, a carbon layer, other hard mask layers, or any combination thereof. The patterned mask layer 121 can be formed using one of the hard mask layer deposition and patterning techniques known to those of ordinary skill in the art of electronic device fabrication.

FIG. 7 is a view 700 similar to FIG. 6 after removing the exposed portions of the insulating layer 102 to form the openings 122, in accordance with an embodiment. As shown in FIG. 7, opening 122 is formed down to conductive feature 104. In an embodiment, the opening 122 includes a trench region 701 and a via region 702. In one embodiment, the exposed portions of the insulating layer 102 are removed using one or more etching techniques (eg, dry etching, wet etching, or two techniques known to those of ordinary skill in the art of electronic device fabrication). In one embodiment, the hard mask layer 121 is removed using one or more hard mask layer removal techniques known to those of ordinary skill in the art of electronic device fabrication. In an embodiment, the hard mask layer 121 is removed using ashing techniques.

Figure 8 is a view 800 similar to Figure 7 after deposition of conductive layer 123 into opening 122, in accordance with an embodiment. As shown in FIG. 8, conductive layer 123 fills opening 122 to form conductive vias to conductive features 104. In one embodiment, conductive layer 123 is deposited using one of the conductive layer deposition techniques known in the art of semiconductor fabrication, such as electroplating, electroless plating, or other conductive layer deposition techniques. In one embodiment, conductive layer 123 is one of the conductive layers as described above with respect to FIG.

Figure 16 is a view showing an insulating layer according to an embodiment A view of a top-down scanning electron microscope (SEM) image 1600 of a self-aligned DSA mask. Metal lines (e.g., metal lines 1601, 1602, and 1603) are deposited on ILD layer 1605 as shown in image 1600. The DSA mask includes a plurality of openings, such as an opening 1604 and an opening 1606 centered over portions of the ILD layer 1605. The DSA mask has no openings on the wire, as shown in Figure 16. Openings 1604 and 1606 are centered over portions of ILD layer 1605 between metal lines 1601 and 1602, as shown in FIG. Openings 1604 and 1606 are arranged substantially parallel to metal lines 1601 and 1602, as shown in FIG. The ILD layer 1605 has a plug region, such as a plug region 1606. The plug area is an ILD area that does not have a metal line. In these areas, the DSA mask still produces periodic openings, such as opening 1607. The dielectric material under the DSA mask is etched to include a plurality of ordered holes similar to those in the ILD layer between the conductive features as described above. Since no metal wires are present in these plug regions, the total porosity is about one-half lower than the total porosity between the metal wires. The DSA mask provides an additional benefit over conventional air gap processing where all ILDs of the plug region are completely etched and challenge the handling of the hard mask layer 118 described above. Typically, the plug region is masked from the air gap etch and this requires another expensive lithography step. In at least some embodiments, the DSA mask only allows for the creation of etched ILD holes in plug regions similar to between conductive features. The challenge of the integrated hard mask layer 118 is similar in both plug and non-plug regions, so no additional lithography steps are required.

Figure 17 is a view 1700 showing a graph 1701 of Young's modulus versus porosity for various ILD films in accordance with an embodiment. Usually, Yang Modulus is a parameter related to the mechanical strength (or stiffness) of the material. Young's modulus defines the relationship between stress (force per unit area) and strain (proportional deformation) in the material. As shown in Figure 1701, for conventional membranes 1 (curves 1702) and 2 (curve 1703), the modulus decreases rapidly as porosity increases and when the pores do not have a controllable shape or interconnected network.

When porosity and pore size distribution were used as experimental inputs, data 1704 was generated for conventional membrane 2 using a finite element model (FEM) technique. The data 1704 accurately fits the curve 1703 for the conventional film 2. As described above, the material 1705 and data 1706 were generated using a FEM model for a non-porous ILD film that was treated to provide controllable vertical cylindrical porosity. FEM data 1705 shows that the modulus of the film having ordered vertical porosity is significantly increased based on porosity along the longitudinal (vertical) axis of the cylinder bore, for example from about three times (3X) to about seven times (7X). FEM data 1706 shows that the modulus of the film with ordered vertical porosity increases approximately two times (~2X) along the transverse axis of the cylinder bore. That is to say, the longitudinal and transverse mechanical stiffness of the ILD film having a vertically ordered porosity is substantially greater than that of the conventional film. The Young's modulus of an ILD film having vertically ordered pores as described herein increases by up to about 7 times in the vertical direction, which determines the mechanical integrity of the ILD during integration, assembly, and thermal stress. Figure 18 is a view 1800 showing the relative radius of porosity versus aperture in accordance with an embodiment. Curve 1801 shows the calculated porosity for all ranges of pore sizes. In the figure, R is the radius of the vertical hole in the DSA (eg, half of the distance 401, 402), which corresponds to the size and shape maintained by the cut-in ILD. Pm is the pitch of the metal interconnect (eg, pitch 110). In the picture Medium, ILD porosity refers to the porous volume of the spacing between metal lines. The insertion point "a" shows the metal line deposited on the insulating layer (the radius of the hole is zero). For the region of curve 1801 between a and c, the holes are small enough and are completely confined within the ILD between the wires (as indicated by insertion point b). When the pores have substantially the same width as the spacing between the metal wires (as indicated by the insertion point "c"), the porosity is about 34%. As shown in Figure 4B, the radius of the DSA mask can be increased by etching or ashing. The structure shown in the insertion points d, e, and f is possible if the metal can tolerate ILD etching, use of a replacement (sacrificial) metal, or both. These structures are created using a DSA mask to create a hole in the insulating layer that is wider than the spacing between the metal lines. When the ILD material is etched, the metal lines block the etch such that the structures shown in the insertion points d, e, and f are produced.

Curve 1801 shows that porosity can be controlled by adjusting the radius of the vertical holes as described above with respect to Figures 4A and 4B. Curve 1801 is calculated based on the DSA mask overlying the ILD film. Since the metal lines under the DSA mask area typically occupy about 50% of the ILD space, the porosity will increase in the region of the ILD between the metal lines.

Curve 1801 shows the calculated porosity that can be achieved by varying the radius r of the cylinder relative to the cylinder pitch P(r/P) for a flat ILD surface without metal lines, according to an embodiment. In an embodiment, the DSA mask provides ordered porosity in the range of porosity given by block 1802. In one embodiment, when the DSA mask is aligned with the underlying metal trench pattern, the resulting porosity of the ILD between the etched metal lines by the DSA mask is approximately 20% to about 45% of the total porosity. Geometrically increase. In an embodiment, as described above with respect to FIG. 4B, the porosity between the metal lines is further increased to correspond to the range of block 1803 by radially increasing the holes in the ILD via a longer etching or ashing procedure. . In one embodiment, when the diameter of the cylindrical hole matches the spacing between the metal lines, the maximum porosity of the ILD between the metal lines is about 34%. In one embodiment, the radius of the hole in the DSA mask is further increased such that some of the metal lines are exposed at the bottom of the DSA mask to increase the porosity between the metal lines.

Figure 19 illustrates an interposer 1900 that includes one or more embodiments of the present invention. The interposer 1900 is an intermediate substrate for bridging the first substrate 1902 to the second substrate 1904. The first substrate 1902 may be, for example, an integrated circuit die. The second substrate 1904 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the mediation layer 1900 is to extend the connection to a wider spacing or to reroute the connection to a different connection. For example, the interposer 1900 may couple the integrated circuit die to a ball grid array (BGA) 1906, which may then be coupled to the second substrate 1904. In some embodiments, the first and second substrates 1902 / 1904 are attached to opposite sides of the interposer 1900. In other embodiments, the first and second substrates 1902 / 1904 are attached to the same side of the interposer 1900. In a further embodiment, three or more substrates are interconnected by an interposer 1900.

The interposer 1900 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as tantalum, niobium, and other III-V and Group IV materials.

As noted above, the interposer may include vias 1910 including, but not limited to, through vias (TSV) 1912, metal interconnects 1908 having ordered porosity in the insulating layer. Interposer 1900 is more likely to include embedded device 1914, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. It is also possible to form more complex devices on the interposer 1900, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices. In accordance with embodiments of the present invention, the devices or programs disclosed herein may be used in the manufacture of the interposer 1900.

In an embodiment, the electronic device includes a plurality of metal layers on the substrate. At least one metal layer of the electronic device has conductive features and holes regularly arranged in the insulating layer with respect to at least one conductive feature, as described with respect to Figures 5, 13, 14, and 15. At least one metal layer of the electronic device includes a conductive feature and an air gap in the non-porous insulating layer.

In another embodiment, each metal layer of the electronic device has electrically conductive features and holes in the insulating layer that are regularly arranged with respect to at least one electrically conductive feature, as described with respect to Figures 5, 13, 14, and 15.

Figure 20 illustrates a computing device 2000 in accordance with an embodiment of the present invention. Computing device 2000 may include some components. In an embodiment, the components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated on a single system die (SoC) die rather than a motherboard. Elements in computing device 2000 include, but are not limited to, integrated circuit die 2002 and at least one communication die 2008. In some implementations, communication Wafer 2008 is fabricated as part of integrated circuit die 2002. The integrated circuit die 2002 may include a processor 2004 such as a central processing unit (CPU), on-die memory 2006, which is often used as a cache memory, such as by embedded DRAM (eDRAM) or spin transfer torque. Memory (STTM or STTM-RAM) technology is available.

Computing device 2000 may include other components that may or may not be physically and electrically coupled to or fabricated within the motherboard. These other components include, but are not limited to, volatile memory 2010 (eg, DRAM), non-volatile memory 2012 (eg, ROM or flash memory), graphics processing unit 2014 (GPU), digital signal processor 2016 (DSP) ), cryptographic processor 2042 (a dedicated processor that performs cryptographic algorithms in the body), chipset 2020, antenna 2022, display or touchscreen display 2024, touchscreen display controller 2026, battery 2029, or other source of electrical power , Global Positioning System (GPS) device 2028, power amplifier (PA), compass, motion coprocessor or sensor 2032 (possibly including accelerometer, gyroscope, and compass), speaker 2034, camera 2036, user input device 2038 (such as keyboard, mouse, stylus, and trackpad), and mass storage device 2040 (such as hard disk drive, compact disc (CD), digital versatile compact disc (DVD), etc.).

The communication chip 2008 initiates wireless communication to transfer data to and from the computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods that may communicate data by using electromagnetic radiation modulated by non-solid media. Technology, communication channels, etc. This term does not mean that the associated device does not contain any lines, although in some embodiments they may not contain any lines. Communication Chip 2008 may implement any of a number of wireless standards or protocols, including but not limited to WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+ , HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G or higher. Computing device 2000 may include a plurality of communication chips 2008. For example, the first communication chip 2008 may be dedicated to a shorter range of wireless communications such as WiFi and Bluetooth, and the second communication chip 2008 may be dedicated to applications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. A longer range of wireless communications.

The term "processor" may refer to any device or any part of a device that processes electronic data from a register and/or memory to convert the electronic data into potentially stored in a register and/or memory. Other electronic materials. One or more elements, such as integrated circuit die 2002, communication chip 2008, GPU 2014, cryptographic processor 2042, DSP 2016, chipset 2020, and other components, may include ordered porous formation in accordance with embodiments of the present invention. Sex. In further embodiments, another component housed within computing device 2000 may comprise ordered porosity formed in accordance with embodiments of the present invention.

In various embodiments, computing device 2000 may be a laptop, a small notebook, a notebook computer, an ultra-thin computer, a smart hand Machine, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable Music player, or digital video recorder. In further implementations, computing device 2000 may be any other electronic device that processes data.

The above description of the exemplary embodiments of the present invention, which are described in the summary, are not intended to be exhaustive or to limit the invention. Various equivalent modifications are possible within the scope of the invention, as will be apparent to those skilled in the relevant art.

These modifications may be made to the invention in light of the above detailed description. The use of the terms in the following claims should not be construed as limiting the invention. Instead, the scope of the invention is to be determined entirely by the scope of the following claims, which are to be construed in accordance

The following examples relate to other embodiments: In one embodiment, a method of fabricating an electronic device includes depositing a directed self-assembled (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a deposition One or more first structures on the insulating layer and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned with respect to the one or more conductive features.

In one embodiment, a method of fabricating an electronic device includes depositing an orientation on one or more conductive features on an insulating layer on a substrate A self-assembled (DSA) layer comprising one or more first structures deposited on an insulating layer, one or more first structures removed, and one or more formed in the insulating layer using a DSA layer as a mask An opening in which one or more openings are self-aligned with respect to one or more conductive features.

In one embodiment, a method of fabricating an electronic device includes depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more deposited on the insulating layer a first structure, and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein at least one of the openings One extends toward the substrate along the first axis.

In one embodiment, a method of fabricating an electronic device includes depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more deposited on the insulating layer a first structure, and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein at least one of the openings is at the top The width is substantially similar to the width at the bottom of at least one opening.

In one embodiment, a method of fabricating an electronic device includes depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more deposited on the insulating layer a first structure, and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein the one or more first structures At least one of them has a cylindrical shape shape.

In one embodiment, a method of fabricating an electronic device includes depositing an insulating layer on a substrate; depositing one or more conductive features in the insulating layer; depositing an orientation on one or more conductive features on the insulating layer on the substrate a self-assembled (DSA) layer, the DSA layer comprising one or more first structures deposited on the insulating layer, and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein one or more pairs of openings One or more conductive features are self-aligned.

In one embodiment, a method of fabricating an electronic device includes depositing a brush layer on one or more conductive features on an insulating layer on a substrate; depositing a directed self-assembly (DSA) layer on one or more conductive features, The DSA layer includes one or more first structures deposited on the insulating layer; and one or more openings formed in the insulating layer using the DSA layer as a mask, wherein the one or more openings are for one or more conductive features alignment.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings.

In one embodiment, one is used to provide ordered porosity A method comprising depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein the first portion of the first component is deposited in a a plurality of conductive features, a second portion of the first component being deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the one or more second portions of the insulating layer; removing the second component One or more portions to form one or more first openings in the DSA layer; and one or more second openings in the insulating layer through the one or more first openings, wherein the one or more second The opening is self-aligned with respect to one or more of the conductive features.

In one embodiment, a method for providing ordered porosity includes depositing a brush layer on one or more conductive features on an insulating layer on a substrate; depositing oriented self-assembly on one or more conductive features (DSA) layer, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, and a second portion of the first component is deposited on the insulating layer Or a plurality of first portions, and wherein the second member is deposited on the one or more second portions of the insulating layer; removing one or more portions of the second member to form one or more first openings in the DSA layer And forming one or more second openings through the one or more first openings in the insulating layer.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features and a second portion of the first component is deposited on the one or more first portions of the insulating layer Dividing, and wherein the second component is deposited on the one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and insulating One or more second openings are formed in the layer through the one or more first openings, wherein at least one of the second openings extends toward the substrate along the first axis.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings, wherein the width at the top of the at least one second opening is substantially similar to the width at the bottom of the at least one second opening.

In one embodiment, a method for providing ordered porosity includes depositing an insulating layer on a substrate; depositing one or more conductive features on the insulating layer; and one or more conductive features on the insulating layer Depositing a directed self-assembly (DSA) layer, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features and a second portion of the first component is deposited on the insulating layer Or a plurality of first portions, and wherein the second member is deposited on the one or more second portions of the insulating layer; removing one or more portions of the second member to form one or more first openings in the DSA layer And forming one through the one or more first openings in the insulating layer Or a plurality of second openings.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings, wherein the second member comprises one or more structures having a predetermined shape.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer On one or more second portions; annealing the DSA layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more in the insulating layer One or more second openings of the first opening.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein the first portion of the first component is deposited with one or more conductive features Upper portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the one or more second portions of the insulating layer; removing one or more of the second component Forming one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the depth of the at least one second opening is similar to or Greater than the thickness of one or more conductive features.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings, wherein removing the second component comprises selectively etching the second component.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings of the port, wherein the one or more second openings are etched using dry etching.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings; and etching a second portion of the first component; and etching a second portion of the first component.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings, wherein the distance between portions of the second component is adjusted based on the distance between the conductive features.

In one embodiment, a method for providing ordered porosity includes one or more conductive features on an insulating layer on a substrate Depositing a directed self-assembly (DSA) layer, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features and a second portion of the first component is deposited on the insulating layer Or a plurality of first portions, and wherein the second member is deposited on the one or more second portions of the insulating layer; removing one or more portions of the second member to form one or more first openings in the DSA layer Forming one or more second openings through the one or more first openings in the insulating layer; depositing a capping layer on the one or more second openings; and forming an interconnect layer on the capping layer.

In one embodiment, a method for providing ordered porosity includes depositing a directed self-assembly (DSA) layer on a conductive feature on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on one or more conductive features, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the second component is deposited on the insulating layer Removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more first openings in the insulating layer One or more second openings, wherein one or more of the conductive features are electrically conductive lines.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer that are self-aligned with respect to one or more conductive features.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, one or more of Opening At least one extends toward the substrate along the first axis.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, wherein at least one opening The width at the top is substantially similar to the width at the bottom of at least one opening.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, one or more of At least one of the openings has a cylindrical shape.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, wherein the conductive features are based The distance between them is to adjust the distance between the openings.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, a plurality of openings in the insulating layer, self-aligning one or more conductive features, one or more a cover layer on the opening and an interconnect layer on the cover layer.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, one or more of One conductive feature is a conductive line.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, wherein at least one opening Width The degree is from 5 nm to 50 nm.

In one embodiment, an electronic device includes one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer, self-aligning one or more conductive features, wherein at least one opening The depth is similar to or greater than the thickness of one or more conductive features.

In the foregoing specification, the methods and apparatus have been described with reference to the specific exemplary embodiments thereof. It is apparent that various modifications may be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as

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Claims (20)

A method of fabricating an electronic device comprising: depositing a self-assembled (DSA) layer on one or more conductive lines on an insulating layer on a substrate, the DSA layer comprising one or more deposited on the insulating layer a first structure; using the DSA layer as a mask to form one or more openings in the insulating layer, wherein the one or more openings are self-aligned to the one or more conductive lines. The method of claim 1, further comprising: removing the one or more first structures. The method of claim 1, wherein at least one of the one or more openings extends toward the substrate along a first axis. The method of claim 1, wherein a width of at least one of the openings is greater than an interval between the conductive features. The method of claim 1, wherein at least one of the one or more openings has an elongated shape. The method of claim 1, further comprising: depositing the insulating layer on the substrate; depositing the one or more conductive lines in the insulating layer. The method of claim 1, further comprising: depositing a brush layer on the one or more conductive lines. A method for providing an ordered porosity comprising: depositing a self-assembled (DSA) layer on a conductive line on an insulating layer on a substrate, the DSA layer comprising a first component and One a second component, wherein a first portion of the first component is deposited on the one or more conductive lines, a second portion of the first component is deposited on the one or more first portions of the insulating layer, and wherein the first portion Depositing two elements on one or more second portions of the insulating layer; removing one or more portions of the second member to form one or more first openings in the DSA layer; and in the insulating layer One or more second openings are formed through the one or more first openings. The method of claim 8, wherein the one or more second openings are self-aligned to the one or more conductive lines. The method of claim 8, further comprising: depositing a brush layer on the one or more conductive lines, wherein the first portion is deposited on the brush layer. The method of claim 8, wherein at least one of the second openings extends toward the substrate along a first axis. The method of claim 8, further comprising: annealing the DSA layer. The method of claim 8, further comprising: etching the second portion of the first component. The method of claim 8, further comprising: depositing a cover layer on the one or more second openings; and forming an interconnect layer on the cover layer. An electronic device comprising: one or more conductive lines on an insulating layer on a substrate; A plurality of openings in the insulating layer are self-aligned between the one or more conductive lines. The electronic device of claim 15, wherein at least one of the one or more openings extends toward the substrate along a first axis. The electronic device of claim 15, wherein at least one of the one or more openings has a cylindrical shape. The electronic device of claim 15, wherein the spacing between the openings is adjusted based on a spacing between the conductive lines. The electronic device of claim 15, further comprising: a cover layer on the one or more openings; and an interconnect layer on the cover layer. The electronic device of claim 15, wherein the depth of at least one of the openings is similar to or greater than the thickness of the one or more conductive lines.