TW201727958A - Flash anneal of a spin hall effect switched magnetic tunnel junction device to reduce resistivity of metal interconnects - Google Patents

Abstract

Embodiments related to magnetic tunnel junction devices including a spin Hall effect metal layer having a first portion with a first crystallographic phase adjacent to a free magnetic layer and a second portion with a second crystallographic phase having a lower conductivity than the first crystallographic phase extending away from the first portion and the free magnetic layer, systems incorporating such devices, and methods for forming them are discussed.

Description

Fast flash annealing of a spin Hall effect switched magnetic tunnel junction device for reducing the resistivity of metal interconnects

Embodiments of the present invention are generally directed to magnetic tunnel junction devices having metal interconnects that reduce resistivity, and more particularly to magnetic tunnel junction devices having spin Hall effect metal layers. The first crystalline phase of the spin Hall effect metal layer is adjacent to the free magnetic layer, and the second crystalline phase having a lower resistivity extends from the first crystalline phase.

In some implementations, a magnetic tunnel junction (MTJ) device, such as a magnetoresistive random access memory (MRAM) device, can include a tunnel barrier layer between the fixed magnetic layer and the free magnetic layer. ). As the name implies, the fixed magnetic layer can be set to a specific magnetic polarity. The free magnetic layer can be altered and characteristics such as resistance can be detected to read the device (eg, read the bit cell of the device). The free magnetic layer or the free magnetic layer can be altered by inducing a magnetic field by flowing a current through the device or using a spin transfer torque (STT) technique. Example In this regard, such a spin transfer torque technique can include providing a charge current flowing through a material adjacent the free magnetic layer to cause a spin current that is orthogonal to the direction of the charge current. The spin current can change the magnetic state or polarity of the free magnetic layer via the spin transfer torque.

As previously discussed, the spin transfer torque can be used to change or flip the polarity of the free magnetic layer of a magnetic tunnel junction device such as a magnetic random access memory. Such spin transfer torque memory can provide advantages such as lower power consumption and better expandability than conventional magnetic random access memories and has advantages over other conventional memory devices. However, significant progress is still needed in implementing such devices.

100‧‧‧Magnetic tunneling junction device

101‧‧‧Substrate

102‧‧‧ Spin Hall effect metal layer

103‧‧‧Free magnetic layer

104‧‧‧Insulator layer

105‧‧‧Fixed magnetic layer

106‧‧‧Antiferromagnetic layer

107‧‧‧Contact layer

108‧‧‧Contact layer

109‧‧‧Charge current

110‧‧‧Spin current

111‧‧‧Magnetic polarity

112‧‧‧Fixed magnetic polarity

113‧‧‧Low resistance section

114‧‧‧Low resistance section

115‧‧‧High Resistance Department

120‧‧‧Material stacking

121‧‧‧ phase

122‧‧‧ phase

123‧‧‧Magnetic tunneling junction

201‧‧‧ phase

202‧‧‧ phase

203‧‧‧ corner

204‧‧‧ corner

205‧‧‧ position

206‧‧‧Location

207‧‧‧ bottom edge

300‧‧‧ integrated circuit

301‧‧‧Magnetic tunneling junction device

302‧‧‧ Spin Hall Effect Metal Layer

313‧‧‧ Low Resistance Section

314‧‧‧ Low Resistance Section

315‧‧‧High Resistance Department

320‧‧‧Material stacking

331‧‧‧Contact

332‧‧‧Contact

333‧‧‧Contact

334‧‧‧Contact

341‧‧‧Interlayer dielectric

400‧‧‧ method

401,402,403‧‧‧ operations

501‧‧‧Magnetic tunneling joint device structure

502‧‧‧Magnetic tunneling junction device structure

503‧‧‧ Spin Hall effect metal layer

504‧‧‧ Spin Hall Effect Metal Layer

505‧‧‧Magnetic tunneling joint device structure

506‧‧‧Block free magnetic layer

507‧‧‧Block insulator layer

508‧‧‧Blocked fixed magnetic layer

509‧‧‧Block antiferromagnetic layer

510‧‧‧Block contact layer

511‧‧‧Block contact layer

512‧‧‧Magnetic tunneling joint device structure

513‧‧‧ mask

514‧‧‧Magnetic tunneling joint device structure

515‧‧‧Magnetic tunneling interface to select the structure of the crystal device

516‧‧‧flash

600‧‧‧MRAM unit

601‧‧‧Magnetic tunneling junction device

602‧‧‧ reference line

603‧‧‧ bit line

604‧‧‧ word line

605‧‧‧Selecting a crystal

606‧‧‧ source line

700‧‧‧Mobile Computing Platform

705‧‧‧display screen

710‧‧‧ integrated system

715‧‧‧Battery

720‧‧‧Expanding

725‧‧‧Integrated Circuit RFIC TX/RX

730‧‧‧Power Management Integrated Circuit (PMIC)

735‧‧‧ Controller

750‧‧‧Memory/Processor/Package with MTJ Device

800‧‧‧ arithmetic device

801‧‧‧ processor

802‧‧‧ motherboard

803‧‧‧ camera

804‧‧‧Communication chip

805‧‧‧Communication chip

806‧‧‧ chipsets

807‧‧‧DRAM

808‧‧‧DRAM

809‧‧‧Power Amplifier

810‧‧‧ROM

811‧‧‧Touch Screen Controller

812‧‧‧Graphic CPU

813‧‧‧GPS

814‧‧‧ compass

815‧‧‧Speaker

816‧‧‧Antenna

817‧‧‧ touch screen display

818‧‧‧Battery

The information described herein is illustrated by way of example and not by way of limitation in the drawings. For the sake of brevity and clarity of the description, elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to the other elements for clarity. Further, where appropriate, the reference numerals are repeated among the drawings to indicate corresponding or similar elements. In the drawings: Figure 1 is a side view of an exemplary magnetic tunneling junction device.

2 illustrates exemplary phase boundaries between a high resistance portion and a low resistance portion of a spin Hall effect metal layer; FIG. 3 is a side view of an exemplary integrated circuit including a magnetic tunnel junction device; .

4 is a flow chart illustrating an exemplary method for forming a magnetic tunnel junction device having a reduced resistivity metal interconnect; 5A, 5B, 5C, 5D, 5E, 5F, and 5G are side views of an exemplary magnetic tunnel junction device structure for performing a specific fabrication operation; and FIG. 6 illustrates the implementation of a magnetic tunnel junction having a reduced resistivity metal interconnection. An exemplary MRAM cell of the device; FIG. 7 is a schematic diagram of a mobile computing platform employing a magnetic tunneling junction device having a reduced resistivity metal interconnect; and FIG. 8 is an operational device all configured in accordance with at least some embodiments of the present disclosure Functional block diagram.

SUMMARY OF THE INVENTION AND EMBODIMENT

One or more embodiments or implementations are now described with reference to the drawings. While discussing specific configurations and configurations, we should understand that this is for illustrative purposes only. Those skilled in the art will appreciate that other configurations and configurations can be employed without departing from the spirit and scope of the invention. It will be apparent to those skilled in the relevant art that the techniques and/or configurations described herein may also be employed in a variety of other systems and applications than those described herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) In the following detailed description, reference is made to the accompanying drawings. It should be understood that the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for the sake of clarity. Furthermore, it is understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references such as up, down, top, bottom, top, bottom, etc. may be The discussion of the drawings and the embodiments is not intended to limit the application of the claimed subject matter. Therefore, the following detailed description is not to be taken in a

In the following detailed description, numerous details are set forth, and it is apparent to those skilled in the art In some instances, well-known methods and devices are shown in block diagrams and not in detail. The "embodiment" or "in an embodiment" referred to throughout the specification means that a specific feature, structure, function or characteristic relating to the embodiment is included in at least one embodiment of the invention. Therefore, terms such as "an embodiment" and "an embodiment" may be used to refer to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in one or more embodiments in any suitable manner. For example, the first embodiment can be incorporated in a second embodiment of two embodiments that are not designated as being mutually exclusive.

The terms "coupled" and "connected" and their derivatives may be used herein to describe the structural relationship between the components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (intermediate elements) physical or electrical contact with each other, and/or that the two or more elements cooperate or interact with each other (eg, as a causal relationship).

The terms "above", "below", "between", "upper" and/or the like, as used herein, mean the relative position of a material layer or component relative to other layers or materials. For example, configured in another A layer above or below one layer may be in direct contact with other layers or one or more intermediate layers. Furthermore, a layer disposed between the two layers may be in direct contact with the two layers or one or more intermediate layers. In contrast, the first layer "on" the second layer is in direct contact with the second layer. Similarly, a feature disposed between two features can be in direct contact with an adjacent feature, or can have more than one intermediate feature, unless explicitly stated elsewhere.

The following describes a magnetic tunnel junction device, a memory, an integrated circuit, a device, a computing platform, and a method for a magnetic tunnel junction device having a reduced resistivity metal interconnect.

As described above, a magnetic tunnel junction device such as a magnetoresistive random access memory device that uses spin transfer torque to change or flip a free magnetic layer can provide advantages over other magnetoresistive random access memory devices. For example, the magnetic tunnel junction device provides the advantages of lower power consumption and better expandability. In an embodiment, the magnetic tunnel junction device may include an insulator layer and a spin Hall effect metal layer, the insulator layer is between the fixed magnetic layer and the free magnetic layer, and the spin Hall effect metal layer has a free magnetic a first portion adjacent to the layer and a second portion extending from the first portion and the free magnetic layer. For example, the first portion may include a first crystalline phase of the spin Hall effect gold layer, and the second portion may include a second crystal having a spin Hall effect metal layer that is lower than the conductivity of the first crystalline phase. phase. As further discussed herein, the first crystalline phase of the spin Hall effect metal layer can, in response to a charge current, provide a spin current via spin transfer torque to convert the polarity of the free magnetic layer. The second crystalline phase of the spin Hall effect metal layer may not provide such spin transfer torque, but may provide a resistivity substantially lower than the first crystalline phase.

Such a magnetic tunneling junction device can be formed using any suitable technique or techniques. In an embodiment, a free magnetic layer may be disposed on the first portion of the spin Hall effect metal layer having the first crystal phase, and an insulator layer may be disposed on the free magnetic layer, and a fixed magnetic layer may be disposed. Arranged on the insulator layer, and a contact layer can be disposed on the fixed magnetic layer such that the second portion of the spin Hall effect metal layer is exposed, and the second portion of the spin Hall effect metal layer can be A crystalline phase is converted into a second crystalline phase that is less conductive than the first crystalline phase. For example, the exposure of the exposed second portion can include a flash annealing operation.

The spin Hall effect metal layer can comprise any suitable material or materials. In some embodiments, the spin Hall effect metal layer comprises or consists of tantalum or tungsten. For example, the first crystalline phase may be a beta phase 钽, and the second crystalline phase may be an alpha phase 钽; or the first crystalline phase may be a beta phase tungsten, and the first The second crystalline phase can be alpha phase tungsten. In some embodiments, the spin Hall effect metal layer comprises or consists of platinum.

Such a magnetic tunnel junction device can be implemented by circuitry or systems such as non-volatile magnetoresistive random access memory circuits or systems. In an embodiment, the non-volatile MRAM cell unit can include a selection transistor and a magnetic tunnel junction device coupled to the selection transistor such that the magnetic tunnel junction device includes an insulator layer and a spin Hall effect metal a layer, the insulator layer is between the fixed magnetic layer and the free magnetic layer, and the spin Hall effect metal layer has a first portion adjacent to the free magnetic layer and a second portion extending from the first portion and the free magnetic layer, such that a spin-Hall effect gold layer The first crystalline phase, and the second portion has a second crystalline phase that is less conductive than the spin Hall effect metal layer of the first crystalline phase, as described above.

1 is a side view of an exemplary magnetic tunnel junction device 100 configured in accordance with at least some implementations of the present disclosure. For example, the magnetic tunnel junction device 100 can have a reduced resistivity interconnect and thus can advantageously be used for low power devices. As shown, the magnetic tunnel junction device 100 can include a substrate 101, a spin Hall effect metal layer 102, a free magnetic layer 103, an insulator layer 104 (eg, a tunnel barrier), a fixed magnetic layer 105, an antiferromagnetic layer. 106 and contact layers 107, 108. For example, material stack 120 can include any of spin Hall effect metal layer 102, free magnetic layer 103, insulator track 104, fixed magnetic layer 105, antiferromagnetic layer 106, and contact layers 107, 108. For example, as discussed herein, material stack 120 can include free magnetic layer 103, insulator layer 104, fixed magnetic layer 105, antiferromagnetic layer 106, and contact layers 107, 108. Further, as shown, the free magnetic layer 103, the insulator layer 104, and the fixed magnetic layer 105 are available for the magnetic tunnel junction 123.

In operation, the fixed magnetic layer 105 can have a fixed magnetic polarity 112. In the illustrated example, the magnetic polarity 112 is in a direction extending from this page (eg, in the y-direction); however, any suitable fixed magnetic pole, such as extending into the page or in the vertical direction (eg, in the z-direction) may be provided. Sex 112. Further, as shown, the magnetic poles 111 of the free magnetic layer 103 can be flipped, switched, changed or modified, etc. by applying a charge current 109 through the spin Hall effect metal layer 102.

For example, the spin Hall effect metal layer 102 may include low resistance portions 113, 114 and a high resistance portion 115. Low resistance parts 113, 114 A particular crystalline phase of the spin Hall effect metal layer 102 can be included and the high resistance portion 115 can include a different crystalline phase of the spin Hall effect metal layer 102. For example, the crystalline phase of the high resistance portion 115 provides the ability to spin the Hall effect metal layer 102 to provide spin transfer torque for flipping or switching the magnetic polarity 111 of the free magnetic layer 103, while the low resistance portions 113, 114 The crystalline phase may not provide such functionality or may severely limit such functionality. As shown, in some embodiments, the high resistance portion 115 can be in direct contact with the free magnetic layer 103. In other embodiments, an intermediate layer or layer may be disposed between the high resistance portion 115 and the free magnetic layer 103 as long as the high resistance portion 115 can provide the free magnetic layer 103 as described herein.

As shown, through the high resistance portion 115 of the spin Hall effect metal layer 102, the charge current 109 can provide a spin current 110 that is orthogonal to the direction of the charge current 109 due to the spin Hall effect (SHE). In an embodiment, the charge current 109 in the x direction can provide a spin current 110 in the y direction and the charge current 109 in the negative x direction can provide a spin current 110 in the negative y direction. For example, the high resistance portion 115 of the spin Hall effect metal layer 102 can include beta phase germanium, beta phase tungsten, or beta phase platinum, which can provide a spin Hall effect to generate a spin current 110. The spin current 110 can flip, switch, change, or modify the magnetic polarity 111 through a spin transfer torque (STT). By switching the direction of the charge current 109, a spin current 110 in the opposite direction can be generated and the opposite polarity of the magnetic polarity 111 can be provided. The difference in polarity of the magnetic polarity 111 can be detected via a change in resistance through the magnetic tunnel junction device 100 such that a memory cell can be provided (eg, the memory cell can change the polarity of the magnetic polarity 111) write In, and read by resistance or the like).

For example, the crystalline phase of the particular material in question (eg, beta phase tantalum, tungsten, or platinum) can provide the ability to switch the state of the magnetic tunnel junction device 100 based on the spin Hall effect. However, as previously discussed, such crystalline phases can provide high resistance (e.g., such phases can be high resistivity phases), which can make them poor interconnects. However, the low resistance portions 113, 114 can advantageously provide lower resistance, and thus better characteristics of the interconnects of the spin Hall effect metal layer 102. For example, the low resistance portions 113, 114 may be different crystal phases for the high resistance portion 115. In one embodiment, the spin Hall effect metal layer 102 may comprise or consist entirely of germanium, the high resistance portion 115 may be beta phase and the low resistance portions 113, 114 may be alpha phase. In another embodiment, the spin Hall effect metal layer 102 may comprise or consist entirely of tungsten, the high resistance portion 115 may be beta phase tungsten and the low resistance portions 113, 114 may be alpha phase tungsten. In still another embodiment, the spin Hall effect metal layer 102 may comprise or consist entirely of platinum, the high resistance portion 115 may be beta phase platinum and the low resistance portions 113, 114 may be alpha phase platinum.

Such low resistance crystalline phases may, as previously discussed, provide preferred characteristics as interconnects; however, such characteristics may not provide spin current 110. Therefore, the spin Hall effect metal layer 102 may include the high resistance portion 115 to provide the spin Hall effect described above, and include the low resistance portions 113, 114 to provide a lower resistance. For example, the low resistance portions 113, 114 may extend from the high resistance portion 115 and the free magnetic layer 103, and as described, may include crystals having conductivity lower than that of the crystalline phase of the high resistance portion 115. phase. In some embodiments, the high resistance portion 115 may be characterized by a spin Hall effect portion, a high resistance crystalline phase portion, a spin Hall effect crystal phase portion or the like, and the low resistance portions 113, 114 may be characterized by interconnection Part, low resistance crystalline phase, interconnected crystalline phase or the like. In some embodiments, the resistance of the high resistance portion 115 may be approximately 5 to 10 times larger than the low resistance portions 113, 114. For example, the resistivity of beta phase tantalum and tungsten is about 10 times greater than that of alpha phase tantalum and tungsten.

In addition, FIG. 1 illustrates two low resistance portions 113 and 114 each extending from the high resistance portion 115 and the free magnetic layer 103 along the substrate 101. However, the magnetic tunnel junction device 100 can include any number of low resistance portions 113, 114, such as a low resistance portion or three or more low resistance portions. The low resistance portions 113, 114 may extend along the top of the substrate 101 as shown, or the low resistance portions 113, 114 may extend within a substrate 101 such as a channel formed in the substrate 101 or the like.

As described, the spin Hall effect metal layer 102 can include a high resistance portion 115 and one or more low resistance portions 113, 114 extending from the high resistance portion 115. The high resistance portion 115 and the low resistance portions 113, 114 may be connected at a phase boundary having any suitable shape, such as a phase boundary 121 between the high resistance portion 115 and the low resistance portion 113 and a high resistance portion 115 and a low resistance portion. The phase boundary 122 between 113. In the embodiment of FIG. 1, the phase boundaries 121, 122 extend substantially vertically downward from the corners of the free magnetic layer 103 to the edges of the spin Hall effect metal layer 102. However, as noted, the phase boundaries 121, 122 can have any suitable shape.

2 illustrates at least some implementation configurations in accordance with the present disclosure Exemplary phase boundaries 201, 202 between the high resistance portion 115 and the low resistance portions 113, 114 of the spin Hall effect metal layer 102. As shown, in some embodiments, the phase boundaries 201, 202 between the high resistance portion 115 and the low resistance portions 113, 114 may have extensions from the corners 203, 204 of the free magnetic layer 103 to the spin Hall effect. The outline of the edge of the metal layer 102. For example, the phase boundary 201 can extend from the corner 203 of the free magnetic layer 103 to the bottom edge 207 of the spin Hall effect metal layer 102 at the location 205, the location 205 being outside of the free magnetic layer 103, and the phase Boundary 202 may extend from a corner 204 of free magnetic layer 103 to a bottom edge 207 of spin Hall effect metal layer 103 at location 206, which is outside of free magnetic layer 103. In the illustrated example, the phase boundaries 201, 202 have a concave curved profile. However, the phase boundaries 201, 202 can have any suitable shape such as a linear profile.

Returning to FIG. 1, as described, the magnetic tunnel junction device 100 can include a substrate 101. Substrate 101 can comprise any suitable material, materials, and devices. In an embodiment. The substrate 101 may include a semiconductor material such as single crystal germanium (Si), germanium (Ge), germanium (SiGe), a material of a group III-V material (for example, gallium arsenide (GaAs)), tantalum carbide (SiC), Sapphire (Al ₂ O ₃ ) or any combination thereof. In an embodiment, the substrate 101 may include a crucible having a (100) crystal orientation. In various examples, substrate 101 can include a metallization interconnect layer for use in an integrated circuit or electronic device, such as a transistor, memory, capacitor, resistor, optoelectronic device, switch, or any other electrically insulating layer ( For example, interlayer dielectrics, trench isolation layers, etc.) separate active or passive electronic devices. For example, substrate 101 can include metal contacts and interconnects as discussed further herein with respect to FIG.

As shown, the magnetic tunnel junction device 100 can include a spin Hall effect metal layer 102 having low resistance portions 113, 114 each extending from the high resistance portion 115 over the substrate 101. In some embodiments, the spin Hall effect metal layer 102 comprises tantalum, tungsten or platinum having low resistance portions 113, 114 and high resistance portions 115 comprising different crystalline phases as discussed herein. The spin Hall effect metal layer 102 can have any suitable thickness, such as a thickness of about equal to or greater than 8 nm. Furthermore, the magnetic tunnel junction device 100 can include a free magnetic layer 103 disposed over the high resistance portion 115 of the spin Hall effect metal layer 102 such that the low resistance portions 113, 114 are exposed to the free magnetic layer 103 and The composition of the other material stacks 120. As is understood by us, the exposed low resistance portions 113, 114 may be covered by a dielectric layer or a passivation layer or the like such that the exposed low resistance portions 113, 114 may be exposed in the material stack 120 but by the dielectric layer Or covered by a passivation layer or the like. The free magnetic layer 103 can comprise any suitable material or materials, such as any suitable thickness of ferromagnetic material, such as a thickness in the range of about 0.4 to 3 nm. In an embodiment, the free magnetic layer 103 is cobalt iron boron (CoFeB).

Moreover, as shown, the magnetic tunnel junction device 100 can include an insulator layer 104 (eg, a tunneling barrier) over the free magnetic layer 103. The insulator layer 104 can comprise any suitable material or materials, such as magnesium oxide of any suitable thickness having a thickness, such as in the range of 0.4 to 3 nm. The fixed magnetic layer 105 can be disposed on the insulator layer 104. And the fixed magnetic layer 105 can comprise any suitable material or materials, such as a ferromagnetic material having any suitable thickness, such as a thickness in the range of 0.4 to 3 nm. In one embodiment, the fixed magnetic layer 105 is cobalt iron boron (CoFeB). The free magnetic layer 103 and the fixed magnetic layer 105 may have the same thickness or their thicknesses may be different. The magnetic tunnel junction device 100 can also include an antiferromagnetic layer 106 over the fixed magnetic layer 105 with the contact layers 107, 108 over the antiferromagnetic layer 106. The antiferromagnetic layer 106 and the contact layers 107, 108 can comprise any suitable material or materials of any suitable thickness. In one embodiment, the antiferromagnetic layer 106 is a synthetic antiferromagnetic (SAF) layer. In an embodiment, the contact layers 107, 108 may comprise tantalum and niobium, respectively. In some embodiments, the contact layers 107, 108 comprise two layers as shown; however, any number of contact layers such as a contact layer can be used. In some embodiments, contact layer 107 and/or contact layer 108 may be characterized by electrodes such as fixed electrodes, and spin Hall effect metal layer 102 may be characterized by electrodes such as free electrodes.

As shown, in some embodiments. The free magnetic layer 103, the insulator layer 104, the fixed magnetic layer 105, the antiferromagnetic layer 106, and the contact layers 107, 108 of the material stack 120 can have substantially vertical sidewalls. However, in some embodiments, such sidewalls may be tapered. Moreover, material stack 120 can have any suitable size. For example, the free magnetic layer 103, the insulator layer 104, the fixed magnetic layer 105, the antiferromagnetic layer 106, and the contact layers 107, 108 of the material stack 120 can have a width of about 50 to 70 nm (eg, in the x direction) and approximately 120 To a depth of 200 nm (eg in the y direction).

3 is a side view of an exemplary integrated circuit 300 that includes a magnetic tunnel junction device 100 and a magnetic tunnel junction device 301, at least configured in accordance with certain embodiments of the present disclosure. For example, the integrated circuit 300 can include a memory circuit, a processor with integrated memory, or a system single chip, and the like. As shown, the integrated circuit 300 can include a magnetic tunnel junction device 100 and a magnetic tunnel junction device 301 having any of the characteristics described herein. For example, the magnetic tunnel junction device 100 can include a material stack 120 that includes a spin Hall effect metal layer 102 having a high resistance portion 115 and low resistance portions 113, 114. Furthermore, the magnetic tunnel junction device 301 can include a material stack 320 that includes a spin Hall effect metal layer 302 having a high resistance portion 315 and low resistance portions 113, 114. The magnetic tunnel junction device 301 can have any of the characteristics described herein with respect to the magnetic tunnel junction device 100. In some embodiments, the magnetic tunneling junction devices 100, 301 can have the same characteristics, and in other embodiments, they can have one or more different characteristics.

As shown, substrate 101 can include contacts 331-334 disposed within interlayer dielectric 341 (ILD). For example, contacts 331-334 can interconnect magnetic tunnel junction devices 100, 301 to devices formed within the underlying layers of substrate 101, such as logic transistors, or other devices, and the like. For example, as shown, the low resistance portions 113, 114 of the spin Hall effect metal layer 102 may extend to the contacts 331, 332, respectively, and the low resistance portions 313, 314 of the spin Hall effect metal layer 302 may be respectively Extends to contacts 333, 334. These low resistance parts can provide like low resistivity The interconnect characteristics, and the high resistance portions 115, 315 can provide operation of the magnetic tunnel junction devices 100, 301 as described herein. In the illustrated example, contacts 331-334 are below magnetic tunnel junction devices 100,301. In other examples, one or more contacts 331-334 may be beside or above the magnetic tunneling junction devices 100,301.

Additional details regarding the features of the magnetic tunneling junction devices 100, 301 are provided herein with respect to Figures 5A-5G and related discussions, which provide additional details regarding the formation of the magnetic tunneling junction devices 100,301. Moreover, the magnetic tunnel junction devices 100, 301 can be implemented in electronic device structures such as logic devices that incorporate memory, or MRAM, etc., as discussed further herein.

4 is a flow diagram illustrating an exemplary method 400 for forming a magnetic tunnel junction device having a reduced resistivity metal interconnect configured to be constructed in accordance with at least certain embodiments of the present disclosure. For example, method 400 can be implemented for magnetic tunnel junction device 100 and/or magnetic tunnel junction device 301, as discussed herein. In the illustrated implementation, method 400 can include one or more operations as illustrated by 401-403. However, the embodiments herein may include additional operations, specific operations that are omitted, or operations that are not performed in the order presented.

The method 400 may begin at operation 401, "Setting a free magnetic layer on a first portion of a spin Hall effect metal layer having a first crystalline phase", wherein a free magnetic layer may be disposed in the first crystalline phase Above a first portion of the spin Hall effect metal layer. For example, the first crystalline phase can be operable to switch the free magnetic layer (eg, the first crystalline phase can be beta phase) The phase of ruthenium, beta phase tungsten, or beta phase platinum, etc.). In an embodiment, the free magnetic layer 103 of the material stack 120 and/or the free magnetic layer of the material stack 320 may be formed over portions of the spin Hall effect metal layers 503, 504, respectively, as further illustrated herein. 5A-5E and the discussion in this article. In one embodiment, a free magnetic layer may be disposed over the first portion of the spin Hall effect metal layer using a bulk deposition technique and subsequent patterning techniques.

The method 400 can continue with operation 402, "providing an insulator layer, a fixed magnetic layer, and a contact layer over the free magnetic layer such that a second portion of the spin Hall effect metal layer is exposed." Wherein, an insulator layer may be disposed on the free magnetic layer, a free magnetic layer may be disposed on the insulator layer, and a contact layer may be disposed on the fixed magnetic layer to form a spin Hall effect metal layer A second part was exposed. In an embodiment, one or both of the insulator layer 104, the fixed magnetic layer 105, and the contact layers 107, 108 of the material stack 120 may be disposed over the free magnetic layer 103, and/or the insulator layer of the material stack 320. One or both of the fixed magnetic layer, and the contact layer may be disposed over the free magnetic layer of the material stack 320, as further discussed herein with respect to Figures 5C-5E and elsewhere herein. In one embodiment, using a large number of placement techniques and subsequent patterning techniques, an insulator layer can be disposed over the free magnetic layer, a fixed magnetic layer can be disposed over the insulator layer, and the contact layer can be disposed over the fixed magnetic layer .

The method 400 can continue with operation 403, "Conversion of the second portion of the spin Hall effect metal layer from the first crystalline phase to the second crystalline phase", wherein the exposed Hall of the spin Hall effect metal layer The second part can The first crystalline phase is converted to a second crystalline phase having a lower conductivity than the first crystalline phase. The exposed second portion of the spin Hall effect metal layer can be converted using any suitable technique or techniques. In one embodiment, the second portion of the spin Hall effect metal layer can be converted from the first crystalline phase to the second crystalline phase via a flash annealing operation, as further discussed herein with respect to FIG. 5F and elsewhere herein.

As previously discussed, method 400 can be implemented to fabricate magnetic tunnel junction device 100 and/or magnetic tunnel junction device 301. Further details associated with such manufacturing techniques are specifically discussed herein with respect to Figures 5A-5G. Any one or more of the operations of method 400 (or the operations discussed herein with respect to Figures 5A-5G) may be performed in response to instructions provided by one or more computer program products. Such a program product may include a signal bearing medium that provides instructions that, when executed by, for example, a processor, may provide the functionality described herein. This computer program product can be provided in any form of computer readable media. Thus, for example, a processor including one or more processor cores can perform one or more of the operations described herein in response to the instructions being transferred to the processor by computer readable media.

5A-5G are side views of an exemplary magnetic tunnel junction device structure for performing a particular fabrication operation, at least in accordance with certain implementations of the present disclosure. FIG. 5A illustrates a side view of a magnetic tunneling junction device structure 501. As shown in FIG. 5A, the magnetic tunnel junction device structure 501 includes a substrate 101 having contacts 331-334 disposed with an interlayer dielectric 341. For example, contacts 331-334 can interconnect subsequently formed magnetic tunnel junction devices 100, 301 to devices previously formed in the lower layer of substrate 101, Such as logic transistors, or other devices. In an embodiment, the contacts 331-334 can provide a connection to the metal layer 102 of the device formed within the substrate 101. Substrate 101 can be formed using any suitable technique or techniques.

FIG. 5B illustrates a magnetic tunnel junction device structure 502 similar to the magnetic tunnel junction device structure 501 after forming the spin Hall effect metal layers 503, 504. The spin Hall effect metal layers 503, 504 can be formed using any suitable technique or techniques. In one embodiment, the spin Hall effect metal layers 503, 504 may be provided by providing a bulk material layer (eg, by electroplating or deposition, etc.) and subsequent patterning (eg, by lithography patterning) And etching techniques, etc.) to form. The spin Hall effect metal layers 503, 504 can include any one or more materials operable to provide spin transfer torque to a subsequently formed free magnetic layer, as discussed herein. In one embodiment, the spin Hall effect metal layers 503, 504 comprise or consist entirely of beta phase germanium. In another embodiment, the spin Hall effect metal layers 503, 504 comprise or consist entirely of beta phase tungsten. In yet another embodiment, the spin Hall effect metal layers 503, 504 comprise or consist entirely of beta phase platinum. Although illustrated with spin Hall effect metal layers 503, 504 having the same composition, in some embodiments, spin Hall effect metal layers 503, 504 can have different compositions. As previously discussed, the spin Hall effect metal layers 503, 504 can extend from the contacts 331, 332 and the contacts 333, 334, respectively. Furthermore, the spin Hall effect metal layers 503, 504 can have any suitable thickness, such as a thickness equal to or greater than 8 nm.

FIG. 5C illustrates a similar magnetic tunneling after forming the bulk free magnetic layer 506, the bulk insulator layer 507, the bulk fixed magnetic layer 508, the bulk antiferromagnetic layer 509, the bulk contact layer 510, and the bulk contact layer 511. The magnetic tunneling junction device structure 505 of the junction device structure 502. The bulk free magnetic layer 506, the bulk insulator layer 507, the bulk fixed magnetic layer 508, the bulk antiferromagnetic layer 509, the bulk contact may be formed using any suitable one or more techniques, such as electroplating, or deposition, or the like. Layer 510 and bulk contact layer 511. Further, the bulk free magnetic layer 506, the bulk insulator layer 507, the bulk fixed magnetic layer 508, the bulk antiferromagnetic layer 509, the bulk contact layer 510, and the bulk contact layer 511 may have any suitable thickness. For example, the bulk free magnetic layer 506 may have a thickness in the range of about 0.4 to 3 nm over the spin Hall effect metal layers 503, 504, and the bulk insulator layer 507 may have a range of about 0.4 to 3 nm. The inner thickness, as well as the bulk fixed magnetic layer 508, may have a thickness in the range of about 0.4 to 3 nm.

FIG. 5D illustrates a magnetic tunnel junction device structure 512 similar to the magnetic tunnel junction device structure 505 after forming the mask 513 of the material stack 120. Mask 513 can be formed using any suitable technique or techniques, such as lithography. In some embodiments, the mask 513 can comprise a hardmask material (eg, hafnium oxide, tantalum nitride, hafnium oxynitride, or aluminum oxide, etc.). The mask 513 can be any material that provides for the bulk free magnetic layer 506, the bulk insulator layer 507, the bulk fixed magnetic layer 508, the bulk antiferromagnetic layer 509, the bulk contact layer 510, and/or the bulk contact. Patterning selectivity of layer 511. In some embodiments, the formation of the material stacks 120, 320 can include material removal techniques such as etching techniques and the like. Surgery.

FIG. 5E illustrates a magnetic tunnel junction device structure 514 similar to the magnetic tunnel junction device structure 512 after removal of the mask 513. The mask 513 can be removed using any suitable technique or techniques, such as ashing techniques, or etching techniques, and the like.

5F illustrates a similar magnetic tunneling junction device structure 514 during the transition of the exposed portion of the spin Hall effect metal layers 503, 504 from the first crystalline phase to the second crystalline phase having a lower conductivity than the first crystal. Magnetic tunneling junction device structure 515. As previously discussed, the second crystalline phase can have a lower electrical conductivity than the first crystalline phase to provide advantageous interconnect properties and such that the second crystalline phase may not be able to convert the free magnetic layer through spin transfer torque, as herein The arguer. As previously discussed, the exposed portions of the spin Hall effect metal layers 503, 504 are converted from the first crystalline phase to the second crystalline phase using any suitable technique or techniques.

In the example of FIG. 5F, the exposed portions of the spin Hall effect metal layers 503, 504 can be converted using a flash anneal operation. For example, flash 516 can provide a radiation 517 that can flash anneat the exposed portions of spin Hall effect metal layers 503, 504 to convert them from the first to the second crystalline phase. In one embodiment, the exposed portion can be beta phase 钽 and flash anneal can anneal the exposed portions to form alpha phase 钽 low resistance portions 113, 114, 313, 314 and leave beta phase 钽 high resistance portions 115, 315. In such an embodiment, the flash annealing may anneal the exposed portion to a temperature of not less than 750 ° C or to anneal the exposed portion at a temperature of not less than 750 ° C. In another embodiment, the exposed portion can be beta phase tungsten and flash Annealing may anneal the exposed portions to form alpha phase tungsten low resistance portions 113, 114, 313, 314 and leave beta phase tungsten high resistance portions 115, 315. In such an embodiment, the flash annealing may anneal the exposed portion to a temperature of not less than 850 ° C or to anneal the exposed portion at a temperature of not less than 850 ° C. In yet another embodiment, the exposed portion can be beta phase platinum and the flash anneal annealed exposed portion to form alpha phase platinum low resistance portions 113, 114, 313, 314 and leave beta phase platinum high resistance portions 115, 315 . In such an embodiment, the flash annealing may anneal the exposed portion to a temperature of not less than 750 ° C or to anneal the exposed portion at a temperature of not less than 750 ° C.

As previously discussed, flash annealing may leave high resistance portions 115, 315. For example, the material stacks 120, 320 can block the high resistance portions 115, 315 from being exposed in the radiation 517 and thereby maintaining the crystalline phase of the high resistance portions 115, 315. The aforementioned flash anneal can be carried out using any suitable technique or techniques. For example, flash annealing can include flash or radiation intensity or power and/or flash or radiation duration. One or both of such strength or power and/or duration may be adjusted to provide the aforementioned flash annealing temperature and/or crystalline phase change. In some embodiments, the radiation 517 can be provided from the flash 516 in the range of microseconds to milliseconds.

FIG. 5G illustrates a magnetic tunnel junction device structure 518 similar to the magnetic tunnel junction device structure 515 after forming the low resistance portions 113, 114, 313, 314. The magnetic tunneling junction device structure 518 can have any of the features discussed herein, such as those discussed with respect to Figures 1-3. Moreover, as we understand, the magnetic tunnel junction device structure 518 can be further processed, such as for creating additional interconnect layers (eg, metal layers and contacts or wear) Backend processing of hole layers, passivation, encapsulation, etc. Such back-end processing may include a limitation on the processing temperature (for example, a temperature limit of not higher than 400 ° C or the like), which ensures that the high-resistance portions 115, 315 do not suffer from a change in the crystal phase (for example, a high-resistance portion) 115, 315 are operable to switch the free magnetic layer, as discussed herein).

5A-5G illustrate an exemplary flow diagram for fabricating magnetic tunnel junction device 100 and/or magnetic tunnel junction device 301 as discussed herein. In various examples, additional operations may be included or specific operations may be omitted.

6 illustrates an example of an exemplary MRAM cell 600 implementing a magnetic tunnel junction device 601 having a reduced resistivity metal interconnect, at least in accordance with certain implementations of the present disclosure. As shown, the MRAM cell 600 can include a magnetic tunnel junction device 601, a select transistor 605, a word line 604, a source line 606, a bit line 603, and a reference line 602. As shown, the magnetic tunnel junction device 601 can be coupled to the select transistor 605 for selection for reading and writing. For example, when the magnetic tunnel junction device 601 is selected through the selection transistor 605 established by the word line 604, the magnetic tunnel junction device 601 can be provided through the bit line 603 and the source line 606. The current of the magnetic tunnel junction device 601 is read. For example, the resistance of the magnetic tunnel junction device 601 can be evaluated to determine the bits of information stored therein. Furthermore, the magnetic tunnel junction device 601 can be written by the current flowing through the high resistance portion 115 of the spin Hall effect metal layer 102 provided by the bit line 603 and the reference line 602 as discussed herein. For example, reference line 602 can be held at a reference potential such as ground And provide a reference plane and more. MRAM cell 600 may include additional read and write circuits (not shown), sense amplifiers (not shown), or bit line references (not shown), etc., as would be appreciated by the art. As understood by those skilled in the art, it is used for the operation of the MRAM unit 600. The MRAM cell 600 can be characterized by a bit cell, an MRAM bit cell, or a spin Hall effect magnetic tunneling junction (SHE-MTJ) bit cell, and the like.

Referring now to Figure 6, the magnetic tunneling junction device 601 can include any of the features discussed with respect to the magnetic tunneling junction device 100 or elsewhere herein. For example, the magnetic tunnel junction device 601 may include an insulator layer and a spin Hall effect metal layer, the insulator layer is between the fixed magnetic layer and the free magnetic layer, and the spin Hall effect metal layer has a adjacent to the free magnetic layer. a first portion and a second portion extending from the first portion and the free magnetic layer such that the first portion includes a first crystalline phase of the spin Hall effect gold layer and the second portion includes conductivity lower than the first crystalline phase The second crystalline phase of the spin Hall effect metal layer. In one embodiment, the spin Hall effect metal layer comprises germanium, the first phase comprises a beta phase and the second phase comprises an alpha phase. In another embodiment, the spin Hall effect metal layer comprises tungsten, the first phase comprises beta phase tungsten, and the second phase comprises alpha phase tungsten. In yet another embodiment, the spin Hall effect metal layer comprises tantalum or tungsten, the free magnetic layer and the fixed magnetic layer comprise cobalt iron boron, and the insulator layer comprises magnesium oxide.

7 is a schematic diagram of a mobile computing platform 700 employing a magnetic tunneling junction device having a reduced resistivity metal interconnect, at least in accordance with certain implementations of the present disclosure. For example, the mobile computing platform 700 can The invention includes a magnetic tunnel junction device having a spin Hall effect metal layer having a first portion having a first crystal phase adjacent to the free magnetic layer and a second crystal phase having lower conductivity than the first crystal phase The second part. The magnetic tunneling junction device can be any of the magnetic tunneling junction devices discussed herein, such as magnetic tunneling junction device 100 or magnetic tunneling junction device 301, and the like. In some examples, the magnetic tunnel junction device and the transistor can be implemented together as an integrated circuit. The mobile computing platform 700 can be any portable device that is configured for each of electronic data display, or electronic data processing, or wireless electronic data transmission, and the like. For example, the mobile computing platform 700 can be any of a tablet, a smart phone, a simple notebook, a laptop, etc., and can include a display screen 705, which in the illustrative embodiment is a touch A screen (eg, a touch screen of capacitive, inductive, resistive, etc.), a wafer level (SoC) or package level integration system 710, and a battery 715.

Integration system 710 is further depicted in expanded view 720. In an exemplary embodiment, package device 750 (labeled "memory/processor" in FIG. 7) includes at least one memory chip (eg, MRAM), and/or at least one processor die (eg, micro-processing) , multi-core processor, or graphics processor, etc.). In one embodiment, package device 750 is a microprocessor that includes MRAM cache memory. In an embodiment, the packaged device 750 includes one or more magnetic tunneling junction devices 100 or magnetic tunnel junction devices 301 or both. For example, a memory unit employed may include a magnetic tunnel junction device 100 or a magnetic tunnel junction device 301. Encapsulation device 750 can be further coupled to (eg, Communicatingly coupled to a board, substrate, interposer 760, and one or more power management integrated circuits (PMICs) 730, RF (wireless) including wideband RF (wireless) transmitters and/or receivers (TX/RX) A integrated circuit (RFIC) 725 (eg, including a digital baseband and analog front-end module further includes a power amplifier on the transmit path and a low noise amplifier on the receive path), and a controller 735 thereof. In general, package device 750 can also be coupled (e.g., communicatively coupled) to display screen 705.

Functionally, the PMIC 730 can perform battery power regulation, DC to DC conversion, etc., as well as inputs coupled to the battery 715 and provide current output to other functional modules. In an embodiment, PMIC 730 can perform high voltage operation. As further illustrated, in an exemplary embodiment, RFIC 725 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family) ), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any designation Other wireless protocols for 3G, 4G, 5G and more. In an alternate embodiment, each of the board level modules can be integrated into a separate IC coupled to the package substrate of the package device 750, or integrated into a single IC (SoC) coupled to the package substrate of the package device 750. Inside.

8 is a functional block diagram of computing device 800 that is configured in accordance with at least some of the implementations of the present disclosure. The computing device 800 can be found, for example, inside the platform 800, and further includes hosting, for example, but not limited to A motherboard 802 of a plurality of components of the processor 801 (eg, an application processor) and one or more communication chips 804, 805. Processor 801 can be physically and/or electrically coupled to motherboard 802. In some embodiments, processor 801 includes integrated circuit dies that are packaged within processor 801. In general, the term "processor" may refer to any device that processes electronic data from a register and/or memory to convert the electronic data into other electronic data that can be stored in a register and/or memory. Or part of the device.

In various examples, one or more of the communication chips 804, 805 can also be physically and/or electrically coupled to the motherboard 802. In further implementations, the communication chip 804 can be part of the processor 801. Computing device 800 may include other components that may or may not be physically and electrically coupled to 802, depending on its application. Such other components may include, but are not limited to, volatile memory (eg, DRAM) 807, 808, non-volatile memory (eg, ROM) 810, graphics processor 812, flash memory, global positioning system (GPS) Apparatus 813, compass 814, chipset 806, antenna 816, power amplifier (AMP) 809, touch screen controller 811, touch screen display 817, speaker 815, camera 803, and battery 818, as depicted, Others such as digital signal processors, cryptographic processors, audio codecs, video codecs, accelerometers, gyroscopes, and mass storage devices (eg, hard disk drives, solid state drives (SSD), compact discs (CDs) ), digital audio and video (DVD), etc.), or the like.

The communication chips 804, 805 can transmit data and receive data from another computing device 800 via wireless communication. The term "wireless" and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels. Etc., transmitting data to non-solid media through the use of modulated electromagnetic waves. The term does not imply that the associated device does not include any circuitry, although in some embodiments the circuitry may not be included. Communication chips 804, 805 can implement any number of wireless standards or protocols, including but not limited to those discussed herein. As previously discussed, computing device 800 can include a plurality of communication chips 804, 805. For example, the first communication chip can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and other.

As used in any of the implementations described herein, the term "module" means any combination of software, firmware, and/or hardware configured to provide the functionality described herein. The software can be implemented as a packaged software, code and/or instruction set or instruction, and "hardware" can be used in any of the implementations described herein, and can include, for example, a single form or any combination, fixed line ( A hardwired circuit, a programmable circuit, a state machine circuit, and/or a firmware that stores instructions executed by the programmable circuit. The modules may be implemented, in whole or in part, as part of a larger system such as an integrated circuit (IC) or a system single chip (SoC).

Although certain features are described herein with reference to various embodiments, the description is not intended to be construed as a limitation. Therefore, various modifications of the embodiments described herein, as well as other embodiments that are readily apparent to those skilled in the art of the present disclosure, are considered to be within the spirit and scope of the disclosure.

The examples below are related to further embodiments.

In one or more first embodiments, a magnetic tunnel junction device includes an insulator layer and a spin Hall effect metal layer between the fixed magnetic layer and the free magnetic layer, the spin Hall effect The metal layer has a first portion adjacent to the free magnetic layer and a second portion extending from the first portion and the free magnetic layer, wherein the first portion includes the first crystal of the spin Hall effect gold layer And the second portion comprises a second crystalline phase of the spin Hall effect metal layer having a lower conductivity than the first crystalline phase.

Further with respect to the first embodiment, the spin Hall effect metal layer comprises germanium, the first phase comprises a beta phase 钽, and the second phase comprises an alpha phase 钽.

Further with respect to the first embodiment, the spin Hall effect metal layer comprises tungsten, the first phase comprises beta phase tungsten, and the second phase comprises alpha phase tungsten.

Further to this first embodiment, the spin Hall effect metal layer is composed of tantalum or tungsten.

Further with regard to the first embodiment, the fixed magnetic layer and the free magnetic layer comprise cobalt iron boron and the insulator layer comprises magnesium oxide.

Further with regard to the first embodiment, the spin Hall effect metal layer is composed of tantalum or tungsten, the fixed magnetic layer and the free magnetic layer comprise cobalt iron boron, and the insulator layer contains magnesium oxide.

Further with regard to the first embodiment, the first portion of the spin Hall effect metal layer is in contact with the free magnetic layer.

Further with respect to the first embodiment, in response to a charge current, the first portion of the spin Hall effect metal layer is used to transmit torque via spin transfer A spin current is provided to switch the polarity of the free magnetic layer.

Further with regard to the first embodiment, the first portion of the spin Hall effect metal layer is in contact with the free magnetic layer and/or in response to a charge current, the first portion of the spin Hall effect metal layer is used The spin current is supplied via spin transfer torque to convert the polarity of the free magnetic layer.

Further with regard to the first embodiment, the magnetic tunneling junction device further includes an antiferromagnetic layer in contact with the fixed magnetic layer and a metal contact layer in contact with the antiferromagnetic layer.

Further with respect to the first embodiment, the first and the second crystalline phase are in phase boundary, the phase boundary having a profile extending from a corner of the free magnetic layer.

Further with regard to the first embodiment, the second portion of the spin Hall effect metal layer extends from the first portion along the substrate to a contact disposed within the substrate.

In one or more second embodiments, a method for fabricating a magnetic tunnel junction device includes: providing a free magnetic layer to a first portion of a spin Hall effect metal layer having a first crystalline phase An insulator layer is disposed on the free magnetic layer, a fixed magnetic layer is over the insulator layer, and a contact layer is over the fixed magnetic layer, wherein the spin Hall effect metal layer is The second portion is exposed and the second portion of the spin Hall effect metal layer is converted from the first crystalline phase to a second crystalline phase having a lower conductivity than the first crystalline phase.

Further with regard to the second embodiment, converting the second portion of the spin Hall effect metal layer comprises a flash annealing operation.

Further with regard to the second embodiment, converting the second portion of the spin Hall effect metal layer comprises a flash annealing operation, the spin Hall effect metal layer comprises germanium, and the flash annealing operation applies the spin The second portion of the effect metal layer is annealed to a temperature of not less than 750 °C.

Further with regard to the second embodiment, converting the second portion of the spin Hall effect metal layer comprises a flash annealing operation, the spin Hall effect metal layer comprises tungsten, and the flash annealing operation applies the spin The second portion of the effect metal layer is annealed to a temperature of not less than 850 °C.

Further with regard to the second embodiment, converting the second portion of the spin Hall effect metal layer comprises a flash annealing operation, the spin Hall effect metal layer comprises germanium, and the flash annealing operation applies the spin The second portion of the effect metal layer is annealed to a temperature of not less than 750 ° C or the spin Hall effect metal layer comprises tungsten, and the flash annealing operation operates the second portion of the spin Hall effect metal layer Anneal to a temperature of not less than 850 °C.

Further to the second embodiment, the method further includes disposing an antiferromagnetic layer between the free magnetic layer and the contact.

In one or more third embodiments, a non-volatile MRAM bit cell includes a selection transistor and a magnetic tunnel junction device coupled to the selection transistor, the magnetic tunnel junction device including an insulator layer and a spin-effect metal layer between the fixed magnetic layer and the free magnetic layer, the spin Hall effect metal layer having a first portion adjacent to the free magnetic layer and from the first portion and the free magnetic a second portion extending from the layer, wherein the first portion comprises a first crystalline phase of the spin Hall effect gold layer and the second portion comprises the spin Hall effect metal having a lower conductivity than the first crystalline phase The second crystalline phase of the layer.

Further with respect to the third embodiment, the spin Hall effect metal layer comprises germanium, the first phase comprises a beta phase, and the second phase comprises an alpha phase.

Further with regard to the third embodiment, the spin Hall effect metal layer comprises tungsten, the first phase comprises beta phase tungsten, and the second phase comprises alpha phase tungsten.

Further with regard to the third embodiment, the spin Hall effect metal layer is composed of tantalum or tungsten, the fixed magnetic layer and the free magnetic layer comprise cobalt iron boron, and the insulator layer contains magnesium oxide.

Further with regard to the third embodiment, the first portion of the spin Hall effect metal layer is in contact with the free magnetic layer.

In one or more fourth embodiments, the mobile computing platform includes the example structure described in relation to the first or second embodiment.

It is to be understood that the invention is not limited to the described embodiments, and that the invention may be practiced without departing from the scope of the appended claims. For example, the above-described embodiments may include specific combinations of features. However, the above-described embodiments are not limited in this respect, and in various embodiments, the above-described embodiments may include: taking only a subset of the features; taking the features in a different order; taking the features Different combinations; and/or taking additional features beyond those explicitly listed. Accordingly, the scope of the invention should be determined by the scope of the appended claims and the scope of the claims.

102‧‧‧ Spin Hall effect metal layer

103‧‧‧Free magnetic layer

113‧‧‧Low resistance section

114‧‧‧Low resistance section

115‧‧‧High Resistance Department

201‧‧‧ phase

202‧‧‧ phase

203‧‧‧ corner

204‧‧‧ corner

205‧‧‧ position

206‧‧‧Location

207‧‧‧ bottom edge

Claims (20)

A magnetic tunneling junction device comprising: an insulator layer between a fixed magnetic layer and a free magnetic layer; and a spin Hall effect metal layer having a first portion adjacent to the free magnetic layer and from the first portion a second portion extending from the free magnetic layer, wherein the first portion comprises a first crystalline phase of the spin Hall effect gold layer, and the second portion comprises a conductivity lower than the first crystalline phase The second crystalline phase of the spin Hall effect metal layer. The magnetic tunnel junction device of claim 1, wherein the spin Hall effect metal layer comprises germanium, the first phase comprises a beta phase 钽, and the second phase comprises an alpha phase ( Alpha phase)钽. The magnetic tunnel junction device of claim 1, wherein the spin Hall effect metal layer comprises tungsten, the first phase comprises beta phase tungsten, and the second phase comprises alpha phase tungsten. The magnetic tunnel junction device of claim 1, wherein the spin Hall effect metal layer is composed of tantalum or tungsten. The magnetic tunnel junction device of claim 1, wherein the fixed magnetic layer and the free magnetic layer comprise cobalt iron boron, and the insulator layer comprises magnesium oxide. The magnetic tunnel junction device of claim 1, wherein the first portion of the spin Hall effect metal layer is in contact with the free magnetic layer. For example, the magnetic tunneling junction device of claim 1 is And responding to the charge current, the first portion of the spin Hall effect metal layer is configured to provide a spin current via a spin transfer torque to switch the polarity of the free magnetic layer. The magnetic tunnel junction device of claim 1, further comprising an antiferromagnetic layer in contact with the fixed magnetic layer and a metal contact layer in contact with the antiferromagnetic layer. The magnetic tunnel junction device of claim 1, wherein the first and the second crystal phase are in phase boundary, the phase boundary having a contour extending from a corner of the free magnetic layer. The magnetic tunnel junction device of claim 1, wherein the second portion of the spin Hall effect metal layer extends along the substrate from the first portion to a contact disposed within the substrate. A method for fabricating a magnetic tunnel junction device includes: disposing a free magnetic layer over a first portion of a spin Hall effect metal layer having a first crystalline phase; and providing an insulator layer to the free magnetic layer Above, a fixed magnetic layer over the insulator layer, and a contact layer over the fixed magnetic layer, wherein a second portion of the spin Hall effect metal layer is exposed; and the spin The second portion of the effect metal layer is converted from the first crystalline phase to a second crystalline phase having a lower conductivity than the first crystalline phase. The method of claim 11, wherein converting the second portion of the spin Hall effect metal layer comprises a flash annealing operation. The method of claim 12, wherein the spin Hall effect metal layer comprises germanium, and the flash annealing operation is performed on the spin Hall The second portion of the effect metal layer is annealed to a temperature of not less than 750 °C. The method of claim 12, wherein the spin Hall effect metal layer comprises tungsten, and the flash annealing operation anneals the second portion of the spin Hall effect metal layer to not less than 850 ° C temperature. The method of claim 11, further comprising providing an antiferromagnetic layer between the fixed magnetic layer and the contact. A non-volatile MRAM (magnetoresistive random access memory) bit cell includes: a selection transistor and a magnetic tunnel junction device coupled to the selection transistor, the magnetic tunnel junction device comprising: an insulator layer Between the fixed magnetic layer and the free magnetic layer; and the spin Hall effect metal layer, having a first portion adjacent to the free magnetic layer and a second portion extending from the first portion and the free magnetic layer, Wherein the first portion comprises a first crystalline phase of the spin Hall effect gold layer, and the second portion comprises a second phase of the spin Hall effect metal layer having a lower conductivity than the first crystalline phase Crystal phase. The non-volatile MRAM cell of claim 16, wherein the spin Hall effect metal layer comprises germanium, the first phase comprises a beta phase, and the second phase comprises an alpha phase. The non-volatile MRAM cell of claim 16, wherein the spin Hall effect metal layer comprises tungsten, the first phase comprises beta phase tungsten, and the second phase comprises alpha phase tungsten. The non-volatile MRAM cell of claim 16, wherein the spin Hall effect metal layer is composed of tantalum or tungsten, the solid The magnetostrictive layer and the free magnetic layer comprise cobalt iron boron, and the insulator layer comprises magnesium oxide. A non-volatile MRAM cell unit of claim 16 wherein the first portion of the spin Hall effect metal layer is in contact with the free magnetic layer.