TW201723467A - Optical systems and methods of characterizing high-k dielectrics - Google Patents

Optical systems and methods of characterizing high-k dielectrics Download PDF

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TW201723467A
TW201723467A TW105131588A TW105131588A TW201723467A TW 201723467 A TW201723467 A TW 201723467A TW 105131588 A TW105131588 A TW 105131588A TW 105131588 A TW105131588 A TW 105131588A TW 201723467 A TW201723467 A TW 201723467A
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dielectric layer
time constant
semiconductor
electron
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TW105131588A
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TWI715638B (en
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菲利浦C 阿德爾
哈利A 亞特華德
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加州理工學院
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Abstract

The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

Description

特徵化高介電係數電介質之方法及其光學系統 Method for characterizing high dielectric constant dielectric and optical system thereof

本發明係關於一種特徵化半導體結構之方法及其光學系統,特別地,更係關於一種高介電係數電介質之特徵化方法。 The present invention relates to a method of characterizing a semiconductor structure and an optical system thereof, and more particularly to a method of characterizing a high dielectric constant dielectric.

隨著互補金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)技術不斷演進,市場對於金屬氧化物半導體(MOS)電晶體之各種元件的性能需求也不斷提高,其中一種此類元件便是MOS電晶體的閘介電層。由於以熱生長二氧化矽為基材製成之閘介電層的物理厚度不斷變薄,已產生無法接受的電流洩漏。為解決電流洩漏的問題,業界以致力於研究將高介電係數(高-k)介電層應用在繼承MOS中以二氧化矽為基材的閘介電層。以相同厚度的介電層來說,較高的介電係數能提供電介質較高的閘極電容。藉由使用高-k電介質,在維持相同電容的情況下,閘介電層的厚度能夠增厚,以減少洩漏流電量。目前已研發出許多高-k介電層用以繼承二氧化矽為基材的閘介電層,包括(例如)以氧化鋁(Al2O3)以及二氧化鉿(HfO2)為基材的高-k介電層,由於這兩種物質不只介電係數高,且在與矽接觸時具有一定程度的熱穩定性,故此兩種材質是目前相當熱門的材質。 As the complementary metal-oxide-semiconductor (CMOS) technology continues to evolve, the market's performance requirements for various components of metal oxide semiconductor (MOS) transistors continue to increase. One such component is MOS. The gate dielectric layer of the transistor. Since the physical thickness of the gate dielectric layer made of thermally grown ruthenium dioxide is continuously thinned, unacceptable current leakage has occurred. In order to solve the problem of current leakage, the industry is working to study the application of a high dielectric constant (high-k) dielectric layer in a gate dielectric layer based on cerium oxide in a MOS. With a dielectric layer of the same thickness, a higher dielectric constant provides a higher gate capacitance of the dielectric. By using a high-k dielectric, the thickness of the gate dielectric layer can be thickened while maintaining the same capacitance to reduce leakage current. A number of high-k dielectric layers have been developed to inherit the gate dielectric layer of germanium dioxide, including, for example, aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ). The high-k dielectric layer, because these two materials not only have a high dielectric constant, but also have a certain degree of thermal stability when in contact with ruthenium, these two materials are currently quite popular materials.

儘管對高-k電介質有必要的需求,但高-k介電層的某些電學性質,使其應用在高階MOS電晶體時仍具有相當的挑戰 與困難。一些結構上的缺陷如固定負電荷、界面狀態和電荷陷阱中心,皆會影響該高-k介電層的特徵表現與良率,如負偏壓溫度不穩定性、閾值電壓偏移與閘極漏電等,進而限制其應用。為了進一步的研究、開發與製造,能夠用於快速、定量化且非破壞性地特徵化高-k電介質之結構缺陷的系統與方法便愈發重要。現有的特徵化技術皆有其缺點存在:特徵化電學性質的方式如電容與電壓(CV)、電流與電壓(IV)的量測,大部分皆使用已被製造生產的儀器結構進行,這些方式不僅費時,且很難導入生產過程;而某些特徵化物理及光學性質的方式如X射線電子能譜(XPS)、二次離子質譜法(SIMS)、紅外線光譜(FTIR)與光學吸收/發散光譜等,雖可用化學或光學性質特徵化部分的結構缺陷,但該等方法不一定能表現其電活性缺陷,而可能引起無法預期之設備或良率的問題。除上述缺點之外,許多檢測方式不僅具有破壞性,更有費時、難以導入生產過程等問題。為解決上述問題與缺點,本發明提供一種能夠量化、快速、非破壞性且易於導入生產過程之特徵化高-k電介質的方法。 Despite the necessary requirements for high-k dielectrics, certain electrical properties of high-k dielectric layers make them quite challenging when applied to high-order MOS transistors. And difficulties. Some structural defects such as fixed negative charge, interface state, and charge trap center affect the characteristic performance and yield of the high-k dielectric layer, such as negative bias temperature instability, threshold voltage shift, and gate. Leakage, etc., thereby limiting its application. For further research, development, and manufacturing, systems and methods that can be used to quickly, quantitatively, and non-destructively characterize structural defects in high-k dielectrics are becoming increasingly important. Existing characterization techniques have their shortcomings: the methods of characterizing electrical properties such as capacitance and voltage (CV), current and voltage (IV) measurements, most of which are performed using instrument structures that have been manufactured and manufactured. Not only time-consuming, but also difficult to introduce into the production process; and some ways to characterize physical and optical properties such as X-ray electron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), infrared spectroscopy (FTIR) and optical absorption/diverging Spectroscopy, etc., although chemical or optical properties can be used to characterize structural defects, but such methods do not necessarily exhibit electrical activity defects, which may cause unpredictable equipment or yield problems. In addition to the above disadvantages, many detection methods are not only destructive, but also time consuming and difficult to introduce into the production process. To address the above problems and disadvantages, the present invention provides a method of characterizing a high-k dielectric that is quantifiable, fast, non-destructive, and easy to import into a production process.

在一方面,本發明之一種特徵化一半導體結構的方法包含:提供一半導體結構,該半導體結構包含一半導體與一形成於該半導體表面之高介電係數介電層,其中該高介電係數介電層具有多數形成於其中的電子陷阱。本發明之方法另外包括:使一具有入射能量之入射光至少部分穿透該高介電係數介電層,並至少部分入射能量被該半導體吸收。該入射能量足以使部分電子從該半導體轉移至該些電子陷阱,並暫時被該些電子陷阱困住。該入射能量足以使該些電子暫時填充該些電子陷阱,並產生一具能量之光線,該光線之能量不同於該入射能量,且該光線之產生 係基於非線性光學效應。本發明之方法另外包括:量測從該具有不同於該入射能量之能量的光線產生之光譜,其中該非線性光譜包含一第一區域與一第二區域,該第一區域係以相較於該第二區域不同地速率改變強度。該方法進一步包含從該光譜測定得一第一區域之第一時間常數或一第二區域之第二時間常數或其組合,並從該第一時間常數或該第二時間常數或其組合,測定該高介電係數介電層中該些電子陷阱的密度。 In one aspect, a method of characterizing a semiconductor structure of the present invention includes: providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed on the surface of the semiconductor, wherein the high dielectric constant The dielectric layer has an electron trap that is mostly formed therein. The method of the present invention additionally includes causing incident light having incident energy to at least partially penetrate the high-k dielectric layer and at least a portion of the incident energy is absorbed by the semiconductor. The incident energy is sufficient to cause a portion of the electrons to be transferred from the semiconductor to the electron traps and temporarily trapped by the electron traps. The incident energy is sufficient for the electrons to temporarily fill the electron traps, and generate an energy light whose energy is different from the incident energy, and the light is generated It is based on nonlinear optical effects. The method of the present invention additionally includes measuring a spectrum generated from the light having an energy different from the incident energy, wherein the nonlinear spectrum includes a first region and a second region, the first region being compared to the The second region varies in intensity at different rates. The method further includes determining, by the spectrum, a first time constant of a first region or a second time constant of a second region, or a combination thereof, and determining from the first time constant or the second time constant or a combination thereof The density of the electron traps in the high dielectric constant dielectric layer.

在另一方面,本發明之一特徵化一半導體結構的方法包含:提供一包含一半導體基體之半導體結構,及一形成於該半導體基材表面之高介電係數介電層,其中該高介電係數介電層設有多數形成於其中的電子陷阱。本發明之方法另外包括:使一具有入射能量之入射光至少部分穿透該高介電係數介電層,且至少部分入射能量被該半導體基體吸收,其中該入射能量足以使部分電子從該半導體基體轉移至該些電子陷阱並暫時被該些電子陷阱困住。該入射能量足以使該些電子暫時填充該些電子陷阱,並產生倍頻效應(harmonic generation,SHG)。該方法進一步包含量測由該倍頻效應產生的二次諧波光譜,其中該二次諧波光譜包含一第一區域與一第二區域,其中該第一區域之強度變化率較該第二區域快。本發明之方法更進一步包含從該二次諧波光譜測定得一第一區域之第一時間常數,或一第二區域之第二時間常數或其組合,並從該第一時間常數或該第二時間常數或其組合,測定該高介電係數介電層中該些電子陷阱的密度。 In another aspect, a method of characterizing a semiconductor structure of the present invention includes: providing a semiconductor structure including a semiconductor body, and a high-k dielectric layer formed on a surface of the semiconductor substrate, wherein the high dielectric layer The electrical coefficient dielectric layer is provided with an electronic trap that is mostly formed therein. The method of the present invention additionally includes: causing at least a portion of the incident light having incident energy to penetrate the high-k dielectric layer, and at least a portion of the incident energy is absorbed by the semiconductor substrate, wherein the incident energy is sufficient to cause a portion of the electrons from the semiconductor The substrate is transferred to the electronic traps and temporarily trapped by the electronic traps. The incident energy is sufficient for the electrons to temporarily fill the electron traps and produce a harmonic generation (SHG). The method further includes measuring a second harmonic spectrum generated by the frequency doubling effect, wherein the second harmonic spectrum comprises a first region and a second region, wherein the first region has a higher rate of change than the second region The area is fast. The method of the present invention further includes determining, by the second harmonic spectrum, a first time constant of a first region, or a second time constant of a second region, or a combination thereof, and from the first time constant or the first The two time constants or a combination thereof determines the density of the electron traps in the high-k dielectric layer.

在另一方面,本發明之一特徵化一半導體結構的系統包含一光源,該光源可發射一具有入射能量之入射光,其中該入射光有至少部分係穿透一形成於一半導體基體表面的高介電係數介電層,且至少部分係被該半導體基體吸收,其中該高介電係數介電層具有多數形成於其中的電子陷阱。該入射能量足以使部 分電子從該半導體結構轉移至該些電子陷阱,並暫時被該些電子陷阱困住。該入射能量足以使該些電子暫時填充該些電子陷阱,並產生一具能量之光線,該光線之能量不同於該入射能量,且該光線之產生係基於非線性光學效應。該系統進一步包含一感測器,用以偵測該光線之光譜,其中該光譜係非線性光譜,該光譜包含一第一區域與一第二區域,其中該第一區域之強度變化速率較該第二區域快。該系統進一步包含一電子裝置,用以測定得一第一區域之第一時間常數,或一第二區域之第二時間常數或其組合,並從該第一時間常數或該第二時間常數或其組合,測定該高介電係數介電層中該些電子陷阱的密度。 In another aspect, a system for characterizing a semiconductor structure of the present invention includes a light source that emits incident light having incident energy, wherein the incident light is at least partially penetrated to form a surface of a semiconductor substrate. A high-k dielectric layer is at least partially absorbed by the semiconductor body, wherein the high-k dielectric layer has an electron trap formed therein. The incident energy is sufficient to make the part Sub-electrons are transferred from the semiconductor structure to the electron traps and temporarily trapped by the electron traps. The incident energy is sufficient for the electrons to temporarily fill the electron traps and generate an energy ray having an energy different from the incident energy, and the light is generated based on a nonlinear optical effect. The system further includes a sensor for detecting a spectrum of the light, wherein the spectrum is a nonlinear spectrum, the spectrum comprising a first region and a second region, wherein the first region has a rate of change of intensity compared to the first region The second area is fast. The system further includes an electronic device for determining a first time constant of a first region, or a second time constant of a second region, or a combination thereof, and from the first time constant or the second time constant or In combination, the density of the electron traps in the high-k dielectric layer is determined.

在另一方面,本發明之一特徵化一半導體結構的系統包含一光源,該光源可發射一具有入射能量之入射光,其中該入射光有至少部分係穿透一形成於一半導體基體表面的高介電係數介電層,且至少部分係被該半導體基體吸收,其中該高介電係數介電層設有多數形成於其中的電子陷阱。該入射能量足以使部分電子從該半導體基體轉移至該些電子陷阱,並暫時被該些電子陷阱困住。其中該入射能量足以使該些電子暫時填充該些電子陷阱,並產生倍頻效應。該系統進一步包含一感測器,用以量測由該倍頻效應產生之二次諧波光譜,其中該二次諧波光譜具有一第一區域與一第二區域,且其中該第一區域之強度變化速率較該第二區域快。該系統更進一步包含一時間常數測定單元,用以從該二次諧波光譜測定得一第一區域之第一時間常數,或一第二區域之第二時間常數或其組合,並從該第一時間常數或該第二時間常數或其組合,測定該高介電係數介電層中該些電子陷阱的密度。 In another aspect, a system for characterizing a semiconductor structure of the present invention includes a light source that emits incident light having incident energy, wherein the incident light is at least partially penetrated to form a surface of a semiconductor substrate. A high-k dielectric layer is at least partially absorbed by the semiconductor body, wherein the high-k dielectric layer is provided with an electron trap formed therein. The incident energy is sufficient to cause a portion of the electrons to be transferred from the semiconductor substrate to the electron traps and temporarily trapped by the electron traps. Wherein the incident energy is sufficient for the electrons to temporarily fill the electron traps and produce a frequency multiplication effect. The system further includes a sensor for measuring a second harmonic spectrum generated by the frequency doubling effect, wherein the second harmonic spectrum has a first region and a second region, and wherein the first region The intensity changes at a faster rate than the second region. The system further includes a time constant measuring unit for determining a first time constant of a first region, or a second time constant of a second region or a combination thereof from the second harmonic spectrum, and from the first The density of the electron traps in the high-k dielectric layer is determined by a time constant or the second time constant or a combination thereof.

100‧‧‧方法 100‧‧‧ method

104、108、112、116、120‧‧‧步驟 104, 108, 112, 116, 120‧‧‧ steps

200a‧‧‧系統 200a‧‧‧ system

200b、200c‧‧‧能帶示意圖 200b, 200c‧‧‧ can bring schematic diagram

202‧‧‧半導體結構 202‧‧‧Semiconductor structure

204‧‧‧半導體基體 204‧‧‧Semiconductor substrate

208‧‧‧界面層 208‧‧‧ interface layer

212‧‧‧高介電係數介電層 212‧‧‧High dielectric constant dielectric layer

216‧‧‧光源 216‧‧‧Light source

220‧‧‧入射光 220‧‧‧ incident light

224‧‧‧反射光 224‧‧‧ reflected light

228‧‧‧二次諧波光 228‧‧‧second harmonic light

232‧‧‧感測器 232‧‧‧Sensor

238a、238b‧‧‧箭號 238a, 238b‧‧ arrows

240‧‧‧電子 240‧‧‧Electronics

242‧‧‧箭號 242‧‧‧Arrow

244‧‧‧電洞 244‧‧‧ holes

246‧‧‧時間常數測定單元 246‧‧‧Time constant measuring unit

248‧‧‧電子陷阱 248‧‧‧Electronic trap

250‧‧‧電子陷阱密度測定單元 250‧‧‧Electronic trap density measuring unit

260‧‧‧電子裝置 260‧‧‧Electronic devices

400‧‧‧二次諧波光譜示意圖 400‧‧‧ second harmonic spectrum diagram

404‧‧‧二次諧波光譜 404‧‧‧Secondary harmonic spectrum

408、412‧‧‧二次諧波訊號 408, 412‧‧‧ second harmonic signal

404a‧‧‧第一區域 404a‧‧‧First area

404b‧‧‧第二區域 404b‧‧‧Second area

500、600、700、800‧‧‧圖表 500, 600, 700, 800‧‧‧ charts

504‧‧‧實施例之二次諧波光譜 504‧‧‧Second harmonic spectrum of the embodiment

508‧‧‧模式配適度 508‧‧‧ mode matching

604、608、704、712‧‧‧樣品之二次諧波光譜 Second harmonic spectrum of samples 604, 608, 704, 712‧‧

604a、608a、704a、712a‧‧‧第一區域 604a, 608a, 704a, 712a‧‧‧ first area

604b、608b、704b、712b‧‧‧第二區域 604b, 608b, 704b, 712b‧‧‧ second area

圖1係以倍頻效應特徵化高介電係數電介質之結構缺陷的方法流程圖。 Figure 1 is a flow chart of a method for characterizing the structural defects of a high-k dielectric with a frequency doubling effect.

圖2A係以倍頻效應特徵化高介電係數電介質之結構缺陷的系統示意圖。 2A is a schematic diagram of a system that characterizes structural defects of a high dielectric constant dielectric with frequency doubling effects.

圖2B、2C係圖2A之半導體結構在圖1之不同實施階段的能帶示意圖。 2B and 2C are schematic views of the energy band of the semiconductor structure of FIG. 2A in different stages of implementation of FIG. 1.

圖3係以倍頻效應量測時間常數與結構缺陷之密度的二次諧波光譜示意圖。 Figure 3 is a schematic diagram of the second harmonic spectrum of the time constant and the density of structural defects measured by the frequency doubling effect.

圖4係以實驗性二次諧波光譜測定時間常數及該高介電係數電介質結構缺陷之密度與一光譜模型重疊比較的實施例。 Figure 4 is an example of an experimental second harmonic spectroscopy time constant and a density of the high dielectric constant dielectric structure defect compared to a spectral model.

圖5、6係以倍頻效應測定不同樣品的時間常數與高介電係數電介質結構缺陷之密度的實施例。 Figures 5 and 6 are examples of the determination of the time constant of different samples and the density of high dielectric constant dielectric structure defects by frequency doubling effect.

圖7係實施例中高介電係數電介質之厚度與時間常數的關係圖。 Figure 7 is a graph showing the relationship between the thickness and the time constant of a high dielectric constant dielectric in the embodiment.

本發明所提供之實施例係用以解決市場對於能夠較快速、非破壞性且易於導入半導體裝置之製造過程並量化高介電係數電介質之電活性結構特徵或電子陷阱的特徵化技術之需求。特別地,以下之具體實施例係利用雷射光在固體中引發的非線性光學效應。 The embodiments provided by the present invention address the market's need for characterization techniques that are relatively fast, non-destructive, and easy to introduce into the fabrication process of semiconductor devices and quantify the electroactive structural features or electron traps of high-k dielectrics. In particular, the following specific embodiments utilize nonlinear optical effects induced by laser light in a solid.

當光線在一固體中傳播,該光線的電磁波會與該固體的偶電極產生交互作用,進而產生非線性光學效應,其中該偶電極係由該固體的原子核與電子所產生。該光線的電磁波與該固體的偶極子產生交互作用使其產生振動後,產生振動的偶極子即成為一個會產生電磁波的源頭。當振動的幅度很小,偶極子發出的電磁波會與入射光有相同的頻率。在本發明的一些實施例中,當入射光的輻射照度夠高,輻射照度與震動幅度會轉變為非線性 的關係,使振動的偶極子產生特定頻率的諧波,即所謂的倍頻或二次諧波。當入射光地輻射照度繼續提高,甚至可能產生更高階的頻率效應。電極化(或單位體積的偶極矩)P可以外加電場E的冪級數展開式表示為:P=ε 0(χE+χ 2 E 2+χ 3 E 3+...)。 [1] When the light propagates in a solid, the electromagnetic wave of the light interacts with the dipole of the solid, thereby producing a nonlinear optical effect, wherein the dipole is produced by the nucleus and electrons of the solid. When the electromagnetic wave of the light interacts with the dipole of the solid to cause vibration, the dipole that generates vibration becomes a source that generates electromagnetic waves. When the amplitude of the vibration is small, the electromagnetic waves emitted by the dipole will have the same frequency as the incident light. In some embodiments of the present invention, when the illuminance of the incident light is sufficiently high, the illuminance and the amplitude of the vibration are converted into a nonlinear relationship, so that the dipole of the vibration generates a harmonic of a specific frequency, so-called frequency doubling or two. Subharmonic. As the illuminance of the incident light continues to increase, even higher order frequency effects may be produced. The polarization (or dipole moment per unit volume) P can be expressed as a power series expansion of the applied electric field E as: P = ε 0 ( χE + χ 2 E 2 + χ 3 E 3 +...). [1]

在方程式[1]中,χ係線性敏感度,χ2、χ3...係非線性光學常數。將外加電場E以電磁波的正弦函數E=E 0 sinωt表示,方程式[1]即可改寫為: In equation [1], the linear sensitivity of the lanthanide, χ 2 , χ 3 ... is a nonlinear optical constant. The applied electric field E is expressed by the sine function E of electromagnetic waves E = E 0 sin ωt , and the equation [1] can be rewritten as:

在方程式[2]中,2ω代表一頻率係兩倍入射頻率的電磁波。當外加電場相對提高,例如使用雷射,2ω的大小就相對變得顯著。第二諧波可在非中心對稱性的固體中被觀察到。在對稱的固體中,一外加電場會使偶極子產生大小相同但方向相反的極化,導致整體的淨極化很微弱,甚至沒有淨極化產生。因此,某些中心對稱性的半導體,例如:矽,便無法產生倍頻效應。然而,在本發明所提供的實施例中,通過半導體與介電層界面的電場可導致倍頻效應的產生。 In equation [2], 2ω represents an electromagnetic wave having twice the incident frequency of a frequency system. When the applied electric field is relatively increased, for example, using a laser, the size of 2ω becomes relatively significant. The second harmonic can be observed in a non-central symmetry solid. In a symmetrical solid, an applied electric field causes the dipole to produce the same magnitude but opposite polarization, resulting in a weak overall net polarization, even without net polarization. Therefore, some centrally symmetric semiconductors, such as germanium, cannot produce frequency doubling effects. However, in the embodiments provided by the present invention, the electric field through the interface of the semiconductor and the dielectric layer can cause the generation of a frequency doubling effect.

以倍頻效應特徵化高介電係數電介質中電子陷阱的方法與系統Method and system for characterizing electron trap in high dielectric constant dielectric by frequency doubling effect

參考圖1,係例舉說明根據本發明之實施例利用倍頻效應特徵化高介電係數電介質中結構缺陷的方法100。參考圖2A,係例舉說明搭配方法100而架設的系統200a。更清楚地,參照圖2A詳細說明根據本發明實施例中的各個光學元件。 Referring to Figure 1, a method 100 for characterizing structural defects in a high-k dielectric in a multi-frequency effect in accordance with an embodiment of the present invention is illustrated. Referring to Fig. 2A, a system 200a that is erected in conjunction with method 100 is illustrated. More clearly, the individual optical elements in accordance with embodiments of the present invention are described in detail with reference to FIG. 2A.

參考圖1,方法100包含步驟104,提供一半導體結構,該半導體結構包含一半導體基體與一形成於該半導體基體表 面的高介電係數介電層,其中該介電層中具有多數形成於其中的電荷載流子陷阱。方法100又包含步驟108,將一具有入射能量之入射光至少部分穿透該高介電係數介電層,且至少部分被該半導體基體吸收。在本發明的實施例中,該入射能量足以使部分電子由該半導體基體轉移至電子陷阱中並暫時被電子陷阱困住。此外,該入射能量足以使該些被電子暫時填充的電子陷阱產生倍頻效應。方法100又包含步驟112,量測由該倍頻效應所產生的二次諧波光譜,該二次諧波光譜包含一第一區域與一第二區域,其中該第一區域的強度變化速率較該第二區域快。方法100進一步包含步驟116,從該二次諧波光譜測定一第一區域之第一時間常數,或一第二區域之第二時間常數或其組合;以及步驟120,從該第一時間常數或第二時間常數或其組合,測定該高介電係數介電層中該些電子陷阱的密度。 Referring to FIG. 1, the method 100 includes a step 104 of providing a semiconductor structure including a semiconductor body and a semiconductor substrate formed on the semiconductor substrate. A high dielectric constant dielectric layer having a majority of charge carrier traps formed therein. The method 100 further includes a step 108 of at least partially penetrating incident light having incident energy through the high-k dielectric layer and at least partially being absorbed by the semiconductor substrate. In an embodiment of the invention, the incident energy is sufficient to cause a portion of the electrons to be transferred from the semiconductor substrate into the electron trap and temporarily trapped by the electron trap. In addition, the incident energy is sufficient to cause a frequency multiplication effect of the electron traps temporarily filled by electrons. The method 100 further includes a step 112 of measuring a second harmonic spectrum generated by the frequency doubling effect, the second harmonic spectrum comprising a first region and a second region, wherein the first region has a rate of change of intensity The second area is fast. The method 100 further includes a step 116 of determining a first time constant of a first region, or a second time constant of a second region, or a combination thereof from the second harmonic spectrum; and step 120, from the first time constant or A second time constant or a combination thereof determines the density of the electron traps in the high-k dielectric layer.

圖2A例舉說明一用於特徵化高介電係數電介質之結構缺陷的系統200a。參照圖2A,該系統200a包含一半導體結構202,該半導體結構202包含一半導體基體204,與一形成於該半導體基體202表面的高介電係數介電層212,其中該高介電係數介電層212具有形成於其中被用來特徵化之電活性結構缺陷,或稱電子陷阱248。 2A illustrates a system 200a for characterizing structural defects in a high-k dielectric. Referring to FIG. 2A, the system 200a includes a semiconductor structure 202 including a semiconductor body 204 and a high-k dielectric layer 212 formed on a surface of the semiconductor substrate 202, wherein the high-k dielectric is dielectric. Layer 212 has an electroactive structural defect, or electron trap 248, formed therein that is characterized.

如本發明提供的實施例,該半導體基體204包含,但不限於一N型或一P型的半導體基體,其中該半導體基體可由第四族元素(如碳、矽、鍺或錫)或由第五族元素形成的合金(如矽鍺合金、矽鍺碳合金、碳化矽、矽化錫、矽錫碳合金、鍺錫合金等);第III、V族化合物之半導體材料(如砷化鎵、氮化鎵、砷化銦等)或第III、V族元素形成的合金;第II、IV族半導體材料(如硒化鎘、硫化鎘、硒化鋅等)或第II、IV族之合金為材料。 According to the embodiment provided by the present invention, the semiconductor body 204 includes, but is not limited to, an N-type or a P-type semiconductor substrate, wherein the semiconductor substrate can be a fourth group element (such as carbon, germanium, antimony or tin) or Alloys formed by five elements (such as bismuth alloy, bismuth carbon alloy, tantalum carbide, antimony telluride, antimony tin carbon alloy, antimony tin alloy, etc.); III, V compound semiconductor materials (such as gallium arsenide, nitrogen) Alloys formed by gallium, indium arsenide, etc. or Group III and V elements; Group II and IV semiconductor materials (such as cadmium selenide, cadmium sulfide, zinc selenide, etc.) or alloys of Group II and IV are materials. .

根據本發明的一些實施例,半導體基體204可係一 半導體或一絕緣體,如矽絕緣體基體(SOI)。矽絕緣體基體基本包含一在矽中間夾入一絕緣體的結構。上述的結構許多係用一絕緣層如埋入一二氧化矽層的方式與支撐基體隔離。其中,根據本發明提供的實施例,許多結構可至少在表面或靠近表面的區域形成一晶膜層。 According to some embodiments of the invention, the semiconductor body 204 can be a A semiconductor or an insulator such as a germanium insulator substrate (SOI). The ruthenium insulator substrate basically comprises a structure in which an insulator is sandwiched between the ruthenium. Many of the above structures are isolated from the support substrate by an insulating layer such as a layer of germanium dioxide. Therein, according to embodiments provided by the present invention, a plurality of structures may form a film layer at least on a surface or in a region close to the surface.

如本發明的一些實施例,半導體結構202可進一步作為一具有許多區域的中間裝置,如作為方法100(參照圖1)串連特徵化步驟的一部分,甚至加工成一具功能的金屬氧化物半導體電晶體。如上述實施例,該半導體結構202可包含摻雜區域,例如在進一步加工時產生的重摻雜區域,以作為一具功能的金屬氧化物半導體電晶體或其他裝置中的源極和/或汲極區。該半導體結構202可能進一步包含隔離區,如淺溝隔離區。在其他實施例中,由於該半導體結構202有一高介電係數介電層212形成於其上,除了可用以特徵化其結構缺陷,更可作為一監測結構,例如監測製造工具或生產線的狀況。 As with some embodiments of the present invention, the semiconductor structure 202 can further serve as an intermediate device having a plurality of regions, such as a portion of the tandem characterization step of the method 100 (see FIG. 1), or even processed into a functional metal oxide semiconductor device. Crystal. As with the above embodiments, the semiconductor structure 202 can include doped regions, such as heavily doped regions that are produced during further processing, as sources and/or germanium in a functional metal oxide semiconductor transistor or other device. Polar zone. The semiconductor structure 202 may further comprise isolation regions, such as shallow trench isolation regions. In other embodiments, since the semiconductor structure 202 has a high-k dielectric layer 212 formed thereon, in addition to characterizing its structural defects, it can be used as a monitoring structure, such as monitoring the condition of a manufacturing tool or production line.

參考圖2A,雖然該半導體結構202係一平面結構,但實施方式並不限於此。例如該半導體結構202可包含一具有隔離區的半導體基體204與一鰭狀半導體結構垂直突出於該些隔離區,以進一步加工成鰭狀電場效應電晶體(FinFETs)。在這些實施例中,高介電係數介電層212可環繞在該鰭狀半導體結構外。 Referring to FIG. 2A, although the semiconductor structure 202 is a planar structure, the embodiment is not limited thereto. For example, the semiconductor structure 202 can include a semiconductor body 204 having an isolation region and a fin-shaped semiconductor structure protruding perpendicularly from the isolation regions for further processing into fin-shaped field effect transistors (FinFETs). In these embodiments, the high-k dielectric layer 212 may surround the fin-shaped semiconductor structure.

本發明所揭露之高介電係數介電層係指介電係數較二氧化矽高的介電材料。根據實施例,該高介電係數介電層212的介電係數k可能大於4、大於8或大於15。根據本發明之各種實施例,高介電係數介電層212的材質可為氮化矽、氧化鉭、鈦酸鍶、氧化鋯、二氧化鉿、氧化鋁、氧化鑭、氧化釔、矽氧化鉿與氧化鑭鋁(包含上述物質的非化學計量形式與各種混合物),以及其組合物、堆疊物或奈米層疊...等。 The high-k dielectric layer disclosed in the present invention refers to a dielectric material having a higher dielectric constant than cerium oxide. According to an embodiment, the dielectric constant k of the high-k dielectric layer 212 may be greater than 4, greater than 8, or greater than 15. According to various embodiments of the present invention, the material of the high-k dielectric layer 212 may be tantalum nitride, hafnium oxide, barium titanate, zirconium oxide, hafnium oxide, aluminum oxide, hafnium oxide, tantalum oxide or hafnium oxide. With yttrium aluminum oxide (including non-stoichiometric forms and various mixtures of the above substances), as well as combinations thereof, stacks or nano-layers, and the like.

參考圖2A,在半導體基體204與高介電係數介電層212之間有一界面層208。當該高介電係數介電層212係以二氧化鉿製成,且該半導體基體204係一矽基體,該界面層208可由矽氧化物或矽氧化鉿...等製成。該界面層208可透過氧氣前驅物在生成該高介電係數介電層212時擴散至高介電係數電介質與基體之界面和/或過量氧原子在該高介電係數介電層212生成時或生成後在該高介電係數介電層212中以體擴散方式不經意產生。在一些實施例中,該界面層208可為一刻意形成之二氧化矽層,用以抑制界面氧化物的自發成長,和/或提供該界面層較佳的性能控制並提供二氧化鉿較穩定的成核作用。本發明的實施例包含但不限制於此。在一些實施例中,界面層208是可省略的。 Referring to FIG. 2A, there is an interfacial layer 208 between the semiconductor body 204 and the high-k dielectric layer 212. When the high-k dielectric layer 212 is made of hafnium oxide and the semiconductor substrate 204 is a tantalum substrate, the interfacial layer 208 may be made of tantalum oxide or tantalum oxide or the like. The interface layer 208 can diffuse to the interface of the high-k dielectric substrate and the substrate and/or excess oxygen atoms when the high-k dielectric layer 212 is formed by the oxygen precursor to generate the high-k dielectric layer 212 or After the formation, the high-k dielectric layer 212 is inadvertently generated in a bulk diffusion manner. In some embodiments, the interfacial layer 208 can be a deliberately formed ceria layer to inhibit the spontaneous growth of interfacial oxides and/or provide better performance control of the interfacial layer and provide more stable cerium oxide. Nucleation. Embodiments of the invention include, but are not limited to, this. In some embodiments, interface layer 208 can be omitted.

如本發明的實施例,該高介電係數介電層212設有多數形成於其中,可使用本發明之方法與系統特徵化之結構缺陷,或稱電子陷阱248。該些結構缺陷可為點缺陷,如高介電係數介電層212中缺失或額外的電子。例如,當該高介電係數介電層212係以氧化物或氮氧化物製成,該些電子陷阱248可包含氧空位,以對應缺失的氧原子;或是間隙氧原子,對應額外的氧原子。若該些電子陷阱248包含氧空位,該些電子陷阱可能帶電或係電中性。例如,二氧化鉿中的氧空位有五種電荷狀態,分別係+2、+1、0、-1和-2。 In accordance with an embodiment of the present invention, the high-k dielectric layer 212 is provided with a plurality of structural defects, or electron traps 248, that are formed therein and that can be characterized using the methods and systems of the present invention. These structural defects may be point defects such as missing or additional electrons in the high-k dielectric layer 212. For example, when the high-k dielectric layer 212 is made of oxide or oxynitride, the electron traps 248 may contain oxygen vacancies to correspond to missing oxygen atoms; or interstitial oxygen atoms, corresponding to additional oxygen. atom. If the electronic traps 248 contain oxygen vacancies, the electronic traps may be charged or electrically neutral. For example, oxygen vacancies in cerium oxide have five charge states, which are +2, +1, 0, -1, and -2, respectively.

參考圖2A,系統200a包含一光源216,該光源216可係一包含雷射、一燈泡和/或發光二極體的第一光源,其配置能引導一具有入射能量hν1的入射光220至該半導體結構202並在瞄準時進一步穿透該界面層208。該光源216進一步配置成能使該入射光220至少部分被該半導體基體204吸收並將能量傳給該半導體基體204,以於其中引發彈性或非彈性過程。更進一步,該光源216係發射一單色入射光220,且該部分穿透的入射光220具有足 夠的入射能量使電荷載子(如電子)至少部分從該半導體基體204轉移至該些電子陷阱248中並暫時被該些電子陷阱248困住,得到一捕獲截面積σ。 Referring to FIG. 2A, the system 200a includes a light source 216 that can be a first light source including a laser, a light bulb, and/or a light emitting diode configured to direct an incident light 220 having an incident energy hν 1 to The semiconductor structure 202 further penetrates the interface layer 208 while aiming. The light source 216 is further configured to enable the incident light 220 to be at least partially absorbed by the semiconductor body 204 and to transfer energy to the semiconductor body 204 to initiate an elastic or inelastic process therein. Further, the light source 216 emits a monochromatic incident light 220, and the partially penetrated incident light 220 has sufficient incident energy to cause charge carriers (such as electrons) to be at least partially transferred from the semiconductor substrate 204 to the electronic traps. 248 is temporarily trapped by the electronic traps 248 to obtain a capture cross-sectional area σ.

在一些實施例中,該光源216可提供一適當的波長範圍,使該些電子陷阱248容易被該些電子暫時填充,並產生一光線;其中該光線的能量不同於該入射光220之入射能量hν1,該光線的產生係基於非線性光學效應。在一些實施例中,該光源216可能提供波長範圍為700-2000奈米,峰值功率約為10千瓦至1吉瓦的光源。 In some embodiments, the light source 216 can provide a suitable wavelength range such that the electronic traps 248 are easily temporarily filled by the electrons and generate a light; wherein the energy of the light is different from the incident energy of the incident light 220. Hν 1 , the generation of this light is based on a nonlinear optical effect. In some embodiments, the source 216 may provide a source of light having a wavelength in the range of 700-2000 nm and a peak power of approximately 10 kW to 1 GW.

在一些實施例中,該光源216可提供一適當的強度或功率密度範圍,使該些電子陷阱248容易被該些電子暫時填充,並產生一光線;其中該光線的能量不同於該入射光220之入射能量hν1,該光線的產生係基於非線性光學效應。在一些實施例中,該光源216可能提供一平均供率介於10毫瓦至10瓦左右,或介於約100毫瓦與約1瓦之間,例如300毫瓦。 In some embodiments, the light source 216 can provide a suitable intensity or power density range such that the electronic traps 248 are easily temporarily filled by the electrons and generate a light; wherein the energy of the light is different from the incident light 220. The incident energy hν 1 is based on a nonlinear optical effect. In some embodiments, the light source 216 may provide an average supply rate of between about 10 milliwatts and about 10 watts, or between about 100 milliwatts and about one watt, such as 300 milliwatts.

參考圖2A,在一些實施例中,該具有入射能量之入射光220足以使該些電子陷阱被電荷載子填充,並產生倍頻效應。如前述,倍頻效應可在非中心對稱的固體中被觀察到。不詳述任何科學原理,即使該半導體基體204係中心對稱,如一具有菱形立方結構的矽,根據方程式[3]:I 2ω (t)=|χ 2+χ 3 E(t)|2(I ω )2, [3]當形成於該半導體基底204表面的介電層設有電子陷阱248,淨極化便可通過半導體/電介質的介面產生。在方程式[3]中,Iω與I分別係基礎與倍頻效應的信號強度,χ2、χ3分別係二階與三階的磁化率,E(t)係穿過界面的電場。由於至少部分結構缺陷或陷阱被電荷載子(如電子)填充,倍頻效應便得以產生。其中該二次諧波 光228的頻率係入射光220的兩倍。 Referring to FIG. 2A, in some embodiments, the incident light 220 having incident energy is sufficient to cause the electron traps to be filled with charge carriers and to produce a frequency multiplication effect. As mentioned above, the frequency doubling effect can be observed in non-centrosymmetric solids. Without explaining any scientific principle, even if the semiconductor body 204 is centrally symmetric, such as a 具有 having a diamond-shaped cubic structure, according to the equation [3]: I 2 ω ( t ) = | χ 2 + χ 3 E ( t )| 2 ( I ω ) 2 , [3] When the dielectric layer formed on the surface of the semiconductor substrate 204 is provided with an electron trap 248, the net polarization can be generated through the interface of the semiconductor/dielectric. In equation [3], I ω and I are the signal strengths of the fundamental and frequency doubling effects, respectively, χ 2 and χ 3 are the second and third order susceptibility, respectively, and E(t) is the electric field passing through the interface. The frequency doubling effect is generated because at least some of the structural defects or traps are filled by charge carriers such as electrons. The frequency of the second harmonic light 228 is twice that of the incident light 220.

參考圖2A,在一些實施例中,系統200a進一步包含一感測器232,用以量測由該具有兩倍於該入射光220的能量之二次諧波光228所產生的二次諧波光譜,並進一步量測或濾出與入射光220具有相同能量的反射光224。該感測器232可為一光電放大管、電耦合照相裝置、崩潰感測器、光電二極體感測器、條紋攝影機和矽感測器,或其他類型的感測器。 Referring to FIG. 2A, in some embodiments, system 200a further includes a sensor 232 for measuring a second harmonic generated by the second harmonic light 228 having twice the energy of the incident light 220. The spectrum is further measured or filtered to reflect light 224 having the same energy as incident light 220. The sensor 232 can be an opto-amplifier tube, an electro-coupling camera, a crash sensor, a photodiode sensor, a stripe camera, and a sputum sensor, or other type of sensor.

在本發明的實施例中,雖然光源216係一單一光源,同時作為致動器與探測器以產生並量測二次諧波光228,但並不限於此。在其他實施例中,可同時提供一分離的第二光源(並未標示在圖式中),該第二光源可係一雷射或一燈泡。在這些實施例中,該光源216可作為致動器或探測器,第二光源則可相對光源216作為探測器或致動器。在一些實施例中,第二光源可提供波長範圍為約80-約800奈米,平均供率介於約10毫瓦至10瓦的光。 In the embodiment of the present invention, although the light source 216 is a single light source and acts as both an actuator and a detector to generate and measure the second harmonic light 228, it is not limited thereto. In other embodiments, a separate second source (not shown) may be provided at the same time, and the second source may be a laser or a bulb. In these embodiments, the light source 216 can act as an actuator or detector, and the second source can act as a detector or actuator relative to the source 216. In some embodiments, the second source can provide light having a wavelength in the range of from about 80 to about 800 nanometers and an average supply rate of between about 10 milliwatts and 10 watts.

雖未明標於圖式中,系統200a可包含其他光學元件。例如該系統200a可包含:一光子計數器;一反射或折射濾波器,可選擇性地過濾二次諧波訊號;一稜鏡,可從較強的多階反射之主光束中分離較弱的二次諧波訊號;一繞射光柵或一薄膜分光器;一用來聚焦與準直的光束;一濾色輪、變焦透鏡和/或偏光器。 Although not shown in the drawings, system 200a can include other optical components. For example, the system 200a can include: a photon counter; a reflection or refraction filter that selectively filters the second harmonic signal; and a dipole that separates the weaker two from the stronger multi-order reflected main beam. Subharmonic signal; a diffraction grating or a thin film splitter; a beam for focusing and collimating; a color filter wheel, a zoom lens and/or a polarizer.

如上述關於圖2A中其他光學元件的敘述與其變化組合,在US 14/690,179“Pump and Probe Type Second Harmonic Generation Metrology”(2015.04.17)、US 14/690,256“Charge Decay Measurement Systems and Methods”(2015.04.17)、US 14/690,251“Field-Based Second Harmonic Generation Metrology”(2015.04.17)、US 14/690,279“Wafer Metrology Technologies”(215.04.17)與US 14/939,750“Systems for Parsing Material Properties From Within SHG Signals”(2015.11.12)中皆有描述。以上文獻皆以參考文獻的 方式併入本發明。 As described above with respect to the description of other optical components in FIG. 2A and variations thereof, in US 14/690,179 "Pump and Probe Type Second Harmonic Generation Metrology" (2015.04.17), US 14/690,256 "Charge Decay Measurement Systems and Methods" (2015.04) .17), US 14/690, 251 "Field-Based Second Harmonic Generation Metrology" (2015.04.17), US 14/690,279 "Wafer Metrology Technologies" (215.04.17) and US 14/939,750 "Systems for Parsing Material Properties From Within It is described in SHG Signals” (2015.11.12). The above documents are all referenced The manner is incorporated in the present invention.

系統200a進一步包含電子裝置或一時間常數測定單元246,用以從該二次諧波光譜測定一第一區域之第一時間常數τ1,或一第二區域之第二時間常數τ2或其組合,其中該第一時間常數τ1至少與該些電子陷阱248困住電子的速率有關,該第二時間常數τ2至少與該些電子陷阱248是放電子的速率有關。 The system 200a further includes an electronic device or a time constant measuring unit 246 for determining a first time constant τ1 of a first region, or a second time constant τ2 of a second region, or a combination thereof, from the second harmonic spectrum. The first time constant τ1 is related to at least a rate at which the electron traps 248 are trapped, and the second time constant τ2 is at least related to a rate at which the electron traps 248 are discharged.

該系統200a進一步包含電子裝置或一電子陷阱密度測定單元250,用以從該第一時間常數τ1或該第二時間常數τ2或其組合測定該高介電係數介電層212中電荷載子陷阱的密度。 The system 200a further includes an electronic device or an electronic trap density determining unit 250 for determining a charge trap in the high-k dielectric layer 212 from the first time constant τ1 or the second time constant τ2 or a combination thereof. Density.

時間常數測定單元246與電子陷阱密度測定單元250可係一電子裝置260的一部分,該電子裝置260可能係一計算裝置,例如一可程式化邏輯電路(FPGA),特別適合用來實施本發明所揭露之方法,如下文所述。該電子裝置260可為一計算裝置、一電腦、一平板電腦、一微處理器或一可程式化邏輯電路。該電子裝置260包含一處理器或一處理電子,可執行一或多個軟體模組。除了執行操作系統,該處理器更可用來執行一或多個軟體應用程式,如網頁瀏覽器、電話應用、電子郵件程式或任何其他軟體應用程式。該電子裝置260可透過執行一機器可讀的非暫時存取記憶體(如隨機存取記憶體RAM、唯讀記憶體ROM、電子抹除式可複寫唯讀記憶體EEPROM等)中的指令實施本發明所揭露之方法。該電子裝置260可包含一顯示裝置和/或一使用者圖形介面與使用者互動。該電子裝置260可透過網路介面與一或多個裝置通信。網路介面可包含發射器、接收器和/或收發器,透過有線或無線方式連接進行通信。 The time constant measuring unit 246 and the electronic trap density measuring unit 250 may be part of an electronic device 260, which may be a computing device, such as a programmable logic circuit (FPGA), which is particularly suitable for implementing the present invention. The method of disclosure is as follows. The electronic device 260 can be a computing device, a computer, a tablet computer, a microprocessor or a programmable logic circuit. The electronic device 260 includes a processor or a processing electronics and can execute one or more software modules. In addition to executing an operating system, the processor can be used to execute one or more software applications, such as a web browser, a phone application, an email program, or any other software application. The electronic device 260 can be implemented by executing instructions in a machine-readable non-transitory memory (such as random access memory RAM, read-only memory ROM, electronic erasable rewritable read-only memory EEPROM, etc.) The method disclosed by the present invention. The electronic device 260 can include a display device and/or a user graphical interface to interact with the user. The electronic device 260 can communicate with one or more devices through a network interface. The network interface can include a transmitter, a receiver, and/or a transceiver to communicate via a wired or wireless connection.

圖2B係例舉說明系統200a(參考圖2A)中半導體結構202的能帶圖200b。更精確地,能帶圖200b係對應量測該二次諧波光譜的初始階段,如該二次諧波光譜的第一區域。 2B illustrates an energy band diagram 200b of semiconductor structure 202 in system 200a (see FIG. 2A). More precisely, the energy band diagram 200b corresponds to the initial phase of the second harmonic spectrum, such as the first region of the second harmonic spectrum.

在能帶圖200b中,高介電係數介電層212設有如上述可能為點缺陷的結構缺陷或電子陷阱248(以分佈曲線表示)。該些電子陷阱248的能極分佈可能係圍繞一峰值,或具有中心能階Eτ。在一些實施例中,該些電子陷阱248可能分布在該高介電係數介電層212地整個厚度中;在另一些實施例中,該缺陷可能局部集中,例如當沒有界面層208存在時,分佈會集中在高介電係數介電層212與半導體基體204的交界處;而例如有界面層208存在時,則會集中在高介電係數介電層212與界面層208的交界處。在一些實施例中,該些電子陷阱248係用來困住從半導體基體204轉移出的電子。 In the energy band diagram 200b, the high-k dielectric layer 212 is provided with a structural defect or electron trap 248 (shown as a distribution curve) as may be a point defect as described above. The energy distribution of the electron traps 248 may surround a peak or have a central energy level E τ . In some embodiments, the electron traps 248 may be distributed throughout the thickness of the high-k dielectric layer 212; in other embodiments, the defects may be locally concentrated, such as when no interfacial layer 208 is present. The distribution will be concentrated at the interface of the high-k dielectric layer 212 and the semiconductor body 204; for example, when the interface layer 208 is present, it will concentrate at the junction of the high-k dielectric layer 212 and the interface layer 208. In some embodiments, the electron traps 248 are used to trap electrons that are diverted from the semiconductor body 204.

如上述,當具有入射能量hν1的入射光220穿透高介電係數介電層212與界面層208時,該入射能量會有部分被半具有一導帶邊緣(CBSUB)與一價帶邊緣(VBSUB)的導體基體204吸收。 As described above, when the incident light 220 having the incident energy hν 1 penetrates the high-k dielectric layer 212 and the interface layer 208, the incident energy will partially have a conduction band edge (CB SUB ) and a valence band. The conductor base 204 of the edge (VB SUB ) is absorbed.

在一些實施例中,當半導體基體204係無摻雜、相對淡摻雜(如低於1*1014/cm3)或p摻雜時,導帶中的電子濃度可能相對較低。在這些實施例中,可選擇入射光220的入射能量hν1,使hν1較半導體基體204的能帶間隙高出至少0.1eV或至少0.3eV,如此半導體基體204中能產生電子240和/或電洞244,轉移至高介電係數界電層212後被電子陷阱248困住。例如當半導體基體204係以矽製成,該入射光220的入射能量hν1較矽的能帶間隙1.12eV(1110奈米)高,以使足夠的電子240填充於該導帶中。舉例來說,該入射光的能量可能為1.2eV,甚至更高。 In some embodiments, when the semiconductor body 204 is undoped, relatively lightly doped (eg, below 1*10 14 /cm 3 ), or p-doped, the concentration of electrons in the conduction band may be relatively low. In these embodiments, the incident energy hν 1 of the incident light 220 can be selected such that hν 1 is at least 0.1 eV or at least 0.3 eV higher than the energy band gap of the semiconductor body 204, such that electrons 240 and/or electrons can be generated in the semiconductor body 204. The hole 244 is transferred to the high dielectric constant boundary layer 212 and trapped by the electron trap 248. For example, when the semiconductor body 204 is made of tantalum, the incident energy hν 1 of the incident light 220 is higher than the energy band gap of 1.12 eV (1110 nm) so that sufficient electrons 240 are filled in the conduction band. For example, the energy of the incident light may be 1.2 eV or even higher.

另一方面,在一些實施例中,若半導體基體204係相對高摻雜的n摻雜(如高於1*1014/cm3),則該入射能量hν1不能高於該半導體基體204的能帶間隙。相對的,由於該半導體基體204的導帶已經被該些電子240填充,該入射光220的入射能 量hν1需將額外的能量傳給填充在導帶中的電子,使電子能轉移至高介電係數界電層212中並被電子陷阱248困住。 On the other hand, in some embodiments, if the semiconductor body 204 is relatively highly doped n-doped (eg, higher than 1*10 14 /cm 3 ), the incident energy hν 1 cannot be higher than the semiconductor substrate 204. Can carry a gap. In contrast, since the conduction band of the semiconductor body 204 has been filled by the electrons 240, the incident energy hν 1 of the incident light 220 needs to transfer additional energy to the electrons filled in the conduction band, so that the electron energy can be transferred to the high dielectric. The coefficient boundary layer 212 is trapped by the electron trap 248.

一旦半導體基體204的導帶被電子填充,該些電子240便會穿透界面層208,並/或至少部分穿透該高介電係數介電層212的厚度,被電子陷阱248困住,如箭號238a所示。 Once the conduction band of the semiconductor body 204 is filled with electrons, the electrons 240 will penetrate the interface layer 208 and/or at least partially penetrate the thickness of the high-k dielectric layer 212, being trapped by the electron trap 248, such as Arrow 238a is shown.

電子240可經由穿隧方式(如直接穿隧或陷阱輔助穿隧),從半導體基體204的導帶轉移至電子陷阱248之能量分佈的能階。電子的直接穿隧係一量子力學的現象,其可能受物理障礙的厚度、電子需穿隧的高度以及其他因素影響,當潛在的障礙厚度和/或高度較低,穿隧的機率便會相對提高。一般來說,在初始狀態(在半導體基體204中)穿隧的機率會較在最終狀態(在高介電係數介電層212中)高。當位於半導體基體204中電子240的能階相對較高,且未落於該些電子陷阱248的能階時,便可能在穿隧之前先發生熱弛緩的現象,如箭號242所示。然而電子的轉移除了穿隧尚有其他機制,如普爾-夫倫克爾轉移效應、Fowler-Norheim隧道效應、熱離子放射以及其他機制。 The electrons 240 can be transferred from the conduction band of the semiconductor body 204 to the energy level of the electron trap 248 via tunneling (eg, direct tunneling or trap assist tunneling). The direct tunneling of electrons is a phenomenon of quantum mechanics, which may be affected by the thickness of physical barriers, the height of electrons to be tunneled, and other factors. When the potential barrier thickness and/or height is low, the probability of tunneling will be relative. improve. In general, the probability of tunneling in the initial state (in the semiconductor body 204) will be higher than in the final state (in the high-k dielectric layer 212). When the energy level of the electrons 240 located in the semiconductor body 204 is relatively high and does not fall within the energy levels of the electron traps 248, thermal relaxation may occur prior to tunneling, as indicated by arrow 242. However, electron transfer has other mechanisms besides tunneling, such as the Pur-Frenkel transfer effect, Fowler-Norheim tunneling, thermionic radiation, and other mechanisms.

在一些實施例中,為了使電子大量從半導體基體204內部,穿隧至高介電係數介電層212之結構缺陷或電子陷阱248中,高介電係數介電層212的厚度,或高介電係數介電層212與界面層208組合後的厚度係不超過5奈米、不超過4奈米或不超過3奈米,以使電子240能通過該高介電係數介電層212和界面層208(如有界面層208存在)的一部分,到達位於高介電係數介電層212中的結構缺陷或電子陷阱248。再者,穿隧基本上會在量測二次諧波光譜間,例如在少於30秒、少於1秒或少於1毫秒的時間內產生。此外,當成為金屬氧化物半導體電晶體製造過程的一部分,高介電係數介電層212或高介電係數介電層212與界面層208組合後有效的氧化物厚度(EOT)係介於約0.5-3奈米、0.5-2 奈米或0.5-1奈米之間。 In some embodiments, the thickness of the high-k dielectric layer 212, or high dielectric, is tunneled into the structural defects of the high-k dielectric layer 212 or the electron trap 248 in order to allow electrons to pass from a large amount inside the semiconductor body 204. The thickness of the combination of the coefficient dielectric layer 212 and the interface layer 208 is no more than 5 nanometers, no more than 4 nanometers, or no more than 3 nanometers, so that the electrons 240 can pass through the high-k dielectric layer 212 and the interface layer. A portion of 208 (if any interface layer 208 is present) reaches a structural defect or electron trap 248 located in the high-k dielectric layer 212. Furthermore, tunneling is essentially produced between measuring the second harmonic spectrum, for example, in less than 30 seconds, less than 1 second, or less than 1 millisecond. In addition, when a high-k dielectric layer 212 or a high-k dielectric layer 212 is combined with the interface layer 208 as part of the metal oxide semiconductor transistor fabrication process, the effective oxide thickness (EOT) is about 0.5-3 nm, 0.5-2 Nano or between 0.5-1 nm.

進一步說明,為了使電子有機會到達高介電係數介電層212中的結構缺陷或電子陷阱248並被困住以實施本發明所揭露的方法,電子陷阱248的缺陷能分佈需與導帶邊緣充分重疊。在本發明的實施例中,電子陷阱248之缺陷能的不同波峰或能量中心Eτ,係少於約2eV、少於約1eV或少於約0.5eV。在一些其他實施例中,Eτ係介於該高介電係數介電層212之導帶與該半導體基體204之導帶之間。 Further, in order to provide electrons with the opportunity to reach structural defects or electron traps 248 in the high-k dielectric layer 212 and be trapped to practice the methods disclosed herein, the defect energy distribution of the electron trap 248 needs to be along with the conduction band edge. Fully overlapping. In an embodiment of the invention, the different peaks or energy centers E τ of the defect energy of the electron trap 248 are less than about 2 eV, less than about 1 eV, or less than about 0.5 eV. In some other embodiments, E τ is between the conduction band of the high-k dielectric layer 212 and the conduction band of the semiconductor body 204.

參考圖2B,在該些結構缺陷或電子陷阱248被電子240填充之前,會產生相對微弱的倍頻效應,發出大部份光子皆具有與入射光220相同的能量hν1的反射光224。 Referring to FIG. 2B, before the structural defects or electron traps 248 are filled by the electrons 240, a relatively weak frequency doubling effect is produced, with most of the photons having reflected light 224 of the same energy hν 1 as the incident light 220.

圖2C係系統200a(參考圖2A)中半導體結構202的能帶示意圖200c。更精確地,能帶圖200c係對應量測該二次諧波光譜的後期階段,如該二次諧波光譜的第二區域。 2C is an energy band diagram 200c of semiconductor structure 202 in system 200a (see FIG. 2A). More precisely, the energy band diagram 200c corresponds to measuring the later stages of the second harmonic spectrum, such as the second region of the second harmonic spectrum.

圖2C係例舉說明圖2A中系統200a的能帶示意圖200c。更精確地,該能帶示意圖200c相較於能帶圖200b(參考圖2B),係對應電子240開始從結構缺陷或電子陷阱248中被釋放的後期階段。在一些實施例中,當大量電子240被電子陷阱248困住,使利於電子240反向穿隧的電場得以建立,顯著的電子釋放也隨之產生,如箭頭所示。 2C illustrates an energy band diagram 200c of system 200a of FIG. 2A. More precisely, the band diagram 200c is compared to the band diagram 200b (see FIG. 2B) for the later stages in which the electrons 240 begin to be released from the structural defects or electron traps 248. In some embodiments, when a large number of electrons 240 are trapped by the electron trap 248, an electric field that facilitates reverse tunneling of the electrons 240 is established, and significant electron release is also produced, as indicated by the arrows.

當電子陷阱248大部分被電子240占據,會產生顯著的倍頻效應,發出能量為入射光220兩倍的二次諧波光228,同時產生能量與入射光220相同的反射光224。 When the electron trap 248 is largely occupied by the electrons 240, a significant frequency doubling effect is produced, emitting second harmonic light 228 having twice the energy of the incident light 220, while producing the same reflected light 224 of energy as the incident light 220.

由於二次諧波的訊號較反射光束微弱,如何提高二次諧波的訊雜比便相當重要。其中一種減低雜訊的方法是積極冷卻感測器。冷卻可減少因熱雜訊產生的假陽性光子感測。此方法可以低溫流體如液態氮/氦或固體冷卻,如以帕耳帖裝置的方式達 成。 Since the signal of the second harmonic is weaker than the reflected beam, how to improve the signal-to-noise ratio of the second harmonic is very important. One way to reduce noise is to actively cool the sensor. Cooling reduces false positive photon sensing due to thermal noise. This method can be cooled by a cryogenic fluid such as liquid nitrogen/helium or solids, as in the form of a Peltier device. to make.

從二次諧波光譜測定時間常數與電子陷阱的密度Determination of time constant and density of electron trap from second harmonic spectrum

參考圖1,方法100包含在步驟112量測一二次諧波光譜之後的步驟116從該二次諧波光譜測定一與電子240被電子陷阱248困住的速率相關的第一時間常數、一與電子240從電子陷阱248中被釋放的速率相關的第二時間常數(參考圖2A-2C)或其組合。 Referring to FIG. 1, method 100 includes a step 116 after measuring a second harmonic spectrum at step 112, from the second harmonic spectrum, a first time constant associated with a rate at which electrons 240 are trapped by electron trap 248, A second time constant (refer to Figures 2A-2C) associated with the rate at which electrons 240 are released from electronic trap 248, or a combination thereof.

圖3係一些實施例中用來測定時間常數與電子陷阱密度的二次諧波光譜示意圖400。二次諧波光譜404中包含一時變相對快速但照射時間相對短暫的第一區域404a與一時變相對緩慢但照射持續時間較長的第二區域404b。 3 is a second harmonic spectrum diagram 400 used to determine time constants and electron trap densities in some embodiments. The second harmonic spectrum 404 includes a first region 404a that is relatively time-varying but relatively short-lived, and a second region 404b that is relatively slow at one time but has a longer duration of illumination.

該第一區域404a可對應至二次諧波光譜404的一部分。如前述,其中該部分的二次光譜訊號係由因被電子240填充而提高之電子陷阱248的密度所主導(如圖2A、2B),因此二次諧波的訊號強度以相對較快的速度增強(以第一時間常數τ1特徵化)。在此狀態下,因電子240被電子陷阱248釋放而產生之電子陷阱密度減低的效應(如圖2C所示)相對較低。 The first region 404a can correspond to a portion of the second harmonic spectrum 404. As described above, the secondary spectral signal of the portion is dominated by the density of the electron trap 248 which is increased by being filled by the electron 240 (Fig. 2A, 2B), so the signal intensity of the second harmonic is relatively fast. Enhancement (characterized by the first time constant τ 1 ). In this state, the effect of the electron trap density reduction (as shown in FIG. 2C) due to the release of the electrons 240 by the electron traps 248 is relatively low.

相反地,第二區域404b所對應之二次諧波光譜404的部分,不再由因被電子240填充而增加之電子陷阱248的密度所主導(如圖2A、2B)。在此狀態下,因電子240被電子陷阱248釋放而產生之電子陷阱密度減低的效應相對較大(如圖2A、2C),使二次諧波光譜的成長相對緩慢(以第二時間常數τ2特徵化)。 Conversely, the portion of the second harmonic spectrum 404 corresponding to the second region 404b is no longer dominated by the density of the electron trap 248 that is increased by the filling of the electrons 240 (Figs. 2A, 2B). In this state, the effect of the electron trap density reduction due to the release of the electrons 240 by the electron trap 248 is relatively large (as shown in FIGS. 2A and 2C), so that the growth of the second harmonic spectrum is relatively slow (with the second time constant τ). 2 characterization).

在一些實施例中,二次諧波光譜404中的第一區域404a及第二區域404b的二次諧波訊號,係與被電子240填充之結構缺陷的密度成正比,並具有對數時間相依性。該對數時間相依性可為一電子陷阱248與高介電係數介電層/半導體基體介面的距離,或與高介電係數介電層/界面層介面(當有界面層存在時)的 距離相關的函數。如前面圖2B、2C所述,當穿隧距離增加,電子轉移的機率減低,電子被困住與釋放的速率也因此增加。由於二次諧波的訊號強度直接與被電子填充之電子陷阱的密度成正比,第一區域404a與第二區域404b中因電子陷阱248被電子240填充而產生的二次諧波訊號之有效的時間相依性可表現為: In some embodiments, the second harmonic signal of the first region 404a and the second region 404b in the second harmonic spectrum 404 is proportional to the density of structural defects filled by the electrons 240, and has logarithmic time dependence. . The logarithmic time dependence may be the distance between an electron trap 248 and the high-k dielectric layer/semiconductor substrate interface, or the distance from the high-k dielectric layer/interface layer interface (when an interfacial layer is present) The function. As previously described in Figures 2B and 2C, as the tunneling distance increases, the probability of electron transfer decreases, and the rate at which electrons are trapped and released increases. Since the signal strength of the second harmonic is directly proportional to the density of the electron trap filled by the electron, the second harmonic signal generated by the electron trap 240 in the first region 404a and the second region 404b is effective. Time dependence can be expressed as: versus

在方程式[4]、[5]中,I1(t)與I2(t)分別係二次諧波光譜404中第一區域404a與第二區域404b的強度,τ1與τ2分別係相對應區域的第一、第二時間常數。整體的二次諧波光譜404可表示為一和式: In equations [4] and [5], I 1 (t) and I 2 (t) are the intensities of the first region 404a and the second region 404b in the second harmonic spectrum 404, respectively, and τ 1 and τ 2 are respectively The first and second time constants of the corresponding regions. The overall second harmonic spectrum 404 can be expressed as a sum:

τ1與τ2可由分別近似兩區域404a、404b中近乎獨立的二次諧波訊號408與412得到,如圖3。 τ 1 and τ 2 can be obtained by approximating the nearly independent second harmonic signals 408 and 412 in the two regions 404a, 404b, respectively, as shown in FIG.

由電子陷阱之填充所主導的τ1可表示為: The τ 1 dominated by the filling of the electronic trap can be expressed as:

在方程式[7a]中,σt係捕獲截面積,νth係電子的熱速度,nc(x,t)係電子從矽基體轉移(如穿隧)至高介電係數電介質中的密度。σt與νth的值可由獨立的理論或實驗測得。如上述,nc(x,t)係與電子從半導體基體穿隧(如直接穿隧)至分佈在高介電係數介電層中之電子陷阱的機率有關。由於穿隧效應係一量子力學的現象,其可能受物理障礙的厚度、電子需穿隧的高度以及其他因素影響,故nc(x,t)受許多因素影響,包含入射光的能量與強度。 當入射光的能量與強度足以使幾乎所有高介電係數介電層中的電子陷阱皆捕獲電子,即可測得幾乎飽和的二次諧波光譜。例如當入射光的能量足以使大部分電子從半導體基體轉移至能量較高的電子陷阱中,且當入射光的強度足以使電子陷阱迅速被填充,所有的結構缺陷基本上都能在開始有電子被釋放前捕獲電子。在此情況下,可獲得一飽和的二次諧波光譜。並非如圖3中所示之二諧波光譜400具有一持續時間較短、時間相依性相對快速的第一區域404a,與一持續時間較長但時間相依性相對緩慢的第二區域404b,一飽和的二次諧波光譜具有一持續時間較短、時間相依性相對快速的第一區域與一時間相依性為常數的第二區域。亦即,一飽和的二次諧波光譜會有與圖3中反卷積的二次諧波光訊號408相似的圖形。在此情況下,方程式[7a]可表示為: In equation [7a], σ t captures the cross-sectional area, the thermal velocity of the ν th- based electrons, and the density of n c (x, t) electrons from the ruthenium matrix (eg, tunneling) to the high-k dielectric. The values of σ t and ν th can be measured by independent theory or experiment. As noted above, n c (x, t) is related to the probability of electrons tunneling from the semiconductor substrate (eg, direct tunneling) to electron traps distributed in the high-k dielectric layer. Since tunneling is a phenomenon of quantum mechanics, which may be affected by the thickness of physical barriers, the height of electrons to be tunneled, and other factors, n c (x, t) is affected by many factors, including the energy and intensity of incident light. . The nearly saturated second harmonic spectrum is measured when the energy and intensity of the incident light is sufficient to capture electrons in almost all of the electron traps in the high-k dielectric layer. For example, when the energy of the incident light is sufficient to transfer most of the electrons from the semiconductor substrate to the higher energy electron trap, and when the intensity of the incident light is sufficient to cause the electron trap to be quickly filled, all structural defects can basically start with electrons. Capture electrons before being released. In this case, a saturated second harmonic spectrum can be obtained. The second harmonic spectrum 400, which is not shown in FIG. 3, has a first region 404a having a short duration and relatively fast time dependence, and a second region 404b having a longer duration but a relatively slow time dependency, The saturated second harmonic spectrum has a second region with a short duration, relatively fast time dependence, and a first region with a constant time dependence. That is, a saturated second harmonic spectrum will have a pattern similar to the deconvolved second harmonic optical signal 408 of FIG. In this case, equation [7a] can be expressed as:

在方程式[7b]中,Nt係介電係數介電層中被填充之電子陷阱與未被填充之電子陷阱的總濃度。在一些實施例中,基於完全填充的Nt與二次諧波強度的定量相關性,Nt可由τ1單獨獲得。 In equation [7b], the N t is the total concentration of filled electron traps in the dielectric layer and unfilled electron traps. In some embodiments, based on the quantitation N t secondary harmonic intensity correlation completely filled, τ 1 N t may be obtained separately.

不同的結構缺陷會導致不同的τ1與τ2。許多實施例皆可量測或提取各時間常數的範圍。例如時間常數的範圍可係0.1飛秒至1飛秒之間、1飛秒至10飛秒之間、10飛秒至100飛秒之間、100飛秒至1皮秒之間、1皮秒至10皮秒之間、10皮秒至100皮秒之間、100皮秒與1奈秒之間、1奈秒與10奈秒之間、10奈秒與100奈秒之間、100奈秒與1微秒之間、1奈秒至100微秒之間、100微秒至1毫秒之間、1微秒至100毫秒之間、100微秒與1秒之間、1秒至10秒之間、10秒至100秒之間,或者更長,或者更短。相同地,探測器與致動器之間或致動器與探測器之間的 延遲時間Δ可介於0.1飛秒至1飛秒之間、1飛秒至10飛秒之間、10飛秒至100飛秒之間、100飛秒至1皮秒之間、1皮秒至10皮秒之間、10皮秒至100皮秒之間、100皮秒與1奈秒之間、1奈秒與10奈秒之間、10奈秒與100奈秒之間、100奈秒與1微秒之間、1奈秒至100微秒之間、100微秒至1毫秒之間、1微秒至100毫秒之間、100微秒與1秒之間、1秒至10秒之間或10秒至100秒之間。時間常數亦可能落於上述範圍之外。 Different structural defects lead to different τ 1 and τ 2 . Many embodiments can measure or extract a range of time constants. For example, the time constant can range from 0.1 femtosecond to 1 femtosecond, between 1 femtosecond to 10 femtoseconds, between 10 femtoseconds to 100 femtoseconds, between 100 femtoseconds to 1 picosecond, and 1 picosecond. Between 10 picoseconds, 10 picoseconds to 100 picoseconds, between 100 picoseconds and 1 nanosecond, between 1 nanosecond and 10 nanoseconds, between 10 nanoseconds and 100 nanoseconds, 100 nanoseconds Between 1 microsecond, 1 nanosecond to 100 microsecond, 100 microsecond to 1 millisecond, 1 microsecond to 100 millisecond, 100 microsecond to 1 second, 1 second to 10 second Between 10 seconds and 100 seconds, or longer, or shorter. Similarly, the delay time Δ between the detector and the actuator or between the actuator and the detector can be between 0.1 femtoseconds to 1 femtosecond, between 1 femtosecond and 10 femtoseconds, 10 femtoseconds Between 100 femtoseconds, 100 femtoseconds to 1 picosecond, 1 picosecond to 10 picoseconds, 10 picoseconds to 100 picoseconds, 100 picoseconds to 1 nanosecond, 1 nanosecond Between 10 nanoseconds, 10 nanoseconds and 100 nanoseconds, between 100 nanoseconds and 1 microsecond, between 1 nanosecond and 100 microseconds, between 100 microseconds and 1 millisecond, and 1 microsecond to Between 100 milliseconds, between 100 microseconds and 1 second, between 1 second and 10 seconds, or between 10 seconds and 100 seconds. The time constant may also fall outside the above range.

儘管電子陷阱的總濃度Nt可從一些二次諧波光譜(如一飽和的光譜)並基於方程式[7a]獲得,獲得Nt的方法並不限於此。參考圖1,方法100在測定τ1與τ2(如上述)之後,進一步包含步驟120從第一時間常數或第二時間常數或其組合,測定高介電係數介電層中電子陷阱的密度。在一些實施例中,電子陷阱的密度可由偏微分方程式測定: Although the total concentration N t of the electron trap can be obtained from some second harmonic spectrum (such as a saturated spectrum) and based on the equation [7a], the method of obtaining N t is not limited thereto. Referring to FIG. 1, after determining τ 1 and τ 2 (as described above), the method 100 further includes the step 120 of determining the density of the electron trap in the high-k dielectric layer from the first time constant or the second time constant or a combination thereof. . In some embodiments, the density of the electron trap can be determined by a partial differential equation:

在方程式[8]中,nt(x,t)係高介電係數介電層中被填充之電子陷阱濃度的曲線,Nt係電子陷阱的總濃度。參考圖3,基於從二次諧波光譜測得的τ1與τ2,nt(x,t)與Nt的一個值可經由如以有限差分法數值求解測定,其他nt(x,t)與Nt係作為輸入值。如實施例,將nt(x,t)作為輸入值,以有限差分法數值求解微分方程式[8],即可測得電子陷阱的總濃度Nt,例如將穿過高介電係數介電層厚度不同的nt(x,t)曲線作為輸入值,像是一常數曲線、一常態分佈曲線或一Δ函數曲線(如在高介電係數介電層與二氧化矽的界面),僅列舉幾個例子。 In equation [8], n t (x, t) is the curve of the electron trap concentration filled in the high-k dielectric layer, and the total concentration of the N t-type electron trap. Referring to FIG. 3, based on the values of τ 1 and τ 2 measured from the second harmonic spectrum, n t (x, t) and N t can be determined by numerical solution as in the finite difference method, and other n t (x, t) and N t are used as input values. As an example, taking n t (x, t) as an input value and solving the differential equation [8] numerically by the finite difference method, the total concentration of the electron trap N t can be measured, for example, passing through a high dielectric constant dielectric. The n t (x, t) curve with different layer thicknesses is used as an input value, such as a constant curve, a normal distribution curve or a Δ function curve (such as the interface between the high-k dielectric layer and the ceria), only List a few examples.

實驗數據Experimental data

參考圖5至圖7,以下例舉說明實施例的二次諧波光譜。該等二次諧波光譜係從以原子層沉積法製成之物理樣品測 得。在每個樣品中,一於(100)矽積體表面以原子層沉積法製成的二氧化鉿薄膜具有約1-5歐姆厘米的電阻率。圖5至圖7中的每個二次諧波光譜皆由一光子能量為1.5895eV,平均雷射功率300mW的入射光引發,使其對應的二次諧波之光子能量為3.179eV。其中該些入射光子以約45度的入射角射入二氧化鉿薄膜的表面。每一道入射光與測得的輸出光皆為P極化。所分析樣本的拆分表如下: Referring to Figures 5 to 7, the second harmonic spectrum of the embodiment will be exemplified below. These second harmonic spectra were measured from physical samples made by atomic layer deposition. In each sample, a cerium oxide film formed by atomic layer deposition on the surface of the (100) slab has about 1-5 ohms . The resistivity of centimeters. Each of the second harmonic spectra in Figures 5 to 7 is induced by an incident light of a photon energy of 1.5895 eV and an average laser power of 300 mW, so that the photon energy of the corresponding second harmonic is 3.179 eV. The incident photons are incident on the surface of the ruthenium dioxide film at an incident angle of about 45 degrees. Each incident light and the measured output light are P-polarized. The split table for the sample analyzed is as follows:

圖4係以上述方法(包含數值求解方程式[8])獲得的一實施例之二次諧波光譜504與一模式配適度508之圖表500。其中該實施例之二次諧波光譜504,係從表1中的樣品7測得。如前述圖3說明的內容,該實施例之二次諧波光譜504與該模式配適度508皆具有一持續時間較短(最久約5秒)且時間相依性相對快速的第一區域(即測得τ1之區域),與一持續時間較長(超過5秒)但時間相依性相對緩慢的第二區域(即測得τ2之區域)。其中測得的τ1與τ2分別為2.6秒與17秒。該實施例之二次諧波光譜504與該模式配適度508具有相當高的一致性。 4 is a graph 500 of a second harmonic spectrum 504 and a mode fit 508 of an embodiment obtained by the above method (including numerical solution of equation [8]). The second harmonic spectrum 504 of this example was measured from sample 7 in Table 1. As described above with respect to FIG. 3, the second harmonic spectrum 504 of the embodiment and the mode fit 508 each have a first region of short duration (approximately 5 seconds maximum) and relatively fast time dependence (ie, The region of τ 1 is measured, with a second region that lasts longer (more than 5 seconds) but has a relatively slow time dependence (ie, the region where τ 2 is measured). The measured τ 1 and τ 2 were 2.6 seconds and 17 seconds, respectively. The second harmonic spectrum 504 of this embodiment has a relatively high consistency with the mode fit 508.

圖5係列示樣品7與樣品9之二次諧波光譜608、604的圖表600,如上述表1,其中樣品7與樣品9經不同時間長度的水蒸氣脈衝處理。如前述圖3說明的內容,該些實施例之二次諧波光譜608與604具有持續時間較短(最久約5秒)且時間 相依性相對快速的第一區域608a、604a,與持續時間較長(超過5秒)但時間相依性相對緩慢的第二區域608b、604b。透過比較兩樣品的二次諧波光譜,可推測鉿前驅物經較長時間的水蒸氣脈衝處理,將導致電子陷阱有更高的填充效率。 Figure 5 shows a graph 600 of the second harmonic spectra 608, 604 of Samples 7 and 9, as in Table 1 above, in which Samples 7 and 9 were pulsed with water vapor of different lengths of time. As explained above with respect to Figure 3, the second harmonic spectra 608 and 604 of these embodiments have a shorter duration (up to about 5 seconds) and time. The first regions 608a, 604a are relatively fast in dependence, and the second regions 608b, 604b are relatively long (more than 5 seconds) but relatively slow in time dependence. By comparing the second harmonic spectra of the two samples, it can be inferred that the strontium precursor is treated with a longer time steam pulse, which will result in higher filling efficiency of the electron trap.

圖6係列示樣品6、樣品7與樣品8之二次諧波光譜712、608以及704的圖表700,如上述表1,其中樣品6、樣品7以及樣品8分別具有不同的薄膜厚度。如前述圖3說明的內容,該些二次諧波光譜712、608與704具有持續時間較短(最久約5秒)且時間相依性相對快速的第一區域712a、608a、704a,與持續時間較長(超過5秒)但時間相依性相對緩慢的第二區域712b、608b以及704b。透過比較三樣品的二次諧波光譜的強度與時間常數,可推測隨著厚度增厚,時間常數τ1會增加,而時間相依性快速之第一區域712a、608a及704a的強度則會下降。 Figure 6 shows a graph 700 of the second harmonic spectra 712, 608, and 704 of Sample 6, Sample 7, and Sample 8, as in Table 1, above, with Sample 6, Sample 7, and Sample 8, respectively, having different film thicknesses. As described above with respect to FIG. 3, the second harmonic spectra 712, 608, and 704 have first regions 712a, 608a, 704a that are relatively short in duration (up to about 5 seconds long) and relatively time dependent, and last. Second regions 712b, 608b, and 704b that are relatively long (more than 5 seconds) but have relatively slow time dependencies. By comparing the intensity and time constant of the second harmonic spectrum of the three samples, it can be inferred that as the thickness increases, the time constant τ 1 increases, and the intensity of the first regions 712a, 608a, and 704a, which are fast in time dependence, decreases. .

圖7係列示以前述之方法測得之樣品6-9的τ1與其厚度之間關係的圖表800。數據點816、808、812、804分別係樣品6、樣品7、樣品8與樣品9的數據。從圖表800顯示,當高介電係數介電層的厚度增厚,電子從矽基體轉移至高介電係數介電層的平均時間會增加,使τ1也隨之增加。將圖7與圖6的結果互相對照參考,可推測結構缺陷不一定會聚集在二氧化鉿/二氧化矽或二氧化鉿/矽的界面,反而會分佈在整個二氧化鉿薄膜的厚度中,使電子從矽基體填充至位於二氧化鉿薄膜之結構缺陷中的機率降低。 Figure 7 is a graph 800 showing the relationship between τ 1 of sample 6-9 and its thickness as measured by the foregoing method. Data points 816, 808, 812, 804 are data for Sample 6, Sample 7, Sample 8, and Sample 9, respectively. From graph 800, when the thickness of the high-k dielectric layer is thickened, the average time for electrons to transfer from the germanium matrix to the high-k dielectric layer increases, and τ 1 also increases. Comparing the results of FIG. 7 and FIG. 6 with reference to each other, it can be inferred that the structural defects do not necessarily accumulate at the interface of cerium oxide/cerium oxide or cerium oxide/cerium, but are distributed throughout the thickness of the cerium oxide film. The probability of filling electrons from the ruthenium matrix to structural defects in the ruthenium dioxide film is reduced.

變化例Change

在上文已說明本發明的示例性方面有關特徵選擇的細節。對於本發明其他的細節,其可以結合上述參考專利和公開內容來理解,或者可以是本發明所屬領域之技術人員習知或理解的。對基於本發明之方法採用通常或邏輯上的額外動作而言,同 樣適用於本發明方法的各方面。根據本發明提供的方法,包含製造與使用的方法,該些方法包含但不限於依照列舉步驟的順序執行,該些方法更可進一步包含任何邏輯上可行的步驟順序。更進一步,當提供一取值範圍的情況下,應當理解的是該範圍的上限和下限之間的值、以及其他任何陳述的值或在該陳述範圍中的中間值,均應被包含在本發明之內。此外,本發明所描述的任何可選特徵,均可被獨立地或與本發明所述任何一個或多個特徵結合地被闡述或要求保護。 The details of the feature selection have been described above in connection with the exemplary aspects of the invention. Other details of the invention can be understood in conjunction with the above-referenced patents and disclosures, or may be understood or understood by those skilled in the art to which the invention pertains. For the method according to the invention to use the usual or logical extra actions, the same It is suitable for use in aspects of the method of the invention. The method provided in accordance with the present invention includes methods of manufacture and use, including but not limited to being performed in the order of enumerating steps, and the methods may further comprise any logically feasible sequence of steps. Further, where a range of values is provided, it is understood that the value between the upper and lower limits of the range, and any other stated value or intermediate value in the stated range, Within the invention. Furthermore, any optional features described herein can be set forth or claimed in isolation or in combination with any one or more of the features described herein.

此外,儘管本發明已經參考若干實施例,視需要地納入各種特徵來描述其實施態樣,但本發明並不被限定於所描述或表示為相對於本發明的每個變型。在不脫離本發明的真正精神和範圍的情況下,可以對所述的發明做出各種改變,並且可以用(在此敘述或為某種程度的簡潔起見未包含在此的)等效物來替換。 In addition, although the present invention has been described with reference to a number of embodiments, the various features are described as being described, and the invention is not limited to the description or representation of each variant. Various changes may be made to the described invention without departing from the true spirit and scope of the invention, and the equivalents (herein described or not included herein) To replace.

本發明所描述的各種步驟可使用一般用途處理器、數位訊號處理器(DSP)、特殊應用積體電路(ASIC)、可程式化邏輯陣列(FPGA)或其他可程式化邏輯裝置、各別的邏輯閘或電晶體邏輯、各別的硬體零組件,或被設計來執行本發明所揭露之功能的任何組合。一般用途處理器可係為一微處理器,但可替代地,處理器可以是任何常規處理器、控制器、微控制器或狀態機。該處理器可進一步係一包含用戶端接口之電腦系統的一部份,其可透過使用者介面與使用者溝通,並接收使用者輸入的指令,及具有至少一記憶體(例如一硬體或任何等效的儲存體,和隨機存取記憶體),該記憶體可儲存電子資訊,該電子資訊包含該處理器控制下的處理程式、透過使用者介面接口的通訊以及視頻輸出,該視頻輸出係透過任何類型的視頻輸出格式產生,例如可調變放大器、數位視訊介面、解析度多媒體介面、顯示埠或任何其他型 式。 The various steps described in the present invention may use a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic array (FPGA) or other programmable logic device, and a separate Logic gate or transistor logic, individual hardware components, or any combination designed to perform the functions disclosed herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. The processor can further be a part of a computer system including a user interface, which can communicate with the user through the user interface, receive commands input by the user, and have at least one memory (eg, a hardware or Any equivalent storage device, and random access memory), the memory can store electronic information including a processing program controlled by the processor, communication through a user interface, and video output, the video output Generated by any type of video output format, such as a variable-amplifier, digital video interface, resolution multimedia interface, display port or any other type formula.

一處理器可進一步係一運算裝置的組合,例如一數位訊號處理器與一微處理器的組合、複數微處理器、至少一微處理器與一數位訊號處理核,或任何類似的配置。這些裝置更可用來選擇如本發明所述裝置的值。 A processor can be further a combination of computing devices, such as a combination of a digital signal processor and a microprocessor, a plurality of microprocessors, at least one microprocessor and a digital signal processing core, or any similar configuration. These devices are more useful for selecting values for devices as described herein.

與本發明所述實施例連結所述的方法或演算步驟,可直接硬體實施、由處理器執行的軟體模組實施,或透過兩者的組合實施。一軟體模組可能常駐在隨機存取記憶體(RAM)、快閃記憶體、唯讀記憶體(ROM)、可消除程式化唯讀記憶體(EPROM)、電子抹除式可複寫唯讀記憶體(EEPROM)、暫存器、硬碟、可移磁碟、唯讀光碟(CD-ROM),或任何於本領域已知的儲存媒介之形式。一示例性的儲存媒介耦合到處理器,使該處理器可從該儲存媒介中讀取訊息,並將訊息寫入該儲存媒介中。可替代地,該儲存媒介可以係該處理器的一部分。該處理器與該儲存媒介可存在於一特殊應用積體電路(ASIC)中。該特殊應用積體電路可存在於使用者端。可替代地,該處理器與該儲存媒介可為使用者端中個別的元件。 The method or the calculation step described in connection with the embodiment of the present invention may be implemented directly by hardware, by a software module executed by a processor, or by a combination of the two. A software module may reside in random access memory (RAM), flash memory, read only memory (ROM), stylized read-only memory (EPROM), electronic erasable rewritable read-only memory Body (EEPROM), scratchpad, hard drive, removable disk, CD-ROM, or any form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read a message from the storage medium and write the message to the storage medium. Alternatively, the storage medium can be part of the processor. The processor and the storage medium may reside in a special application integrated circuit (ASIC). The special application integrated circuit can exist at the user end. Alternatively, the processor and the storage medium can be individual components in the user terminal.

在至少一示例性的實施例中,本發明所述的功能可由硬體、軟體、韌體,或任何其組合執行。若由軟體執行,該些功能可儲存、傳輸或產生分析/計算數據,以一或多個指令、代碼或其他電腦可讀取媒介上的信息輸出。電腦可讀取媒介包含電腦儲存媒介與溝通媒介,該溝通媒介包含任何利於將電腦程式從一端傳送至另一端的媒介。該儲存媒介可為任何能被電腦存取的媒介。該些電腦可讀取媒介可係(但不限於)隨機存取記憶體(RAM)、唯讀記憶體(ROM)、電子抹除式可複寫唯讀記憶體(EEPROM)、唯讀光碟(CD-ROM)或其他光碟儲存器、磁碟儲存器、磁性記憶裝置,或任何能以指令或資料結構的形式攜帶或儲存程式代碼, 並由電腦讀取的媒介。該記憶體可係旋轉磁硬碟驅動機、光碟驅動機、基於快閃記憶體的記憶體驅動裝置或任何固態、磁性或光學儲存裝置。 In at least one exemplary embodiment, the functions described herein can be performed by hardware, software, firmware, or any combination thereof. If executed by software, these functions may store, transfer or generate analytical/computed data for output on one or more instructions, code or other computer readable medium. The computer readable medium includes a computer storage medium and a communication medium, and the communication medium includes any medium that facilitates transferring the computer program from one end to the other. The storage medium can be any medium that can be accessed by a computer. The computer readable medium can be, but is not limited to, random access memory (RAM), read only memory (ROM), electronic erasable rewritable read only memory (EEPROM), CD-ROM (CD) -ROM) or other disc storage, disk storage, magnetic memory, or any program code that can be carried or stored in the form of an instruction or data structure. And the medium read by the computer. The memory can be a rotating magnetic hard disk drive, a compact disk drive, a flash memory based memory drive or any solid state, magnetic or optical storage device.

本發明的運算可透過一網站操作。該網站可在一伺服器電腦或一本地電腦上操作,例如下載到客戶端電腦,或由伺服器場進行運算。該網站可透過手機或個人數位處理器等任何用戶端存取。該網站可使用任何形式的超文件標示語言(HTML)代碼,例如可延伸超文件標示語言(XHTML)或可擴展標示語言(XML),以及通過任何形式,例如級聯式樣表單(CSS)或其他形式。 The operations of the present invention can be operated through a website. The website can be operated on a server computer or a local computer, such as a client computer, or operated by a server farm. The website can be accessed by any client such as a mobile phone or a personal digital processor. The website may use any form of Hypertext Markup Language (HTML) code, such as Extensible Hypertext Markup Language (XHTML) or Extensible Markup Language (XML), and by any form, such as Cascading Style Sheets (CSS) or other form.

此外,本發明之發明人意指僅依照35 USC 112,(f)解釋本發明所述之方法者。更具體地,本發明的保護範圍不限於所提供的實施例和/或本說明書中,而是僅通過與本公開內容相關聯的權利要求語言之範圍來限定。本發明所使用的電腦可係任何形式的電腦,包含通用的電腦或一些特殊功能性的電腦,例如電腦工作站。本發明所述之程式可係由C語言、爪哇語言(Java)、無線二進位執行環境(BREW)或任何程式語言撰寫而成。該些程式可常駐在儲存媒介中,例如磁性或光學性的儲存媒介,像是電腦硬碟驅動器、可移磁碟、記憶卡、安全數位媒介(SD)或任何可移動的媒介。該程式可透過依網路執行,例如透過一伺服器或其他機器將訊號傳送至本地電腦,使本地電腦能進行本發明所述之操作。 Furthermore, the inventors of the present invention mean that the method of the present invention is explained only in accordance with 35 USC 112, (f). More particularly, the scope of the invention is not limited to the embodiments and/or the description, but is defined by the scope of the claims language associated with the disclosure. The computer used in the present invention can be any form of computer, including a general purpose computer or some special functional computer such as a computer workstation. The program of the present invention can be written in C language, Java language (Java), Wireless Binary Execution Environment (BREW) or any programming language. The programs can reside in a storage medium, such as a magnetic or optical storage medium such as a computer hard drive, a removable disk, a memory card, a secure digital medium (SD), or any removable medium. The program can be executed by the network, for example, by transmitting a signal to a local computer through a server or other device, so that the local computer can perform the operations described in the present invention.

應注意的是本發明之實施例所揭露的所有特徵、元件、組件、功能、動作或步驟,皆可與其他實施方式自由組合與替換。可以理解的是除非特別說明,否則本發明所揭露之特徵、元件、組件、功能或步驟即使只揭露於一特定實施例中,仍視為可應用在本發明所提供之其他任何實施例。因此,本段落係做為 申請專利範圍的先行基礎。在任何時候,選自本發明不同實施例的特徵、元件、組件、功能、動作或步驟,或者使用其他實施例之特徵、元件、組件、功能、動作或步驟進行替換,即使在下面的敘述中未明確聲明,這樣的組合或替換仍應屬於本發明的保護範圍。應被認可的是要詳細說明每一可能的組合與替換將使說明書過於累贅,特別是本發明每個組合與替換皆可由本技術領域具有通常知識者輕易認知與執行。 It should be noted that all of the features, elements, components, functions, acts or steps disclosed in the embodiments of the present invention can be combined and replaced with other embodiments. It is to be understood that the features, elements, components, functions, or steps disclosed in the present invention are intended to be applicable to any other embodiment provided by the present invention, even if only disclosed in a particular embodiment. Therefore, this paragraph is The first basis for applying for a patent. At the time, features, elements, components, functions, acts or steps selected from the various embodiments of the invention may be substituted or used in accordance with the features, elements, components, functions, acts or steps of other embodiments, even in the following description. It is not explicitly stated that such combinations or substitutions are still within the scope of the invention. It should be recognized that it is to be understood that each possible combination and substitution will be too cumbersome, and that each combination and substitution of the present invention can be readily recognized and carried out by those of ordinary skill in the art.

在某些情況下,本發明揭露的實體可能被描述為與其他實體耦合。應被理解的是本發明所使用如”互相配合”、”耦合”、”連接”或任何這類的術語,在本發明中皆係可以互換的,並可通用於兩個實體的直接耦合(沒有任何不可忽略的中間實體,如寄生實體)或間接耦合(具有至少一個不可忽略的中間實體)。在本發明中當複數個實體被描述為直接耦合或在其耦合之敘述中並未提及任何中間實體,除非另有特別說明,否則應當理解的是該些實體之間亦可以係間接耦合。 In some cases, the entities disclosed herein may be described as being coupled to other entities. It will be understood that the terms "interacting", "coupled", "connected" or any of the terms used in the present invention are interchangeable in the present invention and can be used interchangeably for the direct coupling of two entities ( There are no intermediate entities that cannot be ignored, such as parasitic entities, or indirect couplings (with at least one non-negligible intermediate entity). In the present invention, when a plurality of entities are described as being directly coupled or in the context of their coupling, no intermediate entities are mentioned, unless otherwise specifically stated, it should be understood that the entities may also be indirectly coupled.

本發明對單一項的提及包含存在多個相同項目的可能性。更具體地,如在本文及其相關的權利要求中所使用的單數形式”一”、”一個”、”所述”、”該”除非另有說明,否則應視為包含複數對象。換言之,冠詞的使用允許本發明之說明書與申請專利範圍中所述項目係”至少一個”。 The reference to a single item of the invention encompasses the possibility of having multiple identical items. Rather, the singular forms "a", "the", "the" In other words, the use of the articles allows the item of the invention to be "at least one"

更進一步,應注意的是本發明之申請專利範圍可被撰寫為排除任何可選的元件,如說明書中指定為”典型”的元件,其”可以”或”可能”被使用。因此,本聲明係做為在申請專利範圍請求之元件的相關陳述中使用這類排他性術語如”單獨”、”僅”,或使用”否定”限制的先行基礎。在不使用這類排他性術語的情況下,本發明之申請專利範圍所使用的術語”包含”應當允許包含任何額外的元件,而不論在申請專利範圍中是否列舉了給定數目的元件 或額外特徵的添加可能被認為改變申請專利範圍中元件的性質。然而,申請專利範圍中諸任何如”包含”這類的術語皆可被修改為”組成”這類排他性的語言。除本發明特別定義,否則本發明使用的所有技術與科學術語,應被本發明領域之技術人員寬廣地賦予一般理解的含義,同時保持申請專利範圍的有效性。 Further, it should be noted that the scope of the present invention can be written to exclude any optional elements, such as those specified as "typical" in the specification, which may be used or may be used. Therefore, this statement is used as antecedent basis for the use of such exclusive terms such as "individual", "only", or "negative" in the relevant statements of the claimed elements. In the absence of such exclusive terms, the term "comprising", used in the scope of the claims of the invention, should be construed to include any additional elements, whether or not a given number of elements are recited in the scope of the claims. The addition of additional features or features may be considered to change the nature of the elements in the scope of the claimed patent. However, any term such as "comprising" in the scope of the claims can be modified to the exclusive language such as "composition." In addition to the particular definitions of the invention, all technical and scientific terms used in the present invention are intended to be broadly understood by those skilled in the <RTIgt;

儘管實施例可進行各種修改與替換,且具體的示例已於本發明之說明書與圖式中詳細說明,但應當理解的是本發明之保護範圍並不限於說明書所揭露的特定形式。在不脫離本發明的精神與範圍的情況下,應包含所有修改、等效物或替換皆應被本發明所保護。此外,實施例中揭露的任何特徵、功能、動作、步驟或元件,包含為限制發明範圍而對特徵、功能、動作、步驟或元件進行否定性限制,皆可引用或添加至申請專利範圍中。因此,本發明的範圍不限於所提供的實施例和/或說明書所揭露的內容,而係僅由本發明下述之申請專利範圍的語言進行限定。 While the invention may be susceptible to various modifications and alternatives, the specific embodiments of the present invention are described in the specification and drawings. All modifications, equivalents, or substitutions are intended to be included within the scope of the invention. In addition, any features, functions, acts, steps or elements disclosed in the embodiments are intended to limit the scope of the invention, and the features, functions, acts, steps, or components are not limited, and may be cited or added to the scope of the patent application. Therefore, the scope of the invention is not limited by the scope of the embodiments and/or the description of the invention, but only by the language of the following claims.

Claims (20)

一種特徵化半導體結構的方法,該方法包含以下步驟:提供一半導體結構,該半導體結構包含一半導體及一形成於該半導體表面之高介電係數介電層,其中該高介電係數介電層設有複數形成於其中的電子陷阱;使一具有入射能量之入射光至少部分穿透該高介電係數介電層,且至少部分入射光被該半導體吸收;該入射光使該半導體中的部分電子暫時轉移至該些電子陷阱中並暫時填充該些電子陷阱,其中該入射能量足以使部分電子由該半導體轉移至該些電子陷阱中並暫時被該些電子陷阱困住;該些電子產生一具有能量之光線,其中該光線的能量不同於該入射光之入射能量,其中該光線之產生係基於非線性光學效應;量測該光線之非線性光譜,其中該光譜具有一第一區域與一第二區域,其中該第一區域之強度變化速率與該第二區域不同;從該非線性光譜測定一第一區域之第一時間常數或第二區域之第二時間常數或其組合;及基於該第一時間常數或該第二時間常數或其組合測定該些電子陷阱的密度。 A method of characterizing a semiconductor structure, the method comprising the steps of: providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed on the surface of the semiconductor, wherein the high-k dielectric layer Providing a plurality of electron traps formed therein; causing incident light having incident energy to at least partially penetrate the high-k dielectric layer, and at least partially incident light is absorbed by the semiconductor; the incident light causes a portion of the semiconductor The electrons are temporarily transferred into the electron traps and temporarily filled with the electron traps, wherein the incident energy is sufficient to transfer part of the electrons from the semiconductor to the electron traps and temporarily trapped by the electron traps; the electrons generate a a light having energy, wherein the energy of the light is different from the incident energy of the incident light, wherein the light is generated based on a nonlinear optical effect; measuring a nonlinear spectrum of the light, wherein the spectrum has a first region and a a second region, wherein the first region has a different rate of change in intensity from the second region; from the nonlinear spectrum A second predetermined time constant of the first time constant or the second area of the first area, or combinations thereof; and a time constant based on the first or the second time constant or a combination of determining the density of the plurality of electron traps. 如請求項1所述的方法,進一步包含於一矽基體上提供一以鉿 (Hf)為基材之高介電係數介電層。 The method of claim 1, further comprising providing one on the substrate (Hf) is a high dielectric constant dielectric layer of the substrate. 如請求項2所述的方法,其中該些電子陷阱包含氧空位。 The method of claim 2, wherein the electronic traps comprise oxygen vacancies. 如請求項3所述的方法,進一步包含在該矽基體與該以鉿(Hf)為基材之高介電係數介電層之間插入一二氧化矽層。 The method of claim 3, further comprising inserting a ruthenium dioxide layer between the ruthenium substrate and the high-k dielectric layer based on ruthenium (Hf). 如請求項4所述的方法,其中該二氧化矽層與該以鉿(Hf)為基材之高介電係數介電層組合後的物理厚度不超過4奈米,使該些電子能在量測該非線性光譜的時間內從該矽基體以穿隧方式轉移至該些氧空位。 The method of claim 4, wherein the cerium oxide layer is combined with the high dielectric constant dielectric layer based on hafnium (Hf) to have a physical thickness of not more than 4 nm, so that the electrons can be The time during which the nonlinear spectrum is measured is transferred from the ruthenium matrix to the oxygen vacancies by tunneling. 如請求項1所述的方法,其中該些電子陷阱之陷阱能階係介於高介電係數介電層之導帶與半導體基體之導帶之間。 The method of claim 1, wherein the trapping potential of the electron traps is between the conduction band of the high-k dielectric layer and the conduction band of the semiconductor body. 如請求項1所述的方法,其中該第一時間常數係至少與一電子陷阱的電子捕獲率相關,且其中該第二時間常數係至少與一電子陷阱的電子釋放率相關。 The method of claim 1, wherein the first time constant is related to at least an electron capture rate of an electron trap, and wherein the second time constant is related to at least an electron release rate of an electron trap. 如請求項1所述的方法,進一步包含從該非線性光譜測定該第一區域之第一時間常數與該第二區域之第二時間常數,並從該第一時間常數與該第二時間常數測定該高介電係數介電層中該些電子陷阱的密度。 The method of claim 1, further comprising determining a first time constant of the first region from the nonlinear spectrum and a second time constant of the second region, and determining from the first time constant and the second time constant The density of the electron traps in the high dielectric constant dielectric layer. 如請求項8所述的方法,其中測定該些電子陷阱的密度更進一步包含對一偏微分方程進行數值求解,該偏微分方程與第一時間常數及第二時間常數之倒數、該些電子陷阱被該些電子填充之變化率相關。 The method of claim 8, wherein determining the density of the electron traps further comprises numerically solving a partial differential equation, the partial differential equation and a reciprocal of the first time constant and the second time constant, the electronic traps It is related to the rate of change of the electronic filling. 如請求項9所述的方法,其中該偏微分方程表示為: 其中nt(x,t)係該高介電係數介電層的電子填充濃度,Nt係該些電子陷阱的總密度,τ1係該第一時間常數,τ2係該第二時間常數。 The method of claim 9, wherein the partial differential equation is expressed as: Where n t (x, t ) is the electron fill concentration of the high-k dielectric layer, N t is the total density of the electron traps, τ 1 is the first time constant, and τ 2 is the second time constant . 如請求項1至10任一項所述的方法,其中該入射能量足以使該些電子暫時填充於該些電子陷阱中並產生倍頻效應,且其中量測該非線性光譜係包含量測一具有該第一區域與該第二區域的二次諧波光譜。 The method of any one of claims 1 to 10, wherein the incident energy is sufficient to temporarily fill the electron traps in the electron traps and generate a frequency doubling effect, and wherein measuring the nonlinear spectroscopy comprises measuring one a second harmonic spectrum of the first region and the second region. 如請求項1至10任一項所述的方法,其中該第一區域之強度變化速率較該第二區域快。 The method of any one of claims 1 to 10, wherein the first region has a rate of change in intensity that is faster than the second region. 一種特徵化一半導體結構的系統,該系統包含:一光源,該光源可發射一具有入射能量之入射光,其中該入射光至少有部分穿透一形成於一半導體表面之高介電係數介電層,且至少部分被該半導體吸收,其中該高介電係數介電層設有複數電子陷阱,其中該入射能量足以使部分電子由該半導體轉移至該些電子陷阱中並暫時被該些電子陷阱困住,該些電子可產生一具有能量之光線,其中該光線的能量不同於入射光之入射能量,其中該光線的產生係基於非線性光學效應;一感測器,用以偵測該光線之非線性光譜,其中該非線性光譜具有一第一區域與一第二區域,其中該第一區域之強度變化速率較該第二區域快; 一電子裝置,用以從該二次諧波光譜測定一第一區域之第一時間常數或一第二區域之第二時間常數或其組合,且進一步用以從該第一時間常數或該第二時間常數或其組合測定該高介電係數介電層中該些電子陷阱的密度。 A system for characterizing a semiconductor structure, the system comprising: a light source that emits incident light having incident energy, wherein the incident light at least partially penetrates a high-k dielectric formed on a semiconductor surface a layer, and at least partially absorbed by the semiconductor, wherein the high-k dielectric layer is provided with a plurality of electron traps, wherein the incident energy is sufficient to cause a portion of electrons to be transferred from the semiconductor to the electron traps and temporarily trapped by the electron traps Trapped, the electrons can generate a light having energy different from the incident energy of the incident light, wherein the light is generated based on a nonlinear optical effect; a sensor for detecting the light a nonlinear spectrum, wherein the nonlinear spectrum has a first region and a second region, wherein the first region has a rate of change of intensity that is faster than the second region; An electronic device for determining a first time constant of a first region or a second time constant of a second region or a combination thereof from the second harmonic spectrum, and further for using the first time constant or the first The two time constants or a combination thereof determines the density of the electron traps in the high-k dielectric layer. 如請求項13所述的系統,其中該高介電係數介電層係以鉿(Hf)為基材之高介電係數介電層,該半導體係以矽為基材製成。 The system of claim 13, wherein the high-k dielectric layer is a high-k dielectric layer based on hafnium (Hf), and the semiconductor is made of tantalum. 如請求項14所述的系統,其中該些電子陷阱包含氧空位。 The system of claim 14, wherein the electronic traps comprise oxygen vacancies. 如請求項15所述的系統,其中該光源所發射之入射光至少部分穿透位於該高介電係數介電層與該半導體之間的一二氧化矽層。 The system of claim 15 wherein the incident light emitted by the light source at least partially penetrates a layer of germanium dioxide between the high-k dielectric layer and the semiconductor. 如請求項16所述的系統,其中該二氧化矽層與該以鉿(Hf)為基材之高介電係數介電層組合後的物理厚度不超過4奈米,使該些電子能在量測該非線性光譜的時間內從該半導體以穿隧方式轉移至該些氧空位。 The system of claim 16, wherein the cerium oxide layer is combined with the high dielectric constant dielectric layer based on hafnium (Hf) to have a physical thickness of not more than 4 nm, so that the electrons can be The time during which the nonlinear spectrum is measured is transferred from the semiconductor to the oxygen vacancies by tunneling. 如請求項17所述的系統,其中該些電子陷阱之陷阱能階係介於該高介電係數介電層之導帶與該半導體之導帶之間。 The system of claim 17, wherein the trapping potential of the electron traps is between the conduction band of the high-k dielectric layer and the conduction band of the semiconductor. 如請求項13至18任一項所述的系統,其中該入射能量足以使該些電子暫時填充於該些電子陷阱中並產生倍頻效應,且其中量測該非線性光譜係包含量測一具有該第一區域與該第二區域的二次諧波光譜。 The system of any one of claims 13 to 18, wherein the incident energy is sufficient to temporarily fill the electron traps in the electron traps and produce a frequency multiplication effect, and wherein measuring the nonlinear spectrum comprises measuring one a second harmonic spectrum of the first region and the second region. 如請求項13至18任一項所述的系統,其中該第一區域之強度變化速率較該第二區域快。 The system of any one of claims 13 to 18, wherein the first region has a rate of change in intensity that is faster than the second region.
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