TW201721919A - Aspect ratio modification via angled implantation - Google Patents

Abstract

This disclosure is directed to aspect ratio modification via angled implantation. For a structure fabricated on a substrate during integrated circuit (IC) manufacture, achieving a certain target aspect ratio (AR) may be important for proper operation of the IC. The target AR may be based on internal dimensions of the structure (e.g., a magnetic tunnel junction). Fabricating the structure to have the target AR employing typical semiconductor fabrication operations may be difficult, expensive, etc. However, the requirements to achieve the target AR may be relaxed, and angled implantation may be used to modify the internal dimensions resulting from fabrication (e.g., a fabrication AR) to the target AR. For example, ions of amorphizing material may be accelerated at an angle into portions of the structure to deactivate at least some material in the structure, which may modify the fabrication AR to the target AR.

Description

Appearance ratio correction technique through angled implants

The present invention relates to semiconductor fabrication, and more particularly to systems for using angled implants to modify the aspect ratio of an integrated circuit structure.

Integrated circuit (IC) fabrication may involve a series of fabrication operations in which a layer of material is deposited on a substrate, the layering of which results in the formation of functional features that may be operated separately or cooperatively. In many instances, these features are based on a group of transistors that are grouped to operate in a manner. The amount of functionality that can be implemented in an IC can depend on the size of the transistors and other devices formed on the substrate. As the footprint of each component (e.g., a transistor) shrinks in size, the amount of functionality that can be applied to a single transistor increases while still being able to operate within power, heat, and the like. In this way, the functionality (eg, data processing, memory, I/O, etc.) that was previously only possible to be implemented in separate physical IC package components can now be implemented on a single system single chip (SOC). ) IC package components.

As mentioned above, more and more functionality is integrated into a single The capabilities in the IC can be heavily dependent on the ability to reduce the footprint of each feature. IC fabrication can produce ICs, for example, using a range of material deposition, masking, and etching operations. A layer of semiconductor material can be deposited and then the photoresist is deposited. Then, a narrow wavelength of light can be drawn onto the photoresist through the mask. During etching, portions of the material may be removed (eg, portions of the material that are not exposed to light, or portions of the material that are not exposed to light, depending on the use of positive or negative photoresist), and the remaining material may form such features. Part of the IC. The narrower the wavelength of the light, the smaller the features can be made, and thus more functionality can be included on a single substrate. However, as the patterning in the lithography process is narrowed to facilitate the fabrication of smaller features, the cost, complexity, and the like of fabrication may increase. These factors make it impossible to reduce these features, which typically limits the amount of functionality that can be incorporated into the IC physical package components and hinder the development of technology.

100A, 100B‧‧‧ structure

102, 102'‧‧‧Magnetic tunneling junction

104A, 104B‧‧‧ Deactivated materials

106A, 106B‧‧‧ Angled planting

108‧‧‧Contacts

110‧‧‧Upper ferrite

112‧‧‧ Tunneling barrier

114‧‧‧ Lower ferromagnet

116‧‧‧Contacts

118, 118'‧‧‧ substrate

200‧‧‧ structure

202‧‧‧Vertical MTJ (pMTJ)

204‧‧‧Deactivated materials

206‧‧‧ Angled planting

300‧‧‧ structure

302‧‧‧Vertical MTJ (pMTJ)

304A, 304B‧‧‧ Deactivated materials

306A, 306B‧‧‧ angled planting

400‧‧‧ structure

402, 402'‧‧‧Flat MTJ (iMTJ)

404A, 404B‧‧‧ Deactivated materials

406A, 406B, 406A', 406B'‧‧‧ angled planting

500‧‧‧ device

504‧‧‧ surface

800‧‧‧ system

802‧‧‧ system circuit

804‧‧‧Processing Circuit

806‧‧‧ memory circuit

808‧‧‧Power circuit

810‧‧‧Interface circuit

812‧‧‧Communication interface circuit

814‧‧‧Communication Module/Communication Circuit

The features and advantages of the various embodiments of the claimed subject matter will be apparent from the description of the accompanying claims An exemplary configuration of at least one embodiment of the present invention is shown; FIG. 2 illustrates an exemplary first configuration of an integrated circuit structure in accordance with at least one embodiment of the present invention; and FIG. 3 illustrates an integrated body in accordance with at least one embodiment of the present invention. Example second configuration of circuit structure; FIG. 4 illustrates an integrated circuit structure in accordance with at least one embodiment of the present invention Example third configuration; FIG. 5 illustrates an exemplary integrated circuit configuration and first fabrication operation in accordance with at least one embodiment of the present invention; FIG. 6 illustrates an exemplary integrated circuit configuration and in accordance with at least one embodiment of the present invention a second fabrication operation; FIG. 7 illustrates an exemplary operation of the appearance ratio correction via angled implantation in accordance with at least one embodiment of the present invention; and FIG. 8 illustrates that at least one embodiment in accordance with the present invention may be utilized, such as FIG. An example system to the device depicted in any of FIG.

While the following embodiments will be described with reference to the embodiments of the present invention, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.

SUMMARY OF THE INVENTION AND EMBODIMENT

The present invention relates to an appearance ratio correction technique via angled implantation. For a structure that is fabricated on a substrate during the fabrication of an integrated circuit (IC), achieving a certain aspect ratio (AR) may be important for proper operation of the IC. In at least one embodiment, the target AR can be fabricated using typical semiconductor fabrication operations to determine the internal dimensions of the structure (eg, magnetic tunnel junction). Having the target AR can be difficult, expensive, etc. . However, consistent with the present invention, the conditions for achieving the target AR may be arbitrary (eg, it may not need to achieve the target AR as part of the main process), and angular placement may be used to internalize the resulting The size (for example, making AR) is corrected to the target AR. For example, ions of an amorphizing material can be accelerated into a portion of the structure at an angle to deactivate at least some material in the structure, which can result in the fabrication of the AR being corrected to the target. AR.

In at least one embodiment, the integrated circuit device can include, for example, a substrate and at least one structure. The at least one structure may be fabricated on the substrate in an orientation perpendicular to a surface of the substrate, wherein a manufacturing appearance ratio due to fabrication of the at least one structure is dependent on an internal dimension of the structure, the fabrication appearance ratio It can be corrected to the target aspect ratio via angled implants.

In at least one embodiment, the at least one structure can be a magnetic tunnel junction. The fabrication can include at least a series of material deposition operations, material masking operations, and material etching operations, the angled implanting can include causing ions of the amorphized atoms or molecules within the electric field to accelerate at an angle of travel relative to the surface of the device such that The plasma strikes at least a portion of the at least one structure, the fabrication appearance being corrected to the target by the plasma impinging at least a portion of the at least one structure to amorphize the material within the at least one structure and reduce the internal dimensions Appearance ratio.

In at least one embodiment, a plurality of structures can be formed on a substrate having substantially similar shapes, heights, and arranged on the substrate in evenly spaced patterns separated by a predetermined length. The angle at which the at least one ion is accelerated may depend at least on the height and spacing length of the plurality of structures. The production appearance ratio can be corrected to a desired appearance ratio based on uniformly angled implantation around the structure. Or, outside of the production The aspect ratio can be corrected to the desired aspect ratio based on performing angled implants only on a portion of the structure. In at least one embodiment, the make-up aspect ratio can be corrected to a desired aspect ratio based on performing angled implants only on both sides of the structure. In accordance with the present invention, an exemplary method for modifying the aspect ratio in a structure can include providing a substrate on which the integrated circuit is fabricated, and fabricating at least one structure on the substrate, wherein the fabrication of the at least one structure results from The production aspect ratio is determined by the internal dimensions of the structure, and the resulting appearance ratio is corrected to the target appearance ratio by angled implantation.

1 illustrates an example structure in accordance with at least one embodiment of the present invention. Initially, reference is made to various semiconductor combinations and/or structures, such as magnetic tunnel junction (MTJ), vertical MTJ (pMTJ), in-plane MTJ (iMTJ), etc., these example combinations and/or structures have been Reference is made to providing a quick understanding perspective view of the embodiments disclosed herein, and it is not intended to limit the actual implementation to only those particular combinations or structures. In addition, the inclusion of an apostrophe (e.g., 100') after the item number in the drawing may indicate that an example embodiment of a particular item is being displayed. These example embodiments are not intended to limit the invention to the drawings, and are shown for purposes of illustration only.

Consistent with the present invention, the angular implantation of an amorphizing agent can be used to achieve the target AR in the structure after completion of semiconductor fabrication. The target AR may depend, for example, on the internal dimensions of at least one structure fabricated on the IC device that may or may not be required to provide some functionality, performance, and the like. In at least one embodiment, Subtractive patterning of high density MTJ devices having a critical dimension (CD) of 30 nm or less is very difficult with conventional immersion lithography techniques and typically requires multiple exposure techniques and several lithography masks. cover. Rather than relying on this method of fabrication, a disposable device fabrication AR can be used, which then achieves the target AR by removing the surrounding activity of the device by planting it at the appropriate angle with the appropriate species. .

Use atoms or molecules with a sufficiently large nuclear mass such as, but not limited to, boron (B), carbon (C), nitrogen (N), phosphorus (P), germanium (Ge), xenon (Xe), etc. Angled implants, the surrounding material of the structure can be amorphized. As referenced herein, amorphizing a material can include converting the material from an electronically and/or magnetically active crystalline material to a deactivated amorphous material. This effect can be used in at least two possible applications to efficiently produce a desired MTJ device that has a smaller size than would be possible with current state of the art immersion lithography.

The example structures 100A and 100B are depicted in FIG. 1, and the structure 100A can include an MTJ 102 mounted on a substrate 118. While structure 100A can include MTJ 102, the embodiments described herein can be applied to other semiconductor structures. The MTJ 102 in structure 100A can be considered an "ideal" MTJ structure because it is substantially cylindrical (eg, having sides that are perpendicular to substrate 118). The MTJ 102 may comprise one or more layers deposited via a sequence of semiconductor fabrication operations. Exemplary semiconductor deposition techniques for depositing layers of semiconductor material may include, but are not limited to, molecular beam epitaxy (MBE), physical vapor deposition ( PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), atomic layer deposition (ALD), and the like. The junction between layers 108-116 can be modified using lithography to incorporate various features. In at least one example embodiment, the MTJ 102 can include an upper contact 108, an upper ferromagnetic body 110, a tunnel barrier 112, a lower ferromagnetic body 114, and a lower contact 116. The tunneling barrier layer 112 can be a thin insulator (eg, a few nanometers) that separates the upper ferromagnetic body 110 from the lower ferromagnetic body 114. Under certain conditions, electrons may pass through ferromagnetic bodies 110 and 114 by "tunneling" through tunneling barrier layer 112. This quantum mechanical effect can be used to set the memory bit state and thus serves as the basis for non-volatile memory, including, for example, hard disk drives, magnetoresistive random access memory (MRAM), and thermally assisted switching (TAS). Memory, spin torque transfer (STT) memory, and various other semiconductor devices.

The example structure 100B is substantially similar to the example structure 100A except that the shape of the MTJ 102' can be more trapezoidal than a cylindrical shape. The trapezoidal shape can be, for example, the result of a limitation of the general IC device process. Thus, while the trapezoidal shape of the MTJ 102' may be more typical in mass production, a more advanced assembly process may enable the structure to have a cylindrical shape that is closer to the MTJ 102. The remaining elements of MTJ 102' may be the same as those described with respect to MTJ 102, and thus the same item number has been used. Although the cylindrical shape of the MTJ 102 may be different from the trapezoidal shape of the MTJ 102', their operation may generally be substantially similar, based only on the internal inaccuracies of the IC process in terms of operational characteristics, and depending on the device. Some changes. In order to make the following disclosure simple and clear, a reference to "MTJ 102" is generally applicable to MTJ 102 and/or MTJ 102'.

Consistent with the present invention, semiconductor fabrication produces MTJ 102 with AR fabrication based on, for example, the limitations of special fabrication techniques. For example, at least from the cross-sectional perspective view shown in FIGS. 1 through 5, the AR can be made to include the internal dimensions of the MTJ 102. The production AR may not be suitable for all cases where the MTJ 102 is used, and thus, it may be desirable (and may be required) to modify the production AR to achieve the target AR. In at least one embodiment, the production AR can be modified to the target AR via use of the angled implants 106A and 106B. Angled implants 106A and 106B can include accelerating ions of an amorphized atom or molecule within an electric field at an angle of travel (eg, relative to a device surface) such that the plasma strikes the at least one structure (eg, MTJ 102) At least part. As a result, regions of deactivated material, such as those shown at 104A and 104B, can be generated within the MTJ 102, which enables the fabrication AR to be corrected to the target AR. In particular, deactivation materials 104A and 104B may form longitudinal boundaries or walls in MTJ 102, which are no longer functional portions of layers 108-116. The position, orientation, thickness, etc. of the deactivating materials 104A and 104B in the MTJ 102 may depend on the type and amount of correction required to reach the target AR, wherein the characteristics of the deactivating materials 104A and 104B may include, for example, amorphization. The type, angle, power, duration, etc. of the atom/molecule are controlled. For example, the use of higher power and/or implantation for longer durations may result in a greater thickness of the deactivated material 104. Although shown to be symmetrical, the characteristics of the deactivation materials 104A and 104B can be different, which can be considered to make the AR "tweaking" into the target AR.

2 illustrates an integrated circuit structure in accordance with at least one embodiment of the present invention. The first configuration of the example. The example structure 200 can include at least a vertical MTJ (pMTJ) 202 as shown in perspective and top views. As can be seen from the top view, the pMTJ 202 can be substantially circular and, although not shown, can include at least one spin transfer torque switching path that can be quickly run along at least the X axis, and an axle The thermal agitation switching path to ground. The pMTJ 202 can additionally comprise a deactivating material 204, which, in accordance with the present invention, can be produced by angled implant 206. As shown in detail in the top view of structure 200, angled implant 206 can be implemented in the vicinity of pMTJ 202 in a substantially uniform manner to produce a substantially uniform layer of deactivated material 204. The angled implant 206 can occur abruptly throughout the entire circumference of the pMTJ 202, or can occur by repeatedly moving back and forth around the pMTJ 202 based on the capabilities of the implanting device. The AR of structure 200 (as shown in Figure 2, which may depend on the ratio of the internal dimensions of X and Y) may remain constant because the thickness of deactivated material 204 may be substantially uniform due to the uniform angular implant 206. However, at least the level of the thickness of the deactivating material 204 in the structure 200 can be used to modify the fabrication CD to the target CD (eg, to control the area defined by the X and Y dimensions of the material of the deactivation material 204).

3 illustrates an example second configuration of an integrated circuit structure in accordance with at least one embodiment of the present invention. The example structure 300 can include at least a vertical MTJ (pMTJ) 302 as shown in perspective and top views. As seen from the top view, the pMTJ 102 can be substantially circular and, although not shown, can include at least one spin that can be quickly run along at least the X axis A transfer torque switching path, and a thermal agitation switching path that can be operated axially. The pMTJ 302 may additionally comprise a deactivating material 304 which, in accordance with the present invention, may be produced by angled implants 306A and 306B. As shown in detail in the top view of structure 300, angled implant 306A can produce deactivated material 304A, while angled implant 306B can produce deactivated material 304B. The position, orientation, thickness, etc. of each of the deactivation materials 304A and 304B can be used to modify the fabrication AR to the target AR, as shown in FIG. 3, which can depend on the ratio of the internal dimensions of X and Y.

4 illustrates an exemplary third configuration of an integrated circuit structure in accordance with at least one embodiment of the present invention. The example structure 400 can include at least a planar MTJ (iMTJ) 402 as shown in perspective and top views. As can be seen from the top view, the iMTJ 402 can be substantially elliptical in shape, and although not shown, can include a spin transfer torque switching path that can be quickly operated at least along the y axis and axially. And a thermal agitation switching path that can be quickly run along the x-axis. As shown at 406A and 406B, the iMTJ 402 can be angled implanted from only two directions, so that the deactivation material 404A and 204B may have no uniform thickness around the perimeter of the iMTJ 402, which is not uniform such that the iMTJ 402 The internal dimensions can be elastically modified to achieve the target AR. In particular, although shown to be symmetrical, the orientation, thickness, etc. of the deactivation materials 404A and 404B may actually be different based on the corrections required to achieve the target AR. As shown in FIG. 2, the target AR may depend on the ratio of the X dimension and the Y dimension.

5 illustrates an example integrated circuit in accordance with at least one embodiment of the present invention For configuration and first fabrication operations, the example device 500 can include a plurality of iMTJs 402' fabricated on a substrate 118' that can be fabricated on the substrate 118 in a uniform pattern (eg, a lattice pattern) 'Upper, such that the plurality of iMTJs 402' can be spread over the surface of the substrate 118' equidistantly. Consistent with the example illustrated in Figure 4, the angled implant 406B' can be used to adjust the internal dimensions of the iMTJ 402' by implanting an amorphized material. For example, implantation from the first direction 406B' can accelerate the atoms or molecules of the amorphized material toward the iMTJ 402' at an angle that produces the deactivated material 405B' on one side of the iMTJ 402'.

Example parameters used to determine the appropriate angle for implantation are shown at 502 of FIG. 5, and the example device 500' can include a plurality of iMTJs 402' in a uniform arrangement, wherein the iMTJ 402A' can correspond to the iMTJ of the first column 402', iMTJ 402B' may correspond to iMTJ 402' of the second column, and iMTJ 402C' may correspond to iMTJ 402' of the third column. The implant angle θ associated with, for example, the surface 504 of the device 500 can be determined based on at least the length L of the distance between the height H of the iMTJ 402' and the iMTJ 402'. With at least these two parameters, the implant angle θ can be selected which will allow angular implantation to occur over the entire side of the iMTJ 402'. More specifically, the implant angle θ can be selected to ensure that the iMTJ 402' (eg, iMTJ 402B') in the first column does not block the iMTJ 402' (eg, iMTJ 402C') configured in subsequent columns. Angle planting. If the implant angle θ is smaller than the example angle shown in Figure 5, blocking of subsequent columns will occur.

6 illustrates an example integrated circuit configuration and a second fabrication operation in accordance with at least one embodiment of the present invention. For example, the plurality of iMTJ 402's can be made The two portions can be exposed to the angled implant 406A', while the deactivated material 404A' is produced on the opposite side of the angled implant side of the iMTJ 402' The performance of the angled implants 406A' and 406B' is different. Although angled implants 406B' are described prior to angled implant 406A', these operations can be performed in the reverse order, simultaneously, and the like. Moreover, while Figures 5 and 6 show angled implants only from both sides, angled implants may occur uniformly from all sides to form pMTJ 202, such as that shown in FIG.

7 illustrates an example operation of appearance ratio correction via angled implants in accordance with at least one embodiment of the present invention. In operation 700, a substrate on which an IC is fabricated may be provided, which may include, for example, a sequence of semiconductor fabrication operations that may include deposition of one or more semiconductor layers, followed by masking/etching operating. Semiconductor fabrication may occur in operation 702, which may result in a structure having an incorrect feature size (eg, making an AR that does not conform to the target AR). In operation 704, the amount of change required to modify the internal dimensions to the target AR may be determined, and the parameters for the angled implant may then be determined in operation 706. For example, angled implants can be determined based at least on the height and spacing of the structures in the device. Moreover, other parameters such as particular amorphized material to be implanted, implant power, implantation period, and the like can be determined, and angular implantation can then be performed in operation 708. In at least one embodiment, operation 708 can be performed more than once depending on, for example, the characteristics of the implant (eg, type, location, orientation, angle, power period, etc.), the ability to plant the device, and the like. For example, in a manufacturing scheme such as that depicted in Figures 2 through 5, the implant can be implemented twice (For example, on two different sides of the structure), or repeatedly for uniform surrounding implantation to produce a substantially evenly distributed deactivated material 204, such as that depicted with respect to pMTJ 202 in FIG.

FIG. 8 illustrates an example system that may use a device such as that depicted in FIG. 4 in accordance with at least one embodiment of the present invention. System 800 is an example of a platform in which one or more devices, such as device 500, may be installed, and is not intended to limit the invention to any particular mode of operation. Examples of system 800 may include, but are not limited to, for example, based on an Android® OS from Google, an iOS® or Mac OS® from Apple, and a Windows® OS from Microsoft. Tizen® OS from Linux Foundation, Firefox® OS from Mozilla Project, Blackberry® OS from Blackberry, Palm® OS from Hewlett-Packard, and Symbian Foundation Mobile communication devices for cellular phones or smart phones of Symbian® OS, etc., such as the iPad® from Apple, the Surface® from Microsoft, and the Samsung (Samsung) ) Galaxy Tab® from the company, Kindle® from Amazon, Tablets with Ultrabook® from Intel's low-power chipset, notebooks, laptops, palmtops Mobile computing devices, such as desktop computers, servers, smart TVs, such as the next generation computing unit (NUC) from Intel Corporation Like pattern of small form factor calculation scheme (e.g., for space is limited, the TV machine A typical stationary computing device, such as a box, etc.).

System circuitry 802 can manage the operation of system 800, which can include, for example, processing circuitry 804, memory circuitry 806, power circuitry 808, user interface circuitry 810, and communication interface circuitry 812. System 800 can additionally include a communication module 814. Although communication module 814 is depicted as being separate from system circuitry 802, the example configuration shown in FIG. 8 is provided for purposes of illustration only. For example, some or all of the functionality associated with communication module 814 may also be incorporated into system circuitry 802.

In system 800, processing circuit 804 can include one or more processors located in separate components, or one or more cores in a single component (eg, in a system single-chip (SoC) configuration), and processing Device-related support circuits (for example, bridge interfaces, etc.). Example processors may include, but are not limited to, various x86 series microprocessors available from Intel Corporation, including Pentium, Xeon, Itanium, Celeron, Atom, Quark, Core i series product families, advanced RISCs (eg, Reduced instruction set calculations) machine or "ARM" processor and so on. An example of a support circuit can include a chipset that is configured to provide an interface (eg, available from Intel Corporation, Northbridge, Southbridge, etc.) via which processing circuitry 804 can Interact with other system components in system 800 that can operate at different speeds, on different bus bars, and the like. Moreover, some or all of the functionality typically associated with the support circuitry may also be included in the package component of the same entity as the processor (eg, such as Sandy Bridge, which is available from Intel Corporation processors). In the family).

The processing circuit 804 can be configured to execute various instructions in the system 800. The instructions can include code that is organized such that the processing circuit 804 implements and reads data, writes data, processes data, formulates data, converts data, and transforms Information, etc. activities. Information (eg, instructions, data, etc.) may be stored in memory circuit 806, which may include random access memory (RAM) and/or read only memory in a fixed or detachable format ( ROM), RAM may include volatile memory that is grouped to hold information during operation of system 800, such as, for example, static RAM (SRAM) or dynamic RAM (DRAM), ROM may be grouped based on BIOS, UEFI, etc. A non-volatile (NV) memory module, programmable memory (such as a programmable ROM (EPROM), flash memory, etc.) that provides instructions when system 800 is booted. Other fixed/detachable memories may include, but are not limited to, magnetic memory such as, for example, floppy disks, hard disk drives, etc., electronic memory such as solid state flash memory (eg, embedded multimedia cards) (eMMC), etc.), a removable card or stick (eg, micro storage device (uSD), USB, etc.), optical memory (such as a disc-based ROM (CD-ROM) ), digital audio and video discs (DVD), Blu-ray discs, etc.).

The power circuit 808 can include internal power sources (eg, batteries, fuel cells, etc.) and/or external power sources (eg, electromechanical or solar generators, power grids, external fuel cells, etc.), and are required for operation The power is supplied to the relevant circuitry of system 800. The user interface circuit 810 can include hardware and/or software that has enabled the user to interact with the system 800. Motion, such as, for example, various input mechanisms (eg, microphones, switches, buttons, knobs, keyboards, speakers, touch-sensitive surfaces, grouped to capture images and/or sense proximity, distance, motion, posture, orientation, biological data) Sensors, etc.) and various output mechanisms (eg, speakers, displays, lighting/flash indicators, electromechanical components for vibration, movement, etc.). The hardware in the user interface circuit 810 can be incorporated into the system 800 and/or can be coupled to the system 800 via a wired or wireless communication medium. The user interface circuit 810 may be optional in some cases, such as, for example, where the system 800 is a server that does not include the user interface circuit 810, but instead relies on a second device (eg, a management terminal) for user interface functionality. The case of a device (for example, a shelf server, a blade server, etc.).

The communication interface circuit 812 can be grouped into packet routing and other control functions for the management communication module 814, which can include resources that are grouped to support wired and/or wireless communication. In some examples, system 800 can include more than one communication module 814 (eg, including separate physical interface modules for wired protocols and/or radios) managed by centralized communication interface circuitry 812. Wired communications can include both serial and parallel wired media, such as, for example, Ethernet, Universal Serial Bus (USB), Firewire, Thunderbolt, Digital Video Interface (DVI), high-definition multimedia interface (HDMI) and the like, wireless communication may include, for example, short-range wireless media (eg, radio frequency (RF) based on RF recognition (RFID) or near field communication (NFC) standards, infrared (IR), etc.), short range Wireless media (for example, Bluetooth, WLAN, Wi-Fi, etc.), long-range wireless media (eg, cellular wide-area radio communication technology, satellite-based communication, etc.), electronic communication via sound waves, and the like. In one embodiment, the communication interface circuitry 812 can be configured to prevent wireless communications that are active in the communication module 814 from interfering with each other. In carrying out this function, the communication interface circuit 812 can schedule the communication module 814 for activity based on, for example, the relative priority of the message waiting for transmission. Although the embodiment disclosed in FIG. 2 illustrates that the communication interface circuit 812 is separated from the communication module 814, the functionality of the communication interface circuit 812 and the communication module 814 may also be incorporated into the same module.

Although FIG. 7 illustrates operations in accordance with an embodiment, it is to be understood that not all of the operations described in FIG. 7 are required for other embodiments. In fact, it is entirely contemplated herein that in other embodiments of the invention, the operations described in FIG. 7, and/or the operations described herein, may not be explicitly shown in any of the figures. The methods are combined but still fully consistent with the present invention. Therefore, the scope of the patent application is intended to be within the scope and spirit of the invention.

As with the users of this application and the scope of the patent application, a list of items linked by the term "and/or" may mean any combination of the items listed. For example, the words "A, B and/or C" may mean A; B; C; A and B; A and C; B and C; or A, B and C. As with the users of this application and the scope of the patent application, a list of items linked by the term "at least one of the terms" may mean any combination of the items listed. For example, the words "A, B or C are at least One (s) can mean A; B; C; A and B; A and C; B and C; or A, B and C.

As used in any embodiment herein, the term "system" can refer to, for example, software, firmware, and/or circuitry that is grouped to perform any of the foregoing operations. The software can be embodied as a set of software, code, instructions, instruction sets and/or data recorded on a non-transitory computer readable storage medium, and the firmware can be embodied as hard coded (eg, non-volatile) A "circuit", such as a hardwired circuit, such as including one or A plurality of individual instruction processing core computer program stylized circuits, state machine circuits, and/or a single or any combination of firmware that stores instructions executed by the stylized circuit. The modules may be implemented together or separately into circuits that form part of a larger system, such as integrated circuits (ICs), system single-chip (SoC), desktop computers, laptops, tablets, Server, smart phone, etc.

A single operation of the operations described herein can be implemented in a system including one or more storage media (eg, non-transitory storage media) having instructions stored individually or in combination The methods are implemented when the instructions are executed by one or more processors. Here, the processor may include, for example, a server CPU, a mobile device CPU, and/or other stylized circuits. Moreover, it is intended that the operations described herein can be spread across multiple physical devices, such as processing structures at one or more different physical locations. The storage medium can contain any type of tangible (tangible) media, for example, any type of disc including a hard disk, a floppy disk, a compact disk, a CD-ROM, a CD-RW, and a magnetic disk, such as Read memory (ROM), random access memory (RAM) such as dynamic and static RAM, erasable stylized read-only memory (EPROM), erasable stylized read-only memory (EEPROM), fast Flash memory, solid state disk (SSD), embedded multimedia card (eMMC), secure digital input/output (SDIO) card, semiconductor device for magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software modules executed by a stylized control device.

Accordingly, the present invention is directed to an aspect ratio correction technique via angled implants. For a structure fabricated on a substrate during the fabrication of an integrated circuit (IC), achieving a certain aspect ratio (AR) may be important for proper operation of the IC, which may depend on the structure (eg, The internal dimensions of the magnetic tunneling junction, using typical semiconductor fabrication operations to fabricate the structure, with the target AR can be difficult, expensive, and the like. However, the conditions for achieving the target AR can be arbitrary, and the angled implant can be used to correct the internal dimensions (eg, making AR) due to fabrication to the target AR. For example, ions of the amorphized material can be accelerated into a portion of the structure at an angle to deactivate at least some of the material in the structure, which can result in the fabrication AR being modified to the target AR.

The following examples relate to other embodiments. The following examples of the invention may include, for example, an apparatus, method, at least one machine readable storage medium (A mechanism for storing instructions, causing the machine to operate based on the method when the instructions are executed), a mechanism for operating based on the method, and/or a system for correcting the appearance ratio via angled implants Subject.

According to the first aspect, there is provided an integrated circuit device, the integrated circuit device comprising: a substrate; and at least one structure fabricated on the substrate in an orientation perpendicular to a surface of the substrate, wherein the at least one structure The production appearance ratio produced by the production is based on the internal dimensions of the structure, and the production appearance is corrected to the target appearance ratio by angled implantation.

Example 2 can include the component of Example 1, wherein the at least one structure is a magnetic tunnel junction.

Example 3 can include the component of Example 2, wherein the device includes at least an upper contact, an upper ferromagnetic body, a tunneling barrier layer, a lower ferromagnetic body, and a lower contact.

Example 4 can include the elements of any of Examples 1 to 3, wherein the making includes at least a series of material deposition operations, material masking operations, and material etching operations.

Example 5 may include the element of any of examples 1 to 4, wherein the angular implanting comprises accelerating ions of the amorphized atom or molecule within the electric field at an angle of travel relative to the surface of the device such that the plasma strikes the at least At least a part of a structure.

Example 6 may include the element of Example 5, wherein the amorphized atom or molecule comprises at least one of boron (B), carbon (C), nitrogen (N), phosphorus (P), germanium (Ge), or xenon (Xe). One.

Example 7 can include the components of any of examples 5 to 6, wherein The fabrication aspect ratio is corrected to the target appearance ratio by impinging at least a portion of the at least one structure to amorphize the material within the at least one structure and reduce the internal dimensions.

Example 8 may include the elements of any of examples 5 to 7, wherein a plurality of structures may be formed on the substrate, the plurality of structures having substantially similar shapes, heights, and arranged on the substrate to be of a predetermined length Separate evenly spaced patterns.

Example 9 can include the elements of Example 8, wherein the angle at which the at least one ion is accelerated can depend at least on the height and spacing length of the plurality of structures.

The example 10 may include the element of any one of examples 8 to 9, wherein the plurality of ions are accelerated, and the angle at which the at least one ion is accelerated is dependent on the plurality of ions striking each of the plurality of structures On the entire side.

Example 11 can include the elements of any of Examples 1 to 10, wherein the production appearance ratio is corrected to a desired appearance ratio based on uniformly performing angular implantation around the structure.

Example 12 can include the elements of any of Examples 1-11, wherein the production appearance ratio is corrected to a desired aspect ratio based on performing angled implantation only on a portion of the structure.

Example 13 can include the elements of Example 12, wherein the production appearance ratio is corrected to a desired appearance ratio based on performing angled implants only on both sides of the structure.

According to Example 14, there is provided a method for correcting the appearance ratio in the structure. The method may include: providing a substrate on which the integrated circuit device is fabricated; fabricating at least one structure on the substrate, wherein the fabrication appearance ratio produced by the fabrication of the at least one structure is based on the structure The internal dimensions; and the resulting appearance ratio is corrected to the target appearance ratio via angled implants.

Example 15 can include the elements of Example 14, wherein the at least one structure is a magnetic tunneling junction.

Example 16 can include the component of Example 15, wherein the device includes at least an upper contact, an upper ferromagnetic body, a tunneling barrier layer, a lower ferromagnetic body, and a lower contact.

Example 17 can include the elements of any of Examples 14-16, wherein fabricating the at least one structure comprises performing a series of material deposition operations, material masking operations, and material etching operations.

Example 18 can include the elements of any of Examples 14-17, and can additionally include: determining a dimensional change required to modify the production aspect ratio to the target appearance ratio based on the internal dimensions.

Example 19 can include the element of any one of examples 14 to 18, wherein the angled implant comprises causing ions of the amorphized atom or molecule within the electric field to accelerate at a travel angle relative to the surface of the device such that the plasma strikes the At least a portion of at least one structure.

Example 20 can include the element of Example 19, wherein the amorphized atom or molecule comprises at least one of boron (B), carbon (C), nitrogen (N), phosphorus (P), germanium (Ge), or xenon (Xe). One.

Example 21 can include elements of any of Examples 19-20, The fabrication appearance ratio is corrected to the target appearance ratio by uniformly impinging the periphery of the at least one structure with the plasma to amorphize the material within the at least one structure and reduce the internal dimensions.

The example 22 may include the element of any one of examples 19 to 21, wherein the fabrication appearance ratio impacts at least a portion of the at least one structure by the plasma to amorphize the material within the at least one structure and reduce the interior The size is corrected to the target aspect ratio.

Example 23 can include the elements of any of Examples 19-22, and can further include: determining an angle at which the plasma is implanted to amorphize at least a portion of the structural material.

Example 24 can include the elements of Example 23, wherein the integrated circuit device includes a plurality of structures fabricated on the substrate, and the angle is determined based on the height and spacing of the plurality of structures.

Example 25 can include the elements of Example 24, wherein the angle is determined based on the plurality of ions striking the entire side of each of the plurality of structures.

According to Example 26, there is provided a system comprising a device configured to perform the method of any of the above Examples 14 to 25.

According to Example 27, there is provided a wafer set configured to perform the method of any of the above Examples 14 to 25.

According to the example 28, there is provided at least one machine readable storage medium comprising a plurality of instructions, and the instructions are executed on a computing device, such that the computing device implements the method of any of the above examples 14 to 25.

According to Example 29, there is provided at least one apparatus configured to implement an aspect ratio for modifying a structure, the at least one apparatus being configured to implement the method of any of the above Examples 14 to 25.

According to Example 30, there is provided a system for modifying the aspect ratio in a structure, the system comprising: means for providing a substrate on which the integrated circuit device is fabricated; for fabricating at least one structure on the substrate The mechanism wherein the manufacturing appearance ratio produced by the fabrication of the at least one structure is based on the internal dimensions of the structure; and the mechanism for correcting the manufacturing appearance ratio to the target appearance ratio via angled implantation.

Example 31 can include the elements of example 30, wherein the at least one structure is a magnetic tunneling junction.

Example 32 can include the elements of Example 31, wherein the apparatus includes at least an upper contact, an upper ferromagnetic body, a tunneling barrier layer, a lower ferromagnetic body, and a lower contact.

The example 33 can include the elements of any of examples 30 to 32, wherein the mechanism for fabricating the at least one structure includes a mechanism for performing a series of material deposition operations, material masking operations, and material etching operations.

The example 34 can include elements of any of the examples 30 through 33, and can further include: a mechanism for determining a dimensional change required to modify the appearance ratio to the target appearance ratio based on the internal size.

Example 35 may comprise the element of any one of examples 30 to 34, wherein the angled implant comprises causing ions of the amorphized atom or molecule within the electric field to accelerate at an angle of travel relative to the surface of the device such that the plasma strikes the At least a portion of at least one structure.

Example 36 can include the element of Example 35, wherein the amorphized atom or molecule comprises at least one of boron (B), carbon (C), nitrogen (N), phosphorus (P), germanium (Ge), or xenon (Xe). One.

The example 37 can include the element of any one of examples 35 to 36, wherein the fabrication appearance ratio uniformly strikes the periphery of the at least one structure by the plasma to amorphize and reduce material within the at least one structure The internal dimensions are corrected to the target aspect ratio.

The example 38 can include the element of any one of examples 35 to 37, wherein the fabrication appearance ratio impacts at least a portion of the at least one structure by the plasma to amorphize the material within the at least one structure and reduce the interior The size is corrected to the target aspect ratio.

Example 39 can include the elements of any of Examples 33-38, and can further include: a mechanism for determining an angle at which the plasma is implanted to amorphize at least a portion of the structural material.

Example 40 can include the elements of Example 39, wherein the integrated circuit device includes a plurality of structures fabricated on the substrate, and the angle is determined based on the height and spacing of the plurality of structures.

Example 41 can include the elements of example 40, wherein the angle is determined based on the plurality of ions striking the entire side of each of the plurality of structures.

The words and phrases used herein have been used for purposes of illustration and not limitation, and are not intended to be Partially excluded, and it is believed that various amendments may be within the scope of the scope of patent application. of. Therefore, the scope of the patent application is intended to cover all such equivalents.

100A, 100B‧‧‧ structure

102, 102'‧‧‧Magnetic tunneling junction

104A, 104B‧‧‧ Deactivated materials

106A, 106B‧‧‧ Angled planting

108‧‧‧Contacts

110‧‧‧Upper ferrite

112‧‧‧ Tunneling barrier

114‧‧‧ Lower ferromagnet

116‧‧‧Contacts

118‧‧‧Substrate

Claims (25)

An integrated circuit device comprising: a substrate; and at least one structure fabricated on the substrate in an orientation perpendicular to a surface of the substrate, wherein the fabrication appearance ratio produced by the fabrication of the at least one structure is based on the structure The internal dimensions of the production are corrected to the target appearance ratio over an angled implant. The device of claim 1, wherein the at least one structure is a magnetic tunneling junction. The apparatus of claim 1, wherein the angled implant comprises causing ions of an amorphized atom or molecule within the electric field to accelerate at an angle of travel relative to a surface of the device such that the plasma strikes at least the at least one structure. portion. The apparatus of claim 3, wherein the manufacturing appearance ratio is caused by the plasma impinging at least a portion of the at least one structure to amorphize the material in the at least one structure and reduce the internal dimensions Corrected to the target aspect ratio. The apparatus of claim 3, wherein a plurality of structures are formed on the substrate, the plurality of structures having substantially similar shapes and heights, and arranged on the substrate to be evenly separated by a predetermined length Interval pattern. The device of claim 5, wherein the angle at which the at least one ion is accelerated depends on at least the height and spacing length of the plurality of structures. The apparatus of claim 1, wherein the production appearance ratio is corrected to the desired appearance ratio based on uniformly performing angular implantation around the structure. The apparatus of claim 1, wherein the production appearance ratio is corrected to the desired appearance ratio based on performing angled implantation only on a portion of the structure. The apparatus of claim 8, wherein the production appearance ratio is corrected to the desired appearance ratio based on performing angled implantation only on both sides of the structure. A method for modifying an aspect ratio in a structure, comprising: providing a substrate on which an integrated circuit device is fabricated; fabricating at least one structure on the substrate, wherein the fabrication ratio of the at least one structure is produced Based on the internal dimensions of the structure; and the resulting appearance ratio is corrected to the target appearance ratio via angled implants. The method of claim 10, wherein the at least one structure is a magnetic tunnel junction. The method of claim 10, further comprising: determining a dimensional change required to reduce the production aspect ratio to the target appearance ratio based on the internal dimension. The method of claim 10, wherein the angled implant comprises causing ions of the amorphized atom or molecule in the electric field to accelerate at an angle of travel relative to the surface of the device such that the plasma strikes the at least one At least part of the structure. The method of claim 13, wherein the manufacturing appearance ratio is such that the plasma uniformly strikes the periphery of the at least one structure to amorphize the material in the at least one structure and reduce the internal dimensions. Corrected to the target aspect ratio. The method of claim 13, wherein the manufacturing appearance ratio is caused by the plasma impinging at least a portion of the at least one structure to amorphize the material in the at least one structure and reduce the internal dimensions. Corrected to the target aspect ratio. The method of claim 13, further comprising: determining an angle at which the plasma is implanted to amorphize at least a portion of the structural material. The method of claim 16, wherein the integrated circuit device comprises a plurality of structures fabricated on the substrate, and the angle is determined based on a height and an interval of the plurality of structures. An at least one machine readable storage medium having instructions for correcting an aspect ratio in a structure stored thereon individually or in combination, causing the one or more when the instructions are executed by one or more processors The processor is configured to: provide a substrate on which the integrated circuit device is fabricated; and fabricate at least one structure on the substrate, wherein the fabrication ratio of the at least one structure is based on an internal dimension of the structure; Correcting the appearance of the production to the target appearance via angled planting ratio. The storage medium of claim 18, wherein the at least one structure is a magnetic tunneling junction. The storage medium of claim 18, further comprising instructions that, when executed by one or more processors, cause the one or more processors to: determine to reduce the appearance of the appearance based on the internal size Small enough that the target looks different than the required size. The storage medium of claim 18, wherein the angled implant comprises accelerating ions of the amorphized atom or molecule in the electric field at an angle of travel relative to the surface of the device such that the plasma strikes the at least one structure At least part. The storage medium of claim 21, wherein the production appearance ratio uniformly strikes the periphery of the at least one structure by the plasma to amorphize the material in the at least one structure and reduce the internal dimensions It was corrected to the appearance ratio of the target. The storage medium of claim 21, wherein the manufacturing appearance ratio causes at least a portion of the at least one structure to impinge a material in the at least one structure and reduce the internal dimensions by the plasma. Corrected to the target aspect ratio. The storage medium of claim 21, further comprising instructions that, when executed by one or more processors, cause the one or more processors to: determine to implant the plasma to cause the plasma At least one of the structural materials The angle of partial amorphization. The storage medium of claim 24, wherein the integrated circuit device comprises a plurality of structures fabricated on the substrate, and the angle is determined based on a height and an interval of the plurality of structures.