TW201719810A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

According to one embodiment, a semiconductor device includes a first insulating layer (13) on an underlying layer (11), a first trench (14a) formed in the first insulating layer (13), and a first graphene layer (23a) provided in the first trench (14a). The first trench (14a) comprises a bottom surface on the underlying (11) and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer (23a) has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer (23a) are each extended upward, which is in a direction opposite to the bottom surface.

Description

Semiconductor device and method of manufacturing same

The embodiments described herein relate broadly to semiconductor devices and methods of fabricating the same.

Graphene sheets, like carbon nanotubes, are innovative carbon materials that exhibit quantum conduction (ballistic conduction) and are attracting attention as an innovative low-resistance interconnect that replaces metal interconnects. Since the average free path of electrons in the graphene sheets is from about 100 nm to about 1 μm, the graphene sheets are highly advantageous for long-distance interconnection in terms of electrical conductivity. The graphene sheets are formed by a thermal reaction between the catalytic metal layer and the carbon layer. However, there has been a decrease in the conductivity of graphene sheets by about half when the catalytic metal contacts the surface of the graphene sheets. In these cases, it is necessary to have a graphene sheet with a low lightning resistance.

2-5‧‧‧ Structure

2-4‧‧‧ structure

2-3‧‧‧ structure

2-2‧‧‧ Structure

2-1‧‧‧ structure

10‧‧‧Semiconductor substrate

11‧‧‧Under

14-3‧‧‧Separating grooves

12‧‧‧First contact/through hole

14-2‧‧‧Separation groove

13‧‧‧First insulation

14-1‧‧‧Separation groove

14‧‧‧ Groove

14a‧‧‧ narrow groove

14b‧‧‧ wide groove

20‧‧‧Interconnect layer

20a‧‧‧thin interconnection

20b‧‧‧thick interconnection

21a‧‧‧First adhesion layer

21b‧‧‧Second adhesion layer

21‧‧‧Adhesive layer

21c‧‧‧ third adhesion layer

22a‧‧‧First carbon layer

22b‧‧‧Second carbon layer

22‧‧‧ Carbon layer

22c‧‧‧ third carbon layer

23a‧‧‧First graphene layer

23b‧‧‧Second graphene layer

23‧‧‧graphene layer

23c‧‧‧ Third graphene layer

24‧‧‧Separation layer

25‧‧‧Second insulation

26‧‧‧Second contact/through hole

30‧‧‧ catalyst layer

31‧‧‧ Masking layer

Fig. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment.

Figure 2 is a cross-sectional view taken along line II-II of Figure 1.

Figure 3 is a cross-sectional view showing a schematic structure of a semiconductor device according to a first embodiment.

Fig. 4 is an enlarged view of a portion indicated by a broken line in Fig. 2.

5 and 6 are cross-sectional views showing steps in the process of the semiconductor device according to the first embodiment, respectively.

Fig. 7 is a view showing the I-V characteristics of each of the first embodiment and the comparative example.

8, 9, and 10 are plan views showing schematic structures of a semiconductor device according to a second embodiment, respectively.

Figure 11 is a cross-sectional view taken along line XI-XI of Figures 8, 9 and 10.

Figure 12 is a cross-sectional view showing a schematic structure of a semiconductor device according to a second embodiment.

Figure 13 is a schematic view showing the steps of the process according to the first and second embodiments.

14 and 15 are cross-sectional views showing the process of the semiconductor device according to the second embodiment, respectively.

SUMMARY OF THE INVENTION AND EMBODIMENT

Generally, according to an embodiment, a semiconductor device includes a first insulating layer on a lower layer, a first trench formed in the first insulating layer, and a first graphene layer disposed in the first trench. The first groove includes a bottom surface on the lower surface and two side surfaces joined to the bottom surface, which are formed in a U shape. First A graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a recess in a central portion. Portions of the graphene sheets located at the edges of the first graphene layer each extend upwardly opposite to the direction of the bottom surface.

Embodiments will now be described with reference to the drawings.

(First Embodiment)

Fig. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. Figure 2 is a cross-sectional view taken along line II-II of Figure 1. The semiconductor device of this embodiment can be applied to the latest semiconductor integrated circuit.

As shown in the drawing, the semiconductor device according to the first embodiment includes: a semiconductor substrate 10 on which semiconductor devices such as transistors and capacitors are formed; a lower layer 11 formed on the semiconductor substrate 10; first contacts/vias 12, embedded in the lower layer 11; a first insulating layer 13 formed on the lower layer 11; a groove 14 formed in the first insulating layer 13, an interconnect layer 20 formed in the groove 14; and a second insulating layer 25. Formed on the first insulating layer 13; and the second contact/via 26 is embedded in the second insulating layer 25.

The semiconductor substrate 10 is, for example, a germanium semiconductor substrate. The lower layer 11 and the first and second insulating layers mainly contain an interlayer insulating layer of ruthenium oxide, tantalum nitride, voids, and the like. Each of the first and second contacts/vias 12, 26 is, for example, copper, aluminum, tungsten or an alloy containing one or more of these elements.

The groove 14 is selectively formed on the wiring pattern including the first and second contacts/vias 12, 26. The groove 14 includes a narrow groove 14a (first groove) having a groove width smaller than or equal to a predetermined width, and a wide groove 14b (second groove) having a groove width larger than a predetermined width.

The interconnect layer 20 is formed in the narrow recess 14a and includes a thin interconnect 20a (first interconnect) having a line width less than or equal to a predetermined width and a line formed in the wide recess 14b and having a width greater than a predetermined width Wide thickness interconnect 20b (second interconnect).

The thin interconnect 20a includes a first adhesion layer 21a, a first carbon layer 22a, and a first graphene layer 23a as an interconnect material having a line width less than or equal to a predetermined width. The thick interconnect 20b includes a second adhesion layer 21b, and a second carbon layer 22b like a second graphene layer 23b having an interconnect material having a line width greater than a predetermined width. However, when the first and second graphene layers 23a, 23b and the first insulating layer 13 (the narrow groove 14a and the wide groove 14b) exhibit excellent adhesion, the first and second adhesion layers 21a, 21b need not be provided. As shown in Figure 3. In the following description, the predetermined width is set to, for example, 10 nm.

Figure 4 is an enlarged view of a section indicated by a broken line in Figure 2.

The narrow groove 14a has a U shape composed of a bottom surface of the lower layer 11 (of the 14a) and first and second side surfaces connected to the bottom surface of the (14a). The first and second side surfaces are formed in the first insulating layer 13.

The first adhesion layer (bonding layer) 21a is formed in the narrow groove 14a along the first side surface, the bottom surface of (14a), and the second side surface Inside.

The first carbon layer 22a is formed on the first adhesion layer 21a.

The first graphene layer 23a is formed on the first carbon layer 22a and is in contact with the first carbon layer 22a. As for the first graphene layer 23a, at least a portion of the bottom surface of (of the 23a) is connected to the first carbon layer 22a, and at least a portion of the upper surface thereof is in contact with the second insulating layer 25.

The upper surface of the first graphene layer 23a includes a first edge at a central portion thereof at a left side higher than a central portion of the recess and a second edge at a right side higher than a central portion of the recess. A plurality of edge portions of the first graphene layer 23a included in the first and second edges extend in a direction of a U-shaped bottom surface of the relatively narrow groove 14a (i.e., upward toward the first and second insulating layers 13) , 25 stacking direction). With this configuration, many edge portions of the first graphene layer 23a are in contact with the second insulating layer 25 and the second contact/via 26 at the first and second edges. The second contact/via 26 fills the recess in the central portion of the first graphene layer 23a, and thus has a reverse convex configuration. Further, it is contemplated that the second contact/via 26 is in contact with the entire area of the edge of the first graphene layer 23a, but it may be in contact with only a portion thereof. For example, as shown in the drawing, one of the two edges of the first graphene layer 23a formed on both sides of the recess passing through the central portion of the first graphene layer 23a may be the second contact/through hole 26 All are covered, however the other edge may be partially covered by the second contact/through hole 26.

The edge of the first graphene layer 23a faces upwardly from the bottom surface of the relatively narrow groove 14a when the first carbon layer 22a contacting the catalyst is changed to the first graphene layer 23a as will be described later. In this way, it It becomes unnecessary to cut the edge of the first graphene layer 23a after the formation of the first graphene layer 23a. That is, the second contact/via 26 may be attached to the edge of the first graphene layer 23a without breaking the first graphene layer 23a. Therefore, the end of the second contact/via 26 and the edge of the first graphene layer 23a are directly connected to each other, and the contact resistance can be further reduced.

This illustration illustrates the narrow trench 14a and illustrates the thin interconnect 20a, but the wide trench 14b and the thick interconnect 20b are similar to the narrow trench 14a and the thin interconnect 20a. The first and second graphene layers 23a, 23b each have an ultrathin film stack structure in which one to about several tens of tabular graphene materials (graphene sheets) are stacked on each other.

Typically, graphene sheets exhibit a resistance that is very lower than the resistance of the metal interconnect when their line width is less than a predetermined width, for example, copper interconnect lines, due to the quantized conduction of electrons. Therefore, it is expected that the line width of the graphene sheets is set to be smaller than a predetermined width. Note that when the line width of the graphene sheets is a predetermined width or less, the resistance of the graphene sheets is substantially constant regardless of the line width of the graphene sheets.

The first and second adhesion layers 21a, 21b are provided to prevent the first and second graphene layers 23a, 23b from being separated from the first insulating layer 13 (the narrow groove 14a and the wide groove 14b) and also to make the first sum An auxiliary layer of a function in which the second graphene layers 23a, 23b are uniformly grown. The first and second adhesion layers 21a, 21b prevent the elements contained in the catalytic layer 30 (Fig. 6) from diffusing into the lower layer 11 and the first and second contacts/vias 12, 26, which will be described later. The first and second adhesion layers 21a, 21b are materials which do not easily change the band structure of the graphene sheets, for example, tantalum, titanium, tantalum, tungsten, aluminum, and one or more of these elements Nitride, chloride or oxide. The first and second adhesion layers 21a, 21b may have a multilayer structure in which layers containing one or more of these elements are stacked on each other. The first and second adhesion layers 21a, 21b may also contain dopants to be introduced to the first and second graphene layers 23a, 23b, for example, bromide, cobalt chloride, copper chloride, ferric chloride or these An alloy or carbide of metal. By introducing dopants into the first and second graphene layers 23a, 23b from the first and second adhesion layers 21a, 21b, it is possible to further reduce the electrical resistance of the first and second graphene layers 23a, 23b.

As shown, the edges of the first and second graphene layers 23a, 23b are opposite to the bottom surfaces of the narrow grooves 14a and the wide grooves 14b and from the uppermost surfaces of the first and second graphene layers 23a, 23b. Correct. With this configuration, it is easy to process (modify) the edge surfaces of the first and second graphene layers 23a, 23b. Therefore, the difference in the degree of modification between the first and second graphene layers 23a, 23b due to the difference in height therebetween can be reduced. In other words, it is possible to reduce variations in characteristics between the graphene sheets included in the first and second graphene layers 23a, 23b, so that desired electrical characteristics are easily obtained. When the change in height between the edges of the graphene sheets is reduced, it becomes possible to prevent the mixing of the edges of the low-resistance graphene sheets and the edges of the high-resistance graphene sheets. Therefore, the resistance can be reduced.

Here, processing (modification) on the edge surface is performed to improve the electron transport characteristics of the graphene sheet.

That is, the treatment (modification) on the edge surface is used to control the configuration of the edges of the graphene sheets, and more particularly, for example, adding some other elements to the edges of the graphene sheets.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 5a, 5b-1, 5b-2, 5c, FIGS. 6a, 6b, 6c and FIG.

The wide recess 14b and the thick interconnect 20b shown in Figs. 2 and 3 correspond to the structures 1-1 and 1-2 in Fig. 13. Structures 1-1 and 1-2 are formed through the first to fifth manufacturing steps.

In the first manufacturing step as shown in FIG. 5a, the lower layer 11 is formed on the semiconductor substrate 10 and the first contacts/vias 12 are embedded in the lower layer 11.

Next, as shown in FIG. 5b-1, after forming the first insulating layer 13 covering the first contact/via 12 on the lower layer 11, the narrow recess 14a and the wide recess 14b are each formed through a damascene process. It is desirable to form the narrow groove 14a and the wide groove 14b so as to be parallel to each other so as not to contact each other.

Next, in the second manufacturing step, after the adhesion layer 21 is formed in the narrow groove 14a and the wide groove 14b, the carbon layer 22 is formed on the adhesion layer 21. The adhesion layer 21 and the carbon layer 22 are formed by spin-on carbon (SoC), photoresist or the like by chemical vapor deposition (CVD). At this stage, the dopant introduced to the graphene may be mixed into the adhesion layer 21. However, as shown in FIG. 5b-2, the adhesion layer 21 does not need to exist.

Then, until the surface of the first insulating layer 13 is exposed, as shown in FIG. 5c, the adhesion layer 21 and the carbon layer 22 are polished by chemical mechanical polishing (CMP), wherein the chemical and mechanical effects cooperate with each other to form the first First and second adhesion layers 21a, 21b and first and second carbon Layers 22a, 22b.

Next, in a third manufacturing step, as shown in FIG. 6a, a catalytic layer 30 is formed on the first insulating layer 13 so as to cover the narrow groove 14a, the wide groove 14b, the first and second adhesion layers 21a, 21b, and First and second carbon layers 22a, 22b. The catalytic layer 30 is required to grow a layer of graphene. The catalytic layer 30 is formed in a form suitable for the first and second carbon layers 22a, 22b, thereby being closely attached to the surfaces of the first and second carbon layers 22a, 22b. The first and second carbon layers 22a, 22b each include a recess in the central portion, a first edge located to the left of the central portion of the recess, and a second edge located to the right of the central portion of the recess. The first and second edges are base points when the graphene layer 23 is grown. That is, the first and second edge portions of the first and second carbon layers 22a, 22b most tightly contact portions of the catalytic layer 30.

The catalytic layer 30 is made of, for example, a simple metal such as cobalt, nickel, iron, ruthenium or copper or an alloy, magnetic material or carbide containing one or more of these elements. In order to uniformly and continuously form the first and second graphene layers 23a, 23b, it is necessary to adjust the thickness of the catalytic layer 30 to a continuous film (for example, 0.5 nm or more).

Next, in a fourth manufacturing step, as shown in FIG. 6b, at least a portion of the first and second carbon layers 22a, 22b are heated (annealed) to interact with the catalytic layer 30 and converted into the first and second graphene layers 23a. 23b. The remaining portions of the first and second carbon layers 22a, 22b which do not interact with the catalytic layer 30 are held in the narrow groove 14a and the wide groove 14b. Therefore, the first and second graphene layers 23a, 23b are in contact with the first and second carbon layers 22a, 22b, respectively.

Next, in the fifth manufacturing step, as shown in FIG. 6c, the catalytic layer 30 is removed by a wet process or the like. Therefore, by arranging the removal of the catalytic layer 30 after the formation of the first and second graphene layers 23a, 23b, it is possible to form the first and second graphene layers 23a, 23b without the catalytic layer 30.

Finally, a second insulating layer 25 covering the narrow recess 14a, the wide recess 14b, the thin interconnect 20a and the thick interconnect 20b is formed on the first insulating layer 13, and the second contact/through hole 26 is embedded. In the second insulating layer 25. A diffusion preventing layer (diffusion barrier layer (not shown)) of tantalum nitride can be formed between the first insulating layer 13 and the second insulating layer 25, for example.

Thus, the semiconductor device of the first embodiment is completed.

Hereinafter, an example of a growth process of the first graphene layer 23a will be described.

First, the first graphene layer 23a is directed from the first edge (or the second edge) of the first carbon layer 22a in a direction parallel to the first side surface of the narrow groove 14a perpendicular to the film surface of the first insulating layer 13. The bottom surface of the narrow groove 14a is grown to form a first edge (first growth) of the first graphene layer 23a. Next, the first graphene layer 23a is grown parallel to the bottom surface of the narrow groove 14a (parallel to the film surface of the first insulating layer 13) to form a central portion (second growth) of the first graphene layer 23a. Finally, the graphene layer 23 grows in the direction of the bottom surface of the narrow groove 14a parallel to the second side surface (perpendicular to the film side surface of the first insulating layer 13) until it reaches the bottom surface of the narrow groove 14a. The second edge of the first carbon layer 22a forms a second edge (third growth) of the first graphene layer 23a.

Meanwhile, when the first growth and the third growth occur simultaneously, the first and second edges of the first graphene layer 23a are self-parallel to the first side surface of the narrow groove 14a (perpendicular to the film surface of the first insulating layer 13) The first and second ends of the first carbon layer 22a are grown until the bottom surface of the narrow groove 14a is reached and then they are grown parallel to the bottom surface of the narrow groove 14a (parallel to the film surface of the first insulating layer 13). To form a central portion (second growth) of the first graphene layer 23a. In other words, the two edges of the first graphene layer 23a (the first and second edges of the first graphene layer 23a) extending the two edges of the narrow groove 14a are joined together on the bottom surface of the narrow groove 14a to form the first A central portion of a graphene layer 23a.

Through such a growth process, the central portion of the first graphene layer 23a and the first and second edge portions are formed on the left side and the right side, respectively, and are formed through the center portion. A plurality of edge portions of the graphene layer 23 included in the first and second edges face upward in the stacking direction of the lower layer 11 and the first insulating layer 13. With this configuration, a plurality of edge portions of the first graphene layer 23a included in the first and second edges are in contact with the catalytic layer 30.

The growth process of the second graphene layer 23b is similar to the growth process of the first graphene layer 23a.

Fig. 7 shows current versus voltage (I-V) characteristics with respect to this embodiment and a comparative example. The broken line in the figure indicates the I-V characteristic of this embodiment, and the solid line indicates the I-V characteristic of the comparative example.

In this embodiment, a single layer structure of graphene sheets is used. On the other hand, in the comparative example, a stacked structure in which the graphene sheets are sandwiched between the metal elements contained in the catalytic layer 30 is used. Gold contained in the catalytic layer 30 The genus element is, for example, nickel, copper or the like.

In the comparative example, the graphene sheets were in contact with the metal elements contained in the catalytic layer 30, and thus the current value was much lower than that of the examples. Therefore, if the graphene sheet contacts the metal element contained in the catalytic layer 30, the electric resistance of the graphene sheet is greatly increased, and the current flowing through the graphene sheet is greatly reduced.

In this embodiment, the catalytic layer 30 is removed after forming the first and second graphene layers 23a, 23b, which makes it possible to obtain that the first and second graphene layers 23a, 23b are not in contact with the catalytic layer 30. This structure. By the removal of the catalytic layer 30, the process of the catalytic layer 30 can be skipped. Further, when the first and second adhesion layers 21a, 21b contain a dopant to be introduced to the graphene, the dopant may undesirably cause corrosion of the catalytic layer 30.

However, according to this embodiment, such a disadvantage can be overcome with the removal of the catalytic layer 30.

(Second embodiment)

Next, the second embodiment will now be explained. As in the first embodiment, the semiconductor device of this embodiment can be applied to the latest semiconductor integrated circuit. Note that the basic structure and manufacturing method of this embodiment are the same as the basic structure and manufacturing method of the first embodiment. Therefore, the description of the items already explained in the first embodiment will be omitted.

8, 9, and 10 are each a plan view showing a main structure of a semiconductor device according to a second embodiment. Figure 11 is a cross-sectional view taken along line XI-XI of Figure 8.

As shown in the figure, the catalytic layer 30 in the second embodiment is also removed from the inner side of the semiconductor device. Further, in the second embodiment, the spacer layer 24 is formed in the wide groove 14b to form a third graphene layer 23c having a line width smaller than a predetermined width of the wide groove 14b. One or more separator layers 24 may be provided to exit the first and second side surfaces of the wide groove 14b, respectively.

The partition layer 24 divides the wide groove 14b into a plurality of partition grooves having a groove width smaller than a predetermined width. Each of the separation grooves includes a bottom surface formed on the lower surface and two side surfaces joined to the bottom surface, formed in a U shape like the wide groove 14b.

When n (n 1) When the partition layer 24 is provided in the wide groove 14b, n+1 partition grooves are formed in parallel with each other in the wide groove 14b. For example, when n = 2, the wide groove 14b is divided into three dividing grooves 14-1, 14-2 and 14-3 by two partition layers 24. In each of the separation grooves, a third adhesion layer 21c (which may be omitted, see FIG. 12), a third carbon layer 22c, and a third carbon layer 22c are formed. The third graphene layer 23c is formed on the third carbon layer 22c and is in contact with the third carbon layer 22c. The third graphene layer 23c includes a central portion, a first edge on the left side of the central portion, and a second edge on the right side of the central portion.

The spacer layer 24 may be a conductive layer or an insulating layer as long as they are formed of a material that inhibits the formation of graphene on the surface of the spacer layer 24. As the spacer layer 24, for example, niobium, titanium, tantalum, tungsten, aluminum, tantalum, or a nitride or oxide of any of these materials can be used. When the low-resistance material uses the separation layer 24, it is possible to use the separation layer 24 as a low-resistance conductor layer. Furthermore, the spacer layer 24 may be the same as the adhesion layer 21 Material or hard masking material or similar material.

The spacer layer 24 and the third adhesion layer 21c may contain a dopant material to be introduced into the third graphene layer 23c. In this case, it is possible to dope the third graphene layer 23c with a dopant.

When the spacer layer 24 is a conductive layer, the third graphene layer 23c functions as the same interconnect. Likewise, when the third adhesion layer 21c is a conductive material, the third graphene layer 23c acts as an interconnection.

In the example in which both the spacer layer 24 and the third adhesion layer 21c are insulators, if the plurality of third graphene layers 23c are at least partially interposed in the wide recess 14b, as shown in FIGS. 8 and 9, the third graphene layer 23c acts as an interconnect.

Furthermore, if the third graphene layer 23c is completely isolated from the wide groove 14b, and the portion not in contact with each other in the third graphene layer 23c is as shown in FIG. 10, it is desirable that the spacer layer 24 and the third layer At least one of the adhesion layers 21c is a conductive material.

In this example in which the spacer layer 24 is an insulator, the spacer layer 24 and the first and second contacts/vias 12, 26 need to be configured to not block (cover) the first contact located below the spacer layer 24. /via 12 or a second contact/via 26 located above the spacer layer 24. For example, it is desirable that the first contact/through hole 12 be formed to overcome the spacer layer 24. In other words, it is desirable to form the third graphene layer 23c on the first contact/via 12 .

In the wide groove 14b, the plurality of third graphene layers 23c are formed in parallel with each other as a conductive layer, and the ratio of the side walls of the third graphene layer 23c The rate increases. Since the quantization of the side wall-based electrons of the third graphene layer 23c is the most activated region in the third graphene layer 23c, the electric resistance of the third graphene layer 23c is further lowered.

Hereinafter, a method of manufacturing the semiconductor device according to the second embodiment will now be described with reference to FIG. Note that the thin interconnection 20a in the narrow groove 14a is similar to that of the first embodiment, and a description thereof will be omitted. As in the first embodiment, the second embodiment provides two different structures depending on whether or not the third adhesion layer 21c is present. Moreover, the second embodiment provides two different structures depending on the timing at which the spacer layer 24 is formed.

In the figure, structures 2-1 and 2-2 and a separator layer 24 are formed after forming the second graphene layer 23b. In this example, a second graphene layer 23b formed on the entire inner surface of the wide groove 14b is divided into a plurality of third graphene layers 23c by the partition layer 24.

In the separation grooves 14-1 and 14-3 on the two edges of the wide groove 14b, the third graphene layer 23c is formed in the vicinity of the side surfaces of the separation grooves 14-1 and 14-3. Many of the edge portions extend in the direction of the opposite (114b upward) bottom surface. On the other hand, many of the edge portions of the third graphene layer 23c formed in the vicinity of the spacer layer 24 extend in the direction parallel to the bottom surface of the lateral direction of (14b). Many of the edge portions of the third graphene layer 23c formed in the remaining spacer layer 14-2 extend in a direction parallel to the bottom surface of the lateral direction of (14b).

The structures 2-1 and 2-2 can be fabricated by forming the second graphene layer 23b and removing the catalytic layer 30 in the first to fifth manufacturing steps described with respect to the first embodiment and then processing the spacer layer 24 in the sixth manufacturing Obtained by the steps.

The ends of the respective separation layers 24 may be formed on the lower layer 11 (on the bottom surface of the wide groove 14b) while passing through the second adhesion layer 21b or between the bottom surface of the wide groove 14b and the second adhesion layer 21b or On the second adhesion layer 21b.

Although there is an additional step of forming the spacer layer 24 as compared to the first embodiment, a step can be omitted by incorporating the step of forming the catalyst layer 30 into the second fabrication step. Note that as for the structure 2-2, the second manufacturing step does not form the second adhesion layer 21b.

As for the structures 2-3 to 2-5 shown in the drawing, unlike the examples of the structures 2-1 and 2-2, the spacer layer 24 is formed before the graphene layer 23 is formed. As in the examples of the structures 2-1 and 2-2, the structures 2-3 to 2-5 may have such a configuration in which the end of the partition layer 24 is formed on the lower layer 11 (on the bottom surface of the wide groove 14b) At the same time, it passes through the second adhesion layer 21b, either between the bottom surface of the wide groove 14b and the second adhesion layer 21b, or on the second adhesion layer 21b.

Although there is an additional step of forming the spacer layer 24 as compared to the first embodiment, a step can be omitted by incorporating the step of forming the catalyst layer 30 into the second fabrication step. Note that as for the structure 2-4, the second manufacturing step does not form the second adhesion layer 21b.

Furthermore, as for the structures 2-3 and 2-4, the second adhesion layer 21b and the second carbon layer 22b are formed before the formation of the separation layer 24, whereas with regard to the structure 2-5, the second adhesion layer 21b and the second carbon The layer 22b is formed after the formation of the spacer layer 24.

In the examples of structures 2-3 and 2-4, the second adhesion layer 21b And the second carbon layer 22b is formed in the wide groove 14b in the first and second manufacturing steps, and then the spacer layer 24 is formed in the sixth manufacturing step. Next, third to fifth manufacturing steps are performed to continuously form the third adhesion layer 21c, the third carbon layer 22c, and the third graphene layer 23c in the wide groove 14b.

In the example of structures 2-5, the wide recessed grooves 14b are formed in the first manufacturing step, and the rear separated layer 24 is formed in the sixth manufacturing step. Next, second to fifth manufacturing steps are performed to continuously form the third adhesion layer 21c, the third carbon layer 22c, and the third graphene layer 23c in the wide groove 14b. As for the structures 2-5, the spacer layer 24 is formed on the lower layer 11 (on the bottom surface of the wide groove 14b) before the second adhesion layer 21b is formed, and the side walls of the spacer layer 24 are covered with the third adhesion layer 21c.

Here, the manufacturing steps for structures 2-3 and 2-4 will be described with reference to Figs. 14 and 15a, 15b, 15c.

First, as in the first embodiment, the first and second adhesion layers 21a, 21b and the first and second carbon layers 22a, 22b are formed in the narrow groove 14a and the wide concave by the first and second manufacturing steps. In the groove 14b. In the second manufacturing step, a dopant introduced into the third graphene layer 23c may be introduced into the first and second adhesion layers 21a, 21b.

Next, as shown in FIG. 14, the masking layer 31 is formed on the first insulating layer 13, and the spacer layer 24 is formed in the sixth manufacturing step by patterning. In the sixth manufacturing step, a dopant introduced into the third graphene layer 23c may be introduced to the spacer layer 24. Here, as an example, the separation layer 24 is formed on the second adhesion layer 21b, but the separation layer 24 may be formed through the second The adhesion layer 21b is on the lower layer 11. As the spacer layer 24 is formed, the third adhesion layer 21c and the third carbon layer 22c are formed in the wide groove 14b.

Next, as shown in FIG. 15a, a catalytic layer 30 is formed on the first insulating layer 13 so as to cover the narrow groove 14a, the wide groove 14b, the first and second adhesion layers 21a, 21b, and the first and second carbon layers. 22a, 22b are in the third manufacturing step.

Next, as shown in FIG. 15b, the first and third graphene layers 23a, 23c are formed by annealing in a fourth fabrication step, and then the catalytic layer 30 is removed in a fifth fabrication step.

Next, as shown in FIG. 15c, a second insulating layer 25 is formed on the first insulating layer 13 and a second contact/via 26 is embedded in the second insulating layer 25 so as to cover the narrow recess 14a and the wide recess. The trench 14b, the first and third adhesion layers 21a, 21c, the first and third carbon layers 22a, 22c, and the interconnect structures of the first and third graphene layers 23a, 23c.

Further, a diffusion preventing layer (diffusion barrier) such as SiN (not shown) may be formed to cover the interconnect structure.

It is noted that the processes described herein are merely examples and may be modified in accordance with the interconnect structure.

As described above, it is also possible to form the graphene sheets in the second embodiment without leaving the catalytic layer 30 as in the first embodiment. Further, in the second embodiment, the separation layer 24 is provided for dividing the second graphene layer 23b having a line width larger than a predetermined width into the third graphene layer 23c having a line width smaller than a predetermined width. With this structure, it is possible to make the resistance of the thick interconnection 20b lower than that of the first embodiment.

Although a few embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. It is to be understood that the novel embodiments described herein may be embodied in a variety of other forms and embodiments of the invention may be practiced without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as are within the scope and spirit of the invention.

10‧‧‧Semiconductor substrate

11‧‧‧Under

12‧‧‧First contact/through hole

13‧‧‧First insulation

14‧‧‧ Groove

14a‧‧‧ narrow groove

14b‧‧‧ wide groove

20‧‧‧Interconnect layer

20a‧‧‧thin interconnection

20b‧‧‧thick interconnection

21a‧‧‧First adhesion layer

22a‧‧‧First carbon layer

23a‧‧‧First graphene layer

21b‧‧‧Second adhesion layer

22b‧‧‧Second carbon layer

23b‧‧‧Second graphene layer

25‧‧‧Second insulation

26‧‧‧Second contact/through hole

Claims (20)

A semiconductor device comprising: a first insulating layer on a lower layer; a first trench formed in the first insulating layer; and a first graphene layer disposed in the first trench, wherein the first recess a groove includes a bottom surface on the lower layer and two side surfaces joined to the bottom surface to form a U shape, the first graphene layer having a stacked structure including a plurality of graphene sheets each including a recess The central portion, and the portions of the graphene located at the edge of the first graphene layer, each extend upwardly in a direction opposite to the bottom surface. The semiconductor device of claim 1, further comprising: a first carbon layer disposed between the lower layer and the first graphene layer in the first trench, wherein the first graphene layer and the first A carbon layer is in contact with each other. The semiconductor device of claim 1, further comprising: a second insulating layer disposed on the first insulating layer and in contact with the plurality of graphene sheets located at the portion of the edge. The semiconductor device of claim 1, further comprising a first adhesion layer disposed along the bottom surface of the first groove and the two side surfaces. The semiconductor device of claim 3, further comprising: a second contact/via, disposed in the second insulating layer and located at the edge The plurality of graphene sheets are in contact with the portion, wherein the second contact/via has a reverse convex configuration to fill the recess. The semiconductor device of claim 1, wherein the first graphene layer contains a dopant. The semiconductor device of claim 6, wherein the dopant comprises bromine, cobalt chloride, copper chloride, iron chloride or an alloy or carbide containing one or more of these. The semiconductor device of claim 1, further comprising a second groove having a groove width greater than a predetermined width, the arrangement being parallel to the first groove in the first insulation layer, wherein the second groove comprises A bottom surface on the lower layer and two side surfaces joined to the bottom surface are formed in a U shape. The semiconductor device of claim 8, further comprising a second graphene layer disposed in the second trench and a stacked structure including a plurality of graphene sheets having a width greater than the predetermined width, wherein the plurality of graphenes The sheets each include a recessed in the central portion, and the graphene sheets at portions of the edges of the second graphene layer each extend upwardly opposite the direction of the bottom surface. The semiconductor device of claim 9, further comprising: a second carbon layer disposed between the lower layer and the second graphene layer in the second trench and having a width greater than the predetermined width, wherein The second graphene layer and the second carbon layer are in contact with each other. A semiconductor device as claimed in claim 8 wherein the pre- The fixed width is 10 nm. The semiconductor device of claim 8 further comprising: n spacer layers disposed in parallel with each other in the second groove; n+1 spacer grooves having a groove width smaller than or equal to the predetermined width, through The second trench is divided into the spacer trenches by the n spacer layers; the third graphene layers each have a line width less than or equal to the predetermined width and are respectively disposed in the n+1 partition recesses And a third carbon layer disposed between the n+1 third graphene layers and the lower layer and respectively in contact with the third graphene layers. A semiconductor device according to claim 12, wherein n is 2. The semiconductor device of claim 12, wherein the n+1 third graphene layers are partially in contact with each other in the second trench for acting as an interconnection. The semiconductor device of claim 12, wherein the n+1 separation grooves each include a bottom surface on the lower layer and two side surfaces joined to the bottom surface, which are formed in a U shape. The semiconductor device of claim 12, wherein the n+1 third graphene layers each have a stacked structure including a plurality of graphene sheets, each of the graphene sheets including a recessed portion at a central portion, and included in the n The plurality of graphene sheets of the portion of the edge of each of the +1 third graphene layers extend upwardly opposite to the direction of the bottom surface. The semiconductor device of claim 12, wherein in each of the (n+1) number of the third graphene layers, a portion located near the two side surfaces of the second groove The plurality of graphene sheets extend upwardly in a direction opposite to the bottom surface, and the remaining portion of the plurality of graphene sheets extend laterally in a direction substantially parallel to the bottom surface. The semiconductor device of claim 12, further comprising a first contact/via provided in the lower layer and electrically connected to the third carbon layers. A method of fabricating a semiconductor device, comprising: forming a first insulating layer on a lower layer; forming a first trench in the first insulating layer; forming a first carbon layer in the first trench; forming the first insulating layer a layer on the layer for covering the first carbon layer; forming a first graphene layer on the first carbon layer by heating to contact the first carbon layer; removing the catalytic layer; forming a second insulating layer The first insulating layer covers the first trench and the first graphene layer; and the second contact/via is formed in the second insulating layer. The manufacturing method of claim 19, further comprising: forming a second recess in the first insulating layer; and forming a second carbon layer in the second recess; wherein the first carbon layer and the first The two carbon layers are formed simultaneously.