TW201711032A - Memory device for resistance drift recovery and operating method thereof - Google Patents

Abstract

A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.

Description

Memory device for resisting drift recovery and operation method thereof

The present invention relates to a high density memory device based on a programmable resistive memory material and a method of operating the same.

In Phase Change Memory (PCM), each memory cell includes a phase change memory element. The phase change memory element is composed of a phase change material having a high resistance value comparison between a crystalline state (low resistance value) and an amorphous state (high resistance value). The phase change material may include an alloy material such as germanium (Ge), antimony (Sb), tellurium (Te), gallium (Ga), indium (In), silver (Ag), selenium (Se), germanium (TI), germanium. (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (Pb), sulfur (S), and gold (Au).

In the operation of the phase change memory element, the current pulse can set or reset the resistance state of the phase change memory element through the phase change memory cell. In order to reset the memory element to an amorphous state, a high amplitude, short time current pulse can be utilized to heat the active region of the memory element to a melting point temperature, which is then rapidly cooled to solidify in an amorphous state. In order to set the memory element to a crystalline state, a medium amplitude current pulse can be used to heat it to a crystallization temperature, and the active region is solidified in a crystalline state by cooling for a long time. To read the state of the memory element, a small voltage can be applied to the selected memory cell and the current result sensed.

The drift of the resistance value is a well-known phenomenon in PCM. The resistance value of the memory cell increases with time and follows the power relationship: where R ₀ is the initial resistance value at the initial time t ₀ , R(t) is the resistance value at time t > t ₀ , and γ is the resistance Drift coefficient.

In order to restore the resistance drift of the PCM memory device, one method uses a Dynamic Random-Access Memory (DRAM) refresh scheme to reprogram multiple Multiple Levels of Cells (MLC) PCM memory cells. Status. In DRAM memory cells, the charge stored in the storage capacitor is gradually dissipated through the access transistor. Therefore, in order to maintain the integrity of the data, the data values stored in the DRAM memory cells must be periodically read out and stored again to their individual complete voltage levels before the stored charge decays to an indistinguishable level. quasi. DRAM refresh requires different actions for different logic levels, and the number of actions required is equal to the number of logic levels.

However, using a DRAM-like refresh scheme to recover the resistance value drift in a PCM memory device is time consuming and consumes tolerance, especially for MLC PCM devices. For example, for a 256 megabit (Mega-Bit, Mb) PCM wafer, the estimated refresh time for the entire wafer can be calculated as follows: where the verification time for MLC memory cell programming is ignored. Therefore, the refresh time alone (for example, 11.5 seconds) accounts for approximately 13.4% of the entire refresh interval (for example, 86 seconds), and the refresh interval is set to the time when the error is generated.

In addition, with DRAM-like refresh, the tolerance is degraded by the periodic refresh. For single-level cell (SLC) memory cells, the total tolerated loss in 10 years can be estimated as follows:

For MLC memory cells, the total tolerated dose in 10 years can be estimated as follows:

Another disadvantage of DRAM-like refresh is the inability to correct the wrong memory cell resistance level. If a memory cell drifts to an error state, the DRAM-like refresh will simply reprogram the memory cell to an error state. Therefore, for the sake of conservatism, the refresh interval of the DRAM-like refresh is shorter than the time when the error is generated (for example, 86 seconds). As shown in FIG. 1B, the first error state occurs during the period. Therefore, a shorter refresh interval will simultaneously reduce performance and increase the loss of tolerance.

Therefore, there is a need to provide an MLC PCM device that can restore the resistance value drift without the performance and tolerance loss caused by DRAM-like refresh.

The present invention describes a resistance value drift recovery process for a phase change memory having a multi-level memory cell. This process reduces losses, delays, and power consumption compared to a DRAM-like refresh scheme. This processing is not like a DRAM-like refresh scheme, and different restoration processing is required for individual resistance value levels. As described herein, at least one reset pulse applied to the stylized memory cell can be independent of the data value of the stylized memory cell.

A method of operating a memory device, the memory device comprising an array of memory cells, the memory cell array comprising a plurality of programmable resistive memory elements. By applying a plurality of stylized pulses to the memory cells, a resistance level is established in a specified range of N resistance values, thereby stabilizing the memory cells in the array to store data, wherein each resistance value specified range corresponds to A specific data value. Performing a resistance value drift recovery process on the memory cells in the array, comprising: applying a recovery pulse having a pulse waveform to a stylized memory cell group, wherein the memory cells in the set of stylized memory cells are applied with the pulse The recovery pulse of the waveform has a resistance level in a specified range of two or more resistance values. The resistance value drift recovery process can be interrupted in response to an external command.

The N specified ranges include a high resistance range and a low resistance range. In the high resistance range, the memory cell includes an active region having a first volume of amorphous material, and in the low resistance range, the memory cell An active region having a second volume of amorphous material is included, the second volume being less than the first volume. The pulse waveform is used to bring the temperature of the active region of the memory cell in the range of high resistance values above a melting point and to cause the temperature of the active region of the memory cell in the range of low resistance values to be lower than the melting point. The N resistance value specification ranges may include one or more intermediate resistance value ranges, and in the one or more intermediate resistance value ranges, the memory cell includes an amorphous state having a volume between the first volume and the second volume The active region of the material, the one or more intermediate resistance values ranging between a range of high resistance values and a range of low resistance values. The number N can be greater than 2, and the memory cells in the stylized memory cell group have resistance value levels in the specified range of the N resistance values.

The method can include applying a set of recovery pulses to the memory cells in the memory cell group, including a first restoration pulse having a first pulse waveform and a second restoration pulse having a second pulse waveform corresponding to the memory cell group The middle memory cell determines the resistance level. The first pulse waveform may be the same as or different from the second pulse waveform.

The method may include reading a memory cell in the memory cell group to determine a resistance level of the memory cell in the memory cell group, and applying a recovery pulse to the memory cell at the determined resistance value level in the memory cell group, the recovery pulse The pulse waveforms each correspond to a determined resistance value level. The method can include reading a memory cell in the memory cell group to determine a resistance level of the memory cell in the memory cell group, and applying the memory cell in the memory cell group at two or more determined resistance value levels A recovery pulse of the same pulse waveform. The method may include applying a recovery pulse having the same pulse waveform to a memory cell having a plurality of resistance values in the memory cell group, without first reading the memory cell in the memory cell group to determine the memory cell in the memory cell group. The resistance value level.

A memory device provided in accordance with the method is also described herein.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Detailed descriptions of embodiments of the present technology are provided with illustrations. It is understood that the present technology is not limited to the specific disclosed embodiments and methods, and may be implemented by other features, elements, methods and embodiments. The preferred embodiments are described to illustrate the technology, but are not intended to limit the scope of the scope of the claims. A variety of equivalent variations described below will be apparent to those of ordinary skill in the art. Similar elements in these embodiments use the same element numbers.

Figure 1A shows the experimental results of the resistance drift coefficient of a multi-level cell (MLC) memory cell in a range. FIG. 1B illustrates the distribution of resistance values after resistance drift for four resistance value targets (eg, 100 k ohms, 200 k ohms, 400 k ohms, 800 k ohms, where k ohms represent kilo ohms) for PCM memory cells. The resistance value distribution of a resistance value target (eg, 100k ohm, 200k ohm, 400k ohm, 800k ohm) varies with time at the lower limit (eg, 110, 120, 130, and 140) and the upper limit (eg, 115, 125, 135, and 145) between. At time = 1 second, approximately 20% of the edge of the resistance value exists between adjacent resistance value distributions. When the resistance value of the memory cell increases with time, the distribution of the resistance values becomes wider, and the edge of the resistance value between adjacent resistance value distributions decreases.

Each resistance value distribution represents a logical level of the MLC PCM memory cell. If the resistance value distribution is sufficiently wide, a dynamic reference can be utilized to distinguish between the two resistance value distributions representing the two logic levels of the MLC PCM memory cell. In the memory cell life cycle, the difficulty of placing a dynamic reference between the two resistance values of the memory cell increases with the widening of the resistance value distribution, because the edge of the resistance value between the two resistance values will be in the life of the memory cell. Reduced during the cycle. As in the example shown in FIG. 1B, at the time when the error is generated = 86 seconds, the lower limit of the resistance value distribution 140 for the resistance value target 800 k ohm and the upper limit 135 of the resistance value distribution for the resistance value target 400 k ohm are overlapped. As a result, it is impossible to distinguish the logic level represented by the resistance value distribution of the resistance value target of 800 k ohms and 400 k ohms.

Similarly, at the time when the error occurs, the lower limit of resistance value distribution 130 for the resistance value target 400 k ohm and the upper limit 125 of the resistance value distribution for the resistance value target 200 k ohm overlap. As a result, it is impossible to distinguish the logic level represented by the resistance value distribution of the resistance value target 400k ohm and 200k ohm. At the time when the error occurs, the lower limit of the resistance value distribution 120 for the resistance value target 200 k ohm and the upper limit 115 of the resistance value distribution for the resistance value target 100 k ohm overlap. As a result, it is impossible to distinguish the logic level represented by the resistance value distribution of the resistance value target 200k ohm and 100k ohm.

Figures 2A, 2B, 2C, 2D, and 2E show two states under resistance drift. The vertical axis represents the ratio R(t)/R ₀ , where R ₀ is the initial resistance value at the initial time t ₀ , and R(t) is the resistance value at the time t > t0. The horizontal axis represents the time when the resistance value drifts, and its scale is log. 2A, 2B, 2C, 2D, and 2E are plotted and measured for the set state at an annealing temperature of 85 ⁰ C, 125 ⁰ C, 150 ⁰ C, 180 ⁰ C, and 200 ⁰ C. data of.

As shown in these figures, the resistance value drift includes a drift phase and a subsequent decay phase. The maximum resistance value R _max and the corresponding time t _max appear at the transition between the drift phase and the decay phase. As shown in Figures 2A and 2B, at relatively low temperatures (e.g., 85 ⁰ C and 125 ⁰ C), the resistance drift is dominated by the drift phase. For example, as shown in Figure 2A, at 85 ⁰ C, the resistance value drift based dominated by phase drift. As shown in Figure 2B, at 125 ⁰ C, the decay phase begins approximately at time = 10 ^6.7 seconds.

As shown in Figures 2C and 2D, at intermediate temperatures (e.g., 150 ⁰ C and 180 ⁰ C), the drift phase ends and the decay phase begins at time _tmax , while the maximum resistance value _Rmax occurs at time _tmax . When the temperature increases, t _{max is} shortened. For example, as shown on FIG. 2C, at 150 ⁰ C, and attenuated phase drift phase ends at time = 10 starting from about ^5.3 seconds. As shown in FIG. 2D, at 180 ⁰ C, and attenuated phase drift phase ends at time = 10 starting from about ^3.8 seconds. As shown on FIG. 2E, at 200 ⁰ C, and attenuated phase drift phase ends at time = 10 starting from about ^3.2 seconds, and thus dominate the decay phase drift resistance.

FIG. 3 illustrates an exemplary flow chart 300 for performing a resistance drift recovery process on one or more sets of memory cells of the memory cell array in the memory device. The array can include a plurality of memory cells, each of the blocks can include a plurality of memory cell pages, and each page in a block can include a plurality of memory cells. A group of memory cells used herein may be a block of memory cells, a multi-block memory cell, a page of memory cells in a block, a multi-page memory cell in a block, or two or more blocks. Multi-page memory cells or combinations thereof.

In step 310, by applying a plurality of stylized pulses to the memory cells, a plurality of resistance value levels are established in the N resistance value specified ranges, thereby stabilizing the memory cells in the array to store data, wherein each specified range Corresponds to a specific data value. The N specified ranges include a high resistance range and a low resistance range. In the high resistance range, the memory cell includes an active region having a first volume of amorphous material, and in the low resistance range, the memory cell An active region having a second volume of amorphous material is included, the second volume being less than the first volume.

The N specified ranges include one or more intermediate resistance value ranges, and in the one or more intermediate resistance value ranges, the memory cell includes an amorphous material having a volume between the first volume and the second volume. An active region, wherein the one or more intermediate resistance value ranges are between a high resistance value range and a low resistance value range. The value N can be greater than two, and the memory cells in a set of stylized memory cells have resistance values in the N specified ranges.

At step 320, it is determined whether the resistance drift recovery process is triggered for one or more sets of memory cells. The resistance drift recovery process can be triggered, for example, periodically, for example, for a period of 50 seconds, or triggered in response to an event. The event may be, for example, when the memory device switches from the standby mode to the startup mode, when an error is detected by an Error Correcting Code (ECC) mechanism, or when at least a portion of the memory cells in the array reach a specified drift resistance valve When the value is.

When the event occurs, the resistance drift recovery process can be taken immediately, or if more urgent work is to be performed on the memory device, it can be scheduled to a later time, which is controlled by the memory device. The system is determined. When the resistance drift recovery process needs to be performed on multiple sets of memory cells, the system can prioritize execution based on the degree of urgency of the data. For example, for memory cells that are more severe than other groups, the priority will be prioritized. Perform resistance drift recovery processing. The system can also prioritize the implementation of resistance drift recovery processing based on which sets of memory cells have data that are more important than other sets of memory cells. For example, when the system power is turned on, the boot code is typically accessed first, so the resistance drift recovery process is prioritized for the boot code.

If one or more sets of memory cells are determined to trigger a resistance drift recovery process, then at step 330, a determination is made as to whether an interrupt or suspend instruction has been received from an external source of the memory device. If an interrupt or pause command has been received, the resistance drift recovery process will be stopped and can be resumed after the resistance drift recovery process is triggered again.

If an interrupt or pause command has not been received, then at step 340, a resistance value wrap recovery process is performed on the memory cells in the array. The resistance value drift recovery process includes applying a reset pulse having a pulse waveform to a set of programmed memory cells, wherein the memory cells in the set of stylized memory cells have a specified range of two or more resistance values The resistance value level. The pulse waveform is used to make the temperature of the active region of the memory cell in the high resistance range higher than a melting point. For further description, please refer to the figures 7A, 7B and 7C, and make the active region of the memory in the low resistance range. The temperature is lower than the melting point. For further description, please refer to Figures 6A, 6B and 6C. For a further description of the pulse waveform, please refer to Figures 12A and 12B. For a further description of the resistance value drift recovery process, please refer to Figure 4 and Figure 5.

After performing a resistance value drift recovery process on a group of memory cells, resistance value drift recovery processing may be performed on more groups of memory cells until an interrupt or pause instruction is received from an external source of the memory device, or until the completion of the The resistance value of one or more sets of memory cells is drifted and restored.

FIG. 4 illustrates an exemplary flow diagram 400 for performing a resistance value drift recovery process on a set of memory cells in a memory cell array, which corresponds to block 340 in FIG. At step 410, the memory cell lines in a set of stylized memory cells are read to determine the resistance level of the memory cells in the group. For example, the determined resistance value level may be within the resistance range before restoration (eg, 813, 823, 833), or an upper limit (eg, 5000 k ohms) beyond the sensing range (eg, 840), As shown in Figure 8.

In steps 420-450, a reset pulse is applied to the memory cells in the set at the determined resistance level, and the individual pulse waveforms of the reset pulses correspond to the determined resistance level. For example, the recovery pulses A, B, and (N-2) can be applied to the memory cells at the determined resistance level A, level B, and level (N-2), respectively. The recovery pulse (N-1) can be applied to the memory cell at the determined resistance level (N-1) and N.

The pulse waveform of the recovery pulse can vary its current amplitude and length of time corresponding to the determined resistance value level. For example, the recovery pulses A, B, (N-2), and (N-1) may have pulse waveforms of 50uA-30ns, 80uA-30ns, 80uA-50ns, and 100uA-50ns, where uA is labeled microampere. Ns represents nanosecond. For a further description of the pulse shape of the recovery pulse, please refer to Figures 12A and 12B.

A recovery pulse having the same pulse waveform can be applied to the memory cells of the group at two or more determined resistance values. For example, as shown in FIG. 4, a reset pulse having the same pulse waveform (for example, a reset pulse (N-1)) can be applied to the determined resistance level (N-1) and level N. Memory cell. For example (not depicted in Figure 4), a recovery pulse (e.g., recovery pulse B) having the same pulse waveform can be applied to a memory cell at a determined resistance level A and level B. For example (not shown in Figure 4), a recovery pulse (e.g., recovery pulse B) having the same pulse waveform can be applied to the determined resistance level A, level B, and level (N-1). ) memory cells. Therefore, for the reset pulse applied to the stylized memory cell group, the number of different pulse waveforms is less than the number of resistance value levels at which the memory cell is programmed.

FIG. 5 is a flow chart 500 showing an example of performing a resistance value drift recovery process on a group of memory cells in a memory cell array, which corresponds to block 340 in FIG. In step 510, a reset pulse having the same pulse waveform, such as a reset pulse of 80uA-50ns, can be applied to a memory cell in a stylized memory cell group at a plurality of resistance value levels without first reading. The memory cells in the group determine the resistance level of the memory cells in the group. Thus, the at least one reset pulse applied to the stylized memory cell can be independent of the data value of the stylized memory cell, wherein the data values are represented by the resistance level of the stylized memory cell. The recovery pulse having the same pulse waveform is applied to the memory cells located at a plurality of resistance value levels. The experimental results of the resistance value drift recovery processing are described with reference to the eighth, 9, 10, 11A, 11B, 11C, and 11D. , 11E and 11F maps.

Table 1 below shows the difference in thermal conductivity between amorphous and crystalline GST (GeSbTe), excerpted from Ciocchini, N.; Palumbo, E.; Borghi, M.; Zuliani, P.; Annunziata, R.; Ielmini D. et al., "Modeling Resistance Instabilities of Set and Reset States in Phase Change Memory With Ge", published in the journal Electron Devices, IEEE Transactions on , vol.61, no.6, pp.2136, 2144, June 2014 -Rich GeSbTe" literature.

The face-centered cubic (fcc) crystalline state and the hexagonally close-packed (hcp) crystalline state have greater thermal conductivity than the amorphous GST.

The lower thermal conductivity of amorphous GST helps capture more heat and increase memory cell temperature. This allows a portion of the amorphous region to be melted with a weaker stylized pulse (e.g., 80 uA / 30 ns) to achieve resistive drift recovery of the amorphous region. On the other hand, for crystalline GST memory cells, the higher thermal conductivity allows heat to be dissipated through large volumes without the memory cell temperature being high enough to reach a critical melting point.

FIG. 6A illustrates that the memory cell includes a memory element having an active region, and the active region includes a crystalline material. The memory element can, for example, comprise a GST (GeSbTe) material. The memory cell has a first electrode 611 extending through the medium 612, a memory element 613 comprising a crystalline material, and a second electrode 614 on the memory element 613. For example, the memory element 613 may have a height of 100 nm (nano) and a width of 100 nm. The first electrode 611 is coupled to one end of an access device (not shown), and the access device is like a diode or a transistor. The second electrode 614 is coupled to the bit line and may be part of the bit line (not shown). The width of the first electrode 611 may be smaller than the width of the second electrode 614 and the memory element 613, which establishes a small contrast region between the phase change material body and the first electrode 611, and is between the phase change material body and the second electrode 614. A relatively high ratio region is established to achieve a high current density with a small current absolute value through the memory element 613. Because of this small contrast region at the first electrode 611, the current density is maximized in the region adjacent to the first electrode 611 during operation, resulting in a "skull" active region 615 as shown in FIG. 6A. This smaller contrast zone can be referred to as a heater (e.g., 620) because the high current density in the smaller contrast zone can produce high temperatures. For example, the heater has a height of about 10 nm.

In this example, a reset pulse having a pulse waveform of 80uA-30ns is applied to a memory cell including a memory element including an active region having a crystalline material.

Figure 6B illustrates a temperature profile 640 through the center of memory element 613, including through the center of active region 615 having a crystalline material, as indicated by dashed line 630. Temperature profile 640 is based on thermal simulation of memory cells including memory element 613. As shown in FIG. 6B, at about 10 nm from the beginning of the vertical distance of the memory element 613, the temperature in the heater 620 is stopped at about 300 ⁰ K, and rises to about 500 ⁰ K at a vertical distance of the memory element 613 of about 40 nm. The memory element 613 is lowered back to about 300 ⁰ K at a vertical distance of about 100 nm. Since the melting point 650 is approximately 600 ⁰ K, and the recovery pulse having a pulse waveform of 80 uA - 30 ns is a weak pulse, it is not sufficient to raise the temperature of the active region having the crystalline material beyond the melting point 650.

Figure 6C is a heat map corresponding to the memory elements of Figures 6A and 6B. As shown in FIG. 6C, the active region having the crystalline material in the memory element has a vertical distance along the height of between about 30 nm and 40 nm, a horizontal distance along the width of between about 45 nm and 60 nm, and a temperature of about 500 ⁰ K. And below the melting point of 600 ⁰ K.

FIG. 7A illustrates a memory cell including a memory element including an active region having an amorphous material. Similar elements in Fig. 7A are referred to using similar reference numerals in Fig. 6A. The description of the memory cell in conjunction with Figure 6A is generally applicable to Figure 7A.

In this example, a reset pulse having a pulse waveform of 80uA-30ns is applied to a memory cell including a memory element including an active region having a crystalline material. The pulse waveform of 80uA-30ns is the same as the recovery pulse applied to the memory cell including the active region having the crystalline material as described in FIG. 6A.

Figure 7B illustrates a temperature profile 740 through the center of memory element 613, including through the center of the active region (e.g., 715) having an amorphous material, as indicated by dashed line 630. Temperature profile 740 is based on thermal simulation of memory cells including memory element 613. As shown on FIG. 7B, the memory device 613 starts the vertical distance of about 10nm, the temperature of the heater 620 is stopped at about 300 ⁰ K, and increased to about 700 ⁰ K at about 20nm memory element 613 from the vertical, and in The memory element 613 is lowered back to about 300 ⁰ K at a vertical distance of about 100 nm.

Since the melting point 650 is approximately 600 ⁰ K, a recovery pulse having a pulse waveform of 80 uA - 30 ns raises the temperature of the active region having the amorphous material beyond the melting point between about 15 nm and 25 nm along the vertical distance of the height. In contrast, a recovery pulse having a pulse waveform of 80 uA - 30 ns is not sufficient to raise the temperature of the active region having a crystalline material above the melting point 650.

Figure 7C is a heat map corresponding to the memory elements of Figures 7A and 7B. As shown in FIG. 7C, the active region having the amorphous material in the memory element has a temperature between about 15 nm and 25 nm along the vertical distance of the height, and a horizontal distance along the width of between about 35 nm and 65 nm exceeds the melting point.

Fig. 8 is a graph showing experimental results of resistance drift recovery using an example of a recovery pulse having a pulse waveform of 80 uA to 30 ns. Three sets of resistance values are shown, with each set including an initial range, a pre-recovery range, and a post-recovery range. For example, the time between the initial range and the pre-recovery range is 3 days. The arrows for these three groups indicate the range of resistance values generated by the resistance value drift recovery processing. In each group, the post-recovery range (eg, 812, 822, and 832) is closer to the initial range (eg, 811, 821, and 831) than the pre-recovery range (eg, 813, 823, and 833). The fourth set of resistance values ranges from the upper limit of the sensing range (eg, 5000 k ohms) to a vertical line (eg, 840) because the range of resistance values in the fourth set exceeds the upper limit of the sensing range of the memory device. Each of the four sets of resistance values corresponds to a specific data value of an MLC memory cell. For example, a fourth-order memory cell can include data values 00, 01, 11, and 10.

Figure 9 shows that the error resistance level of the memory cell can be corrected by the resistance value drift recovery process, which uses an example of a recovery pulse having a pulse waveform of 80 uA - 30 ns. Similar elements in Fig. 9 are referred to using similar reference numerals in Fig. 8.

As shown in the example of Fig. 9, the erroneous resistance level occurs at the overlap of the pre-recovery range (e.g., 823) in the second set of resistance values and the third set of resistance values (e.g., 831, 832, 833). As indicated by circle 920, and those erroneous resistance levels are corrected in the restored range of the second set of resistance values (e.g., 822) such that the second set of resistance values are in the restored range (e.g., 822). ) does not overlap with the third set of resistance values.

The erroneous resistance level occurs in the third set of resistance values before the pre-recovery range (eg, 833) at least partially beyond the upper limit of the sensing range, as indicated by circle 930, and those erroneous resistance levels are corrected The post-recovery range (eg, 832) in the third set of resistance values ranges such that the post-recovery range (eg, 832) in the third set of resistance values is below the upper limit of the sensing range.

In contrast, through the DRAM-like refresh scheme, the wrong resistor value level will be reprogrammed to the same error resistor level instead of being corrected.

Figure 10 is a diagram showing the first error in the experimental data with and without the resistance value drift recovery process described herein, wherein the resistance value drift recovery process uses a recovery pulse having a pulse waveform of 80 uA - 30 ns. . If the resistance value drift recovery process is not used, the first error occurs in 5000 seconds. In contrast, if the resistance value drift recovery process is used, the first error occurs on the 140th day, and the overall improvement is 2400 times. The resistance value ranges for the periods (1), (2), (3), (4), (5), and (6) are shown in the 11A, 11B, 11C, 11D, 11E, and 11F, respectively.

11A, 11B, 11C, 11D, 11E, and 11F are diagrams showing the resistance value drift recovery corresponding to the periods (1), (2), (3), (4), (5), and (6) in FIG. The experimental results were processed using an example of a recovery pulse having a pulse waveform of 80 uA - 30 ns. The periods (1), (2), (3), (4), (5), (6) generally correspond to 30, 1, 600, 7,000, 16,000, 30,000, and 60,000 kiloseconds, respectively.

The three sets of resistance values are as shown in Fig. 11A, wherein each group includes an initial range, a pre-recovery range, and a post-recovery range. The first set of resistance ranges in the three groups corresponds to a low resistance value range, which includes an initial range 1111 corresponding to the image shown above FIG. 11A and between about 10k ohms and 20k ohms in the lower graph. The pre-recovery range 1113 in the lower graph and the post-recovery range 1112 in the upper graph.

Similarly, the second set of resistance ranges in the three groups corresponds to an intermediate resistance value range including an initial range 1121 corresponding to between about 50 k ohms and 200 k ohms, which is shown above the 11A map and in the lower graph. The pre-recovery range 1123 shown in the lower figure and the post-recovery range 1122 shown in the upper figure are shown. The third set of resistance ranges in the three groups corresponds to a high resistance value range, which includes an initial range 1131 corresponding to between about 500 k ohms and 2000 k ohms, which is shown above the 11A map and in the lower graph. The pre-restoration range 1133A in the lower graph and the post-recovery range 1132A in the upper graph.

In general, the range of resistance values caused by the resistance value drift recovery process causes the restored range to move toward the initial range compared to the pre-recovery range. The first set of resistance values exhibits less movement than the second set of resistance values and the third set of resistance values. The fourth set of resistance values ranges from the upper limit of the sensing range (eg, 5000 k ohms) to a vertical line (eg, 1140) because the range of resistance values in the fourth set exceeds the upper limit of the sensing range of the memory device.

As shown in the lower diagram of Figure 11A, the erroneous resistance level can occur in the third set of resistance values before the pre-recovery range (e.g., 1133A) at least partially beyond the upper limit of the sensing range, as indicated by circle 1150A. As shown in the upper graph of Figure 11A, those erroneous resistance levels are corrected in the restored range of the third set of resistance values, such that the restored range (eg, 1132A) in the third set of resistance values is lower than The upper limit of the sensing range.

Similarly, as shown in the lower diagram in FIG. 11B, the erroneous resistance level may occur in the third set of resistance values before the pre-recovery range (eg, 1133B) at least partially beyond the upper limit of the sensing range, such as a circle frame. 1150B is shown. As shown in the upper graph of Figure 11B, those erroneous resistance levels are corrected in the restored range of the third set of resistance values such that the restored range (e.g., 1132B) in the third set of resistance values is lower than The upper limit of the sensing range.

As shown in the lower diagram of FIG. 11C, the erroneous resistance level may occur in the third set of resistance values in the pre-restoration range (eg, 1133C) at least partially beyond the upper limit of the sensing range, as indicated by circle 1150C. . As shown in the upper graph of Figure 11C, those erroneous resistance levels are corrected in the post-recovery range of the third set of resistance values, such that the post-recovery range (eg, 1132C) in the third set of resistance values is lower. The upper limit of the sensing range.

As shown in the lower diagram in Figure 11D, the erroneous resistance level may occur in the third set of resistance values before the pre-recovery range (eg, 1133D) at least partially beyond the upper limit of the sensing range, as indicated by circle 1150D. . As shown in the upper graph of Figure 11D, those erroneous resistance levels are corrected in the restored range of the third set of resistance values such that the restored range (eg, 1132D) in the third set of resistance values is lower than The upper limit of the sensing range.

For periods longer than 140 days (5) and (6) as shown in the lower panel of Figures 11E and 11F, the wrong resistance level can occur in the pre-recovery range of the fourth set of resistance values (eg 1143E and 1143F). ) at least partially beyond the upper limit of the sensing range, as indicated by circle 1150E and 1150F. With reference to the 2A, 2B, 2C, 2D and 2F diagrams, the erroneous resistance level can also occur in the pre-recovery range (eg 1143E and 1143F) in the fourth set of resistance values due to the attenuation phase in the resistance drift. An area that is partially within the sensing range but overlaps the third set of resistance values. As shown in the upper graph of Figures 11E and 11F, the erroneous resistance level will not be corrected during the period of more than 140 days (5) and (6).

Thus, the 11A, 11B, 11C, 11D, 11E, 11F diagram illustrates that the first error occurs within 140 days when the resistance value drift recovery process described herein is employed, as compared to the absence of this description. When the resistance value drift recovery process, the first error occurred in 5000 seconds, resulting in a 2400-fold improvement.

Figures 12A and 12B illustrate pulse waveforms of a recovery pulse suitable for use in the resistance value drift recovery process described herein. For example, the pulse waveform may include a rectangular pulse waveform (e.g., 1210), a ramp-up pulse waveform (e.g., 1220), and an L-type pulse waveform (e.g., 1230), as shown in Fig. 12A. The pulse waveform can be defined by parameters including voltage magnitude, current magnitude, power magnitude, temperature magnitude, or length of time.

A rectangular pulse waveform (eg, 1210) can transition from a low amplitude (eg, 1211) to a high amplitude (eg, 1212) at a rising edge (eg, 1213) and from a high amplitude to a low amplitude at a falling edge (eg, 1214), And there is a length of time between the rising edge and the falling edge (such as 1215). Rectangular pulse waveforms may, for example, have different current amplitude and time length variations: 50uA-30ns, 80uA-30ns, 80uA-50ns, and 100uA-50ns, where uA represents microamperes and ns represents nanoseconds. In practice, recovery pulses with different pulse waveforms can be applied to memory cells at different determined resistance levels.

A triangular pulse waveform (eg, 1220) can transition from a low amplitude (eg, 1221) to a high amplitude (eg, 1222) on a rising slope (eg, 1223), and then transition from a high amplitude to a low amplitude at a falling edge (eg, 1224) . The length of the triangular pulse waveform (eg, 1225) may include the rise time of the rising ramp and the fall time of the falling edge. The rise time can be substantially longer than the fall time and can include at least 50% of the triangular pulses.

In the example of Fig. 12B, in the resistance value drift recovery processing, a set of reset pulses includes a reset pulse having a first pulse waveform (e.g., 1210), and a second reset pulse having a second pulse waveform can be applied to the memory. The cell, wherein the second pulse waveform corresponds to a determined resistance level of the memory cells in the group. The first pulse waveform may be the same or different from the second pulse waveform in amplitude and/or length of time.

For example, the first pulse waveform (eg, 1210) can be as depicted in FIG. 12A, and the second pulse waveform (eg, 1240) can be a rectangular pulse waveform. The second pulse waveform (eg, 1240) can transition from a low amplitude (eg, 1211) to a high amplitude (eg, 1242) at a rising edge (eg, 1243) and transition from a high amplitude to a low amplitude at a falling edge (eg, 1244) And has a length of time between the rising edge and the falling edge (such as 1245).

For example, both the first pulse waveform and the second pulse waveform may include 50uA-30ns or 100uA-50ns. Alternatively, the first pulse waveform and the second pulse waveform may include 80uA-30ns and 80uA-50ns, respectively, or 80uA-50ns and 100uA-50ns, respectively. In practice, the first and second reset pulses having different pulse waveforms can be applied to memory cells located at different determined resistance levels.

Figure 13 shows an example of setting, resetting, reading, and restoring pulses for phase change memory cells. The recovery pulse can be used in the resistance value drift recovery process described herein. Reset, set, reset, and read pulses (eg, 1310, 1320, 1330, and 1340, respectively) may be described by parameters including voltage, current, or power magnitude and length of time. In order to compare the pulses applied to different types of memory cells, the set, reset, read, and reset pulses shown begin at time zero. In write (eg, set or reset), read, and wander recovery operations, set, reset, read, and reset pulses are applied at different times. As used herein, the term "stylized pulse" may refer to a reset pulse applied to a memory cell to reset the memory cell to an amorphous state, and applied to a memory cell to set the memory cell to a crystalline state. Set pulse.

The reset pulse may have an amplitude lower than the reset pulse and higher than the read pulse, and has a length of time shorter than the reset pulse and longer than the read pulse. For example, the amplitude of the healing pulse can be less than half of the reset pulse and have a length of time that is about one-fifth of the set pulse. The description of the recovery pulse can be further combined with the 6A, 6B, 6C, 7A, 7B and 7C diagrams.

In the operation of a memory cell including a phase change memory element, the resistance state of the phase change memory element can be set or reset by an electrical pulse of the memory cell. To reset the memory element to an amorphous state, a high-amplitude, short-time reset pulse (such as 1310) can be used to heat the active region of the memory element to a melting point temperature (eg, 1350), followed by rapid cooling. Cured in an amorphous state. To set the memory element to a crystalline state, a medium amplitude set pulse (e.g., 1320) can be used to heat it to a crystallization temperature (e.g., 1360) and the active region is allowed to solidify in a crystalline state by prolonged cooling. To read the state of the memory element, a small amplitude, short time read pulse (e.g., 1340) can be applied to the selected memory cell and the current result sensed.

For example, the reset pulse can have a current amplitude (eg, 1335) between 50uA and 100uA and a length of time between 30ns and 50ns (eg, T2). The set pulse can have a current amplitude (eg, 1325) between 100 uA and 200 uA and a length of time between 100 ns and 500 ns (eg, T4). The reset pulse can have a current amplitude of about 400 uA (such as 1315) and a length of time between 50 ns and 100 ns (such as T3). The read pulse can have a current amplitude of about 30 uA (such as 1345) and a time length of about 50 ns (such as T1).

Figure 14 is a simplified block diagram of a memory device (e.g., 1400). The memory device includes an array of memory cells (e.g., 1460), the memory cells including programmable resistive memory elements. In some embodiments, array 1460 can include multiple SLCs. In some embodiments, array 1460 can include multiple MLCs.

Memory device 1400 includes a controller (e.g., 1410) coupled to the array. Controller 1410 is implemented, for example, by a state machine that can provide signals to control the power supply bias configuration generated or provided by voltage supply or block 1420 to perform various different operations, including writing, reading, and wiping memory cells. In addition to drifting recovery operations. The controller can be implemented using conventional special purpose logic circuits. In an alternate embodiment, the controller includes a general purpose processor that can be implemented on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, a special purpose logic circuit and a general purpose processor can be used to implement the controller.

The controller 1410 is configured to program the memory cells in the array, and store the data by applying a stylized pulse to the memory cells to establish a resistance value level in a specified range of the N resistance values, wherein each specified range corresponds to a specific data value, and the control is performed. The device 1410 performs a resistance value drift recovery process on the memory cells in the array, including applying a recovery pulse having a pulse waveform to the stylized memory cell group, wherein the memory cell in the stylized memory cell group is applied with a recovery pulse having a pulse waveform. , so that its resistance value level is within the specified range of two or more resistance values. The resistance value drift recovery process can be interrupted in response to an external command, such as an instruction from an external source of the memory device 1400.

The N specified ranges include a high resistance range and a low resistance range. In the high resistance range, the memory cell includes an active region having a first volume of amorphous material, and in the low resistance range, the memory cell An active region having a second volume of amorphous material is included, the second volume being less than the first volume. The pulse waveform is used to bring the temperature of the active region of the memory cell in the range of high resistance values above a melting point and to cause the temperature of the active region of the memory cell in the range of low resistance values to be lower than the melting point. The N resistance value specification ranges may include one or more intermediate resistance value ranges, and in the one or more intermediate resistance value ranges, the memory cell includes an amorphous state having a volume between the first volume and the second volume The active region of the material, the one or more intermediate resistance values ranging between a range of high resistance values and a range of low resistance values. The number N can be greater than 2, and the memory cells in the stylized memory cell group have resistance value levels in the specified range of the N resistance values.

The controller 1410 can be configured to apply a reset pulse group to the memory cells in the memory cell group, including a first reset pulse having a first pulse waveform and a second reset pulse having a second pulse waveform corresponding to the memory cell The memory cell in the group determines the resistance level. The first pulse waveform may be the same as or different from the second pulse waveform.

The controller 1410 can be used to read the memory cells in the memory cell group to determine the resistance level of the memory cells in the memory cell group, and to apply a recovery pulse to the memory cells in the memory cell group at the determined resistance value level. The pulse waveforms of the pulses each correspond to a determined resistance value level. The controller 1410 can be used to read the memory cells in the memory cell group to determine the resistance level of the memory cells in the memory cell group, and to apply to the memory cells in the memory cell group at two or more determined resistance value levels. A recovery pulse having the same pulse waveform. The controller 1410 can be used to apply a recovery pulse having the same pulse waveform to the memory cells in the memory cell group at a plurality of resistance value levels, without first reading the memory cells in the memory cell group to determine the memory cells in the memory cell group. The resistance value level.

The at least one reset pulse described herein can be independent of the data value of the stylized memory cell.

In some embodiments, the memory array can include multiple SLCs. In other embodiments, array 1460 can include multiple MLCs. The word line decoder 1440 is coupled to the plurality of word lines 1445 arranged in columns in the memory array 1460. Bit line decoder 1470 is coupled to memory array 1460 via global bit line 1465. The global bit line 1465 is coupled to logical bit lines (not shown) arranged in a row in the memory array 1460. The address on bus 1430 is provided to bit line decoder 1470 (row address) and word line decoder 1440 (column address). The sensing circuit/data input structure in block 1480 includes voltage and/or current sources for operations such as writing, reading, erasing, and resistance drift recovery processing, coupled to the bit line through the data bus 1475 Decoder 1470. Through line 1485, the data is provided to other circuits 1490 on the integrated circuit, such as a general purpose processor or a special purpose application circuit, or a system on chip (system-on-a) supported by the memory device 1400. -chip) Function module combination. Other circuits 1490 may, for example, include input/output ports.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

110, 120, 130, 140‧‧‧ lower limit
115, 125, 135, 145 ‧ ‧ upper limit
R _max ‧‧‧maximum resistance
t _max ‧‧‧ time
300, 400, 500‧‧‧ flow chart
310, 320, 330, 340, 410, 420, 430, 440, 450, 510 ‧ ‧ steps
611‧‧‧first electrode
612‧‧‧Media
613‧‧‧ memory components
614‧‧‧second electrode
615, 715‧‧ ‧ active area
620‧‧‧heater
630‧‧‧ dotted line
640, 740‧‧ ‧ temperature profile
650‧‧‧ melting point
812, 822, 832, 1112, 1122, 1132A, 1132B, 1132C, 1132D‧‧‧Recovered range
813, 823, 833, 1113, 1123, 1133A, 1133B, 1133C, 1133D, 1143E, 1143F‧‧‧
811, 821, 831, 1111, 1121, 1131 ‧ ‧ initial range
840, 1140‧‧ vertical lines
920, 930, 1150A, 1150B, 1150C, 1150D, 1150E, 1150F‧‧‧ circle
(1), (2), (3), (4), (5), (6) ‧ ‧ hours
1210‧‧‧Rectangular pulse waveform
1211, 1221‧‧‧ low amplitude
1212, 1222, 1242‧‧‧ high amplitude
1213, 1243‧‧‧ rising edge
1223‧‧‧Uphill
1214, 1224, 1244‧‧‧ falling edge
1215, 1225, 1245‧‧ ‧ length of time
1220‧‧‧ oblique pulse waveform
1230‧‧‧L type pulse waveform
1240‧‧‧second pulse waveform
1310‧‧‧Reset pulse
1320‧‧‧Set pulse
1330‧‧‧Recovery pulse
1340‧‧‧Read pulse
1350‧‧‧ melting point temperature
1360‧‧ crystallization temperature
1315, 1325, 1335, 1345‧‧‧ Current amplitude
T1, T2, T3, T4‧‧‧ length of time
1400‧‧‧ memory device
1410‧‧‧ Controller
1420, 1480‧‧‧ squares
1430‧‧‧ Busbar
1440‧‧‧ character line decoder
1445‧‧‧ character line
1460‧‧‧ memory array
1465‧‧‧Global bit line
1470‧‧‧ bit line decoder
1475‧‧‧ data bus
Line 1485‧‧
1490‧‧‧Other circuits

FIG. 1A illustrates the resistance value drift coefficient of the MLC PCM memory cell in a range of resistance values. Figure 1B shows the distribution of resistance values after the PCM memory cell drifts with time. Figures 2A, 2B, 2C, 2D, and 2E show two states under the drift of the resistance value. FIG. 3 is a flow chart showing an example of performing a resistance value drift recovery process on one or more sets of memory cells of the memory cell array in the memory device. FIG. 4 is a flow chart showing an example of performing a resistance value drift recovery process on a group of memory cells in a memory cell array, wherein recovery pulses having different pulse waveforms are used. FIG. 5 is a flow chart showing an example of performing a resistance value drift recovery process on a group of memory cells in a memory cell array, wherein a recovery pulse having the same pulse waveform is used. Figure 6A illustrates a memory cell having a memory element that includes an active region having a crystalline material. Fig. 6B is a view showing a temperature profile passing through the center of the memory element corresponding to Fig. 6A. Figure 6C is a heat map corresponding to the memory elements of Figures 6A and 6B. FIG. 7A illustrates a memory cell including a memory element including an active region having an amorphous material. Fig. 7B is a view showing a temperature profile passing through the center of the memory element corresponding to Fig. 7A. Figure 7C is a heat map corresponding to the memory elements of Figures 7A and 7B. Fig. 8 is a graph showing experimental results of recovery of resistance value drift using an exemplary recovery pulse. Figure 9 shows that the error resistance level of the memory cell can be corrected by the resistance value drift recovery process. Figure 10 illustrates the first error in the experimental data with and without the resistance value drift recovery process described herein. 11A, 11B, 11C, 11D, 11E, and 11F are diagrams showing the resistance value drift recovery corresponding to the periods (1), (2), (3), (4), (5), and (6) in FIG. Process the experimental results. Figures 12A and 12B illustrate pulse waveforms of a recovery pulse suitable for use in the resistance value drift recovery process described herein. Figure 13 shows an example of setting, resetting, reading, and restoring pulses for phase change memory cells. Figure 14 is a simplified block diagram of the memory circuit.

300‧‧‧ Flowchart

310, 320, 330, 340‧ ‧ steps

Claims (15)

A method of operating a memory device, the memory device comprising an array of a plurality of memory cells, the method comprising: applying a plurality of stylized pulses to the memory cells to establish a plurality of resistance values in a specified range of N resistance values Leveling, thereby stabilizing the memory cells in the array to store data; and performing a resistance value drift recovery process on the memory cells in the array, comprising: applying a reset pulse having a pulse waveform to a The group of stylized memory cells, wherein the memory cells in the set of stylized memory cells have resistance level levels in at least two of the specified ranges of resistance values. The method of claim 1, wherein the N resistance value specification ranges include a high resistance value range and a low resistance value range, and in the high resistance value range, the memory cells include a first An active region of a volume of amorphous material, wherein the memory cells comprise an active region having a second volume of amorphous material, the second volume being smaller than the first volume, and the pulse The waveform is used to cause the temperature of the active regions of the memory cells in the high resistance range to be higher than a melting point, and to cause the temperature of the active regions of the memory cells in the low resistance range Below this melting point, where N is greater than 2. The method of claim 2, wherein the N resistance value specification ranges include one or more intermediate resistance value ranges, and in the one or more intermediate resistance value ranges, the memory cells include a volume And an active region of the amorphous material between the first volume and the second volume, the one or more intermediate resistance values ranging between the high resistance value range and the low resistance value range, wherein N is greater than 2. The method of claim 1, further comprising: applying a set of recovery pulses, the set of recovery pulses comprising the reset pulse having the pulse waveform and a second reset pulse having a second pulse waveform, the The two pulse waveform corresponds to a determined resistance level of a memory cell in the set of stylized memory cells. The method of claim 1, further comprising: reading the memory cells in the set of stylized memory cells to determine a resistance level of the memory cells in the set of stylized memory cells; A plurality of restoration pulses are applied to the memory cells of the set of stylized memory cells at the determined resistance level, and the pulse waveforms of the restoration pulses respectively correspond to the determined resistance value level. The method of claim 1, further comprising: reading the memory cells in the set of stylized memory cells to determine a resistance level of the memory cells in the set of stylized memory cells; A plurality of reset pulses are applied to the memory cells of the set of stylized memory cells at the plurality of determined resistance value levels, the reset pulses having an identical pulse waveform. The method of claim 1, comprising: applying a plurality of restoration pulses to the memory cells of the set of stylized memory cells at a plurality of resistance value levels, the restoration pulses having an identical pulse waveform. A memory device comprising: an array of a plurality of memory cells having a programmable resistive memory element; and a controller coupled to the array by applying a plurality of stylized pulses to the memory cells, Establishing a plurality of resistance value levels in the specified range of the N resistance values, thereby stabilizing the memory cells in the array to store data, and performing a resistance value drift recovery processing on the memory cells in the array The resistance value drift recovery process includes: applying a reset pulse having a pulse waveform to a set of stylized memory cells, wherein the memory cells in the set of stylized memory cells have at least two of the resistance values The resistance value level is specified in the specified range. The memory device of claim 8, wherein the N resistance value specification ranges include a high resistance value range and a low resistance value range, and the memory cells in the high resistance value range include a first An active region of a volume of amorphous material, the memory cells in the low resistance range comprising an active region having a second volume of amorphous material, the second volume being smaller than the first volume, and the pulse waveform The temperature of the active regions of the memory cells in the high resistance range is higher than a melting point, and the temperature of the active regions of the memory cells in the low resistance range is low. At the melting point, wherein N is greater than 2. The memory device of claim 9, wherein the N resistance value specified ranges include one or more intermediate resistance value ranges, and the memory cells in the one or more intermediate resistance value ranges include a volume An active region of the amorphous material between the first volume and the second volume, the one or more intermediate resistance values ranging between the high resistance value range and the low resistance value range, wherein N is greater than 2. The memory device of claim 8, wherein the controller is configured to apply a set of reset pulses, the set of reset pulses including the reset pulse having the pulse waveform and a second reset pulse having a second pulse waveform The second pulse waveform corresponds to a determined resistance level of a memory cell in the set of stylized memory cells. The memory device of claim 8, wherein each of the resistance value specified ranges corresponds to a specific data value. The memory device of claim 8, wherein the controller is configured to: read the memory cells in the set of stylized memory cells to determine resistance values of the memory cells in the set of stylized memory cells; And applying a plurality of resetting pulses to the memory cells of the set of stylized memory cells at the determined resistance level, the pulse waveforms of the restored pulses respectively corresponding to the determined resistance value level. The memory device of claim 8, wherein the controller is configured to: read the memory cells in the set of stylized memory cells to determine resistance values of the memory cells in the set of stylized memory cells; And applying a plurality of reset pulses to the memory cells of the set of stylized memory cells at the plurality of determined resistance value levels, the reset pulses having an identical pulse waveform. The memory device of claim 8, wherein the controller is configured to apply a plurality of recovery pulses to the memory cells of the set of stylized memory cells at a plurality of resistance levels, the restoration pulses having the same pulse Waveform.