TW201707325A - Surge protection circuit comprising a power input terminal, a first transistor, a NOT gate, a AND gate, a first electrical potential converter, a base control unit and a power output terminal - Google Patents

Abstract

The invention relates to a surge protection circuit, comprising a power input terminal, a first transistor, a NOT gate, an AND gate, a first electrical potential converter, a base control unit and a power output terminal; the invention controls the base control unit through a logic circuit composed of the NOT gate and the AND gate. When there is no surge voltage, the base of the first transistor is electrically connected to the drain of the first transistor for forming a forward bias diode so as to directly transmit power voltage received by the power input terminal to the power output terminal. When there is a surge voltage, the base of the first transistor is electrically connected to the source of the first transistor for forming a reverse bias diode so as to cause a non-conducting first transistor to avoid the surge voltage being transmitted to the power output terminal. It can protect an interior circuit electrically connected the power output terminal from being damaged by the surge voltage.

Description

Surge protection circuit

The invention is a protection circuit, especially a surge protection circuit.

The integrated circuit (IC) inside the existing mobile electronic device is mostly supplied with a low voltage as a power source, such as a voltage of 5 volts (V) or 3.3 volts (V). When the power of the mobile electronic device is exhausted, for the sake of convenience, the manufacturer designs the existing commercial power supply, so that the user can directly connect to a utility outlet to obtain electric energy by using one of the mobile electronic devices. And the charger converts the 110V voltage of the commercial power supply into a 5V voltage, and then charges the mobile electronic device with the 5V voltage.

When the charger of the mobile electronic device is electrically connected to the mains power supply, a surge voltage is generated, that is, a high voltage of about 20V is generated instantaneously, and the surge voltage enters the mobile electronic device. In the integrated circuit inside the device, the integrated circuit is damaged. Therefore, if the surge voltage cannot be effectively removed, there is a high risk of damage when the mobile electronic device is charged.

In the prior art, a high voltage resistant metal oxide semiconductor field effect transistor (MOSFET) is used in an integrated circuit inside the mobile electronic device to withstand the surge voltage, and a Zener diode is used to eliminate the Surge voltage. However, the high voltage resistant MOSFET requires more layout area than the low voltage MOSFET. Therefore, when the MOSFET in the integrated circuit uses the high voltage resistant MOSFET, the overall area of the circuit design is greatly increased, so that the integrated circuit is The area increases, which in turn affects the layout of other circuits. Using the Zener diode to eliminate the surge voltage increases the cost of the integrated circuit. Therefore, the prior art method of eliminating the surge voltage still needs further improvement.

In view of the fact that the method for eliminating the surge voltage in the prior art causes an increase in the overall area of the integrated circuit, and the use of the Zener diode causes an increase in cost, the present invention provides a surge protection circuit that further reduces the overall size of the integrated circuit. Area, and the Zener diode is not needed to further save costs.

In order to achieve the above object, the surge protection circuit of the present invention comprises: a power input terminal for receiving a power source; a first transistor having a drain, a source, a gate and a base, the drain Electrically connected to the power input end; wherein the first transistor is an N-type metal oxide semiconductor field effect transistor (NMOS); a reverse gate has a reverse gate input terminal and a reverse gate output terminal, the reverse gate The input terminal serves as a surge detection signal input terminal, and receives a surge detection signal. The first gate has a first input terminal, a second input terminal and a gate output terminal, and the first input terminal serves as a uniform energy end. Receiving a uniform energy signal, the second input terminal is electrically connected to the reverse gate output terminal; a first potential converter having a high potential input terminal, a low potential input terminal, a control terminal and an output terminal, the high The potential input end is electrically connected to the power input end, the low potential input end is electrically connected to the source of the first transistor, the control end is electrically connected to the sluice output end, and the output end is electrically connected to the first electric The gate of the crystal; where the control terminal When the potential is at a high level, the high potential input terminal is electrically connected to the output end, and when the potential of the control terminal is a low level, the low potential input terminal is electrically connected to the output end; a base control a unit electrically connected to a base, a drain, a source, and a gate output end of the first transistor; wherein when the potential of the gate output is at a high level, the base is electrically connected to the gate a pole, when the potential of the output of the gate is a low level, controlling the base to be electrically connected to the source; and a power output end electrically connected to the source of the first transistor.

The invention uses the enable signal received by the enable terminal and the surge detection signal received by the surge detection signal input terminal as a judgment basis, and controls the gate potential of the first transistor to be electrically connected to the base. a drain or the source to further control conduction between the drain and the source of the first transistor. When a surge voltage is generated, the gate of the first transistor is electrically connected to the source without being turned on, and when no surge voltage is generated, the gate of the first transistor is electrically connected to the drain and turned on, and When no surge voltage is generated, the base of the first transistor is electrically connected to the drain to form a forward biased diode, thereby enabling the first transistor to conduct more current. The power output terminal is further electrically connected to an internal circuit of an electronic device. When the electronic device is charged, the power of the power source is received through the power input terminal, and after passing through the surge protection circuit of the present invention, the power supply is Power is delivered to the power output. In this way, through the arrangement of the present invention, the surge voltage can be prevented from being transmitted to the power output end, thereby ensuring that the internal circuit of the electronic device does not receive the surge voltage, and in the internal circuit The use of low-voltage electronic components to reduce the overall area of the circuit design, and the present invention does not need to provide a Zener diode, can save production costs.

The technical means adopted by the present invention for achieving the intended purpose are further explained below in conjunction with the drawings and preferred embodiments of the present invention.

Referring to FIG. 1 , the present invention is a surge protection circuit 10 . The first preferred embodiment of the surge protection circuit 10 includes a power input terminal I/P1 , a first transistor MN1 , and a reverse gate 11 . And a gate 12, a first potential converter 13, a base control unit 14, and a power output O/P1.

The power input terminal I/P1 receives a power source (not shown). The first transistor MN1 has a drain, a source, a gate and a body, and the drain is electrically connected to the power input terminal I/P1. The source is electrically connected to the power output O/P1. In the preferred embodiment, the first transistor MN1 is an N-type metal oxide semiconductor field effect transistor (NMOS).

The reverse gate 11 has a reverse gate input terminal and a reverse gate output terminal, and the reverse gate input terminal serves as a surge detection signal input terminal I/P3 to receive a surge detection signal. The sluice 12 has a first input end, a second input end and a sluice output end. The first input end serves as a uniform energy end I/P2 for receiving a uniform energy signal, and the second input end is electrically connected to The reverse gate output.

The first potential converter 13 has a high potential input terminal (HIN), a low potential input terminal (LIN), a control terminal (CON) and an output terminal (OUT). The high-potential input terminal is electrically connected to the power input terminal I/P1, the low-potential input terminal is electrically connected to the source of the first transistor MN1, and the control terminal is electrically connected to the gate output terminal, and the output terminal is electrically Connected to the gate of the first transistor MN1. When the potential of the control terminal is at a high level, the first potential converter 13 controls the high potential input terminal to be electrically connected to the output terminal. When the potential of the control terminal is at a low level, the first potential converter 13 controls the low potential input terminal to be electrically connected to the output terminal.

The base control unit 14 is electrically connected to the base, the drain, the source of the first transistor MN1 and the AND gate output of the AND gate 12. When the potential of the damper output is at a high level, the base control unit 14 controls the base to be electrically connected to the drain. When the potential of the damper output is at a low level, the base control unit 14 controls the base to be electrically connected to the source.

The enable signal and the surge detection signal are generated by a controller (not shown) of an external circuit (not shown), and the controller detects whether the voltage of the power source received by the power input terminal I/P1 exceeds a start. The voltage or a protection voltage, and the protection voltage is greater than the startup voltage.

When the power supply voltage does not reach the startup voltage, it represents that the surge protection circuit 10 of the present invention has not been activated. Therefore, the enable signal and the surge detection signal are both a low voltage level, and the reverse gate 11 and the The logic circuit of the gate 12 outputs a low potential from the AND gate output terminal to the first potential converter 13 and the base control unit 14. Therefore, the first potential converter 13 controls the low potential input terminal to be electrically connected to the output terminal, so that the gate of the first transistor MN1 is electrically connected to the source, and the base control unit 14 controls the base electrical connection. To the source. At this time, according to the NMOS principle, the NMOS is an N-type semiconductor, the base is a P-type semiconductor, and the source is an N-type semiconductor. When the base is electrically connected to the source, the first transistor MN1 forms a diode. Body, but the current flow when the first transistor MN1 is turned on flows from the drain to the source, and therefore, a reverse bias is applied to the diode formed by the first transistor MN1, and The gate is electrically connected to the source such that the gate-source voltage V _GS of the first transistor is zero, so the first transistor MN1 is not turned on.

When the power supply voltage exceeds the startup voltage but does not reach the protection voltage, it represents that the surge protection circuit 10 of the present invention is activated but no surge voltage is generated. Therefore, the enable signal is a high level potential, but the burst The wave detection signal is a low voltage level, and the logic circuit of the gate 11 and the gate 12 passes through the gate output terminal to output a high potential to the first potential converter 13 and the base control unit 14. Therefore, the high potential input terminal is electrically connected to the output terminal through the first potential converter 13, so that the gate of the first transistor MN1 is electrically connected to the drain, and the base control unit 14 controls the base electrode. Connect to the bungee. At this time, according to the NMOS principle, the NMOS is an N-type semiconductor, the base is a P-type semiconductor, and the source is an N-type semiconductor. When the base is electrically connected to the drain, the first transistor MN1 forms a diode. And the current flowing when the first transistor MN1 is turned on flows from the drain to the source, and therefore, directly turns on the diode formed by the first transistor MN1 by applying a forward bias And because the gate is electrically connected to the drain, the gate-source voltage V _{GS of} the first transistor MN1 is greater than 0, further increasing the drain current of the first transistor MN1, allowing the power source The supply voltage of the input terminal I/P1 can be directly supplied to the power supply output terminal O/P1 as much as possible.

When the power supply voltage exceeds the protection voltage, the surge protection circuit 10 of the present invention is activated and a surge voltage is generated. Therefore, the enable signal and the surge detection signal are both at a high voltage level, and the reverse gate is passed. 11 and the logic circuit of the gate 12, the gate output terminal outputs a low potential to the first potential converter 13 and the base control unit 14. Therefore, when the power supply voltage does not reach the starting voltage, the gate-source voltage V _GS of the first transistor MN1 is 0, so the first transistor is not turned on.

According to the above principle, the present invention turns on the first transistor MN1 to turn on the power received by the power input terminal I/P1 to the power output terminal O only when the power supply voltage exceeds the startup voltage but does not reach the protection voltage. /P1 is used to supply an internal circuit of an electronic device. When a surge voltage is generated, the gate of the first transistor MN1 is electrically connected to the source and the base of the first transistor MN1 is electrically connected to the source, forming a reverse biased diode without being turned on. . When no surge voltage is generated, the gate of the first transistor MN1 is electrically connected to the drain and turned on, and the base of the first transistor MN1 is electrically connected to the drain to form a forward biased diode. The body, in turn, enables the first transistor MN1 to conduct more current. The power output terminal O/P1 is an internal circuit electrically connected to the electronic device. When the electronic device is charged, the power of the power source is received through the power input terminal I/P1, and passes through the surge protection circuit of the present invention. After 10, the power of the power source is transmitted to the power output terminal O/P1. In this way, through the arrangement of the present invention, the surge voltage can be prevented from being transmitted to the power output end, thereby ensuring that the internal circuit of the electronic device does not receive the surge voltage, and in the internal circuit The use of low-voltage electronic components to reduce the overall area of the circuit design, and the present invention does not need to provide a Zener diode, can save production costs.

Referring to FIG. 2, the second preferred embodiment of the surge protection circuit 10 of the present invention further includes a charge pump 15, a second potential converter 16, and a first embodiment. Two transistors MN2.

The charge pump 15 has a boost input terminal and a boost output terminal, and the boost input terminal is electrically connected to the power input terminal I/P1. The high potential input of the first potential converter 13 is directly electrically connected to the boost output terminal and is not electrically connected to the power supply input terminal I/P1. The charge pump 15 is provided by first boosting the power supply voltage received by the power input terminal I/P1, and outputting the boost output terminal to the high potential input terminal of the first potential converter 13. In this way, when the power supply voltage exceeds the startup voltage but does not reach the protection voltage, the high potential input end of the first power converter 13 is electrically connected to the output terminal, and is further electrically connected to the first transistor MN1. The gate of the first transistor MN1 further increases the gate voltage of the first transistor MN1 and increases the gate-source voltage V _{GS of} the first transistor MN1. Therefore, the first transistor MN1 can be fully turned on for the maximum current that the first transistor MN1 can withstand, so that the power supply voltage of the power input terminal I/P1 can reduce the loss as much as possible. Directly supplied to the power supply output O/P1.

The second transistor MN2 has a drain, a source, a gate and a body, and the source of the second transistor MN2 is electrically connected to the power output. The terminal O/P1, the base of the second transistor MN2 is electrically connected to the source of the second transistor MN2. The source of the first transistor MN1 is directly electrically connected to the drain of the second transistor MN2, and is not electrically connected to the power output terminal O/P1. In the preferred embodiment, the second transistor MN2 is an N-type metal oxide semiconductor field effect transistor (NMOS).

The second potential converter 16 has a high potential input terminal (HIN), a low potential input terminal (LIN), a control terminal (CON) and an output terminal (OUT). The high potential input end of the second potential converter 16 is electrically connected to the high potential input end of the first potential converter 13, the low potential input end is electrically connected to the source of the second transistor MN2, and the control terminal is electrically Connected to the gate output, the output is electrically connected to the gate of the second transistor MN2. When the potential of the control terminal of the second potential converter 16 is at a high level, the second potential converter 16 controls the high potential input terminal of the second potential converter 16 to be electrically connected to the second potential converter 16 Output. When the potential of the control terminal of the second potential converter 16 is at a low level, the second potential converter 16 controls the low potential input end of the second potential converter 16 to be electrically connected to the second potential converter 16 Output.

By further arranging the second transistor MN2 and the second potential converter 16, the power input terminal I/P1 of the surge protection circuit 10 and the power output terminal O/P1 are transmitted through the first transistor MN1. Electrically connected to the second transistor MN2, when the first transistor MN1 and the second transistor MN2 are not conducting, can withstand a greater between the power input terminal I / P1 and the power output terminal O / P1 The voltage difference is such that when the surge voltage is excessively large and the first transistor MN1 cannot withstand, the surge voltage breakdowns the first transistor MN1 to cause damage to the internal circuit. The gate voltage of the second transistor MN2 is controlled by the output terminal of the second potential converter 16, and the control terminal of the second potential converter 16 and the first potential converter 13 are electrically connected thereto. Gate output. Therefore, with the above principle of controlling the gate voltage of the first transistor MN1, the second transistor MN2 is turned on only when the surge voltage is not generated and the surge protection circuit 10 is activated, and the first transistor is simultaneously turned on. MN1 is also turned on, so that the power supply voltage of the power input terminal I/P1 is supplied to the power output terminal O/P1.

Referring to FIG. 3, the base control unit 14 includes a first reverse gate 141, a third transistor MN3, and a fourth transistor MN4. The first reverse gate 141 has a first reverse gate input terminal and a first reverse gate output terminal, and the third transistor MN3 has a drain, a source, and a gate. And a body, the fourth transistor MN4 also has a drain, a source, a gate and a body. In the preferred embodiment, the third transistor MN3 and the fourth transistor MN4 are both an N-type metal oxide semiconductor field effect transistor (NMOS).

The gate 12 and the gate output are electrically connected to the first reverse gate input of the first reverse gate 141. The first reverse gate output of the first reverse gate 141 is electrically connected to the gate of the fourth transistor MN4.

The drain of the third transistor MN3 is electrically connected to the drain of the first transistor MN1, and the source of the third transistor MN3 is electrically connected to the base of the first transistor MN1, the third transistor MN3 The gate is electrically connected to the gate output, and the base of the third transistor MN3 is electrically connected to the base of the first transistor MN1. The drain of the fourth transistor MN4 is electrically connected to the source of the first transistor MN1, and the source of the fourth transistor MN4 is electrically connected to the source of the third transistor MN3, the fourth transistor MN4 The base is electrically connected to the base of the third transistor.

When the power supply voltage does not reach the startup voltage, it represents that the surge protection circuit 10 of the present invention has not been activated. Therefore, the enable signal and the surge detection signal are both a low voltage level, and the reverse gate 11 and the The logic circuit of the gate 12 outputs a low potential from the sum gate output terminal to the first reverse gate 141 and the third transistor MN3 of the base control unit 14. The gate of the third transistor MN3 is not turned on because it is directly electrically connected to the gate output terminal, but the gate of the fourth transistor MN4 receives a high potential through the first reverse gate 141. When turned on, the base of the first transistor MN1 is electrically connected to the source of the first transistor MN1 through the conduction of the fourth transistor MN4.

When the power supply voltage exceeds the startup voltage but does not reach the protection voltage, the surge protection circuit 10 of the present invention is activated but no surge voltage is generated. Therefore, the enable signal is a high voltage level, but the burst is The wave detection signal is a low voltage level, and the logic circuit of the back gate 11 and the gate 12 outputs a high potential from the gate output terminal to the first reverse gate 141 and the third power of the base control unit 14. Crystal MN3. The gate of the third transistor MN3 is turned on because the direct connection is directly connected to the gate output terminal, but the gate of the fourth transistor MN4 receives a low potential through the first reverse gate 141. The base of the first transistor MN1 is electrically connected to the drain of the first transistor MN1 through the conduction of the third transistor MN3.

When the power supply voltage exceeds the protection voltage, the surge protection circuit 10 of the present invention is activated and a surge voltage is generated. Therefore, the enable signal and the surge detection signal are both at a high voltage level, and the reverse gate is passed. 11 and the logic circuit of the gate 12, the gate output terminal outputs a low potential to the first reverse gate 141 and the third transistor MN3 of the base control unit 14. The gate of the third transistor MN3 is not turned on because it is directly electrically connected to the gate output terminal, but the gate of the fourth transistor MN4 receives a high potential through the first reverse gate 141. When turned on, the base of the first transistor MN1 is electrically connected to the source of the first transistor MN1 through the conduction of the fourth transistor MN4.

As shown in the above graph, the low potential is represented by 0 and the high potential is represented by 1. The potential level of the enable terminal I/P2 and the surge detection signal input terminal I/P3 determines that the base of the first transistor MN1 is electrically connected to the drain or the source of the first transistor, thereby The first transistor forms a reverse biased diode or a forward biased diode, so that the first transistor MN1 blocks current when forming the reverse biased diode without being turned on. Flowing, or letting a current flow when the forward biased diode is formed, and the potential of the enable terminal I/P2 and the surge detection signal input terminal I/P3 is based on the power supply The magnitude of the voltage is determined to effectively prevent the surge voltage from entering the internal circuit. Therefore, the internal circuit can use low-voltage electronic components to reduce the overall area of the circuit design, and there is no need to provide a Zener diode, which can save production costs.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to equivalent embodiments by using the above-disclosed technical contents without departing from the technical scope of the present invention. It is still within the scope of the technical solution of the present invention to make any simple modifications, equivalent changes and modifications to the above embodiments.

10‧‧‧ Surge protection circuit
11‧‧‧Backgate
12‧‧‧ and gate
13‧‧‧First potential converter
14‧‧‧Base control unit
141‧‧‧First reverse gate
15‧‧‧Charging pump
16‧‧‧Second potential converter

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a first preferred embodiment of the present invention. Figure 2 is a circuit diagram of a second preferred embodiment of the present invention. Figure 3 is a circuit diagram of a preferred embodiment of the base control unit of the present invention.

10‧‧‧ Surge protection circuit

11‧‧‧Backgate

12‧‧‧ and gate

13‧‧‧First potential converter

14‧‧‧Base control unit

Claims (5)

A surge protection circuit comprising: a power input end receiving a power supply; a first transistor being an N-type metal oxide semiconductor field effect transistor having a drain, a source, a gate and a base electrically connected to the power input end; a reverse gate having a reverse gate input terminal and a reverse gate output terminal, the reverse gate input terminal serving as a surge detection signal input terminal for receiving a surge a detection signal; a gate having a first input terminal, a second input terminal and a gate output terminal, wherein the first input terminal serves as a uniform energy terminal and receives a uniform energy signal, and the second input terminal is electrically connected to the a first potential converter having a high potential input terminal, a low potential input terminal, a control terminal and an output terminal, the high potential input terminal being electrically connected to the power input terminal, the low potential input The terminal is electrically connected to the source of the first transistor, the control terminal is electrically connected to the gate output terminal, and the output terminal is electrically connected to the gate of the first transistor; wherein the potential of the control terminal is a high level Bit, control the high potential input Connected to the output terminal, when the potential of the control terminal is a low level, the low potential input terminal is electrically connected to the output terminal; a base control unit is electrically connected to the base of the first transistor, a pole, a source, and a gate output of the gate; wherein when the potential of the gate output is at a high level, the base is electrically connected to the drain, and when the potential of the gate is low When the level is in position, the base is electrically connected to the source; and a power output is electrically connected to the source of the first transistor. The surge protection circuit of claim 1, further comprising: a charge pump electrically connected between the power input terminal and the high potential input end of the first potential converter, and having a boost input terminal And a boost output terminal; wherein the boost input terminal is electrically connected to the power input terminal, and the boost output terminal is electrically connected to the high potential input end of the first potential converter. The surge protection circuit of claim 1 or 2, further comprising: a second transistor, an N-type metal oxide semiconductor field effect transistor, and electrically connected to the source of the first transistor Between the output end of the power supply, a drain, a source, a gate and a base, the drain of the second transistor is electrically connected to the source of the first transistor, the second The source of the crystal is electrically connected to the output end of the power supply, and the base of the second transistor is electrically connected to the source of the second transistor and a second potential converter having a high potential input terminal and a low potential input terminal a control terminal and an output terminal, the high potential input end of the second potential converter is electrically connected to the high potential input end of the first potential converter, and the low potential input end is electrically connected to the source of the second transistor The control terminal is electrically connected to the gate output terminal, and the output terminal is electrically connected to the gate of the second transistor; wherein when the potential of the control terminal of the second potential converter is at a high level, the a high potential input terminal of the second potential converter is electrically connected to the second power The output of the converter, when the potential of the control terminal of the second voltage converter is a low level, controlling the second voltage converter is connected to the second voltage converter output terminal of the low voltage power input terminal. The surge protection circuit of claim 1 or 2, wherein the base control unit comprises: a third transistor having a drain, a source, a gate and a base, the third a gate of the crystal is electrically connected to a drain of the first transistor, a base of the third transistor is electrically connected to a base of the first transistor, and a gate of the third transistor is electrically connected to the gate An output end, the source of the third transistor is electrically connected to the base of the first transistor; and a fourth transistor has a drain, a source, a gate and a base, the fourth a drain of the transistor is electrically connected to a source of the first transistor, a source of the fourth transistor is electrically connected to a source of the third transistor, and a base of the fourth transistor is electrically connected to the first a base of the three transistors; a first reverse gate having a first reverse gate input and a first reverse gate output, the first reverse gate input being electrically connected to the gate output, the first reverse a gate input and a gate of the third transistor. The surge protection circuit of claim 3, wherein the base control unit comprises: a third transistor having a drain, a source, a gate and a base, the third transistor The drain is electrically connected to the drain of the first transistor, the base of the third transistor is electrically connected to the base of the first transistor, and the gate of the third transistor is electrically connected to the gate output The source of the third transistor is electrically connected to the base of the first transistor; and a fourth transistor has a drain, a source, a gate and a base, and the fourth transistor The anode is electrically connected to the source of the first transistor, the source of the fourth transistor is electrically connected to the source of the third transistor, and the base of the fourth transistor is electrically connected to the third a base of the crystal; a first reverse gate having a first reverse gate input and a first reverse gate output, the first reverse gate input being electrically connected to the gate output, the first reverse gate input The terminal and the gate of the third transistor.