TW201702871A - Methods for re-configuring a storage controller when control logic fails and apparatuses using the same - Google Patents

Abstract

An embodiment of a method for re-configuring a storage controller when control logic fails, which is executed by a processing unit, is described. The method comprises of the following steps. After determining that a storage controller fails, a re-configuration control logic of a fixed region of the storage controller is driven to reprogram the entire reconfigurable region of the storage controller, where the reconfigurable region is implemented in FPGA (Field-Programmable Gate Array).

Description

Method for reconfiguring a storage controller when controlling logic errors and apparatus using the same

The present invention is related to a flash memory device, and more particularly to a method of reconfiguring a memory controller when controlling logic errors and a device using the same.

For controllers in Solid State Drive (SSD) storage systems packaged in Field-Programmable Gate Array (FPGA), Single Event Upset (SEU) is the cause of control. One of the reasons for the logic error. Single-event flipping is a state in which a sensitive device in a microelectronic device flips due to alpha particles or cosmic ray impact. Accordingly, the present invention is directed to a method of reconfiguring logic in a controller when controlling logic errors and apparatus using the same to overcome the above problems.

Embodiments of the present invention provide a method of reconfiguring a memory controller when controlling logic errors, executed by a processing unit, including the following steps. After determining that the storage controller has an error, driving the reconfiguration control logic in the fixed area of the storage controller to reprogram the entire reconfigurable area of the storage controller A domain in which the reconfigurable area is implemented as a field programmable gate array.

Embodiments of the present invention provide an apparatus for reconfiguring a controller when controlling logic errors, including a fixed area and a reconfigurable area. The fixed area contains the processing unit and reconfiguration control logic. After the processing unit determines that the memory controller has an error, it drives the reconfiguration control logic in the fixed area of the memory controller to reprogram the entire reconfigurable area of the memory controller. The reconfigurable area is implemented as a field programmable logic gate array.

10‧‧‧System

110‧‧‧Processing unit

120‧‧‧Read-only memory

130‧‧‧Static Random Access Memory

140‧‧‧Dynamic random access memory

150‧‧‧Access interface

160‧‧‧Main device

170‧‧‧Access interface

180‧‧‧ storage unit

210‧‧‧Memory cell array

220‧‧‧ line decoding unit

230‧‧‧ column coding unit

240‧‧‧ address unit

250‧‧‧data register

300a‧‧‧Reconfigurable area

300b‧‧‧Fixed area

310‧‧‧Reconfiguration Control Logic

S410~S480‧‧‧ method steps

S510~S520‧‧‧ method steps

1 is a system architecture diagram of a solid state drive storage system in accordance with an embodiment of the present invention.

2 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention.

Figure 3 is a schematic diagram showing the logical division of a memory controller in accordance with an embodiment of the present invention.

4 is a flow chart of a method of reconfiguring a memory controller in accordance with an embodiment of the present invention.

Figure 5 is a flow diagram of a method of reconfiguring a memory controller in accordance with an embodiment of the present invention.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual invention must refer to the scope of the patent application that follows.

It must be understood that the "include" and "packages" used in this specification The words "and" are used to indicate that there are specific technical features, numerical values, method steps, operational processes, components and/or components, but do not exclude additional technical features, numerical values, method steps, and operational processing. Element, component, or any combination of the above.

The words "first", "second" and "third" are used in the scope of the patent application to modify the elements in the scope of the patent application, and are not intended to indicate a priority order, an advancing relationship, or One component precedes another component, or the chronological order in which the method steps are performed, and is only used to distinguish components with the same name.

1 is a system architecture diagram of a solid state drive storage system in accordance with an embodiment of the present invention. The system architecture 10 of the solid state drive storage system includes read only memory 120 that stores information for reconfiguring the storage controller. It should be noted here that this information can also be backed up in the storage unit 180. When the processing unit 110 executes the control core algorithm of the SRAM 130, the data is written to the specified address in the storage unit 180 according to the command issued by the host device 160 through the access interface 150, or from the storage unit 180. Read the data in the specified address. In detail, the processing unit 110 can write data to a specified address in the storage unit 180 through the access interface 170, and read data from a specified address in the storage unit 180. The system architecture 10 uses a plurality of electronic signals to coordinate data and command transfer between the processing unit 110 and the storage unit 180, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction (command latch enable, CLE), write enable (write Enable, WE) and other control signals. The access interface 170 can communicate with the storage unit 180 using a double data rate (DDR) protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR toggle), or Other interface. The processing unit 110 can also use the access interface 150 to communicate with the main device 160 through a specified communication protocol, for example, a universal serial bus (USB), an advanced technology attachment (ATA), and an advanced technology. (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E) or other interface. The processing unit 110, the read-only memory 120, the static random access memory 130, and the access interfaces 150 and 170 may be collectively referred to as a storage controller.

2 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention. The storage unit 180 may include an array 210 composed of MxN memory cells, and each memory unit stores at least one bit of information. The flash memory can be a NAND type flash memory, or other kinds of flash memory. In order to correctly access the signal, the row decoding unit 220 is configured to select a row specified in the memory cell array 210, and the column encoding unit 230 is configured to select a data of a certain number of bytes in the specified row as an output. Address unit 240 provides row information to row decoder 220 in which those rows in select memory cell array 210 are defined. Similarly, column decoder 230 selects a certain number of columns in a specified row of memory cell array 210 for read or write operations based on the column information provided by address unit 240. A row can be called a wordline, and a column can be called a bitline. A data buffer 250 can store data read from the memory cell array 210 or data to be written into the memory cell array 210. The memory unit can be single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs).

Figure 3 is a schematic diagram showing the logical division of a memory controller in accordance with an embodiment of the present invention. The memory controller may include a reconfigurable region 130a and a fixed region 300b. The fixed area 300b may include an I/O control logic, a master-device communications logic, and a re-configuration control logic 310. The fixed area 300b may further include an arithmetic logic unit of the processing unit 110 for performing mathematical operations and controlling other components in accordance with the loaded firmware. For example, the input/output control logic includes input/output control for the read only memory 120, the static random access memory 130, and the like. The master device communication logic can be implemented in the access interface 150. The logic in fixed area 300b cannot be reconfigured. The reconfigurable area 300a is implemented as a field programmable logic gate array. The reconfigurable area 300a includes the control core algorithm of the solid state drive storage system, which can account for more than 90% of the space of the storage controller. The reconfigurable area 300a includes an array of programmable logic blocks and hierarchical reconfigurable interconnections such that the blocks can be connected to the blocks. For example, several logic gates can be connected to each other according to different configurations. together. Some logic blocks can be configured to perform complex, comprehensive functions, or simple logic gates such as AND, OR, OR, or XOR. Some logic blocks can contain memory elements, consisting of simple flip-flops or complete memory blocks. The control core algorithm in the reconfigurable area 300a and the logic in the fixed area 300b can be organized into several codes Code segments are protected by a CRC-Cyclic Redundancy Check in each code segment. The decoding unit may use the loop redundancy check code to check whether the control core algorithm and logic in the memory controller have an error, and attempt to correct the error when the error occurs. However, when the control core algorithm and logic cannot be repaired (also known as control logic errors), a method needs to be performed to reconfigure the storage controller. Control logic errors can also represent errors in the storage controller.

In one embodiment, the memory controller can detect which portion of the reconfigurable region 300a has an unrecoverable error, and then only reconfigure the portion where the error occurred. Specific hardware and/or software instructions are required to perform this detection. Alternatively, additional time is required to complete the detection, and it may not be possible to complete the reconfiguration and process the command until the command issued by the host device 160 expires. In another embodiment, the memory controller can reconfigure the entire reconfigurable area 300a without performing the detection as described above. 4 is a flow chart of a method of reconfiguring a memory controller in accordance with an embodiment of the present invention. Those skilled in the art understand that when the memory controller receives a command from the host device 160, the control core algorithm is used to drive the access interface 170 to complete the command, such as a data read command, a data write command, and the like. Before using the control core algorithm, the decoding unit needs to first check whether the control core algorithm and logic in the storage controller are correct. When the decoding unit is unable to repair an error occurring in the control core algorithm and logic of the memory controller, the highest priority interrupt can be issued to the processing unit 110. When the processing unit 110 receives the interrupt (step S410), the access is suspended (step S420). In other words, processing unit 110 does not use a control core algorithm that includes unrecoverable errors to drive access interface 170. Next, save The current execution state (for example, the execution of the variable value, the data that has not been written to the storage unit 180, the data that has been read but not yet replied to the host device 160, etc.) is in the dynamic random access memory 140 (step S430). In detail, in step S430, the processing unit 110 drives the input/output control logic to store the current execution state to the dynamic random access memory 140. The processing unit 110 drives the start of the reconfiguration control logic 310 to perform a reconfiguration job for reprogramming the entire reconfigurable area 300a (step S440). In detail, the reconfiguration control logic 310 drives the information stored in the read-only memory 120 through the input/output control logic, for example, instructions written in a hardware description language (HDL), and interconnections between logical blocks. The comparison table, etc., and reprograms the entire reconfigurable area 300a based on this information. Next, a loop is repeatedly executed to inquire whether the reconfiguration control logic 310 reconfiguration job is completed (step S450). When the reconfiguration control logic 310 returns a message that the reconfiguration job is completed (the path of YES in step S450), the processing unit 110 starts a re-initiation operation of the entire storage controller so that the storage controller is available. State (step S460). Next, the execution state is restored from the dynamic random access memory 140 (step S470), and resume access is resumed according to the restored execution state (step S480). Through the above methods, the operations that have not been performed can be continued from the interruption point. The storage controller expires only for a short period of time (less than 1 second) and then resumes normal after reconfiguration.

Figure 5 is a flow diagram of a method of reconfiguring a memory controller in accordance with an embodiment of the present invention. When the access is suspended (step S420), the operation in the current pipeline is completed (step S510). When the operation in the current pipeline is completed (step S510), the processing unit 110 drives the start of the reconfiguration control logic 310. The line reconfiguration job is used to reprogram the entire reconfigurable area 300a (step S440). Next, when the processing unit 110 starts the reinitialization job of the entire storage controller so that the storage controller is in the usable state (step S460), the access is resumed (step S520). For detailed technical content of steps S410, S420, S440, S450, and S460, please refer to the description of FIG. 4, and details are not described again for brevity.

For how to determine the error of the above storage controller, please refer to the method flow described in FIG. 4 and FIG. 5: some embodiments detect the occurrence of a single event flipping error through an interrupt handler mechanism, once received. Interrupt, then reconfigure. In some embodiments, processing unit 110 may also periodically poll the decoding unit for single event inversion errors. Once the decoding unit replies with a single-event rollover error, it is reconfigured.

Although the above-described components are included in FIG. 1, it is not excluded that more other additional components are used without departing from the spirit of the invention, and a better technical effect has been achieved. Further, although the flowcharts of FIGS. 4 and 5 are executed in the specified order, those skilled in the art can modify the order among the steps without achieving the same effect without departing from the spirit of the invention. Therefore, the present invention is not limited to the use of only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the patent application must be interpreted in the broadest sense to include all obvious modifications and similar arrangements.

S410~S480‧‧‧ method steps

Claims (24)

A method for reconfiguring a memory controller when controlling a logic error, executed by a processing unit, comprising: determining that a memory controller has an error; suspending operation of the memory controller; driving a weight in a fixed area of a memory controller Configuring control logic for reprogramming an entire reconfigurable area of the storage controller; and restoring operation of the storage controller. A method of reconfiguring a memory controller as described in claim 1 for controlling logic errors, wherein the reconfigurable area is implemented as a field programmable logic gate array. The method for reconfiguring the storage controller when controlling logic errors as described in claim 1 further includes: suspending an access and storing an execution before reprogramming the reconfigurable area of the storage controller. a state to a dynamic random access memory; and after reprogramming the reconfigurable area of the memory controller, initiating a reinitialization operation of the memory controller, restoring the execution state, and restoring the access according to the execution state . A method for reconfiguring a memory controller when a control logic error is described in claim 3, wherein the fixed area includes a host device communication logic for receiving an indication from a master device to access a memory unit A command for information. The method for reconfiguring a storage controller when controlling logic errors as described in claim 3, wherein the step of driving a reconfiguration control logic in a fixed area of the storage controller further includes: periodicity Inquiring whether the reconfiguration control logic one reconfiguration job is completed; and when the reconfiguration control logic returns that the reconfiguration operation has been completed, continuing the subsequent processing. The method for reconfiguring a storage controller when controlling a logic error as described in claim 1, wherein the step of driving a reconfiguration control logic in a fixed area of the storage controller further comprises: The information stored in the read-only memory reprograms the entire reconfigurable area of the storage controller. The method for reconfiguring a memory controller when controlling logic errors as described in claim 6 wherein the fixed area further includes an input/output control logic and is re-created according to a message stored in a read-only memory. The step of programming the entire reconfigurable area of the memory controller further includes: driving the input/output control logic to read the information stored in the read-only memory. A method for reconfiguring a memory controller when a control logic error is described in claim 1, wherein the control logic error represents that the control core algorithm of the reconfigurable area and the logic of the fixed area cannot be included A decoder corrected error. Reconfigure as described in item 8 of the patent application for control logic errors A method of storing a controller, wherein a control core algorithm of the reconfigurable area and a logical structure of the fixed area are organized into a plurality of code segments, and a loop redundancy check code is added to each of the code segments Protect. a method for reconfiguring a memory controller when controlling logic errors as described in claim 9 wherein said decoder uses said loop redundancy check code to check said control core algorithm of said reconfigurable region and said Whether the logic of the fixed area has an error and attempts to correct the error when the above error occurs. The method for reconfiguring a storage controller when controlling a logic error as described in claim 1, wherein the step of determining a memory controller error comprises: receiving an interrupt representing a control logic error. A method of reconfiguring a memory controller as described in claim 11 in the context of a control logic error, wherein the interrupt has the highest priority. An apparatus for reconfiguring a memory controller when controlling a logic error, comprising: a fixed area, including a processing unit and a reconfiguration control logic; and a reconfigurable area; wherein the processing unit determines that a memory controller has an error; And a reconfiguration control logic in a fixed area driving a memory controller for reprogramming an entire reconfigurable area of the memory controller. An apparatus for reconfiguring a memory controller as described in claim 13 of the scope of the patent, wherein the reconfigurable area is implemented as a field programmable logic gate array. The apparatus for reconfiguring a memory controller when controlling logic errors as described in claim 13 wherein the processing unit suspends an access and storage before reprogramming the reconfigurable area of the memory controller. An execution state to a dynamic random access memory; and after reprogramming the reconfigurable area of the memory controller, initiating a reinitialization operation of the memory controller, restoring the execution state, and restoring the foregoing according to the execution state access. The apparatus for reconfiguring a memory controller when a control logic error is described in claim 15 wherein the fixed area includes a host device communication logic for receiving an indication from a master device to access a storage unit. A command for information. An apparatus for reconfiguring a storage controller when a control logic error is described in claim 15 wherein the processing unit periodically queries whether the reconfiguration control logic reconfiguration operation is completed; and when the reconfiguration control logic replies When the above reconfiguration job has been completed, the subsequent processing is continued. The apparatus for reconfiguring a memory controller when controlling a logic error as described in claim 13 wherein the processing unit reprograms the entire storage controller according to an information stored in a read-only memory. Reconfigure the area. The apparatus for reconfiguring a memory controller when controlling logic errors as described in claim 18, wherein the fixed area further includes an input/output control logic, and the processing unit drives the input/output control logic to read the Read the above information stored in the memory. The apparatus for reconfiguring a memory controller when controlling logic errors as described in claim 13 of the patent application, wherein the control logic error represents that the control core algorithm of the reconfigurable area and the logic of the fixed area cannot be included A decoder corrected error. The apparatus for reconfiguring a storage controller when controlling logic errors as described in claim 20, wherein the control core algorithm of the reconfigurable area and the logical area of the fixed area are organized into a plurality of code segments, and A loop redundancy check code is added to each of the above code segments for protection. The apparatus for reconfiguring a memory controller when controlling logic errors as described in claim 21, wherein the decoder uses the loop redundancy check code to check a control core algorithm of the reconfigurable area and the foregoing Whether the logic of the fixed area has an error and attempts to correct the error when the above error occurs. The apparatus for reconfiguring a memory controller when controlling logic errors as described in claim 13 wherein the processing unit receives an interrupt representing a control logic error, and determines that the memory controller has an error. A device for reconfiguring a memory controller when controlling logic errors as described in claim 23, wherein the interrupt has the highest priority.