TW201640660A - Back side illumination image sensor - Google Patents

Abstract

A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Description

Backlit image sensor

The present disclosure relates to an image sensor, and more particularly to a backlight image sensor.

Many modern electronic devices include optical imaging devices (eg, digital cameras) that use image sensors. The image sensor converts the optical image into digital data that can represent the image. The image sensor can include an array of pixel sensors and support logic. The pixel sensor measures incident radiation (eg, light), and the support logic can facilitate reading the measured value. One of the image sensors commonly found in optical imaging devices is a back-side illumination (BSI) image sensor. For low cost, small size and high throughput, the manufacture of backlight image sensors can be integrated into conventional semiconductor processes. In addition, the backlight image sensor has low operating voltage, low power consumption, high quantum efficiency, low readout noise, and allows random access.

In some embodiments, a backlight image sensor includes a pixel sensor, a metal gate segment, and a dielectric grid segment. The pixel sensor is disposed within a semiconductor substrate. The metal grid is disposed above the pixel sensor and has a metal gate opening therein. The metal gate segment has a metal grid height. The dielectric gate segment is disposed over the metal gate segment and has a dielectric gate opening therein. The dielectric grid segment has a dielectric grid height. The ratio of the height of the dielectric grid to the height of the metal grid is between about 1.0 and about 8.0.

In some embodiments, a backlight image sensor includes a pixel sensor, a metal gate segment, and a dielectric grid segment. The pixel sensor is disposed within a semiconductor substrate. The metal grid is disposed above the pixel sensor and has a metal gate opening therein. The metal gate segment has a top metal gate width. The metal gate opening has a bottom metal gate opening width. The dielectric gate segment is disposed over the metal gate segment and has a dielectric gate opening therein. The dielectric gate segment has a top dielectric gate width. The backlight image sensor satisfies at least one of: a ratio of a top dielectric gate width to a top metal gate width of between about 0.1 and about 2.0; and a ratio of a top dielectric gate width to a bottom metal gate opening width It is between about 0.1 and about 0.9.

In some embodiments, a backlight image sensor includes a pixel sensor, a metal gate segment, and a dielectric grid segment. The pixel sensor is disposed within a semiconductor substrate. The metal grid is disposed above the pixel sensor and has a metal gate opening therein. The metal gate opening has a bottom metal gate opening width. The dielectric gate segment is disposed over the metal gate segment and has a dielectric gate opening therein. Stacked gate structure height from semiconductor substrate and metal gate It extends to the upper surface of one of the dielectric grid segments. The ratio of the height of the stacked gate structure to the width of the bottom metal gate opening is between about 0.5 and about 2.0.

In some embodiments, a backlight image sensor includes a pixel sensor, a metal gate segment, and a dielectric grid segment. The pixel sensor is disposed within a semiconductor substrate. The metal gate is disposed above the pixel sensor and has a metal gate opening therein. The dielectric gate segment is disposed over the metal gate segment and has a dielectric gate opening therein. An angle between a lower surface of one of the dielectric grid segments and a sidewall of one of the dielectric grid segments is between about 60 degrees and less than about 90 degrees.

100A, 100B, 100C, 500, 600, 700, 800, 900, 1000, 1100, 1200A, 1200B, 1300A, 1300B‧‧

102‧‧‧Semiconductor substrate

104‧‧‧pixel sensor

106‧‧‧ Detector

108‧‧‧Anti-reflective layer

110‧‧‧buffer layer

112‧‧‧ upper surface

113‧‧‧Stacking grid

114‧‧‧Metal grid

116, 116'‧‧‧ dielectric grid

118‧‧‧Metal gate opening

120, 120'‧‧‧ dielectric grid opening

120", 120A‧‧‧ remaining dielectric grid openings

120B‧‧‧ Dielectric grid opening

120C‧‧‧ Dielectric grid opening

122‧‧‧ lower surface

124‧‧‧Bending the lower surface

124A‧‧‧ recessed lower surface

124B‧‧‧ protruding lower surface

124C‧‧‧ lower surface

126, 126’‧‧‧metal gate

128, 128'‧‧‧ dielectric grid

130, 130' ‧ ‧ etch stop layer

132, 132’‧‧‧ Coverage

132”, 132A, 132B‧‧‧ remaining cover

132C‧‧‧ Coverage

134, 134A, 134B, 134C, 136, 136A, 136B, 136C, 138, 138A, 138C‧‧‧ color filters

140, 142‧‧‧ upper surface

144‧‧‧Microlens

146‧‧ ‧ protruding upper surface

148A, 148B‧‧‧ rays

152‧‧‧metal fence

154‧‧‧Dielectric grid section

200A, 200B‧‧‧ray map

202‧‧‧Color filter

204‧‧‧ recessed lower surface

206‧‧‧Light

208‧‧‧Under

210‧‧‧ normal axis

216‧‧‧ color filter

218‧‧‧ protruding lower surface

220‧‧‧Light

222‧‧‧Under

224‧‧‧ normal axis

226‧‧ ‧ focus

228‧‧‧ focal plane

300‧‧‧section view

302‧‧‧Integrated circuit

304‧‧‧ Back side

306‧‧‧BEOL metal stacking

308‧‧‧ Carrier substrate

310, 312‧‧‧ metal layer

314‧‧‧Interlayer dielectric layer

316‧‧‧Contact points

318‧‧‧through hole

400‧‧‧ Flowchart

402-422‧‧‧Steps

702‧‧‧First photoresist layer

704‧‧‧ etchant

1002‧‧‧Second photoresist layer

1004, 1202, 1302‧‧‧ etchant

1400A, 1400B, 1400C‧‧‧ graphics

θ ₁ ‧‧‧ incident angle

θ ₂ ‧‧ ‧ refraction angle

The aspects of the present invention will be best understood from the following detailed description when read in conjunction with the drawings. It should be noted that various features are not necessarily drawn to scale, according to the standard practice in the art. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1A is a cross-sectional view of some embodiments of a backlight (BSI) image sensor having a color filter with a concave lower surface.

FIG. 1B illustrates a cross-sectional view of some embodiments of a backlight image sensor having a color filter with a convex lower surface.

FIG. 1C is a cross-sectional view showing some embodiments of a backlight image sensor having a color filter with a planar lower surface.

FIG. 2A illustrates a ray diagram of some embodiments of a backlight image sensor having a color filter with a concave lower surface.

FIG. 2B illustrates a ray diagram of some embodiments of a backlight image sensor having a color filter with a convex lower surface.

Figure 3 illustrates a cross-sectional view of some embodiments of a backlight image sensor having a color filter with a curved lower surface.

Figure 4 illustrates a flow diagram of some embodiments of a method for fabricating a backlight image sensor having a color filter with a curved lower surface.

5 through 11 , 12A and 12B, and FIGS. 13A and 13B illustrate a series of cross-sectional views of some embodiments of a backlight image sensor at various stages of fabrication.

Figures 14A through 14C illustrate some embodiments of the figures, the examples showing design parameters that have an impact on optical performance and barrier properties.

This document provides many different embodiments, or examples, for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present case. Of course, the specific examples are merely examples and are not intended to be limiting. For example, a structure in which the first feature is located above or above the second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include wherein additional features can be formed in the first feature Between the second feature and the second feature, the first feature and the second feature may not be in direct contact with each other. Moreover, the present invention may repeat the component symbols and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself dictate the relationship between the various embodiments and/or configurations discussed.

In addition, such as "beeath", "below", "lower", "above" Spatially relative terms such as "upper" and the like may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the drawings. Spatially relative terms may be used to encompass different orientations of the device in use or operation in addition to the orientation shown. The device may additionally be turned (rotated 90 degrees or other orientations) and the spatially relative description language used herein may be interpreted accordingly accordingly.

A backlight (BSI) image sensor includes a pixel sensor disposed within a semiconductor substrate of an integrated circuit. The pixel sensor is disposed between the back side of the integrated circuit and the metal stack of the back-end-of-line of the integrated circuit. The microlens and the color filter corresponding to the pixel sensor are stacked on the back side of the integrated circuit above the corresponding pixel sensor. A color filter is arranged to selectively transmit radiation of a specified wavelength to a respective pixel sensor, and the microlens is arranged to focus incident radiation (eg, photons) onto the color filter.

The stacked grid is disposed on the back side of the integrated circuit. The stacked gate includes a metal gate and a dielectric gate covering the metal gate. The metal grid is disposed laterally around the metal gate opening corresponding to the pixel sensor. The metal gate opening is filled by a cap layer that vertically spaces the dielectric gate from the metal gate. A dielectric grid is laterally disposed about the dielectric gate opening, the dielectric gate opening corresponding to the pixel sensor and having a flat lower surface. The dielectric gate opening is filled with a color filter. The dielectric grid is arranged to direct or otherwise focus the radiation into the color filter by total internal reflection towards the pixel sensor. However, after reaching the flatness of the dielectric gate opening After the surface, the radiation can diverge (eg, by refraction). This divergence can increase crosstalk between adjacent pixel sensors and reduce optical performance. In addition, the design parameters of the stacked grid are carefully controlled to achieve proper optical performance and barrier properties.

In view of the above, the present disclosure relates to a backlight image sensor having a dielectric gate opening and a method for fabricating a backlight image sensor having a curved lower surface for focusing radiation. In some embodiments, the backlit image sensor includes a pixel sensor disposed within the semiconductor substrate. The metal gate is disposed over the semiconductor substrate, and the dielectric gate is disposed over the metal gate. The metal gate and the dielectric gate define sidewalls of the metal gate opening and sidewalls of the dielectric gate opening respectively over the pixel sensor. The capping layer is disposed between the metal gate and the dielectric gate and fills the metal gate opening. In addition, the cover layer defines a curved lower surface of the dielectric gate opening. A color filter is disposed in the dielectric gate opening, and the microlens is disposed above the color filter. The refractive index of the color filter is different from the refractive index of the cover layer.

The different refractive indices of the color filter and the cover layer and the curved lower surface of the dielectric gate opening can focus the radiation entering the color filter and illuminate the radiation toward the curved lower surface toward the pixel sensor. In a sense, the curved lower surface can be used as a lens. By focusing the radiation toward the pixel sensor, crosstalk between adjacent pixel sensors can be reduced and optical performance improved. In addition, by aligning the etching process, a curved lower surface can be formed without additional processing steps.

Further, the disclosure relates to a backlight image sensor, and the backlight image sensor has a careful control for improving optical performance and barrier properties. Design parameters. In some embodiments, the backlit image sensor includes a pixel sensor disposed within the semiconductor substrate. The metal gate is disposed over the semiconductor substrate, and the dielectric gate is disposed over the metal gate. The ratio of the height of the dielectric grid to the height of the metal grid can be, for example, between about 1.0 and about 8.0. Further, the angle between the lower surface of the dielectric grid and the sidewall of the dielectric gate may be, for example, about 60 degrees to about 90 degrees. In some embodiments, the angle between the lower surface of the dielectric grid and the sidewall of the dielectric gate can be, for example, less than about 90 degrees. The metal gate and the dielectric gate define sidewalls of the metal gate opening and sidewalls of the dielectric gate opening respectively over the pixel sensor. The backlight image sensor can satisfy at least one of the following cases: 1 the ratio of the top dielectric gate width to the top metal gate width can be, for example, between about 0.1 and about 2.0; and 2 the ratio of the top dielectric gate width to the metal gate opening width For example between about 0.1 and about 0.9. The capping layer is disposed between the metal gate and the dielectric gate and defines a lower surface of the dielectric gate opening. The ratio of the height of the stacked gate structure to the width of the metal gate opening can be, for example, from about 0.5 to about 2.0, wherein the stacked gate structure comprises a dielectric gate and a metal gate and a cap layer.

Advantageously, optical performance and optical barrier properties can be improved by controlling design parameters. Design parameters may include, for example, one or more of stacked gate structure height, metal gate height, dielectric gate height, metal gate opening width, metal gate width, and dielectric gate width. Optical performance and optical barrier properties can be achieved by reducing crosstalk, achieving a minimum signal-to-noise ratio (SNR) of about 10 (ie, SNR-10), and quantum efficiency; QE) etc. to improve.

Referring to Figure 1A, a cross-sectional view 100A of some embodiments of a backlit image sensor is provided. The backlight image sensor includes a semiconductor substrate 102 And the pixel sensor 104, the pixel sensor 104 is disposed in the semiconductor substrate 102 in the form of columns and/or rows. Pixel sensor 104 is arranged to convert incident radiation (eg, photons) into electrical signals. The pixel sensor 104 includes a corresponding photodetector 106, and in some embodiments, the pixel sensor 104 includes a corresponding amplifier (not shown). The photodetector 106 can be, for example, a photodiode, and the amplifier can be, for example, a transistor. The photodiode may include a first region (not shown) within the semiconductor substrate 102 having a first doping type (eg, n-type doping), and the photodiode may also be included in the semiconductor substrate 102. And covering a corresponding second region of the first region (not shown) having a second doping type (eg, p-type doping), the second doping type being different from the first doping type.

An antireflective coating (ARC) 108 and/or a buffer layer 110 are disposed over the semiconductor substrate 102 along the upper surface 112 of the semiconductor substrate 102. In embodiments having both anti-reflective layer 108 and buffer layer 110, buffer layer 110 is disposed over anti-reflective layer 108. The anti-reflective layer 108 can be, for example, an organic polymer or a metal oxide. The buffer layer 110 can be, for example, an oxide such as hafnium oxide. The anti-reflective layer 108 and/or the buffer layer 110 vertically space the semiconductor substrate 102 from the stacked gate 113 covering the semiconductor substrate 102.

The stacked gate 113 includes a metal gate 114 and a dielectric gate 116 covering the metal gate 114. The metal gate 114 and the dielectric gate 116 respectively define a metal gate opening 118 corresponding to the sidewall of the pixel sensor 104, and the dielectric gate opening 120A corresponds to the sidewall of the pixel sensor 104, and the metal gate 114 and the dielectric gate 116 The arrangement is directed to encircle the pixel sensor 104 and direct the radiation entering the openings 118, 120A. The metal and/or dielectric gate openings 118, 120A are at least partially covered Corresponding pixel sensor 104. In some embodiments, as shown, the center of the metal gate opening 118 and/or the dielectric gate opening 120A is aligned above the center of the respective pixel sensor 104. In an alternate embodiment, as shown, the center of the metal gate opening 118 and/or the dielectric gate opening 120A is laterally displaced or offset from the center of the corresponding pixel sensor 104. Metal gate opening 118 has a generally planar lower surface 122 that may be defined by anti-reflective layer 108 and/or buffer layer 110. The dielectric gate opening 120A has a curved lower surface. The curved lower surface has a curvature that depends on the refractive index of the color filter (described below) and the underlying cover layer (described below). For example, as shown in FIG. 1A, if the refractive index of the color filter is greater than the refractive index of the cover layer, the dielectric gate opening 120A will have a concave lower surface 124A.

The metal gate 114 and the dielectric gate 116 are respectively disposed within the metal and dielectric gate layers 126, 128 stacked on the reflective layer 108 and/or the buffer layer 110. The metal gate 114 is disposed within the metal gate layer 126 overlying the anti-reflective layer 108 and/or the buffer layer 110. Metal gate layer 126 can be, for example, tungsten, copper, or aluminum copper. Dielectric grid 116 is disposed within dielectric gate layer 128 stacked over metal gate layer 126. In some embodiments, the dielectric gates 116 are further disposed within other layers (eg, one or more additional dielectric gate layers) below the etch stop layer 130 and/or the dielectric gate layer 128. Dielectric gate layer 128 can be, for example, an oxide such as hafnium oxide. The etch stop layer 130 can be, for example, a nitride such as tantalum nitride.

The cap layer 132A is disposed over the metal gate layer 126 and between the metal gate layer 126 and the dielectric gate layer 128. The cap layer 132A spaces the dielectric gate 116 from the metal gate 114 and fills the metal gate opening 118. In addition, coverage Layer 132A defines a recessed lower surface 124A of dielectric gate opening 120A, and in some embodiments, cover layer 132A partially defines a sidewall of dielectric gate opening 120A. The cap layer 132A is a dielectric such as hafnium oxide. In some embodiments, the cap layer 132A is the buffer layer 110 and/or the dielectric gate layer 128 or comprises the same material as the buffer layer 110 and/or the dielectric gate layer 128. For example, in some embodiments without etch stop layer 130, cap layer 132A and dielectric gate layer 128 have the same molecular structure and/or different regions corresponding to successive layers (eg, layers formed by a single deposition).

Color filters 134A, 136A, 138A corresponding to pixel sensor 104 are disposed in dielectric gate opening 120A to fill dielectric gate opening 120A. Color filters 134A, 136A, 138A have a flat upper surface 140 that is substantially coplanar with upper surface 142 of dielectric gate layer 128. Color filters 134A, 136A, 138A are arranged corresponding to radiation of a specified color or wavelength and are arranged to transmit radiation corresponding to a specified color or wavelength to respective pixel sensor 104. Color filters 134A, 136A, 138A may alternate between red, green, and blue such that color filters 134A, 136A, 138A include red color filter 134A, green color filter 136A, blue color Filter 138A. In some embodiments, the color filter alternates between red, green, and blue light according to a Bayer mosaic. The color filters 134A, 136A, 138A are a first material having a refractive index greater than the refractive index of the second material, and the second material is adjacent to the first recessed surface 124A of the dielectric gate opening 120A. material. The second material is the material of the cap layer 132A and/or the dielectric gate layer 128.

Microlenses 144 corresponding to pixel sensors 104 are disposed over color filters 134A, 136A, 138A and pixel sensor 104. The center of the microlens 144 is aligned with the center of the pixel sensor 104, but the center of the microlens 144 can be laterally shifted or offset from the center of the pixel sensor 104. Microlens 144 is arranged to focus incident radiation (eg, light) toward pixel sensor 104. In some embodiments, the microlens 144 has a convex upper surface 146 that is configured to focus radiation toward the color filters 134A, 136A, 138A and/or the pixel sensor 104.

In operation, the recessed lower surface 124A of the dielectric gate opening 120A can serve as a lens that focuses or concentrates radiation on the corresponding pixel sensor 104. Radiation entering the color filters 134A, 136A, 138A and illuminating the concave lower surface 124A of the dielectric gate opening 120A may be refracted toward the metal gate 114 by a refraction angle greater than the angle of incidence. After illuminating the metal grid 114, the radiation can be reflected toward the pixel sensor 104. For example, assume that light ray 148A enters color filter 136A, exits the sidewall of color filter 136A toward the concave lower surface of the respective dielectric gate opening, and illuminates the concave lower surface at an angle of incidence θ ₁ . Further, it is assumed that the color filter 136A has a refractive index n ₁ and the cover layer 132A has a refractive index n ₂ . In this case, since n ₁ is greater than n _2, so that θ ₁ and θ ₂ is larger than θ ₂ may be calculated according to the following law of Snell.

Advantageously, focusing or concentrating radiation on the pixel sensor 104 can reduce crosstalk between adjacent pixel sensors and improve optical performance.

Referring to Figure 1B, a cross-sectional view 100B of another embodiment of a backlit image sensor is provided. Backlit image sensor included in the overlay Dielectric grid 116 above 132B. The dielectric gate 116 defines a sidewall that covers the dielectric gate opening 120B of the corresponding pixel sensor 104, and the cover layer 132B defines a convex lower surface 124B of the dielectric gate opening 120B. Color filters 134B, 136B, 138B corresponding to pixel sensor 104 are disposed in dielectric gate opening 120B to fill dielectric gate opening 120B. The color filters 134B, 136B, and 138B are a first material having a refractive index lower than a refractive index of the second material, and the second material is adjacent to the first surface of the lower surface 124B of the dielectric gate opening 120B. material. The second material is the material of the cap layer 132B and/or the dielectric gate layer 128.

In operation, the raised lower surface 124B of the dielectric gate opening 120B can serve as a lens that focuses or concentrates radiation on the corresponding pixel sensor 104. The color filters 134B, 136B, 138B are entered, and the radiation incident on the convex lower surface 124B of the dielectric gate opening 120B can be refracted toward the pixel sensor 104 by a refraction angle θ ₂ that is smaller than the incident angle θ ₁ . For example, it is assumed that the light ray 148B enters the color filter 136B, the side wall away from the color filter 136B is reflected toward the convex lower surface of the corresponding dielectric gate opening, and is incident on the convex lower surface at the incident angle θ ₁ . Further, it is assumed that the color filter 136B has a refractive index n ₁ and the cover layer 132B has a refractive index n ₂ . In this case, since n ₁ is less than n _2, so that less than θ ₁ and θ ₂ θ ₂ may be calculated according to Snell's law. Advantageously, focusing or concentrating radiation on the pixel sensor 104 can reduce crosstalk between adjacent pixel sensors and improve optical performance.

The above embodiments relate to a dielectric gate opening having a curved lower surface. However, in some embodiments, the dielectric grid opening has a flat lower surface. In this embodiment, improved control of design parameters is achieved for proper optics Performance and optical barrier properties are important. Design parameters may include, for example, one or more of gate height, metal gate opening width, and top width.

Referring to Figure 1C, a cross-sectional view 100C of another embodiment of a backlit image sensor is provided. The backlit image sensor includes a stacked gate structure 150 that covers the semiconductor substrate 102. The stacked gate structure 150 includes a stacked gate 113 that is vertically spaced from the semiconductor substrate 102 by the anti-reflective layer 108 and/or the buffer layer 110. The anti-reflective layer 108 and/or the buffer layer 110 are disposed between the stack gate 113 and the semiconductor substrate 102, typically the buffer layer 110 is over the anti-reflective layer 108. The stacked gate structure 150 has a height _HSG , and in some embodiments (as shown), the stacked gate structure 150 includes a buffer layer 110.

The stacked gate 113 includes a metal gate 114 and a dielectric gate 116 covering the metal gate 114. The metal gate 114 has a height H _MG and the dielectric grid has a height H _DG . In some embodiments, the ratio of the dielectric grid height H _DG to the metal grid height H _MG (ie, H _DG /H _MG ) is from about 1.0 to about 8.0. For example, the ratio H _DG /H _MG can be from about 1.0 to about 3.0, from about 3.0 to about 6.0, or from about 6.0 to 8.0. The metal gates and dielectric gates 114, 116 define sidewalls corresponding to the dielectric and metal gate openings 118, 120C of the pixel sensor 104 disposed in the semiconductor substrate 102, respectively. The metal gate opening 118 has a lower width W _MGO and the dielectric gate opening 120C has a generally planar lower surface 124C. In some embodiments, the height H _SG stacked gate structure of the metal gate of the opening ratio of the width W _MGO (i.e., H _SG / W _MGO) of from about 0.5 to about 2.0. For example, the ratio H _SG /W _MGO can be from about 0.5 to about 1, or from about 1.0 to about 2.0. The metal and dielectric gates 114, 116 are arranged to encircle the respective pixel sensor 104 and direct radiation into the metal and dielectric gate openings 118, 120C. The metal and dielectric gates 114, 116 are each comprised of a plurality of overlapping dielectric and metal gate segments 152, 154.

The metal and dielectric grid segments 152, 154 are annular, such as square or rectangular, and have sidewalls that are inclined at an angle θ , Φ from the respective lower surface. In some embodiments, the dielectric grid sidewall angle θ is from about 60 degrees to about 90 degrees. For example, the dielectric grid sidewall angle θ can be from about 70 degrees to about 80 degrees. Further, metal and dielectric gate segments 152, 154 correspond to metal and dielectric gate openings 118, 120C and laterally surround respective metal and dielectric gate openings 118, 120C. Metal gate segment 152 has a top width W _MG and dielectric gate segment 154 has a top width W _DG . The top widths W _MG , W _DG span from the inner sidewalls of the respective gate segments 152 , 154 to the outer sidewalls of the respective gate segments 152 , 154 (the gate segments 152 , 154 are annular). In some embodiments, the ratio of the dielectric gate width W _DG to the metal gate width W _MG (ie, W _DG /W _MG ) is from about 0.1 to about 2.0. For example, the ratio W _DG /W _MG can be from about 0.1 to about 1.0, or from about 1.0 to about 2.0. Further, in some embodiments, the ratio of the dielectric gate width W _DG to the metal gate opening width W _MGO (ie, W _DG /W _MGO ) is from about 0.1 to about 0.9. For example, the ratio W _DG /W _MGO can be from about 0.1 to about 0.5, or from about 0.5 to about 0.9.

A cap layer 132C of the stacked gate structure 150 is disposed between the metal gate 114 and the dielectric gate 116 to define a lower surface 124C of the dielectric gate opening 120C. In addition, color filters 134C, 136C, 138C corresponding to pixel sensor 104 are disposed in dielectric gate opening 120C to at least partially fill dielectric gate opening 120C. The color filters 134C, 136C, 138C have a different refractive index than the dielectric grid 116 and have a height H _CF . In some embodiments, the height H _DG and the color filter _CF of the ratio of the height H of the gate dielectric (i.e., H _DG / H _CF) is from about 0.1 to about 2.0. For example, the ratio H _DG /H _CF can be from about 0.1 to about 1.0, or from about 1.0 to about 2.0.

Advantageously, optical performance and optical barrier properties can be improved by controlling design parameters (eg, by reducing crosstalk, SNR-10, etc.). Design parameters may include, for example, stacked gate structure height H _SG , metal gate height H _MG , dielectric gate height H _DG , color filter height H _CF , metal gate opening width W _MGO , metal gate width W _MG , and One or more of the dielectric gate widths W _DG . In addition, although the 1Cth figure relates to the metal gate opening width W _MGO , it should be understood that the pixel pitch (for example, the lateral distance between the centers of adjacent pixel sensors) may be used instead of the metal gate opening width W _MGO . ratio.

Referring to Figure 14A, some embodiments of graph 1400A are provided to illustrate the effect of the ratio of dielectric grid height H _DG to color filter height H _CF (i.e., H _DG /H _CF ) on optical performance. The horizontal axis corresponds to this ratio and is from -0.1 to about 1.1. The vertical axis corresponds to either the normalized SNR-10 or the normalized sensitivity, depending on which side of the graphic 1400A the vertical axis corresponds to. On the left side of graph 1400A, the vertical axis corresponds to normalized SNR-10 and from about 0.8 to about 1.15. On the right side of graph 1400A, the vertical axis corresponds to normalization sensitivity and is from about 0.88 to about 1.02.

Diamond marks and triangle marks are drawn on the graphic 1400A, respectively, and are used to mark the normalized SNR-10 and the normalized sensitivity, respectively, and the lines are interconnected to make the trend clearer. The mark corresponding to the known value of the ratio is divided by a broken line ellipse. As shown, the normalized SNR-10 is advantageously decremented as the ratio increases from about 0.1 to about 2. Furthermore, the normalization sensitivity is advantageously increased as the ratio increases. The ratio of the dielectric grid height H _DG to the metal grid height H _MG (i.e., H _DG /H _MG ) can be expected to have a similar trend of SNR-10 and normalization sensitivity.

Referring to Figure 14B, some embodiments of pattern 1400B are provided to illustrate the effect of the ratio of dielectric gate width W _DG to metal gate opening width W _MGO (i.e., W _DG /W _MGO ) to normalized SNR-10. The horizontal axis corresponds to this ratio and is from about 0.12 to about 0.16. The vertical axis corresponds to the normalized SNR-10 and is from about 0.88 to about 1.00.

The diamond mark and the triangle mark are respectively drawn on the graphic 1400B, and are respectively used to indicate different ratios of the dielectric gate height H _DG and the color filter height H _CF (as shown in FIG. 14A), and the optimum line is connected to the mark. Between to make the trend clearer. The diamond mark corresponds to a ratio of the dielectric grid height H _DG of about 1.00 to the color filter height H _CF . The triangular mark corresponds to a ratio of the dielectric grid height H _DG of about 0.56 to the color filter height H _CF . As can be seen, as the ratio of the dielectric gate width W _DG to the metal gate opening width W _MGO increases from about 0.125 to about 0.155, the normalized SNR-10 increases. This is because, as the dielectric gate width W _DG increases, less light enters the color filters 134C, 136C, and 138C, thereby reducing signal and noise. A ratio of the dielectric gate width W _DG to the metal gate width W _MG (i.e., W _DG /W _MG ) can be expected to have a similar SNR-10 trend. Therefore, a ratio of the dielectric gate width W _DG to the metal gate opening width W _MGO between 0.1 and 0.9 is preferred.

Referring to Figure 14C, some embodiments of graph 1400C are provided to illustrate the effect of metal gate opening width W _MGO on optical performance. The horizontal axis corresponds to the metal gate opening width W _MGO in micrometers (μm). The vertical axis corresponds to either optical QE (in percent) or average crosstalk (in percent), depending on which side of the graph 1400C the longitudinal axis corresponds to. On the left side of graph 1400C, the vertical axis corresponds to optical QE and is from about 45% to about 75%. On the right side of graph 1400C, the vertical axis corresponds to average crosstalk and is from about 15% to about 40%.

Diamond marks and triangle marks are drawn on the pattern 1400C, respectively, and are used for average crosstalk and optical QE, respectively, and the lines interconnect the marks to make the trend clearer. As can be seen, the average width W _MGO crosstalk decreases with increasing opening of the metal gate. Further, as the optical QE metal gate opening width W _MGO increases.

Referring to FIG. 2A, a ray diagram 200A of some embodiments of a backlight image sensor is provided, the backlight image sensor having a color filter 202 having a concave lower surface 204. As shown, light 206 enters color filter 202 and is illuminated in parallel onto recessed lower surface 204. Because the color filter 202 has a first index of refraction and the first index of refraction is greater than the second index of refraction of the lower adjacent layer 208, the ray 206 will refract away from the corresponding normal axis 210 to be adjacent to the underlying pixel sensor. Focus 212 (similar to a convex lens). In other words, the higher refractive index of color filter 202 relative to lower layer 208 may cause light 206 to have a refraction angle θ ₂ greater than the corresponding angle of incidence θ ₁ to focus ray 206 toward the underlying pixel sensor. Other rays (not shown) that are not parallel to the ray 206 and that enter the color filter 202 are refracted as described above and intersect other points of focus on the focal plane 214, wherein the focal plane 214 includes the focus 212.

Referring to FIG. 2B, a ray diagram 200B of some embodiments of a backlight image sensor is provided, and the backlight image sensor has a color filter 216. This color filter 216 has a convex lower surface 218. As shown, light 220 enters color filter 216 and is incident on the convex lower surface 218 in parallel. Because the color filter 216 has a first index of refraction, and the first index of refraction is less than the second index of refraction of the lower adjacent layer 222, the ray 220 will refract toward the corresponding normal axis 224 to be close to the underlying pixel sensor. Focus 226 (similar to a convex lens). In other words, the low refractive index of color filter 216 relative to lower layer 222 may cause light 220 to have a refraction angle θ ₂ that is less than the corresponding angle of incidence θ ₁ , thereby focusing ray 220 toward the underlying pixel sensor. Other rays (not shown) that are not parallel to the ray 220 and that enter the color filter 216 are refracted as described above and intersect other points of focus on the focal plane 228, wherein the focal plane 228 includes the focus 226.

Referring to Figure 3, a cross-sectional view 300 of another embodiment of a backlit image sensor is provided. The backlit image sensor includes an array of pixel sensors 104 arranged in columns and rows, the array being located between the back side 304 of the integrated circuit 302 and the BEOL metal stack 306 of the integrated circuit 302, and located in the product. In the semiconductor substrate 102 of the body circuit 302. The pixel sensor 104 includes a corresponding photodetector 106, and in some embodiments, the pixel sensor 104 includes an amplifier (not shown). The detector 106 is configured to convert incident radiation (e.g., photons) into electrical signals, and the optical detector 106 can be, for example, a photodiode.

The BEOL metal stack 306 is located below the semiconductor substrate 102 and between the semiconductor substrate 102 and the carrier substrate 308. The BEOL metal stack 306 includes a plurality of metal layers 310, 312 stacked within an interlayer dielectric (ILD) layer 314. One or more contact points 316 of the BEOL metal stack 306 extend from the metal layer 310 to the pixel sensor 104. Additionally, one or more vias 318 of the BEOL metal stack 306 extend between the metal layers 310, 312 to interconnect the metal layers 310, 312. Interlayer dielectric layer 314 can be, for example, a low-k dielectric (i.e., a dielectric having a dielectric constant less than about 3.9) or an oxide. Metal layers 310 and 312, contact points 316, and vias 318 can be, for example, metals such as copper or aluminum.

The anti-reflective layer 108 and/or the buffer layer 110 are disposed along the back side 304 of the integrated circuit 302, and the stacked gate 113 is disposed over the anti-reflective layer 108 and/or the buffer layer 110. The stacked gate 113 includes a metal gate 114 and a dielectric gate 116 covering the metal gate 114. The metal gate 114 and the dielectric gate 116 are respectively disposed within the metal and dielectric gate layers 126, 128 stacked on the anti-reflective layer 108 and/or the buffer layer 110. In some embodiments, the dielectric gate 116 is further disposed within the etch stop layer 130, and the etch stop layer 130 is under the dielectric gate layer 128 of the dielectric gate 116. In addition, the metal gate 114 and the dielectric gate 116 define sidewalls of the corresponding pixel sensor 104 of the metal gate opening 118 and sidewalls of the corresponding pixel sensor 104 of the dielectric gate opening 120, respectively. The metal gate opening 118 has a generally planar lower surface 122 that may be defined by the anti-reflective layer 108 and/or the buffer layer 110; and the dielectric gate opening 120 has a curved lower surface 124. The curved lower surface 124 can be concave (eg, as shown, and as depicted in FIG. 1A) or convex (eg, as depicted in FIG. 1B).

The cap layer 132 is disposed over the metal gate 114 and between the metal gate layer 126 and the dielectric gate layer 128. In addition, color filters 134, 136, 138 and microlenses 144 corresponding to pixel sensor 104 are above respective pixel sensors 104. Color filters 134, 136, 138 fill dielectric gate openings 120, and microlenses 144 mask color filters 134, 136, 138 to focus light into color filters 134, 136, 138.

Referring to Figure 4, there is shown a flow diagram 400 of some embodiments of a method for fabricating a backlight image sensor having a color filter and a color filter having a curved lower surface.

At step 402, an integrated circuit having a pixel sensor is provided, the pixel sensor being disposed in the semiconductor substrate of the integrated circuit and between the back side of the integrated circuit and the BEOL metal stack of the integrated circuit.

In step 404, an anti-reflective layer is formed on the back side, a buffer layer is formed on the anti-reflective layer, and a metal gate layer is formed on the buffer layer.

At step 406, a first etch is performed into the metal gate layer to form a metal gate. The metal grid defines sidewalls for the metal gate openings corresponding to the pixel sensors.

At step 408, a capping layer is formed over the metal gate and fills the metal gate opening.

At step 410, a chemical mechanical polish (CMP) is performed into the cover layer to planarize the upper surface of the cover layer.

At step 412, an etch stop layer is formed over the cap layer and a dielectric gate layer is formed over the etch stop layer.

At step 414, a second etch is performed into the dielectric gate layer until the etch stop layer is formed to form a dielectric gate. The dielectric grid defines a dielectric gate opening corresponding to the pixel sensor.

At step 416, a third etch is performed into the etch stop layer to remove the exposed regions of the etch stop layer in the dielectric gate opening.

At step 418, a fourth etch is performed into the cap layer to bend the lower surface of the dielectric gate opening.

At step 420, a color filter is formed that fills the opening of the dielectric gate, the color filter having a refractive index different from the refractive index of the cover layer. Advantageously, this different refractive index and the curved lower surface of the dielectric gate opening will cause the radiation to focus towards the lower pixel sensor. This advantageously reduces the dispersion of radiation close to the lower surface of the dielectric grid and reduces crosstalk between adjacent pixel sensors. Moreover, this advantageously improves optical performance.

At step 422, a microlens is formed over the color filter.

Although the method of flowchart 400 is illustrated and described herein as a series of acts or events, the order of the acts, events, or events is not limited. For example, some acts may occur in a different order and/or in parallel with other acts or events (other than the acts or events shown and/or described herein). Moreover, not all of the acts are required in one or more embodiments, and one or more of the acts illustrated herein can be performed in one or more separate acts and/or stages.

In some alternative embodiments, the second and third etches, and/or the third and fourth etches may be performed simultaneously (eg, using a common etchant). Moreover, in some embodiments, the etch stop layer and step 416 can be omitted. In this embodiment, the second etch may be a time based etch using a known etch rate. Moreover, in some alternative embodiments, the capping layer and the dielectric gate layer may correspond to different regions of the common layer. In this embodiment, steps 408, 410, 412 may be omitted. Instead of steps 408, 410, and 412, a common layer can be formed (eg, in a single deposition) over the metal gate and filled with a metal gate opening. Further, chemical mechanical polishing can be performed into the common layer to planarize the upper surface of the common layer, and steps 414 to 422 can be performed. Moreover, in some embodiments, the fourth etch can be omitted.

Referring to Figures 5 to 11, 12A and 12B, and 13A and 13B, cross-sectional views of some embodiments of backlight image sensors at various stages of fabrication are provided to illustrate Figure 4 method. Although Figures 5 to 11, 12A and 12B, and 13A and 13B relate to the above method, it should be understood that in Figures 5 to 11, 12A and 12B The structures illustrated in FIGS. 13A and 13B are not limited to such methods, but may alternatively be constructed independently of the methods. Similarly, although FIGS. 5 to 11 , 12A and 12B , and 13A and 13B relate to the method, it should be understood that the method is not limited to those in FIGS. 5 to 11 and 12A. And the structure shown in FIG. 12B and FIGS. 13A and 13B, but may alternatively be independent of FIGS. 5 to 11 , 12A and 12B, and 13A. And the method outside the structure disclosed in Fig. 13B.

FIG. 5 depicts a cross-sectional view 500 corresponding to some embodiments of step 402. As shown, a semiconductor substrate 102 is provided having a pixel sensor 104 disposed within the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 is part of an integrated circuit, and the pixel sensor 104 is disposed on the back side of the integrated circuit (eg, the upper surface 112 of the semiconductor substrate 102) and the BEOL metal stack of the integrated circuit. Between (not shown). The pixel sensor 104 includes a photodetector 106, such as a photodiode. The semiconductor substrate 102 can be, for example, a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

FIG. 6 depicts a cross-sectional view 600 corresponding to some embodiments of step 404. As shown, the anti-reflective layer 108 and/or the buffer layer 110 are sequentially stacked on the semiconductor substrate 102. Further, a metal gate layer 126' is formed over the anti-reflective layer 108 and/or the buffer layer 110. The anti-reflective layer 108, the buffer layer 110, and the metal gate layer 126' may be formed sequentially by deposition techniques such as spin coating or vapor deposition. The anti-reflective layer 108 may be formed of, for example, an organic polymer or a metal oxide. The buffer layer 110 may be formed of an oxide such as cerium oxide. The metal gate layer 126' may be formed of, for example, tungsten, copper, aluminum, or aluminum copper.

FIG. 7 depicts a cross-sectional view 700 corresponding to some embodiments of step 406. As shown, a first etch is performed into the metal gate layer 126', through the area overlying the pixel sensor 104, up to the anti-reflective layer 108 and/or the buffer layer 110. The first etch forms a metal gate 114 that defines a sidewall that corresponds to the metal gate opening 118 of the pixel sensor 104. Metal gate opening 118 at least partially covers respective pixel sensor 104.

The process for performing the first etch may include forming a first photoresist layer 702 that masks a region of the metal gate layer 126' corresponding to the metal gate 114. Etchant 704 can then be applied to metal gate layer 126' according to the pattern of first photoresist layer 702 to define metal gate 114. Etchant 704 can select metal gate layer 126' relative to anti-reflective layer 108 and/or buffer layer 110. Additionally, etchant 704 can be, for example, a dry etchant. After the etchant 704 is applied, the first photoresist layer 702 can be removed or otherwise stripped.

FIG. 8 depicts a cross-sectional view 800 corresponding to some embodiments of step 408. As shown, a cap layer 132' is formed over the metal gate 114 and the remaining metal gate layer 126 and fills the metal gate opening 118. The cover layer 132' may be formed of, for example, a dielectric such as an oxide, and/or the cover layer 132' may be formed of, for example, the same material as the buffer layer 110. Further, the cover layer 132' may be formed using a deposition method such as spin coating or vapor deposition.

FIG. 9 depicts a cross-sectional view 900 corresponding to some of the embodiments of steps 410 and 412. As shown, chemical mechanical polishing is performed to a location in the cap layer 132' over the remaining metal gate layer 126 to create a substantially planar upper surface 902. As also shown, the etch stop layer 130' and the dielectric gate layer 128' are sequentially stacked over the remaining cap layer 132". The etch stop layer 130' and the dielectric gate layer 128' can be used, for example, by vapor deposition. A deposition method is formed. The etch stop layer 130' may be formed of a nitride such as tantalum nitride. The dielectric gate layer 128' may be formed, for example, of hafnium oxide, and/or the dielectric gate layer 128' may be, for example, from the remaining cap layer 132" the same material is formed. In an alternate embodiment, the etch stop layer 130' may be omitted.

FIG. 10 depicts a cross-sectional view 1000 corresponding to some embodiments of step 414. As shown, a second etch is performed into the dielectric gate layer 128' through the area covering the pixel sensor 104 until the etch stop layer 130'. The second etch forms a dielectric gate 116' that defines a sidewall corresponding to the dielectric gate opening 120' of the pixel sensor 104. Dielectric grid opening 120' at least partially covers respective pixel sensor 104.

The process for performing the second etch may include forming a second photoresist layer 1002 that masks a region of the dielectric gate layer 128' corresponding to the dielectric gate 116'. Etchant 1004 can then be applied to dielectric gate layer 128' in accordance with the pattern of second photoresist layer 1002 to define dielectric gate 116'. Etchant 1004 can be selective to dielectric gate layer 128' with respect to etch stop layer 130'. Further, the etchant 1004 can be, for example, a dry etchant. After the etchant 1004 is applied, the second photoresist layer 1002 can be removed or otherwise stripped.

FIG. 11 depicts a cross-sectional view 1100 corresponding to some embodiments of step 416. As shown, a third etch is performed into the etch stop layer 130' through the exposed regions in the dielectric gate opening 120' until the remaining cap layer 132". The third etch removes the dielectric gate opening 120' The region of the etch stop layer 130'. The process for performing the third etch may include, for example, applying an etchant 1102 to an etch stop layer 130'. The etchant 1102 may be opposite the dielectric gate layer 128 and/or the remaining cap layer 132" The etch stop layer 130' is selective. Additionally, etchant 1102 can be, for example, a wet etchant.

12A and 12B illustrate cross-sectional views 1200A, 1200B corresponding to some embodiments of steps 418, 420, and 422. Embodiments relate to dielectric gate openings having recessed lower surfaces.

As shown in FIG. 12A, a fourth etch is performed through the exposed regions of the remaining cap layer 132" into the remaining cap layer 132" to form a recessed lower surface 124A of the remaining dielectric gate opening 120". The fourth etch process can include, for example, applying one or more etchants 1202 to the remaining cap layer 132", the etch parameters of the etchant (eg, etch rate) being calibrated to define the recessed lower surface 124A. For example, the etch parameters are tuned such that the remaining cap layer 132" etches faster at the center of the remaining dielectric gate openings 120" than at the periphery of the remaining dielectric gate openings 120". One or more etchants 1202 can be opposed to The remaining etch stop layer 130 is selective to the remaining cap layer 132", and/or the one or more etchants 1202 can be, for example, a wet etchant or a dry etchant. Because one or more etchants 1202 are applied through the remaining dielectric gate openings 120", and the remaining dielectric gate layers 128 and the remaining cap layer 132" can be the same material, one or more etchants 1202 can erode the remaining dielectric The sidewall of the gate opening 120".

In an alternate embodiment, the fourth etch may be replaced by another method to form a recessed lower surface 124A. In one of the alternative embodiments, the recessed lower surface 124A can be formed by a reflow process (eg, a servo controlled reflow process). In other embodiments of the alternative embodiment, the recessed lower surface 124A can be formed by deposition, and its deposition parameters (e.g., deposition rate) can be adjusted to define the recessed lower surface 124A. For example, the deposition parameters can be tuned such that the deposition rate is at the center of the remaining dielectric gate openings 120" than at the periphery of the remaining dielectric gate openings 120" The side is slower. This deposition can be understood as an extension of the second cover layer and/or the remaining cover layer 132".

As shown in FIG. 12B, color filters 134A, 136A, 138A corresponding to the pixel sensor 104 are formed in the remaining dielectric gate openings 120A of the corresponding pixel sensors 104, wherein the upper surface 140 and the remaining dielectric are The upper surface 142 of the gate layer 128 is substantially flush. Color filters 134A, 136A, 138A are provided for radiation of a specified color or wavelength (e.g., according to a Bayer filter mosaic), and are provided with materials to transmit radiation of a specified color or wavelength to respective pixel sensors 104. In addition, color filters 134A, 136A, 138A are formed from a material having a refractive index greater than the refractive index of the remaining cover layer 132A, and/or formed from any other material that is adjacent and located below the recessed lower surface 124A. For each of the different color filters, the process for forming color filters 134A, 136A, 138A can include forming a color filter layer and patterning the color filter layers. A color filter layer can be formed to fill the remaining dielectric gate openings 120A and cover the remaining dielectric gate layers 128. Prior to patterning the color filter layer, the color filter layer may be planarized (e.g., by chemical mechanical polishing) and/or etched back to approximately flush with the upper surface 142 of the remaining dielectric gate layer 128.

As also shown in FIG. 12B, microlenses 144 corresponding to pixel sensors 104 are formed over color filters 134A, 136A, 138A of respective pixel sensors 104. The process for forming microlenses 144 can include forming a microlens layer over color filters 134A, 136A, 138A (e.g., by spin coating or deposition processes). In addition, it can be above the microlens layer A microlens template having a curved upper surface is patterned. The microlens layer can then be selectively etched according to the microlens template to form microlenses 144.

FIGS. 13A and 13B illustrate cross-sectional views 1300A, 1300B corresponding to other embodiments of steps 418, 420, and 422. Embodiments relate to a dielectric gate opening having a convex lower surface.

As shown in FIG. 13A, a fourth etch is performed through the exposed regions of the remaining cap layer 132" into the remaining cap layer 132" to form the raised lower surface 124B of the remaining dielectric gate opening 120". The four etch process can include, for example, applying one or more etchants 1302 to the remaining cap layer 132", the etch parameters of which can be tuned to define the raised lower surface 124B. For example, the etch parameters can be tuned such that the remaining cap layer 132" etches faster at the periphery of the remaining dielectric gate openings 120" than at the center of the remaining dielectric gate openings 120". One or more etchants 1302 can be opposite The remaining etch stop layer 130 is selective to the remaining cap layer 132", and/or the one or more etchants 1302 can be, for example, a wet etchant or a dry etchant.

In an alternate embodiment, the fourth etch may be replaced by another method to form a convex lower surface 124B. In one of the alternative embodiments, the raised lower surface 124B can be formed by a reflow process. In the alternative embodiment, the convex lower surface 124B may be formed by a deposition process whose deposition parameters may be calibrated to define a convex lower surface 124B. For example, the deposition parameters can be tuned such that the deposition rate is slower at the periphery of the remaining dielectric gate openings 120" than at the center of the remaining dielectric gate openings 120". This deposition can be understood as an extension of the second cover layer and/or the remaining cover layer 132".

As shown in FIG. 13B, the color filters 134B, 136B, 138B corresponding to the pixel sensor 104 are formed in the remaining dielectric gate openings 120A of the corresponding pixel sensors 104, wherein the upper surface 140 and the remaining dielectric The upper surface 142 of the gate layer 128 is substantially flush. In addition, color filters 134B, 136B, 138B are formed from a material having a refractive index that is less than the refractive index of the remaining cover layer 132B, and/or formed from any other material that is adjacent and located below the convex lower surface 124A.

As also shown in FIG. 13B, microlenses 144 corresponding to pixel sensors 104 are formed over color filters 134B, 136B, 138B of respective pixel sensors 104.

The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that the skilled artisan can readily use the present invention as a basis for designing or altering other processes and structures. Other processes and structures are used for the same purpose and/or achievement of the embodiments introduced herein. The same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that the equivalent constructions do not depart from the spirit and scope of the present invention. It should be understood that the equivalent constructions may be variously changed, substituted and changed without departing from the spirit and scope of the present invention.

100A‧‧‧section view

102‧‧‧Semiconductor substrate

104‧‧‧pixel sensor

106‧‧‧ Detector

108‧‧‧Anti-reflective layer

110‧‧‧buffer layer

112‧‧‧ upper surface

114‧‧‧Metal grid

113‧‧‧Stacking grid

116‧‧‧ dielectric grid

118‧‧‧Metal gate opening

120A‧‧‧Other dielectric gate openings

122‧‧‧ lower surface

124A‧‧‧ recessed lower surface

126‧‧‧metal gate

128‧‧‧Dielectric gate layer

130‧‧‧etch stop layer

132A‧‧‧ remaining cover

134A‧‧ color filter

136A‧‧‧Color Filter

138A‧‧ color filter

140‧‧‧ upper surface

142‧‧‧ upper surface

144‧‧‧Microlens

146‧‧ ‧ protruding upper surface

148A‧‧‧Light

θ ₁ ‧‧‧ incident angle

θ ₂ ‧‧ ‧ refraction angle

Claims (10)

A backlight image sensor includes: a pixel sensor disposed in a semiconductor substrate; a metal gate segment disposed on the pixel sensor and having a metal gate opening therein, wherein the metal gate The segment has a metal gate height; and a dielectric gate segment disposed over the metal gate segment and having a dielectric gate opening therein, wherein the dielectric gate segment has a dielectric gate height; wherein the dielectric gate The ratio of the height to the height of the metal grid is between about 1.0 and about 8.0. The backlight image sensor of claim 1, further comprising: a color filter disposed within the dielectric gate opening and having a color filter height; wherein the dielectric grid height and the color filter One of the ratios of the heights of the optics is between about 0.1 and about 2.0. The backlight image sensor of claim 1, further comprising: a cover layer disposed over the metal gate segment between the metal gate segment and the dielectric gate segment, and defining the dielectric gate opening One flats the lower surface. The backlight image sensor of claim 1, further comprising: a buffer layer disposed on the semiconductor substrate between the semiconductor substrate and the metal gate segment; wherein a stacked gate structure is height from the buffer layer One of the lower surfaces extends to an upper surface of the dielectric gate segment, wherein the metal gate opening has a bottom gold The gate opening width, and wherein the ratio of the stacked gate structure height to the bottom metal gate opening width is between about 0.5 and about 2.0. A backlight image sensor includes: a pixel sensor disposed in a semiconductor substrate; a metal gate segment disposed on the pixel sensor and having a metal gate opening therein, wherein the metal gate The segment has a top metal gate width, and the metal gate opening has a bottom metal gate opening width; and a dielectric gate segment disposed over the metal gate segment and having a dielectric gate opening therein, wherein the dielectric The gate segment has a top dielectric gate width; wherein at least one of: a ratio of the top dielectric gate width to the top metal gate width is between about 0.1 and about 2.0; and the top dielectric gate width A ratio to one of the bottom metal gate opening widths is between about 0.1 and about 0.9. The backlight image sensor of claim 5, further comprising: a buffer layer disposed on the semiconductor substrate between the semiconductor substrate and the metal gate segment; wherein a stacked gate structure is height from the buffer layer One of the lower surfaces extends to an upper surface of the dielectric gate segment, and wherein a ratio of the stacked gate structure height to the bottom metal gate opening width is between about 0.5 and about 2.0. A backlight image sensor comprising: a pixel sensor disposed in a semiconductor substrate; a metal gate segment disposed over the pixel sensor and having a metal gate opening therein, wherein the metal gate opening has a bottom metal gate opening width; and a dielectric gate segment disposed in the metal gate segment And having a dielectric gate opening therein; wherein a stacked gate structure height extends from the semiconductor substrate and the metal gate segment to an upper surface of the dielectric gate segment, and the stacked gate structure height and the bottom metal One of the gate opening width ratios is between about 0.5 and about 2.0. The backlight image sensor of claim 7, further comprising: a color filter disposed within the dielectric gate opening and having a color filter height; wherein the dielectric gate segment has a dielectric A grid height, and a ratio of the height of the dielectric grid to the height of the color filter is between about 0.1 and about 2.0. A backlight image sensor comprising: a pixel sensor disposed in a semiconductor substrate; a metal gate segment disposed on the pixel sensor and having a metal gate opening therein; and a dielectric a gate segment disposed over the metal gate segment and having a dielectric gate opening therein; wherein an angle between a lower surface of the dielectric gate segment and a sidewall of the dielectric gate segment is between about 60 degrees Less than about 90 degrees. The backlight image sensor of claim 9, further comprising: a cover layer disposed on the metal gate between the metal gate and the dielectric gate, and defining one of the dielectric gate openings to be flat lower surface.