TW201640633A - Semiconductor package structure and semiconductor packaging method - Google Patents

Abstract

The disclosure provides a semiconductor package structure, including a substrate, a first insulating layer disposed on the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer.

Description

Semiconductor package structure and semiconductor package method

The embodiments disclosed in the present invention relate to a semiconductor packaging method, and more particularly to a semiconductor packaging method that does not require a die bonding, a bonding wire, a lead frame, a molding process, and the like, and a related semiconductor package structure. .

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. In space, the interlayer area is used to expand the available wiring area on the board to meet the demand for integrated circuits with high electron density.

The conventional semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate, perform wire bonding, and then solder a solder ball on the back surface of the substrate to electrically connect with external electronic components. The purpose of the number. However, when it is used at a higher frequency, it will have a high impedance characteristic due to the long connection path of the wire, and the electrical performance cannot be improved, and there is a limit. In addition, because the traditional packaging requires multiple connection interfaces, the complexity of the process is relatively increased.

Figure 1 is a cross-sectional view of a conventional semiconductor package structure. The semiconductor package structure 10 includes a substrate 11 , a die 12 , a plurality of metal wires 13 , and an encapsulant 14 . The die 12 is fixed to the surface of the substrate 11 by an adhesive 15 and electrically connected to the plurality of pads 112 of the substrate 11 by a plurality of metal wires 13 respectively. A plurality of vias 114 are formed in the insulating layer 111 of the substrate 11. Therefore, the plurality of pads 112 can be electrically connected to the plurality of pads 113 at the bottom of the substrate 11 by a plurality of vias 114. A plurality of pads 113 can be combined with solder balls (not shown) to form a ball grid array (BGA) package. In order to protect the die 12 and the plurality of metal wires 13 from damage, the encapsulant 14 coats the die 12 and the plurality of metal wires 13 to isolate the environment.

The above-mentioned conventional semiconductor package structure not only needs to be completed by a complicated process such as a die bond, a bonding wire and a sealant, but also requires a substrate of a lead frame or a circuit board to carry the die, so that the package cost cannot be effectively reduced, and further improvement is needed. The complex packaging technology of the above conventional semiconductor components.

One of the objects of the present invention is to provide a semiconductor package structure and related semiconductor package method to improve the above problems.

According to a first embodiment of the present invention, a semiconductor package structure includes: a substrate; a first insulating layer disposed on the substrate; and a die disposed on the first insulating layer; wherein the die includes a a first carrier pad and a second carrier pad, the first carrier pad is coupled to a first portion of a metal layer, the second carrier pad is coupled to a second portion of the metal layer, and the metal layer The first portion and the second portion are separated by a second insulating layer.

According to a second embodiment of the present invention, a semiconductor package structure includes: a substrate; a first insulating layer disposed on the substrate; a first die disposed on the first insulating layer; and a second crystal The granules are disposed on the first insulating layer; wherein the first die includes a first carrier pad and a second carrier pad, and the second die includes a third a carrier pad and a fourth carrier pad, the first carrier pad is coupled to a first portion of a metal layer, and the second carrier pad is coupled to the third portion by a second portion of the metal layer a carrier pad, the fourth carrier pad is coupled to a third portion of the metal layer, and the first portion, the second portion, and the third portion of the metal layer are separated by a second insulating layer open.

According to a third embodiment of the present invention, a semiconductor package method includes: providing a substrate; forming a first insulating layer on the substrate; and disposing a die on the first insulating layer, wherein the die includes a first carrier pad and a second carrier pad; forming a second insulating layer on the first insulating layer, the die, the first carrier pad and the second carrier pad; removing a portion of the second insulating layer, Forming a first window and a second window to expose the first carrier pad and the second carrier pad; forming a first metal layer on the second insulating layer and the first window and the second window And the first metal layer is coupled to the first carrier pad and the second carrier pad; forming a third insulating layer on the first metal layer; removing a portion of the third insulating layer to form a third a window and a fourth window exposing a portion of the first metal layer; forming a second metal layer on the first metal layer in the third window and the fourth window; and removing the third insulating layer And a portion of the first metal layer to make the first bearing Pad not coupled to the second carrier via the first metal layer pad.

The semiconductor package structure of the present invention uses an insulating substrate as a carrier and directly bonds at least one die on the insulating substrate to save material cost, and to simplify the process and improve yield and manufacturing cost.

10‧‧‧Semiconductor package structure

11, 202, 1402‧‧‧ substrate

111‧‧‧Insulation

112‧‧‧ solder pads

113‧‧‧ pads

114‧‧‧Connecting column

12, 204, 1404, 1406‧‧ ‧ grains

13‧‧‧Metal wire

14‧‧‧Package colloid

15‧‧‧Viscos

206, 1408‧‧‧ first insulation

208, 1410‧‧‧ protective layer

302, 1420‧‧‧Second insulation

210, 1416‧‧‧First carrying mat

212, 1418‧‧‧Second bearing mat

402‧‧‧First window

404‧‧‧ second window

502, 1424‧‧‧ first metal layer

602, 1428‧‧‧ third insulation layer

702‧‧‧ third window

704‧‧‧ fourth window

802, 1422‧‧‧ second metal layer

1002‧‧‧fourth insulation

1102‧‧‧ fifth window

1104‧‧‧ sixth window

1302, 1426‧‧‧ first metal end

1304, 1430‧‧‧ second metal end

1412‧‧‧3rd carrying mat

1414‧‧‧four carrying mat

The technical features and advantages of the present disclosure are fully understood by reference to the foregoing description and the accompanying drawings.

1 is a cross-sectional view showing a conventional semiconductor package structure; and FIGS. 2 to 11 are cross-sectional views showing a packaging process of a semiconductor package method according to the present invention; 12 is a cross-sectional view showing an embodiment of a semiconductor package structure according to the present invention; FIG. 13 is a cross-sectional view showing another embodiment of a semiconductor package structure according to the present invention; and FIG. 14 is a semiconductor package according to the present invention; A cross-sectional view of another embodiment of the structure.

In the related drawings, reference symbols may be repeated throughout the embodiments, but the features of one embodiment are not necessarily applicable to another embodiment, even if the features share the same reference symbols. The drawings are provided for reference purposes only, but are not necessarily drawn to scale, and in some cases, the drawings may be enlarged and/or simplified. Any variations and modifications that may be conceived in the description of the present embodiments, as well as any further principles in this document, will be apparent to those skilled in the art.

2 to 11 are cross-sectional views showing a packaging process of a semiconductor package method according to the present invention. First, a plurality of dies cut from the wafer are subjected to a pick and place process, and at least the plurality of dies are based on the predetermined matrix and/or according to the size of the dies. One of them is arranged on a substrate 202, wherein the substrate 202 is an insulating substrate. In order to facilitate the description of the features of the present invention, only one die 204 is illustrated in the embodiment illustrated in FIGS. 2-11. As shown in FIG. 2, a first insulating layer 206 and a protective layer 208 are respectively attached to the upper surface of the upper surface of the substrate 202. Wherein the first insulating layer 206 and the protective layer 208 are preferably a dry film, and the component thereof may be selected from the group consisting of polyimide, epoxy resin, benzocyclobutene resin (BCB) or high. At least one of a molecular polymer. The die 204 can be bonded to the first insulating layer 206 and fixed to the surface of the first insulating layer 206 via a curing process; the protective layer 208 can be used to protect the substrate 202 and prevent the substrate 202 from being fragmented. However, the present invention is not limited thereto, and may be omitted in some embodiments of the present invention. Protective layer 208. In the present embodiment, the die 204 has a first die pad 210 and a second carrier pad 112. However, the invention is not limited thereto, and in some embodiments, the die 204 may have other numbers of carrier pads.

Next, as shown in FIG. 3, a second insulating layer 302 is attached to the first insulating layer 206 and covers the die 204, the first carrier pad 210, and the second carrier pad 212. The second insulating layer 302 is a photosensitive dry film, and the component thereof may be selected from at least one of polyimine, epoxy, benzocyclobutene resin or high molecular polymer. In FIG. 4, an exposure and development process is performed to respectively transfer the preset pattern to the second insulating layer 302 over the first carrier pad 210 and the second carrier pad 112 of the die 204 by an exposure development process. The second insulating layer 302 removes a portion of the second insulating layer 302 and forms a first window 402 and a second window 404 to expose the first carrier pad 210 and the second carrier pad 212. In FIG. 5, along the surface of the second insulating layer 302 and the outlines of the first window 402 and the second window 404, a first metal layer 502 is formed, and the first metal layer 502 is used as a subsequent metal layer. a diffusion barrier layer between the first carrier pad 210 and the second carrier pad 212 (dielectric layer) to improve electrical reliability, and to avoid copper atom drift or diffusion in the case where the subsequent metal layer contains copper It is a case that the first metal layer 502 may include titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), nitrogen-tellurium-tellurium (Ta-Si-N), and nitrogen. Tungsten (WN) is covered and covers the surface of the third insulating layer, the outline of the first window 402 and the second window 404, and the first carrier pad 210 and the second carrier pad 212 exposed in FIG.

In FIG. 6, a third insulating layer 602 is formed on the first metal layer 502, and the pattern is transferred by an exposure development process to form a third window 702 and a fourth image as shown in FIG. Window 704. Thus, a plating process can be performed in FIG. 8, and a second metal layer 802 is deposited as a connection pad in the second window 702 and the fourth window 704. In some embodiments, a thin and continuous seed layer can be formed after the first metal layer 502 is fabricated and prior to the plating process. (not shown in the figure) to improve adhesion and promote copper growth during plating. The second metal layer 802 may be selected from the group consisting of palladium (Pd), aluminum (Al), chromium (Cr), nickel (Ni), titanium (Ti), gold (Au), copper (Cu), or platinum (Pt). At least one of them. Next, the third insulating layer 602 and the first metal layer 502 not covered by the second metal layer 802 are removed by a process of removing the insulating layer, as shown in FIG. A fourth insulating layer 1002 formed in FIG. 10 covers the second insulating layer 302, the first metal layer 502, and the second metal layer 802. In Fig. 11, an exposure developing program is used to transfer the pattern to form a fifth window 1102 and a sixth window 1104 as shown in Fig. 11. The material of the third insulating layer 602 and the fourth insulating layer 1002 may be the same as the second insulating layer 302.

As can be seen from FIG. 11 , the first carrier pad 210 of the die 204 is coupled to a first portion of the second metal layer 802 by the first metal layer 502 (eg, the left portion of the second metal layer 802 of FIG. 11 ). The second carrier pad 212 of the die 204 is coupled to a second portion of the second metal layer 802 by the first metal layer 502 (eg, the right portion of the second metal layer 802 of FIG. 11), and The first portion and the second portion are separated by an insulating material (eg, the fourth insulating layer 1002 of FIG. 11). In addition, in the present embodiment, the thickness of the substrate 202 of the semiconductor package structure of FIG. 11 can be polished as required, but the invention is not limited thereto. Further, as mentioned earlier, when a plurality of crystal grains are included in the substrate 202, the substrate 202 can be diced according to the number of crystal grains, and finally a single semiconductor package structure as shown in Fig. 12 is obtained. 12 is a cross-sectional view showing an embodiment of a semiconductor package structure according to the present invention, wherein the semiconductor package structure of FIG. 12 is flipped and the second metal layer 802 is coupled to an external circuit by solder, such that the semiconductor of FIG. The package structure can transmit electrical signals to and from external circuits.

Figure 13 is a cross-sectional view showing another embodiment of a semiconductor package structure in accordance with the present invention. In some embodiments, the ends of the semiconductor package structure of Figure 12 may be silvered or a process of immersing copper and forming a first metal end 1302 and a second metal end 1304, the first metal end 1302 and the second metal end 1304 being silver or copper, and The first metal end 1302 and the second metal end 1304 are rolled with a metal such as nickel or tin. Note that in other embodiments, the first metal end 1302 and the second metal end 1304 may be other kinds of metals, such as palladium. Aluminum, chromium, nickel, titanium, gold or platinum. The semiconductor package structure of FIG. 13 can be soldered to an external circuit without being flipped to a specific direction, for example, can be placed on an external circuit board in a front, back or side manner and electrically connected to the external circuit board via soldering, Can greatly increase the convenience of the application. In some embodiments, the die 204 has more than three carrier pads, in which case the semiconductor package structure will have more than three silver or copper-impregnated metal ends.

14 is a cross-sectional view showing still another embodiment of a semiconductor package structure according to the present invention. The semiconductor package structure of FIG. 14 includes a first die 1404 and a second die 1406 respectively attached over the substrate 202. On a first insulating layer 1408 of the surface, a protective layer 1410 is additionally attached to the lower surface of the substrate 202, but the protective layer 1410 may be omitted. The first die 1404 has a first carrier pad 1416 and a second carrier pad 1418. The second die 1406 has a third carrier pad 1412 and a fourth carrier pad 1414. The semiconductor package structure of FIG. 14 further includes a second insulating layer 1420, a first metal layer 1424, a second metal layer 1422, a third insulating layer 1428, a first metal end 1426, and a second metal end 1430. The second carrier pad 1418 of the first die 1404 is coupled to the third carrier pad 1412 of the second die 1406 via a second portion of the first metal layer 1424 and the second metal layer 1422. The first carrier pad 1416 of the first die 1404 is coupled to the first metal end 1426 via a first portion of the first metal layer 1424 and the second metal layer 1422; the fourth carrier pad 1414 of the second die 1406 is A third portion of the first metal layer 1424 and the second metal layer 1422 is coupled to the second metal end 1430.

In the embodiment shown in FIG. 14, the first die 1404 and the second die 1406 may be capacitive elements. The first die 1404 and the second die 1406 are formed by the semiconductor package structure shown in FIG. They are connected in series to obtain an effect different from that of the individual capacitive elements. In other embodiments, more than one die may be formed via the semiconductor package described above. In series or in parallel with each other, the inner metal layers are used to couple the carrier pads that are required to be electrically connected to each other, and the carrier pads that are required to be electrically connected externally are coupled to the metal ends of the two ends.

The function of the crystal grains in the present invention is not limited to a specific element, and may be any digital element, analog element, mixing element or any active and passive element, such as a capacitive element, a resistive element, an inductive element, and transient voltage suppression (Transient- Voltage-suppression, TVS) diode or operator.

While the invention has been described in connection with the embodiments, the invention Rather, the scope of the invention is limited only by the appended claims. In addition, although the inventive features may be described in conjunction with the specific embodiments, those skilled in the art will appreciate that the various features of the described embodiments can be combined in accordance with the present invention. In the claims, the <RTIgt; "comprising" does not exclude the presence of other elements or steps.

In addition, although a plurality of means, elements or methods are separately listed, they should be implemented by, for example, a single unit, a processor, or a controller. In addition, although individual features may be included in different claims, the combination may be advantageously combined, and the inclusion in the different claims does not mean that the combination of features is not feasible and/or advantageous. Further, a feature contained in a category of claims is not meant to be limited to the category, but rather to the same.

In addition, the order of features in the claims is not intended to be in any specific order, and the order of the various steps in the method claims does not mean that the steps must be performed in the order. Rather, these steps can be performed in any suitable order. In addition, singular references do not exclude a plurality. Therefore, terms such as "a", "first" and "second" do not exclude a plurality.

The technical content and technical features of the disclosure have been disclosed above, but those having ordinary knowledge in the technical field of the disclosure should understand that the application is not deviated from the application. The teachings and disclosures of the present disclosure can be variously substituted and modified within the spirit and scope of the disclosure. For example, many of the devices or structures disclosed above may be implemented in different ways or substituted with other structures, or a combination of the two.

202‧‧‧Substrate

204‧‧‧ grain

206‧‧‧First insulation

208‧‧‧protection layer

210‧‧‧First carrying mat

212‧‧‧Second bearing pad

302‧‧‧Second insulation

502‧‧‧First metal layer

802‧‧‧Second metal layer

1002‧‧‧fourth insulation

1302‧‧‧First metal end

1304‧‧‧Second metal end

Claims (17)

A semiconductor package structure comprising: a substrate; a first insulating layer disposed on the substrate; and a die disposed on the first insulating layer; wherein the die includes a first carrier pad and a second carrier pad The first carrier pad is coupled to a first portion of a metal layer, the second carrier pad is coupled to a second portion of the metal layer, and the first portion and the second portion of the metal layer are A second insulating layer is spaced apart. The semiconductor package structure of claim 1, further comprising a protective layer disposed on the other side of the substrate opposite to the first insulating layer. The semiconductor package structure of claim 1, wherein the metal layer is selected from at least one of palladium, aluminum, chromium, nickel, titanium, gold, copper or platinum. The semiconductor package structure of claim 1, wherein the first insulating layer and the second insulating layer are photosensitive dry films, the components of which are selected from the group consisting of polyimine, epoxy resin, and benzo At least one of a cyclobutene resin or a high molecular polymer. The semiconductor package structure of claim 1, wherein at least a portion of the metal layer is exposed at both ends of the substrate. The semiconductor package structure of claim 5, wherein the semiconductor package structure comprises a first metal end formed at one end of the substrate and coupled to the first portion of the metal layer, and the semiconductor package structure comprises a A second metal end is formed on the other end of the substrate and coupled to the second portion of the metal layer. The semiconductor package structure of claim 6, wherein the first metal end and the second metal end are selected from at least one of silver or copper. A semiconductor package structure comprising: a substrate; a first insulating layer disposed on the substrate; a first die disposed on the first insulating layer; and a second die disposed on the first insulating layer; The first die includes a first carrier pad and a second carrier pad. The second die includes a third carrier pad and a fourth carrier pad. The first carrier pad is coupled to a metal layer. In a first part, the second carrier pad is coupled to the third carrier pad by a second portion of the metal layer, and the fourth carrier pad is coupled to a third portion of the metal layer. And the first portion, the second portion and the third portion of the metal layer are separated by a second insulating layer. The semiconductor package structure of claim 8, wherein at least a portion of each of the first portion and the third portion of the metal layer is exposed at both ends of the substrate. The semiconductor package structure of claim 9, wherein the semiconductor package structure comprises a first metal end formed at one end of the substrate and coupled to the first portion of the metal layer, and the semiconductor package structure comprises a A second metal end is formed on the other end of the substrate and coupled to the third portion of the metal layer. A semiconductor package method includes: providing a substrate; forming a first insulating layer on the substrate; and disposing a die on the first insulating layer, wherein the die includes a first carrier pad and a second carrier a pad; a second insulating layer is formed on the first insulating layer, the die, the first carrier pad and the second carrier pad; Removing a portion of the second insulating layer to form a first window and a second window to expose the first carrier pad and the second carrier pad; the second insulating layer and the first window and the second Forming a first metal layer on the window, and the first metal layer is coupled to the first carrier pad and the second carrier pad; forming a third insulating layer on the first metal layer; a third insulating layer forming a third window and a fourth window to expose a portion of the first metal layer; forming a second metal layer in the first metal layer in the third window and the fourth window And removing the third insulating layer and the portion of the first metal layer such that the first carrier pad is not coupled to the second carrier pad via the first metal layer. The semiconductor package method of claim 11, further comprising: forming a fourth insulating layer on the second metal layer: and removing the portion of the fourth insulating layer to form a fifth window and a first Six windows expose a portion of the second metal layer. The semiconductor package method of claim 11, further comprising forming a protective layer on the other surface of the substrate opposite to the first insulating layer. The semiconductor package method of claim 11, wherein the second metal layer is selected from at least one of palladium, aluminum, chromium, nickel, titanium, gold, copper or platinum. The semiconductor package method of claim 11, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are photosensitive dry films, the components of which are selected from the group consisting of And at least one of polyimine, epoxy resin, benzocyclobutene resin or high molecular polymer. The semiconductor packaging method according to claim 15 of the patent application, further comprising: Forming a first metal end coupled to the second metal layer exposed at the fifth window, and forming a second metal end coupled to the sixth window at the other end of the substrate The second metal layer. The semiconductor package method of claim 16, wherein the first metal end and the second metal end are selected from at least one of silver or copper.