TW201639149A - Field effect transistor constructions and methods of programming field effect transistors to one of at least three different programmed states - Google Patents

Abstract

A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Description

Field effect transistor structure and method for staging a field effect transistor into one of at least three different stylized states

Embodiments disclosed herein relate to field effect transistor structures and to methods for staging field effect transistors into one of at least three different stylized states.

A type of memory system integrated circuit that is used in computer systems for storing data. The memory can be fabricated in one or more arrays of individual memory cells. Digital lines (which may also be referred to as bit lines, data lines, sense lines or data/sensing lines) and access lines (which may also be referred to as word lines) may be written to the memory unit or Memory unit read. The digit lines can electrically interconnect the memory cells along the rows of the array, and the access lines can electrically interconnect the memory cells along the columns of the array. Each memory cell can be uniquely addressed by a combination of a bit line and an access line.

The memory unit can be volatile or non-volatile. Non-volatile memory units can be stored for extended periods of time, including when the computer is turned off. The volatile memory is dissipated and therefore needs to be renewed/rewritten multiple times per second in multiple instances. In any event, the memory unit is configured to retain or store the memory in at least two different selectable states. In a binary system, the state is treated as a "0" or a "1". In other systems, at least Some individual memory cells can be configured to store more than two levels or states of information.

An effect cell system can be used for one type of electronic component in a memory cell. The transistors include a pair of conductive source/drain regions with a half of the conductive channel region therebetween. A conductive gate is adjacent to the channel region and is separated therefrom by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is prevented from flowing through the channel region to a great extent. Field effect transistors may also include additional construction, such as a reversible programmable charge storage region that is part of the gate structure. A transistor other than a field effect transistor (e.g., a bipolar transistor) may additionally or alternatively be used in the memory cell. The transistor can be used in many types of memory. In addition, transistors can be used and formed in arrays other than memory.

One type of electromorphic system, a ferroelectric field effect transistor (FeFET), wherein at least some portion of the gate structure comprises a ferroelectric material. These materials are characterized by two stable polarization states. By different threshold voltages can be (V _t) for different channels, or by a selected operating voltage of the conductive properties of the field effect transistor in such different states of the transistors used. The polarization state of the ferroelectric material can be altered by the application of a suitable stylized voltage, and this results in one of high channel conductance or low channel conductance. The high conductance and low conductance invoked by the ferroelectric state are maintained (at least for a time) after the removal of the programmed gate voltage. The state of the channel conductance can be read by applying a smaller drain voltage that does not disturb the ferroelectric polarization.

3-3‧‧‧ line

10‧‧‧ Field effect crystal structure

10a‧‧‧ Field Effect Crystal Structure

10b‧‧‧ Field effect crystal structure

10c‧‧‧ Field Effect Crystal Structure

10d‧‧‧ Field effect crystal structure

10e‧‧‧ Field Effect Crystal Structure

10f‧‧‧ Field Effect Crystal Structure

10g‧‧‧ field effect crystal structure

10m‧‧‧ field effect crystal structure

12‧‧‧Semiconducting channel core/semiconductor channel core

12d‧‧‧Semiconducting channel core/semiconductor channel core

12f‧‧‧Semiconducting channel core/semiconductor channel core

14‧‧‧Source/bungee area

16‧‧‧Source/bungee area

18‧‧‧ gate

18a‧‧‧ gate

18b‧‧‧ gate

18c‧‧‧ gate

18m‧‧‧ gate

20‧‧‧Gate insulator/dielectric material/tunnel dielectric/non-ferroelectric

20a‧‧‧gate insulator

20d‧‧‧gate insulator

20e‧‧‧gate insulator

20f‧‧‧gate insulator

20g‧‧‧gate insulator

22‧‧‧Local area

22a‧‧‧Local area

22f‧‧‧Local area

22g‧‧‧Local area

23‧‧‧Local area

23a‧‧‧Local area

23f‧‧‧Local area

23g‧‧‧Local area

24‧‧‧Local area

24a‧‧‧Local area

24f‧‧‧Local area

24g‧‧‧Local area

25‧‧‧Local area

25a‧‧‧Local area

25f‧‧‧Local area

25g‧‧‧Local area

26‧‧‧ Ferroelectric materials/ferroelectrics

26m‧‧‧ferroelectric materials/ferroelectrics

28‧‧‧Electrical materials

28m‧‧‧conductive materials

30‧‧‧Dielectric materials

32‧‧‧Charge trapping materials

36‧‧‧Local area

36e‧‧‧Local area

37‧‧‧Local area

37e‧‧‧Local area

38‧‧‧Local area

38e‧‧‧Local area

39‧‧‧Local area

39e‧‧‧Local area

40‧‧‧Local area

40e‧‧‧Local area

41‧‧‧Local area

41e‧‧‧Local area

1 is a diagrammatic perspective view of one of a portion of a substrate segment including a field effect transistor structure in accordance with an embodiment of the present invention.

Figure 2 is a view of the structure of Figure 1 for removing a material for the sake of brevity.

Figure 3 is a cross-sectional view taken through line 3-3 of Figure 1.

Figure 4 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure.

Figure 5 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure.

Figure 6 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure.

Figure 7 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure with one of the materials removed for simplicity.

Figure 8 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure with one material removed for simplicity.

Figure 9 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure with one of the materials removed for simplicity.

Figure 10 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure with one of the materials removed for simplicity.

Figure 11 is a diagrammatic cross-sectional view of one of the portions of the substrate of Figure 1 in a stylized state.

Figure 12 is a diagrammatic cross-sectional view of one of the portions of the substrate of Figure 1 in a stylized state.

Figure 13 is a diagrammatic cross-sectional view of one of the portions of the substrate of Figure 1 in a stylized state.

Figure 14 is a diagrammatic cross-sectional view of one of the portions of the substrate of Figure 1 in a stylized state.

Figure 15 is a cross-sectional view of a portion of an alternative embodiment of a transistor structure.

An exemplary field effect transistor structure in accordance with an embodiment of the present invention is first described with reference to FIGS. 1 through 3. For the sake of simplicity, this shows that there is no transistor structure 10 surrounding one of the materials and circuits. Other components of the integrated circuit may be contoured outward, contoured inward, and/or to the side relative to the crystal structure 10. In addition, a plurality of such transistors will be able to construct portions of the integrated circuit, for example, an array of such transistors that can be used in memory circuits, logic circuits, or other circuits.

Any of the materials and/or structures described herein may be homogeneous or heterogeneous, and How can it be continuous or intermittent above any material so covered. As used herein, "different ingredients" need only be chemically and/or physically different from the two stated materials that directly abut each other (eg, if such materials are not homogeneous). If the two stated materials do not directly abut each other, the "different components" need only be chemically and/or physically different from the two stated materials that are closest to each other (if such materials are not homogeneous). In this document, a material or construction "directly abuts" the other when there is a touch contact with at least one entity that states the material or structure relative to each other. In contrast, "directly", "above" and "resistance" without "directly" before it cover "directly resist" and intermediate materials Or the construction does not result in a structure that states that the material or construction is in physical contact with respect to each other. In addition, unless otherwise stated, various materials may be formed using any suitable or yet to be developed technique, in which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples. .

The field effect transistor structure 10 is shown as being vertically oriented, although horizontal orientation or orientation other than vertical or horizontal may be used. In this document, the vertical system is generally orthogonal to one of the horizontal directions, wherein horizontal refers to one of the general directions along a major surface (which is processed relative to a substrate during manufacture). Moreover, the vertical and horizontal axes as used herein are independent of the generally perpendicular direction of the substrate orientation in three-dimensional space relative to each other. In addition, the contours, upper and lower are referenced to the vertical direction. Moreover, in the context of this document, a vertically oriented transistor is characterized by a primary current flowing through the channel in a vertical direction. A horizontally oriented transistor is characterized by a primary current flowing through the channel in a horizontal direction.

The field effect transistor structure 10 includes one half of the conductive channel core 12 and one of the source/drain regions 14, 16 at the opposite ends of the channel core 12. Any suitable and suitably doped semiconducting material can be used, for example, single crystal germanium or polycrystalline germanium. The crystal structure 10 can be either n-type or p-type, and LDD, halo or other regions (not shown) can be formed as part of the components 12, 14 and/or 16. A gate 18 is adjacent to one of the perimeters of the channel core 12, with a gate insulator (i.e., electricity) 20 being provided between the gate 18 and the channel core 12. In one embodiment, the gate 18 is completely enclosed The channel core 12 is wound, and in one embodiment, the gate insulator 20 completely surrounds the channel core 12. Gate 18 may be comprised of any suitable electrically conductive (i.e., electrically) material, such as one or more of a conductive doped semiconducting material, an elemental metal, an alloy of elemental metals, and a conductive metal compound. In an embodiment, the gate 18 can include a charge trapping material as will be described below. Exemplary radial thicknesses for channel core 12, gate insulator 20, and gate 18 are about 100 angstroms to 300 angstroms, about 10 angstroms to 100 angstroms, and about 50 angstroms to 400 angstroms, respectively.

In one embodiment, the gate insulator has a partial region extending radially therethrough, the local regions having different (ie, at least two) capacitances at different circumferential locations relative to the perimeter of the channel core, eg, four such Local regions 22, 23, 24 and 25 are designated as in Figure 3. For example, different capacitances may be achieved by one or both of different components or different thicknesses between at least two of the partial regions 22, 23, 24, and 25. The gate insulator may be homogeneous around the channel core 12 or may be non-homogeneous around the channel core 12. In any event, in one embodiment, the local regions individually and collectively have at least one of at least two different radial thicknesses, wherein Figure 3 shows that each has a constant radial thickness but has two different radial thicknesses in common. Local areas 22, 23, 24 and 25. Figure 3 depicts, as an example, partial regions 22 and 24 having the same and constant radial thickness. The partial regions 23 and 25 also have the same and constant radial thickness but have a value less than one of the thicknesses of the partial regions 22 and 24. Alternatively, as an example, the partial regions may have a constant radial thickness individually and collectively (not shown in Figures 1-3), wherein the different components between the at least two locations are relative to the perimeter of the channel core Different capacitances are achieved at different circumferential positions. In addition, fewer than four or more partial regions may be used, regardless of whether the number of partial regions is even or odd.

In one embodiment, the gate insulator 20 comprises a ferroelectric material. Any suitable ferroelectric material that is currently available or still to be developed can be used. Examples include a ferroelectric having one or more of a transition metal oxide, zirconium, zirconium oxide, hafnium, tantalum oxide, lead zirconate titanate, and barium titanate, and may have a dopant therein, including germanium, One or more of aluminum, lanthanum, cerium, lanthanum, calcium, magnesium, cerium and a rare earth element. Two specific examples are Hf _x Si _y O _z and Hf _x Zr _y O _z .

Alternatively, the gate insulator 20 may not include any ferroelectric material, and in one embodiment, the transistor structure 10 does not have any ferroelectric material. In the context of this document, any ferroelectric material does not have a structure that means that it does not have any region that exhibits iron polarization switching. Exemplary non-ferroelectric materials include one or more of cerium oxide, cerium nitride, and cerium oxide. In one embodiment in which the gate insulator comprises a ferroelectric material, the ferroelectric material directly abuts the semiconducting channel core 12, as shown (eg, an MFS structure). In one embodiment in which the gate insulator 20 comprises a ferroelectric material, a non-ferroelectric material (not shown) may be between the ferroelectric material and the channel core 12 (eg, an MFIS structure).

4 depicts an alternative embodiment field effect transistor structure 10a with respect to one of the field effect transistor structures shown by FIG. The same element symbols from the above embodiments have been used where appropriate, some of which are indicated by the suffix "a". The gate insulator 20a is shown to have a substantially constant radial thickness around the channel core 12 (ie, at locations other than the four corner regions due to the variable diagonal thickness). Different capacitances can be achieved by using different components in at least some of at least any of the two partial regions 22a, 22b, 22c, and 22d. Any other property or structure as described above can be used.

FIG. 5 depicts an alternative embodiment field effect transistor structure 10b with respect to one of the field effect transistor structures illustrated by FIGS. 3 and 4. The same element symbols from the above-described embodiments have been used where appropriate, some of which differ from the use of the suffix "b" or the use of different component symbols. Structure 10b includes a ferroelectric material 26 that is radially inward toward gate 18b. The electrically conductive material 28 is radially inward toward the ferroelectric material 26, wherein both the ferroelectric material 26 and the electrically conductive material 28 are radially outward from the gate insulator 20. The ferroelectric material 26 can have any suitable composition, such as the ferroelectric materials described above. Likewise, conductive material 28 can have any suitable composition, such as those described above with respect to gate 18, and material 28 can have components that are the same or different from the composition of material 18. The gate insulator 20 can be a non-ferroelectric, wherein in one example, the structure 10b is MFMIS. In addition, those skilled in the art can regard "F" and "I" in a MFMIS transistor structure as a gate insulator of the structure, and put the clip in "F" and A conductive material M between "I" is part of the gate insulator structure. Exemplary radial thicknesses for ferroelectric material 26 and conductive material 28 are from about 10 angstroms to about 100 angstroms, respectively, from about 10 angstroms to about 200 angstroms. Any other property or structure as described above can be used.

In an alternate embodiment corresponding to the embodiment of FIG. 5, the ferroelectric material 26 can have any configuration and/or different composition properties as described for the dielectric material 20, regardless of the configuration and compositional properties of the dielectric material 20. This alternative embodiment is shown in Figure 15 with respect to a field effect transistor structure 10m. The same element symbols from the above embodiments have been used where appropriate, some of which are indicated by the suffix "m". The exemplary structure 10m has a core structure 12/20a as in the core structure of FIG. 4, in which a conductive material 28m surrounds the structure. The thickness of the ferroelectric material 26m is configured to be similar to the thickness of the dielectric material 20 shown in FIG. Thus, the ferroelectric material 26m has localized regions that extend radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the perimeter of the channel core. Any other property or structure as described above can be used.

Figure 6 illustrates an alternate embodiment field effect transistor structure 10c in the form of a fast lightning crystal structure relative to the field effect transistor structure illustrated by Figures 3 through 5 and 15. The same element symbols from the above-described embodiments have been used where appropriate, with some structural differences being indicated using the suffix "c" or using different component symbols. The gate 18c in the transistor structure 10c is a control gate and the gate insulator 20 is a tunnel dielectric. The dielectric material 30 is radially inward toward the control gate 18c and the charge trapping material 32 is radially inward toward the dielectric material 30. The charge trapping material 32 and the dielectric material 30 are radially outward from the tunneling dielectric 20. Exemplary dielectric 20 comprises one or a combination of cerium oxide and tantalum nitride, and a ferroelectric can be used. An exemplary charge trapping material comprises any of tantalum nitride, aluminum oxide, and ruthenium oxide with or without a suitable dopant. Desirably, the charge trapping material has a material that is a localized energy barrier that prevents electrons from jumping from one location to another within the charge trapping material. Exemplary thicknesses for dielectric material 30 and charge trapping material 32 are from about 5 angstroms to about 200 angstroms, respectively, from about 50 angstroms to about 400 angstroms. Any other property or structure as described above can be used.

In an embodiment in accordance with the invention, a field effect transistor structure includes a gate insulator including at least two pairs of two opposite diameter regions, the partial regions being opposite to the periphery of the channel core Radially extending through the gate insulator at different circumferential locations, at least two of which have different common capacitances. For example, with respect to the embodiment of Figures 1 through 6, local regions 22, 24 (Figures 3, 5, and 6) and local regions 22a, 24a (Figure 4) can be considered to have two representative local regions, respectively. One pair (they are opposite to each other with respect to the channel core 12). The partial regions 23, 25 (Figs. 3, 5, and 6) and the partial regions 23a, 25a (Fig. 4) can be considered as the other two opposite diameter regions at different circumferential positions relative to the channel core 12, respectively. a pair. The common (ie, total) capacitance from the two opposing regions is different from the other pair of the respective transistor structures with respect to each pair. In one embodiment, the individual regions that are individually within each pair have the same capacitance. The attributes just described are also applied to the structure of Fig. 15. Any other property or structure as described above can be used.

1 through 6 and 15 illustrate an exemplary embodiment in which the transistor structure includes only two pairs of opposing diameter partial regions that extend radially through the gate insulator at different circumferential locations relative to the perimeter of the channel core. . Embodiments also anticipate more than two of these pairs (eg, 3, 4, 5, etc.). This alternative exemplary field effect transistor structure 10d is shown in FIG. The same element symbols from the above-described embodiments have been used where appropriate, some of which differ from the use of the suffix "d" or the use of different component symbols. Figure 7 corresponds to the structural view shown by Figures 3 through 6, and shows only the channel core 12d and closely surrounding the gate insulator 20d for simplicity. Components remote from the radially outward direction can be as described in any of the above embodiments. 3 through 6 and 15 show the semiconducting channel core 12 as having a quadrilateral shape (e.g., a rectangle) in a horizontal cross section and the semiconducting channel core 12d in Fig. 7 being a hexagon. By way of example, FIG. 7 shows three pairs of two opposing pairs of partial regions that extend radially through the gate insulator 20d at different circumferential locations relative to the perimeter of the channel core 12d, for example, a pair of 26, 27 ; a pair of 38, 39; and a pair of 40, 41. Figure 7 also shows an exemplary embodiment in which each partial region individually has a length along its respective circumference. The portion has a constant radial thickness and wherein the relative local locations within each pair have the same radial thickness along a majority of their respective circumferential lengths. In addition, the radial extent of the partial regions 38, 39 is greater than the radial thickness of the partial regions 36, 37, which in turn is greater than the radial thickness of the partial regions 40, 41. However, any other property or structure as described above may be used.

Figure 8 depicts an alternative embodiment hexagonal core field effect transistor structure 10e with respect to structure 10d of Figure 7. The same element symbols from the above embodiments have been used where appropriate, some of which are indicated by the suffix "e". Again for the sake of simplicity, only the semiconductor channel core 12d is shown and closely surrounding the gate insulator 20e. In FIG. 8, the gate insulator 20e has a substantially constant radial thickness around the semiconductor via core 12d (ie, at the corner region due to the variable diagonal thickness), whereby the local region 36e, 38e, 40e, 37e, 39e and 41e also have the same radial thickness. Any other property or structure as described above can be used.

The above embodiment depicts a linear straight-faced semiconductor channel core, for example, four sides in FIGS. 1 through 6 and FIG. 15 and six sides in FIGS. 7 and 8. Polygons that replace the shape and the number of faces can be used, and whether they are regular or irregular polygons. In any event, the localized regions may have a radially outermost surface that is linear along at least a majority of their respective circumferential lengths (e.g., in a generally circumferential direction about one of the semiconductor channel cores). Alternative embodiments are contemplated, for example, where the localized regions have a radially outermost surface that is curved along at least a majority of their respective circumferential lengths. This exemplary embodiment field effect transistor structure 10f is shown in FIG. The same element symbols from the above embodiments have been used where appropriate, some of which are indicated by the suffix "f". Again for the sake of simplicity, only the semiconductor channel core 12f and the closely surrounding gate insulator 20f are shown. In structure 10f, the circumference of semiconductor channel core 12f is shown as a circle, although other configurations may be used. The exemplary gate insulator 20f is not shown as being circular, for example, having radial (i.e., average) localized regions 22f, 24f that are thinner than the local regions 23f, 25f. Four or fewer regions may alternatively be used. Any other attribute or knot as described above can be used Structure.

FIG. 10 depicts another embodiment of a field effect transistor structure 10g as an alternative to FIG. The same element symbols from the above embodiments have been used where appropriate, some of which are indicated by the suffix "g". Again for the sake of simplicity, only the semiconductor channel core 12f and the closely surrounding gate insulator 20g are shown. Gate insulator 20g is also circular and coaxial with an exemplary circular outline of semiconductor channel core 12f. Thereby, the gate insulator 20g has a constant radial thickness around the semiconductor channel core 12f, wherein the exemplary partial regions 22g, 23g, 24g and 25g also have a constant radial thickness around the channel core. By way of example, at least two different capacitances of the exemplary four partial regions can be accomplished by varying the composition of the gate insulator material in at least two partial regions. Any other property or structure as described above can be used.

The above configuration can be formed by any existing or yet to be developed. For example, a horizontal trench that is elongated in length may be initially formed as a semiconductive material relative to the formation of the four-sided semiconductor channel core. A suitable insulator material may be used to coat the sidewalls of the semiconducting material of the trenches with a suitable insulator component. Next, the horizontal trenches may be formed to be orthogonal to the initially formed trenches, thereby forming a four-sided semiconductive pillar that will individually constitute the semiconductor channel core of the individual field effect transistor structure. At this point, both of the opposing faces of the cores are covered by the gate insulator liner, while other opposing faces are not. Next, an additional insulator material (having the same or a different composition than the first material) may be deposited to lining the surface of the previously unlined core of the core and additionally lateral/radial deposition onto the previously deposited gate insulator. Thereby, the semiconductor channel core surface on which the first insulator is deposited will be radially thicker than the other sidewalls of the semiconductor channel core. Alternative or additional processing may occur whereby the particular different circumferential locations around a channel core are covered or exposed while laterally forming gate insulators over some partial regions rather than other regions.

Field effect transistor having different capacitances at different locations around the circumference of the core of a semiconductor channel of the above embodiment may be in accordance with the total V _t by different relative to one another at least three characteristics of the state by using different stylized stylized. A first example is described with reference to the embodiment of Figs. 1 to 3 in which the gate insulator 20 is ferroelectric. Figures 11, 12, 13 and 14 may or may display four different programmable state V _t. Again for the sake of simplicity, the figures show only the ferroelectrics 20 surrounding the semiconductor channel core 12. Each of the two possible ferroelectric states is shown in the respective regions 22, 23, 24, and 25 by an arrow indicating one of the two directions of iron polarization in each of the regions.

Figure 11 shows a single polarization state in which localized regions are polarized in the same polarization state, with all arrows pointing radially outward, which is referred to hereinafter as "outer arrow" for convenience. Figure 14 shows another single polarization state in which local regions are polarized in other identical polarization states, with all arrows pointing radially inward, which is referred to hereinafter as the "inner arrow" for convenience. Any state can be directly reached from any previous state by applying a suitable gate staging voltage sufficient to change any relative state to the desired state. Any localized area that is already in the desired state will simply remain there after applying the polarization changing voltage.

Figures 12 and 13 show possible mixed polarization states. For example, if in the stylized state of FIG. 11, if the total capacitance of the thinner relative partial regions 23, 25 is greater than the total capacitance of the thicker local regions 22, 24, a stylized voltage can be applied to the surrounding gate (not As shown in Figures 11-14, the stylized voltage is sufficient to reverse the direction of polarization in the thinner regions 23, 25 to the inner arrow, but not large enough to reverse the direction in the thicker regions 22, 24. The inward arrow thus causes the stylized state from Figure 11 to proceed to the stylized state of Figure 12. Similarly, Figure 14 can be applied by applying a suitable stylized voltage that is sufficient to invert the polarization in the thinner localized region to the outer arrow but not to reverse the polarization in the thicker local region to the outer arrow. The stylized state obtains the stylized state of Figure 13.

In each of the four exemplary stylized person's state, the field effect transistor structure having different V _t with respect to each one of those other programmable state. For example, although the local threshold voltage or local capacitance along a circumferential length of one of the channel core surfaces may vary for different local regions of the gate insulator, this individually contributes to the entire transistor device in each case. One of the common or total V _t , which is effectively different from V _t of any of the other stylized states.

Although the above description with respect to FIGS. 11 to 14 refers to the embodiment of FIGS. 1 to 3 in which the insulator 20 is a ferroelectric, this is also applied to FIGS. 5 and 15 with respect to the ferroelectric 26/26m. An embodiment. For example, the polarization change can occur with different stylized voltages to the polarization change of one of the four states depicted in Figures 11-14, but occurs in the ferroelectric 26/26m instead of A non-ferroelectric body 20. This is due to the different capacitances provided across the localized regions of the insulator 20 due to different radial thicknesses and/or material compositions.

Similarly, where different capacitances (ie, different local capacitances) are provided in different localized regions due to different compositions within the insulator 20a/20d/20e/20f/20g, different stylized voltages can be used to cause The difference in structure is the total V _t 's, thus defining different stylized states.

Similar stylization can occur in one of the flash devices of Figure 6 due to different local capacitances at two (at least two) different circumferential positions relative to one of the perimeters of a channel core. In this case, different stylized voltages caused by the amount of change in charge injected into the charge trapping material at different circumferential positions due to the changing polarization not from a ferroelectric, but due to different local capacitances Get different V _t .

Embodiments of the invention include methods that do not require a stylized field effect transistor that encompasses one or more of the above described architectural attributes. In this exemplary embodiment, a method includes staging a ferroelectric field effect transistor to one of at least three different program states characterized by different V _t (ie, total V _t ) relative to each other. The programmed transistor includes a semiconductor channel core. The ferroelectric material is close to one of the perimeters of the channel core. A gate is close to one of the ferroelectric materials. Comprises a stylized stylized voltage is applied to the gate, the voltage reversal in stylized rather than in the direction of polarization of the ferroelectric material at the other circumferential positions of a circumferential position so that the transistor is applied to the free V _t V _t which is changed before the programmable voltage. The above exemplary method of exemplifying from FIG. 11 to FIG. 12 or from FIG. 14 to FIG. 13 exemplifies these embodiment methods, and is applied to the embodiment of FIG. 3, FIG. 4 or FIG.

In accordance with an embodiment of the present invention, a method comprises a ferroelectric field effect transistor is programmable by four different V _t at least one of the available programmable state relative to each other different characteristics of the person. The transistor includes a semiconductor channel core having at least four radially outermost surfaces that are linear along at least a majority of their respective circumferential lengths. A ferroelectric material is near the outermost surface. A gate is close to one of the ferroelectric materials. The stylization method includes applying a stylized voltage to the gate, the stylized voltage reversing the polarization direction within the ferroelectric material above the opposite surface of the at least four surfaces without reversing at least four The direction of polarization within the ferroelectric material above the surface opposite the surface. Further, the method of performing the stylization in FIG. 11 to FIG. 12 and from FIG. 14 to FIG. 13 exemplifies these methods.

Similar stylization can occur with respect to a flash field effect transistor structure. For example, one of the fast lightning crystal structures shown in Figure 6 can be programmed into one of three different stylized states. A stylized state will be a situation in which the charge trapping material surrounding the channel core is fully loaded with a charge. Another state would be the case where the charge trapping material is fully discharged around the channel core completely circumferentially. A third state would be the case where the charge trapping material in one of the two pairs of opposing diameter regions is sufficiently loaded with charge and the other pair of opposite diameter regions is loaded with a lower amount of charge than the region of sufficient load. Thereby, providing a total of three different V _t 's, one for each different state and may be sensed. The third intermediate state of charge can be directly reached from the fully discharged state.

Example comprises a field effect transistor is a stylized relative to each other by different V _t of the characteristics of at least one of the available three different programmable state by the method according to one of the present invention. The transistor includes a semiconductor channel core. A tunneling dielectric is adjacent to one of the cores of the channel. The charge trapping material is near one of the perimeters of the tunneling dielectric. The external dielectric is near the perimeter of one of the charge trapping materials. The conductive control gate material is adjacent to one of the outer dielectrics. The method includes a stylized stylized voltage is applied to the control gate, the programmable voltage different quantum electron injection to the charge trapping at different circumferential positions of the material to make the transistor V _t is applied to the programmable voltage free before the Its V _t changes. The above treatment, which has just been described with respect to a fast lightning crystal structure, is an example of self-discharge to an intermediate state of charge.

Some embodiments of the invention encompass field effect transistor structures that are independent of whether the gate insulator has a local region having a different capacitance radially across the different circumferential locations relative to the perimeter of the channel core. In this embodiment, a field effect transistor structure includes a semiconductor channel core and a source/drain region at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A ferroelectric gate insulator is between the gate and the channel core. The ferroelectric gate insulator has a partial region extending radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the perimeter of the channel core. In one embodiment, such local regions having different radial thicknesses have different capacitances relative to each other. Any other property or structure as described above can be used.

In another such embodiment, a field effect transistor structure includes a semiconductor channel core and a source/drain region at the opposite end of the channel core. A gate structure is adjacent to one of the perimeters of the channel core. An outer conductive material approaches the perimeter of the channel core. The outer ferroelectric material approaches the outer periphery of the channel core radially inward toward the outer conductive material. The inner conductive material approaches the outer periphery of the channel core radially inward toward the outer ferroelectric material. The inner dielectric is radially between the inner conductive material and the channel core, wherein the inner dielectric has a partial region extending radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the perimeter of the channel core . In one embodiment, local regions having different radial thicknesses have different capacitances relative to each other. Any other property or structure as described above can be used.

In one embodiment, a field effect transistor structure includes a semiconductor channel core having one of four radially outermost surfaces that are linear along at least a majority of their respective circumferential lengths. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A gate insulator is between the gate and the channel core above each of the four surfaces. Above the four surfaces, the two opposite diameters are above the opposite surface The gate insulator is radially thinner than the gate insulator above the two opposing surfaces opposite the four surfaces. In one embodiment, the radially thinner gate insulator provides a local capacitance that is greater than the gate insulator provided above both after the opposite diameters of the four surfaces.

to sum up

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A gate insulator is between the gate and the channel core. The gate insulator has a partial region extending radially therethrough, the local regions having different capacitances at different circumferential locations relative to the perimeter of the channel core.

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A ferroelectric gate insulator is between the gate and the channel core, the ferroelectric gate insulator having a partial region extending radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the periphery of the channel core.

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A ferroelectric gate insulator is between the gate and the channel core, the ferroelectric gate insulator having a constant radial thickness around the channel core and the ferroelectric gate insulator having a different composition at different circumferential locations relative to the periphery of the channel core region.

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate structure is adjacent to one of the perimeters of the channel core. The gate structure includes an outer conductive material proximate the perimeter of one of the channel cores. The outer ferroelectric material approaches the outer conductive material radially inwardly toward one of the perimeters of the channel core. The inner conductive material approaches the outer periphery of the channel core radially inward toward the outer ferroelectric material. The internal dielectric is radially between the inner conductive material and the channel core. The inner dielectric has a partial region extending radially therethrough, the partial regions being at different circumferential positions relative to the periphery of the channel core Have different radial thicknesses.

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate structure is adjacent to one of the perimeters of the channel core. The gate structure includes an outer conductive material proximate the perimeter of the channel core. The outer ferroelectric material approaches the outer periphery of the channel core radially inward toward the outer conductive material. The outer ferroelectric material has localized regions extending radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the perimeter of the channel core. The inner conductive material approaches the outer periphery of the channel core radially inward toward the outer ferroelectric material. The internal dielectric is radially between the inner conductive material and the channel core.

In some embodiments, a field effect transistor structure includes a half conductive channel core. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A gate insulator is between the gate and the channel core. The gate insulator includes at least two pairs of opposing regions of opposite diameters that extend radially through the gate insulator at different circumferential locations relative to the perimeter of the channel core. The at least two pairs have different common capacitances.

In some embodiments, a field effect transistor structure includes a semiconducting channel core having one of four radially outermost surfaces that are linear along at least a majority of their respective circumferential lengths. A source/drain region is at the opposite end of the channel core. A gate is near the perimeter of one of the channel cores. A gate insulator is between the gate and the channel core above each of the four surfaces. The gate insulators above the two opposite diameter opposing surfaces before the four surfaces are radially thinner than the gate insulators above the two opposing surfaces opposite the four surfaces.

In some embodiments, a method comprises a ferroelectric field effect transistor is a stylized relative to each other by different V _t characterization of at least three persons using different state of one stylized. The transistor includes a half of the conductive channel core. The ferroelectric material is close to one of the perimeters of the channel core. A gate is close to one of the ferroelectric materials. The method comprises applying a voltage to the gate stylized, rather than the stylized voltage reversal in the direction of polarization of the ferroelectric material at the other circumferential positions of a circumferential position so that the transistor is applied from the V _t It changed before its V _t .

In some embodiments, a method comprises a ferroelectric field effect transistor is programmable by four different V _t at least one of the available programmable state relative to each other different characteristics of the person. The transistor includes a semiconducting channel core having at least four radially outermost surfaces that are linear along at least a majority of their respective circumferential lengths. A ferroelectric material is near the outermost surface. A gate is close to one of the ferroelectric materials. The method includes applying a stylized voltage to the gate, the stylized voltage reversing the polarization direction within the ferroelectric material above the at least four surfaces opposite the opposite surface, without reversing after at least four surfaces The direction of polarization within the ferroelectric material above the opposite surface of the two pairs of diameters.

In some embodiments, the method includes a field effect transistor is a stylized V _t by different relative to each other at least three of the characteristics of one of the available state by different stylized. The transistor includes a half of the conductive channel core. A tunneling dielectric is adjacent to one of the cores of the channel. The charge trapping material is near one of the perimeters of the tunneling dielectric. The external dielectric is near the perimeter of one of the charge trapping materials. The conductive control gate material is adjacent to one of the outer dielectrics. The method includes a programmable voltage applied to the control gate, the programmable voltage different quantum electron injection to the charge trapping at different circumferential positions of the material to make the transistor V _t V _t which is applied prior to the change of free .

In accordance with the Act, the subject matter disclosed herein has been described in a language that is more or less specific to the structure and method features. It should be understood, however, that the invention is not limited to the particular features shown and described, as the method disclosed herein includes exemplary embodiments. Therefore, the scope of the patent application should provide the full scope of the wording as a word, and should be properly explained in accordance with the teachings of the equivalent.

3-3‧‧‧ line

10‧‧‧ Field effect crystal structure

14‧‧‧Source/bungee area

16‧‧‧Source/bungee area

18‧‧‧ gate

Claims (34)

A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; a gate adjacent to a periphery of the channel core; and a gate An insulator between the gate and the channel core, the gate insulator having a partial region extending radially therethrough, the partial regions having different capacitances at different circumferential locations relative to the periphery of the channel core. The structure of claim 1 wherein the gate insulator comprises a ferroelectric material. The structure of claim 2, wherein the ferroelectric material directly abuts the semiconductive channel core. The structure of claim 1, comprising a ferroelectric material radially inward toward the gate and a conductive material radially inward toward the ferroelectric material, the ferroelectric material and the conductive material being radially away from the gate insulator outward. As claimed in claim 1, it does not have any ferroelectric material. The structure of claim 1 is a fast lightning crystal structure, wherein the gate is a control gate and the gate insulation system tunnels through the dielectric and includes a radial inward direction toward the control gate. An electrically conductive material and a charge trapping material radially inward toward the dielectric material, the dielectric material and the charge trapping material being radially outward away from the tunneling dielectric. The structure of claim 1, wherein the gate insulator is homogenous around the channel core. The structure of claim 1, wherein the gate insulator is heterogeneous around the channel core. The structure of claim 1, wherein the partial regions have a constant radial shape individually and collectively thickness. The structure of claim 1, wherein at least one of the partial regions individually and collectively has at least two different radial thicknesses. The structure of claim 1 wherein the partial regions have a radially outermost surface that is linear along at least a majority of their respective circumferential lengths, each of the individual regions having a constant radial thickness . The structure of claim 11, wherein the partial regions collectively have at least two different radial thicknesses. The structure of claim 1, wherein the gate completely surrounds the channel core. The structure of claim 1 wherein the gate insulator completely surrounds the channel core. A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; a gate adjacent to a periphery of the channel core; and a ferroelectric gate a pole insulator between the gate and the channel core, the ferroelectric gate insulator having a partial region extending radially therethrough, the partial regions having different radial thicknesses at different circumferential locations relative to the periphery of the channel core . The structure of claim 15 wherein the local regions having different radial thicknesses have different capacitances relative to each other. A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; a gate adjacent to a periphery of the channel core; and a ferroelectric gate a pole insulator between the gate and the channel core, the ferroelectric gate insulator having a constant radial thickness around the core of the channel, the ferroelectric gate insulator having a different circumferential position relative to a periphery of the channel core to make Partial area. A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; and a gate structure adjacent to a periphery of the channel core, the gate The structure includes an outer conductive material proximate the perimeter of the channel core, an outer ferroelectric material that is radially inward toward the periphery of the channel core toward the outer conductive material, and an inner conductive material that is radially inward toward the outer ferroelectric material Adjacent to the periphery of the core of the channel; and an internal dielectric radially between the inner conductive material and the core of the channel, the inner dielectric having a partial region extending radially therethrough, the partial regions being opposite to the channel There are different radial thicknesses at different circumferential locations around the core. The structure of claim 18, wherein the partial regions having different radial thicknesses have different capacitances relative to each other. A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; and a gate structure adjacent to a periphery of the channel core, the gate The structure includes: an outer conductive material proximate to a periphery of the channel core; an outer ferroelectric material that is radially inward toward the outer periphery of the channel core toward the outer conductive material, the outer ferroelectric material having a partial region extending radially therethrough, The local area is at a different circumferential position relative to the periphery of the core of the channel There are different radial thicknesses; an inner electrically conductive material that faces radially inwardly toward the outer periphery of the channel core; and an inner dielectric that is radially between the inner electrically conductive material and the channel core. A field effect transistor structure comprising: a half conductive channel core; a source/drain region at an opposite end of the channel core; a gate adjacent to a periphery of the channel core; and a gate An insulator between the gate and the channel core, the gate insulator comprising at least two pairs of opposite partial regions of opposite diameters, the partial regions extending radially at different circumferential locations relative to the periphery of the channel core Through the gate insulator, the at least two pairs have different common capacitances. As with the structure of claim 21, it includes only the pair. The structure of claim 21 includes both of the pairs. The structure of claim 21, wherein the partial regions have a radially outermost surface that is linear along at least a majority of their respective circumferential lengths. The structure of claim 21, wherein the partial regions have a radially outermost surface that is curved along at least a majority of their respective circumferential lengths. As in the structure of claim 21, wherein the individual regions within each pair have the same capacitance. A field effect transistor structure comprising: a semi-conducting channel core having four radially outermost surfaces, the radially outermost surfaces being straight along at least a majority of their respective circumferential lengths; a source/drain region at an opposite end of the channel core; a gate adjacent one of the perimeters of the channel core; and a gate insulator at the gate above each of the four surfaces Between the pole and the core of the channel, the gate insulator above the two opposing surfaces opposite the four surfaces is radially thinner than the gate insulator above the two opposing surfaces opposite the four surfaces. The structure of claim 27, wherein the radially thinner gate insulator provides a local capacitance greater than that provided by the gate insulator above the latter two. A method of staging a ferroelectric field effect transistor into one of at least three different stylized states characterized by different V _t relative to each other; the transistor comprising one half of the conductive channel core, adjacent to one of the channel cores a peripheral ferroelectric material and a gate adjacent to one of the ferroelectric materials; the method comprising: applying a stylized voltage to the gate, the stylized voltage being reversed at a circumferential location rather than another the direction of polarization within the ferroelectric material at a circumferential position to make the transistor of V _t V _t which is applied prior to the change of freedom. The method of claim 29, wherein the ferroelectric material directly abuts the channel core. The method of claim 29, wherein the transistor comprises another dielectric directly opposite the periphery of the semiconductive channel core and another gate directly adjacent to a periphery of the other dielectric, the iron The electrical system directly abuts the dielectric surrounding one of the other gates. The method of claim 31, wherein the other dielectric does not have any ferroelectric material. A ferroelectric field effect transistor is a stylized V _t is different by at least by one of four different methods available programmable characteristics of the state opposite to each other; comprising the transistor having at least a half of the four outermost radial surface a conductive channel core, the radially outermost surfaces being linear along at least a majority of their respective circumferential lengths, the ferroelectric material being proximate to the outermost surfaces, and a gate proximate to one of the ferroelectric materials; The method includes: applying a stylized voltage to the gate, the stylized voltage reversing a polarization direction in the ferroelectric material above the two opposite diameter surfaces before the at least four surfaces without inverting at least The two opposite diameters of the four surfaces are opposite to the direction of polarization within the ferroelectric material above the surface. A method of staging a mode transistor into one of at least three different stylized states characterized by different V _t relative to each other; the transistor comprising a half of the conductive channel core, proximate to a periphery of the channel core a tunneling dielectric, a charge trapping material proximate to a periphery of the tunneling dielectric, an external dielectric proximate to a periphery of the charge trapping material, and a conductive control gate material proximate to a periphery of the external dielectric The method includes applying a stylized voltage to the control gate, the stylizing voltage injecting different quantum electrons into the charge trapping material at different circumferential positions such that V _{t of the} transistor is free of the application It changes with its V _t .