TW201637089A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor technology, and more particularly to a semiconductor device and a method of fabricating the same.

Etching is a very important process module, and the etching is mainly in the form of wet etching and dry etching. Dry etching is to ionize or dissociate the reaction gas in the reaction chamber to generate plasma, and accelerate the reactive ions to the wafer, and drive the etching reaction by chemical reaction between the ions and the material to be etched on the surface of the wafer. .

At present, in order to increase the wafer throughput of the production machine, it is necessary to use high-power plasma to increase the etching speed. However, when high-power plasma etching is used to form via openings or contact openings, the metal layer at the bottom of the opening is susceptible to splashing onto the sidewalls of the opening due to high power plasma, which will result in sidewalls of the opening. Residues (such as metal polymers) are produced. The above-mentioned residue is not easily removed in the subsequent process, which causes abnormal conduction of the semiconductor element, thereby causing a short circuit.

The present invention provides a semiconductor device and a method of fabricating the same that avoids the generation of residues on the sidewalls of the opening in the step of defining the opening.

The present invention provides a method of manufacturing a semiconductor device. First, a dielectric layer is formed on the barrier layer. Next, a first opening is formed in the dielectric layer. The first opening exposes a portion of the barrier layer. Then, a protective layer is formed on the barrier layer at the bottom of the first opening. The thickness of the central portion of the protective layer is greater than the thickness of the edge portion. Then, with the protective layer as a mask, a portion of the barrier layer is removed to form a second opening. The second opening has at least one secondary opening located in the barrier layer adjacent the sidewall of the second opening.

In an embodiment of the invention, the bottom of the second opening has a W-shaped cross-sectional shape.

In an embodiment of the invention, the method of forming the first opening and the second opening each comprises performing a plasma etching method.

In an embodiment of the invention, the etching gas used to form the first opening includes nitrogen gas, and the flow rate of the nitrogen gas increases as the depth of the first opening increases.

In an embodiment of the invention, the etching gas used to form the second opening includes sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), argon (Ar), and fluorocarbon gas (C _x F _y ) and nitrogen, wherein x and y are both greater than zero.

In an embodiment of the invention, a protective layer is formed on the barrier layer at the bottom of the first opening while forming the first opening in the dielectric layer.

In an embodiment of the invention, the method further includes: forming a shallow opening in the dielectric layer before forming the first opening in the dielectric layer; and performing an anisotropic etching process to deepen the shallow opening, and further A first opening is formed in the electrical layer, wherein the gas used to form the shallow opening does not contain nitrogen.

The present invention further provides a semiconductor device including a barrier layer and a dielectric layer. The dielectric layer is on the barrier layer. The dielectric layer has an opening therein, the opening exposing a portion of the barrier layer, wherein the opening has at least one secondary opening, the secondary opening being located in a barrier layer adjacent the sidewall of the opening.

In an embodiment of the invention, the bottom of the opening has a W-shaped cross-sectional shape.

In an embodiment of the invention, the thickness of the barrier layer at the middle bottom of the opening is greater than the thickness of the barrier layer at the bottom of the secondary opening and less than the thickness of the barrier layer under the dielectric layer.

Based on the above, in the method of the present invention, while performing an etching process to form a U-shaped opening, a protective layer is formed on the barrier layer at the bottom of the U-shaped opening, and the protective layer is used as a mask to continue the etching process. And adjust the flow rate of nitrogen to form a W-shaped opening. Moreover, the protective layer can be used to prevent the barrier layer from splashing onto the sidewall of the opening due to the use of high radio frequency power plasma, thereby preventing residue on the sidewall of the opening, thereby improving the performance of the component.

The above described features and advantages of the invention will be apparent from the following description.

1A-1G are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention.

Referring to FIG. 1A, first, a substrate 10 is provided. The material of the substrate 10 may include a semiconductor material, an insulator material, a conductor material, or any combination of the above. The material of the substrate 10 is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In an embodiment, the material of the substrate 10 is, for example, tantalum or niobium. Further, the substrate 10 may have a single layer structure. Alternatively, the substrate 10 may be a multilayer structure including a conductor layer, a dielectric layer, a gate structure, and the like.

Next, a barrier layer 12 is formed on the substrate 10. The material of the barrier layer 12 includes titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. In an embodiment, the material of the barrier layer 12 is, for example, a combination of titanium and titanium nitride. In another embodiment, the material of the barrier layer 12 is, for example, a combination of tantalum and tantalum nitride. The formation method of the barrier layer 12 is, for example, a chemical vapor deposition method or a physical vapor deposition method. The thickness of the barrier layer 12 is, for example, between 300 Å and 1,000 Å.

Then, a dielectric layer 14 is formed on the barrier layer 12. The material of the dielectric layer 14 includes an oxide, a nitride, an oxynitride, or a combination thereof. In an embodiment, the material of the dielectric layer 14 is, for example, yttrium oxide. In another embodiment, the dielectric layer 14 can also be a layer of dielectric material having a dielectric constant of less than four. The method of forming the dielectric layer 14 is, for example, a thermal oxidation method or a chemical vapor deposition method. The thickness of the dielectric layer 14 is, for example, between 1,000 Å and 15,000 Å. Thereafter, a patterned mask layer 16 is formed on the dielectric layer 14. The material of the patterned mask layer 16 is, for example, a photoresist.

Next, referring to FIG. 1B , the mask layer 16 is patterned as a mask, and an etching process S1 is performed to remove a portion of the dielectric layer 14 to form a shallow opening 15 in the dielectric layer 14 . The etching process S1 includes an anisotropic etching process, such as a dry etching process. The dry etching method may be a plasma etching method. In this embodiment, the etching process S1 is, for example, a plasma etching method having high radio frequency power (RF power). The energy of the plasma etching method for high radio frequency power is, for example, between 1000 watts and 5,000 watts. The etching gas used in the etching process S1 includes sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), argon (Ar), and a fluorocarbon gas (C _x F _y ), wherein x and y are both greater than zero. For example, x is an integer between 1-5 and y is an integer between 4-8. The fluorocarbon gas may include a fluorocarbon, a fluoroolefin or a fluoroacetylene gas. In one embodiment, the etching gas used in the etching process S1 does not contain nitrogen.

It is worth mentioning that deposits 20 are formed on the dielectric layer 14 at the bottom of the shallow opening 15 while forming the shallow openings 15 in the dielectric layer 14. The deposit 20 is, for example, a polymer residue obtained by reacting the above-described etching gas used in the etching process S1.

The depth D of the shallow opening 15 is, for example, about 1/2 to 4/5 of the thickness h1 of the dielectric layer 14. More specifically, the shallow opening 15 does not penetrate the dielectric layer 14, and the sum of the depth D of the shallow opening 15 and the thickness h2 of the dielectric layer below the shallow opening 15 is substantially equal to the thickness h1 of the dielectric layer 14. In one embodiment, the thickness h1 of the dielectric layer 14 is, for example, between 8,000 Å and 15,000 Å, and the depth D of the shallow opening 15 is, for example, between 4,000 Å and 12,000 Å. However, the above numerical ranges are merely illustrative and are not intended to limit the invention.

Then, referring to FIG. 1C, the mask layer 16 is patterned as a mask, and an etching process S2 is performed to deepen the shallow opening 15, thereby forming an opening 17 in the dielectric layer 14, and the opening 17 is partially exposed. 12. Further, a protective layer 22 is formed on the barrier layer 12 at the bottom of the opening 17. The etching process S2 includes an anisotropic etching process, such as a dry etching process. The dry etching method may be a plasma etching method. The etching gas used in the etching process S2 is different from the etching gas used in the etching process S1. The etching gas used in the etching process S2 contains nitrogen gas; and the etching gas used in the etching process S1 does not contain nitrogen gas. In one embodiment, the etching process S2 is, for example, a plasma etching method having high radio frequency power, the energy of which is, for example, between 1000 watts and 5,000 watts. The etching gas used in the etching process S2 includes sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), argon (Ar), fluorocarbon gas (C _x F _y ), and nitrogen, wherein x and y are both Greater than zero, for example x is an integer between 1-5 and y is an integer between 4-8. Further, the flow ratio of nitrogen to fluorocarbon gas is, for example, about 1:6 to 1:4.

In an embodiment, the flow of nitrogen used to form the opening 17 increases as the depth of the opening 17 increases. For example, the flow rate of nitrogen used at the beginning of the etching process S2 is, for example, between 0 sccm and 50 sccm. Thereafter, as the depth of the opening 17 increases, the flow rate of nitrogen gas is adjusted to be between 50 sccm and 300 sccm. However, the invention is not limited thereto. Those skilled in the art to which the present invention pertains can adjust the flow rate of nitrogen gas as needed.

In one embodiment, the protective layer 22 is formed on the barrier layer 12 at the bottom of the opening 17 while the opening 17 is formed in the dielectric layer 14 while the etching process S2 is being performed. In other words, the protective layer 22 and the opening 17 are formed at the same time. In this embodiment, the protective layer 22 is, for example, a polymer residue obtained by reacting the above etching gas used in the etching process S2. The material of the protective layer 22 includes a polymer containing carbon, fluorine, and nitrogen. In an embodiment, the material of the protective layer 22 is, for example, a C _x F _y N _z polymer, wherein x, y, and z are all greater than zero. The thickness of the protective layer 22 may be uniform or non-uniform. In an embodiment, the thickness h3 of the central portion of the protective layer 22 is, for example, greater than the thickness h4 of the edge portion of the protective layer 22. In another embodiment, the protective layer 22 is, for example, covered with a portion of the barrier layer 12 to expose a portion of the barrier layer 12 adjacent the sidewalls of the opening 17. Alternatively, the edge portion of the protective layer 22 may have an extremely thin thickness to facilitate subsequent etching processes to remove the extremely thin edge portion and the portion of the barrier layer 12 underneath.

1D and FIG. 1E, with the protective layer 22 and the patterned mask layer 16 as a mask, a portion of the barrier layer 12 is removed to form an opening 19 in the dielectric layer 14, and the opening 19 is through the dielectric. Layer 14. Specifically, the protective layer 22 is gradually consumed in the step of forming the opening 19, while at least one secondary opening 19a is formed in the barrier layer 12 on at least one side of the protective layer 22, as shown in FIG. 1D. In an embodiment, the secondary opening 19a can be disposed around the protective layer 22. When the protective layer 22 is exhausted, a portion of the barrier layer 12 at the middle bottom of the opening 19 is also removed and the secondary opening 19a is also deepened, as shown in FIG. 1E. In an embodiment, in the step of FIG. 1E, the protective layer 24 is also formed on the barrier layer 12 at the middle bottom of the opening 19. The protective layer 24 is similar in material to the protective layer 22. Specifically, the protective layer 24 is the same as the main components (for example, C, F, and N) of the protective layer 22, but the ratios between the elements are different. In an embodiment, the bottom of the opening 19 has a W-shaped cross-sectional shape. The opening 19 can have at least one secondary opening 19a. The secondary opening 19a is, for example, located in a portion of the barrier layer 12 adjacent the sidewall of the opening 19. The depth D1 of the secondary opening 19a is, for example, between about 1/3 and 2/3 of the thickness of the barrier layer 12. In this embodiment, the thickness h5 of the barrier layer 12 at the intermediate bottom of the opening 19 is, for example, greater than the thickness h6 of the barrier layer 12 at the bottom of the secondary opening 19a. Further, the thickness h7 of the barrier layer 12 under the dielectric layer 14 is, for example, greater than the thickness h5 of the barrier layer 12 at the intermediate bottom of the opening 19.

In an embodiment of the invention, the etching process S2 includes, for example, the step of forming the opening 17 and the opening 19. Specifically, in the above manufacturing method, when the flow rate of the nitrogen gas increases with the depth of the opening 17 to expose the barrier layer 12, at this time, the protective layer 22 is used as a mask to remove at least one side of the protective layer 22. A portion of the barrier layer 12 is formed to form an opening 19 having at least one secondary opening 19a. The flow rate of the nitrogen gas used to form the opening 19 is, for example, between 50 sccm and 300 sccm. Further, by adjusting the flow rate of nitrogen gas, an opening 19 having a W-shaped cross section can be formed.

It should be noted that in the above etching process S2, the protective layer 22/24 can be used to prevent the barrier layer 12 from splashing onto the sidewall of the opening 17/19 due to the use of high radio frequency power plasma, thereby preventing the opening 17 Residues are produced on the sidewalls of /19.

Thereafter, referring to FIG. 1F, the protective layer 24 and the patterned mask layer 16 are removed. The method of removing the protective layer 24 and the patterned mask layer 16 includes performing a wet etching process.

Next, referring to FIG. 1G, a conductor layer 26 is formed in the opening 19. The material of the conductor layer 26 includes a metal, a metal alloy, a doped polysilicon or a combination thereof. The metal is, for example, tungsten. The metal alloy is, for example, an aluminum-bismuth alloy. The method of forming the conductor layer 26 is, for example, a chemical vapor deposition method. In addition, another barrier layer (not shown) may be formed on the sidewalls and the bottom of the opening 19 before forming the conductor layer 26. The material of the other barrier layer includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. In one embodiment, the material of the other barrier layer is, for example, a combination of titanium and titanium nitride. In another embodiment, the material of the other barrier layer is, for example, a combination of tantalum and tantalum nitride. Another method of forming the barrier layer is, for example, chemical vapor deposition or physical vapor deposition. The thickness of the other barrier layer is, for example, between 10 Å and 100 Å. So far, the fabrication of the semiconductor device 100 is completed.

Hereinafter, the structure of the semiconductor element of the present invention will be described using FIG. 1F. As shown in FIG. 1F, the semiconductor device of the present invention includes a substrate 10, a barrier layer 12, and a dielectric layer 14. The barrier layer 12 is on the substrate 10 and the dielectric layer 14 is on the barrier layer 12. The dielectric layer 14 has an opening 19 therein, and the opening 19 exposes a portion of the barrier layer 12. The opening 19 has at least one secondary opening 19a, and at least one secondary opening 19a is located in the barrier layer 12 adjacent the sidewall of the opening 19. In an embodiment, when the opening 19 is a via opening or a contact opening, a secondary opening 19a is disposed in the barrier layer 12 along the bottom of the opening 19. In another embodiment, when the opening 19 is an opening in the form of a trench, the two secondary openings 19a are respectively disposed in the barrier layer 12 along opposite sides of the bottom of the opening 19. However, regardless of the above, the bottom of the opening 19 has a W-shaped cross-sectional shape.

The thickness h5 of the barrier layer 12 at the intermediate bottom of the opening 19 is, for example, greater than the thickness h6 of the barrier layer 12 at the bottom of the secondary opening 19a. Further, the thickness h7 of the barrier layer 12 under the dielectric layer 14 is greater than the thickness h5 of the barrier layer 12 adjacent to the intermediate bottom of the opening 19. That is, h7>h5>h6. In one embodiment, h7 is between 50 nm and 100 nm; h6 is between 15 nm and 75 nm; and h5 is between 25 nm and 100 nm.

The method for fabricating a semiconductor device according to the embodiment of the present invention can be applied to a dynamic random access memory (DRAM), a NAND flash, a NOR flash, or the like. The invention is not limited thereto.

2 is a photograph of a transmission electron microscope of a semiconductor element in accordance with an example of the present invention.

As shown in FIG. 2, the thickness h8 of the barrier layer at the middle bottom of the opening is greater than the thickness h9 of the barrier layer at the bottom of the secondary opening.

In summary, in the method of the present invention, while performing an etching process to form a U-shaped opening (such as the opening 17), a protective layer is formed on the barrier layer at the bottom of the U-shaped opening, and the protective layer is used as a cover. Curtain, continue the etching process described above, and adjust the flow rate of nitrogen to form a W-shaped opening (such as opening 19). Moreover, the protective layer can be used to prevent the barrier layer from splashing onto the sidewall of the opening due to the use of high radio frequency power plasma, thereby preventing residue on the sidewall of the opening, thereby improving the performance of the component.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base
12‧‧‧Barrier layer
14‧‧‧Dielectric layer
15‧‧‧Shallow opening
16‧‧‧ patterned mask layer
17, 19‧‧‧ openings
19a‧‧ openings
20‧‧‧Sediment
22, 24‧‧ ‧ protective layer
26‧‧‧Conductor layer
D, D1‧‧ depth
H1, h2, h3, h4, h5, h6, h7, h8, h9‧‧ thickness
S1, S2‧‧‧ etching process

1A-1G are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention. 2 is a photograph of a transmission electron microscope (TEM) of a semiconductor device in accordance with an example of the present invention.

10‧‧‧Base

12‧‧‧Barrier layer

14‧‧‧Dielectric layer

16‧‧‧ patterned mask layer

19‧‧‧ openings

19a‧‧ openings

24‧‧‧Protective layer

D1‧‧ depth

H5, h6‧‧‧ thickness

S2‧‧‧ etching process

Claims (10)

A method of fabricating a semiconductor device, comprising: forming a dielectric layer on a barrier layer; forming a first opening in the dielectric layer, the first opening exposing a portion of the barrier layer; Forming a protective layer on the barrier layer at the bottom, the central portion of the protective layer has a thickness greater than the thickness of the edge portion; and the protective layer is used as a mask to remove a portion of the barrier layer to form a second opening Wherein the second opening has at least one secondary opening, the secondary opening being located in the barrier layer adjacent to a sidewall of the second opening. The method of manufacturing a semiconductor device according to claim 1, wherein a bottom portion of the second opening has a W-shaped cross-sectional shape. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the first opening and the second opening each comprises performing a plasma etching method. The method of manufacturing a semiconductor device according to claim 3, wherein the etching gas used to form the first opening includes nitrogen gas, and a flow rate of the nitrogen gas increases as the depth of the first opening increases. The method of manufacturing a semiconductor device according to claim 3, wherein the etching gas used for forming the second opening comprises sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), and argon (Ar) ), a fluorocarbon gas (C _x F _y ) and nitrogen, wherein x and y are both greater than zero. The method of fabricating a semiconductor device according to claim 1, wherein the protective layer is formed on the barrier layer at the bottom of the first opening while the first opening is formed in the dielectric layer. The method for fabricating a semiconductor device according to claim 1, further comprising: forming a shallow opening in the dielectric layer before forming the first opening in the dielectric layer; and performing anisotropic etching The process is to deepen the shallow opening to form the first opening in the dielectric layer, wherein the gas used to form the shallow opening does not contain nitrogen. A semiconductor device comprising: a barrier layer; and a dielectric layer on the barrier layer, the dielectric layer having an opening, the opening exposing a portion of the barrier layer, wherein the opening has at least one time An opening located in the barrier layer adjacent to a sidewall of the opening. The semiconductor device according to claim 8, wherein the bottom of the opening has a W-shaped cross-sectional shape. The semiconductor device of claim 8, wherein a thickness of the barrier layer at a middle bottom of the opening is greater than a thickness of the barrier layer at a bottom of the sub-opening and smaller than a barrier under the dielectric layer The thickness of the layer.