TW201633575A - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is disposed in the recess and has a top surface exposed from an opening of the recess. The spacer overlaps a portion of the top surface, by which a contact area is defined on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on and electrically contacts with the memory layer.

Description

Memory element and manufacturing method thereof 【0001】

The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, there is a variable resistive memory (ReRAM) device and a method of fabricating the same.

【0002】

Non-Volatile Memory (NVM) components have the property of not losing information stored in the memory unit when the power is removed. Currently widely used is a Charge Trap Flash (CTF) memory component that uses a charge trap. However, as the accumulation density of memory components increases, the critical size and pitch of the components shrink, and the charge storage type flash memory device faces its physical limit and cannot operate.

[0003]

The variable resistance memory element utilizes the size of the memory element resistance as a basis for interpretation of the information storage state. It is superior to flash memory in terms of device density, power consumption, stylization/erasing speed or three-dimensional space stacking characteristics. Therefore, it has become one of the memory components that have received much attention in the industry.

[0004]

A typical variable resistance memory device includes a vertically stacked lower metal electrode layer/memory layer/upper metal electrode layer stack structure. High density storage of the crossbar array configuration can be achieved. In order to increase the bonding between the metal electrode layer and the substrate, the conventional variable resistance memory device generally forms an alcove on the substrate, and then forms a barrier layer, such as nitrogen, at the bottom of the cavity and the sidewall. Titanium (TiN) barrier layer. The recess is filled with a metal material, such as tungsten (W), to form a lower metal electrode layer, and then an oxide metal layer is formed on the top surface of the lower metal electrode layer by an oxidation or deposition process, as a memory layer, and then a metal oxide. The layer is covered with a metal electrode layer.

[0005]

However, the memory layer formed by the oxidation or deposition process does not easily cover the top surface of the lower metal electrode layer, and may expose the top surface of the lower metal electrode layer to a corner of the sidewall of the recess (including a portion of the barrier layer). Outside. As a result, the upper metal electrode layer that subsequently covers the memory layer may be electrically connected to the lower metal electrode layer and/or the barrier layer, thereby causing a leakage problem or even causing component failure.

[0006]

Therefore, there is a need to provide a more advanced memory component and method of making the same to improve the problems faced by conventional techniques.

【0007】

An embodiment of the present specification is to provide a memory device including: a substrate, a first electrode layer, a spacer, a memory layer, and a second electrode layer. Wherein the substrate has an alcove. The first electrode layer is located in the recess and has an upper surface that is exposed to the outside by the opening of the recess. The spacer covers a portion of the upper surface to define a contact area on the upper surface. A memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and is in electrical contact with the memory layer.

[0008]

Another embodiment of the present specification is to provide a method of fabricating a memory device, the method of fabricating the memory device comprising the steps of: first providing a substrate having at least one recess and forming a first in the recess; The electrode layer is such that the first electrode layer has an upper surface exposed to the outside by the opening of the recess. Next, a spacer is formed covering a portion of the upper surface to define a contact region on the upper surface. Then, a memory layer is formed on the contact area. Subsequently, a second electrode layer is formed on the memory layer such that the second electrode layer is in electrical contact with the memory layer.

【0009】

According to the above embodiment, the present invention provides a memory element and a method of fabricating the same. The first electrode layer is formed in the recess of the substrate, and a spacer is formed to cover the upper surface of the first electrode layer to define a contact region. A memory layer is formed in the contact region to form a second electrode layer covering the memory layer. The upper surface of the first electrode layer is close to the corner of the sidewall of the recess by the spacer formed on the sidewall of the recess, so as to prevent incomplete coverage of the memory layer, resulting in the second electrode layer and the first electrode layer or The barrier layer (if any) produces unintended electrical contact. Solving the problem that the conventional memory component is thus ineffective due to leakage.

[0033]

100‧‧‧Variable Resistive Memory Components
101‧‧‧Substrate
101a‧‧‧Basic semiconductor layer
101b‧‧‧Insulation
101c‧‧‧Substrate surface
102‧‧ ‧ alcove
102a‧‧‧Aperture opening
102b‧‧‧ alcove sidewall
103‧‧‧Barrier layer
104‧‧‧First electrode layer
104a‧‧‧ Upper surface of the first electrode layer
105‧‧‧Interface between the first electrode layer and the barrier layer
106‧‧‧ spacer
107‧‧‧ memory layer
108‧‧‧Second electrode layer
200‧‧‧Variable Resistive Memory Components
201‧‧‧ dielectric layer
202‧‧‧through hole
203‧‧‧Barrier layer
204‧‧‧First electrode layer
204a‧‧‧ Upper surface of the first electrode layer
205‧‧‧Interface between the first electrode layer and the barrier layer
206‧‧‧ spacer
207‧‧‧ memory layer
208‧‧‧Second electrode layer
A1‧‧‧Contact area
A2‧‧‧Contact area
D1‧‧‧Distance between the contact area and the side wall of the alcove
D2‧‧‧Distance between the contact area and the side wall of the alcove

[0010]

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.
1A to 1F are schematic cross-sectional views showing a series of process structures for fabricating a variable resistance memory device according to an embodiment of the present invention; and FIGS. 2A to 2E are diagrams according to another embodiment of the present invention. A schematic cross-sectional view of a series of process structures for fabricating a variable resistance memory device.

[0011]

The invention provides a memory component and a manufacturing method thereof, which can solve the problem that the conventional memory component is uncomplete due to incomplete coverage of the memory layer, thereby causing an unexpected leakage problem. The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

[0012]

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

[0013]

Referring to FIGS. 1A to 1F, FIGS. 1A to 1F are schematic cross-sectional views showing a series of process structures for fabricating a variable resistive memory device 100 according to an embodiment of the present invention. The method of making the variable resistive memory element 100 includes the steps of first providing a substrate 101 having at least one recess 102. In some embodiments of the present invention, the substrate 101 may be an insulating layer 101b including a base semiconductor layer 101a and a base semiconductor layer 101a. The recess 102 is vertically extended downward into the insulating layer 101b by an opening 102a on the surface 101c of the insulating layer 101b (substrate 101) (as shown in Fig. 1A).

[0014]

In some embodiments of the present invention, the base semiconductor layer 101a comprises a polycrystalline germanium structure or any suitable semiconductor material, such as a crystalline germanium; a compound semiconductor such as tantalum carbide, gallium arsenide, gallium phosphide, phosphide iodine A wafer composed of arsenic arsenide and/or bismuth iodide, or a combination thereof. In the present embodiment, the substrate 101 is a wafer composed of polysilicon. The insulating layer 101b includes hafnium oxide (SiO ₂ ).

[0015]

Next, a first electrode layer 104 is formed in the recess 102 such that the first electrode layer 104 has an upper surface 104a exposed by the opening 102a of the recess 102 (as shown in FIG. 1B). In some embodiments of the present invention, the first electrode layer 104 may be fabricated by a deposition process, such as a Low Pressure Chemical Vapor Deposition (LPCVD) process, or other suitable process. The material constituting the first electrode layer 104 may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or other possible metallic or non-metallic conductive materials. In the present embodiment, the material constituting the first electrode layer 104 is preferably tungsten.

[0016]

In still other embodiments of the present invention, a barrier layer 103 is preferably formed on the bottom of the recess 102 and the sidewall 102b prior to forming the first electrode layer 104. (as shown in Figure 1B). The barrier layer 103 can also be fabricated by a deposition process such as a low pressure chemical vapor deposition process. The material constituting the barrier layer 103 may include titanium nitride (TiN).

[0017]

Next, an etch back process is performed on the first electrode layer 104 of the barrier layer 103 to expose a portion of the sidewall 102b of the recess 102 adjacent to the opening 102a of the recess 102, and the upper surface 104a of the first electrode layer 104 is lower than the recess. The opening 102a of the chamber 102 (as shown in Figure 1C). In the present embodiment, the upper surface of the barrier layer 103 is also lower than the opening 102a of the recess 102, and the interface 105 between the first electrode layer 104 and the barrier layer 103 is also exposed to the outside via the opening 102a of the recess 102.

[0018]

Thereafter, the spacer 106 is formed to cover a portion of the upper surface 104a of the first electrode layer 104, thereby defining a contact area A1 on the upper surface 104a (as shown in FIG. 1D). Wherein, the spacer 106 is formed on the sidewall 102b exposed by the recess 102 and is in contact with the first electrode layer 104 and the barrier layer 103. In some embodiments of the invention, the spacers 106 may be fabricated by a deposition process, such as a low pressure chemical vapor deposition process. The material constituting the spacer 106 may be tantalum nitride (SiN), yttrium oxide (SiO), yttrium oxynitride (SiON) or other possible dielectric materials.

[0019]

In the present embodiment, the spacers 106 are composed of tantalum nitride. Wherein, the spacer 106 covers the barrier layer 103 and the interface 105 between the first electrode layer 104 and the barrier layer 103; and covers a portion of the upper surface 104a of the first electrode layer 104 in an annular manner, thereby exposing the contact region A1 Outside. The size of the contact area A1 is smaller than the size of the recess 102. In other words, there is a distance between the contact area A1 and the barrier layer 103, and between the contact area A1 and the side wall 102b of the recess 102.

[0020]

Then, a memory layer 107 is formed on the contact area A1. In some embodiments of the invention, memory layer 107 may comprise a metal oxide such as tungsten oxide (WO _x ) or hafnium oxide (HfO _x ). In some embodiments of the invention, the step of forming the memory layer 107 may include performing a deposition process whereby a metal oxide layer is formed on the upper surface 104a of the first electrode layer 104 in the contact region A1. However, in other embodiments of the present invention, the first electrode layer 104 located in the contact region A1 may be directly oxidized by an oxidation process such as a thermal oxidation process to form a metal oxide layer on the upper surface 104a.

[0021]

In the present embodiment, the formation of the memory layer 107 includes performing a winding process in which a tungsten oxide (WO _x ) layer is formed on the upper surface 104a of the first electrode layer 104 in the contact region A1. In addition, according to the above, since the memory layer 107 is formed on the contact area A1, there is also a distance between the memory layer 107 and the barrier layer 103, and between the memory layer 107 and the sidewall 102b of the recess 102. 1E is shown). In a preferred embodiment of the invention, the distance D1 between the contact zone A1 and the sidewall 102b of the recess 102 is substantially greater than 5 nanometers (nm).

[0022]

Subsequently, the second electrode layer 108 is formed on the memory layer 107, and the second electrode layer 108 is electrically contacted with the memory layer 107 (as shown in FIG. 1F) to complete the preparation of the variable resistive memory device 100. The manufacturing method and material of the second electrode layer 108 may be the same as or different from the manufacturing method and material of the first electrode layer 104. In the present embodiment, the second electrode layer 108 is also fabricated by a deposition process such as a low pressure chemical vapor deposition process. The material constituting the second electrode layer 108 also includes tungsten.

[0023]

Referring to FIG. 1F again, the variable resistive memory device 100 prepared by the foregoing method may include: a substrate 101, a barrier layer 103, a first electrode layer 104, a spacer 106, a memory layer 107, and a second electrode layer. 108. Among them, the substrate 101 has an alcove 102. The first electrode layer 104 is located in the recess 102 and has an upper surface 104a that is exposed to the outside by the opening 102a of the recess 102. The barrier layer 103 is located on the sidewall 102a of the recess 102 and isolates the first electrode layer 104 from the substrate 101. The gap 106 wall covers the barrier layer 103 and a portion of the upper surface 104a of the first electrode layer 104, thereby defining a contact area A1 on the upper surface 104a. The memory layer 107 is formed on the contact area A1. The second electrode layer 108 is formed on the memory layer 107 and is in electrical contact with the memory layer 108.

[0024]

2A to 2E are schematic cross-sectional views showing a series of process structures for fabricating the variable resistance memory device 200 according to another embodiment of the present invention. The method of making the variable resistive memory element 200 includes the steps of first providing a substrate 101 having at least one recess 102. Since the material of the substrate 101 on which the variable resistance memory devices 100 and 200 are prepared is the same as the structure, it will not be described here. The method of fabricating the variable resistance memory device 200 is continued from FIG. 1A and then from FIG. 2A.

[0025]

The first electrode layer 204 is formed in the recess 102 such that the first electrode layer 204 has an upper surface 204a exposed by the opening 102a of the recess 102. In other embodiments, a barrier layer 203 (as shown in FIG. 2A) is preferably formed on the bottom of the recess 102 and the sidewall 102b prior to forming the first electrode layer 204. Since the methods and materials for fabricating the first electrode layer 204 and the barrier layer 203 have been described in detail above, they are not described herein.

[0026]

Then, a dielectric layer 201 is formed on the surface 101c of the insulating layer 101b (substrate 101), and the dielectric layer 201 is patterned, thereby forming at least one through hole 202 surrounding the opening 102a of the recess 102, thereby The surface 101c of the insulating layer 101b (substrate 101) and the entire opening 102a are exposed to the outside (as shown in FIG. 2B). In some embodiments of the invention, the dielectric layer 201 can be fabricated by a deposition process, such as a low pressure chemical vapor deposition process. The material constituting the dielectric layer 201 may be tantalum nitride, hafnium oxide, tantalum oxynitride, tantalum carbide or other possible dielectric materials. In the present embodiment, the dielectric layer 201 is composed of tantalum nitride.

[0027]

Thereafter, the spacers 206 are formed to cover a portion of the upper surface 204a of the first electrode layer 204, thereby defining a contact region A2 on the upper surface 204a (as shown in FIG. 2C). The spacer 106 is formed on the sidewall 202a of the via 202 and extends into the recess 102 and is in contact with the first electrode layer 204 and the barrier layer 203. In the present embodiment, the spacers 206 cover the barrier layer 203 and the interface 205 between the first electrode layer 204 and the barrier layer 203; and cover a portion of the upper surface 204a of the first electrode layer 204 in an annular manner, thereby The contact area A2 is exposed to the outside. The size of the contact area A2 is smaller than the size of the recess 102. In other words, there is a distance between the contact area A2 and the barrier layer 203, and between the contact area A2 and the side wall 102b of the recess 102.

[0028]

Then, a memory layer 207 is formed on the contact area A2. Since the memory layer 207 is formed on the contact area A2, there is also a distance between the memory layer 207 and the barrier layer 203, and between the memory layer 207 and the sidewall 102b of the recess 102 (as depicted in FIG. 2D). Show). In a preferred embodiment of the invention, the distance D2 between the contact zone A2 and the sidewall 102b of the recess 102 is substantially greater than 5 nanometers (nm).

[0029]

Subsequently, the second electrode layer 208 is formed on the memory layer 207, and the second electrode layer 208 is electrically contacted with the memory layer 207 (as shown in FIG. 2E) to complete the preparation of the variable resistance memory device 200.

[0030]

Referring to FIG. 2E again, the variable resistive memory device 200 prepared by the foregoing method may include: a substrate 101, a dielectric layer 201, a barrier layer 203, a first electrode layer 204, a spacer 206, and a memory layer 207. And a second electrode layer 208. Among them, the substrate 101 has an alcove 102. The first electrode layer 204 is located in the recess 102 and has an upper surface 204a that is exposed to the outside by the opening 102a of the recess 102. The barrier layer 203 is located on the sidewall 102a of the recess 102 and isolates the first electrode layer 204 from the substrate 101. The dielectric layer 201 is located above the substrate 101 and has a through hole 202 surrounding the recess 102. The spacers 206 are formed on the sidewalls of the vias 202 and extend into the recesses 102 and cover the barrier layer 203 and a portion of the upper surface 204a of the first electrode layer 204, thereby defining a contact region on the upper surface 204a. A2. The memory layer 207 is formed on the contact area A2. The second electrode layer 208 is formed on the memory layer 207 and is in electrical contact with the memory layer 208.

[0031]

According to the above embodiment, the present invention provides a memory element and a method of fabricating the same. The first electrode layer is formed in the recess of the substrate, and a spacer is formed to cover the upper surface of the first electrode layer to define a contact region. A memory layer is formed in the contact region to form a second electrode layer covering the memory layer. The upper surface of the first electrode layer is close to the corner of the sidewall of the recess by the spacer formed on the sidewall of the recess, so as to prevent incomplete coverage of the memory layer, resulting in the second electrode layer and the first electrode layer or The barrier layer (if any) produces unintended electrical contact. Solving the problem that the conventional memory component is thus ineffective due to leakage.

[0032]

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Variable Resistive Memory Components

101‧‧‧Substrate

101a‧‧‧Basic semiconductor layer

101b‧‧‧Insulation

101c‧‧‧Substrate surface

102‧‧ ‧ alcove

102a‧‧‧Aperture opening

102b‧‧‧ alcove sidewall

103‧‧‧Barrier layer

104‧‧‧First electrode layer

104a‧‧‧ Upper surface of the first electrode layer

105‧‧‧Interface between the first electrode layer and the barrier layer

106‧‧‧ spacer

107‧‧‧ memory layer

108‧‧‧Second electrode layer

A1‧‧‧Contact area

D1‧‧‧Distance between the contact area and the side wall of the alcove

Claims (17)

[Item 1] A memory component, comprising:
a substrate having an alcove;
a first electrode layer is located in the recess and has an upper surface exposed by an opening of the recess;
a spacer wall covering a portion of the upper surface to define a contact region on the upper surface;
a memory layer is formed on the contact region; and a second electrode layer is formed on the memory layer and is in electrical contact with the memory layer.
[Item 2] The memory device of claim 1, further comprising: a barrier layer on the sidewall of the recess, and isolating the first electrode layer from the substrate, and the spacer covers the resistor Barrier layer.
[Item 3] The memory device of claim 2, wherein the upper surface is lower than the opening, and the spacer is formed on a sidewall of the recess and is in contact with the barrier layer and the upper surface.
[Item 4] The memory device of claim 2, further comprising a dielectric layer on the substrate having a through hole surrounding the recess; wherein the spacer is formed on a sidewall of the through hole And extending into the recess and contacting the barrier layer and the upper surface.
[Item 5] The memory device of claim 1, wherein the contact region has a size smaller than the recess
[Item 6] The memory device of claim 1, wherein the contact region and the sidewall of the recess have a distance substantially greater than 5 nanometers (nm).
[Item 7] The memory device of claim 1, wherein the substrate comprises cerium oxide (SiO ₂ ); the first electrode layer and the second electrode layer comprise tungsten (W); and the memory layer comprises tungsten oxide (WO _x ) or tantalum oxide (HfO _x ); and the spacer includes tantalum nitride (SiN)
[Item 8] A method of fabricating a memory component, comprising:
Providing a substrate such that the substrate has an alcove;
Forming a first electrode layer in the recess, the first electrode layer having an upper surface exposed by an opening of the recess;
Forming a spacer wall covering a portion of the upper surface to define a contact region on the upper surface;
Forming a memory layer on the contact region; and forming a second electrode layer on the memory layer to electrically contact the second electrode layer with the memory layer.
[Item 9] The method of fabricating the memory device of claim 8, wherein before forming the first electrode layer in the recess, a barrier layer is further formed on a sidewall of the recess.
[Item 10] The method of fabricating the memory device of claim 8, wherein the forming the spacer further comprises performing an etch back process on the first electrode layer and the barrier layer, and the portion of the recess is The sidewall is exposed to the outside and the upper surface is lower than the opening.
[Item 11] The method of fabricating a memory device according to claim 10, wherein the spacer is formed on a sidewall of the recess and is in contact with the barrier layer and the upper surface.
[Item 12] The method for fabricating a memory device according to claim 8, wherein before forming the spacer, the method further comprises:
Forming a dielectric layer over the substrate; and patterning the dielectric layer to form a via surrounding the recess.
[Item 13] The method of fabricating a memory device according to claim 12, wherein the spacer is formed on a sidewall of the through hole and extends into the recess and is in contact with the barrier layer and the upper surface.
[Item 14] The method of fabricating the memory device of claim 8, wherein the step of forming the memory layer comprises performing a thermal oxidation process on the contact region to form a metal oxide on the upper surface of the contact region. Floor.
[Item 15] The method of fabricating the memory device of claim 8, wherein the step of forming the memory layer comprises performing a deposition process to form a metal oxide layer on the upper surface of the contact region.
[Item 16] The method of fabricating the memory device of claim 8, wherein the step of forming the spacer comprises making the contact region have a size smaller than the recess.
[Item 17] The method of fabricating a memory device according to claim 16, wherein the contact region and the sidewall of the recess have a distance substantially greater than 5 nm.