TW201633320A - Memory device and operating method of the same - Google Patents

Abstract

A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

Description

Memory device and method of operating same 【0001】

The present disclosure relates to a memory device and a method of operating the same. In particular, there is a memory device having an extra arrays of reconfigurable size.

【0002】

Memory devices are widely used in different electronic applications. A memory device can include a plurality of pages

[0003]

According to an embodiment disclosed herein, a memory device includes a memory array including a plurality of pages for storing array data, and a plurality of extra arrays. , corresponding to these pages, used to store extra data. The memory device also includes a logic unit communicatively coupled to the memory array, the logic unit being configured to receive a read instruction and in a first access mode ( A read operation is performed in the first access mode or a second access. In the first access mode, the logic unit sequentially reads out the array data stored in the pages. In the second access mode, the logic unit sequentially reads the array data stored in the pages and the additional data stored in the additional array.

[0004]

According to another embodiment disclosed herein, a memory device includes an array of memory, the memory array including a plurality of pages for storing array data, and a plurality of additional arrays corresponding to the pages for storing additional data. The memory device also includes a logic unit coupled to the memory array, and the logic unit is configured to receive a program instruction including an address of the selected page and an address to be The data is written and a program operation is performed in a first access mode or a second access. In the first access mode, the logic unit writes the received data in the selected page. In the second access mode, the logic unit writes the received data into an additional array located in the selected page and corresponding to the selected page.

[0005]

In accordance with yet another embodiment disclosed herein, a method of operating a memory device is provided. The memory device includes a plurality of array blocks for storing array data, and a plurality of additional array blocks corresponding to the array blocks for storing additional data. The method includes receiving a read command including a read command code and determining whether the read command code is a first read command code or a second read command code. If the read command code is determined as the first read command code, the method includes sequentially reading the array data stored in the array blocks; if so, the read command code is determined to be the second read command code. The method includes sequentially reading out array data stored in the array blocks and storing additional data stored in the additional array blocks.

[0006]

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

[0030]

100‧‧‧ memory device
110‧‧‧Input/Output Interface
120‧‧‧Logical unit
122‧‧‧Processing Circuit
124‧‧‧Internal registers
130‧‧‧Memory array
140‧‧‧Non-volatile memory
200‧‧‧Array block
210‧‧‧Additional Array Blocks
220‧‧‧page
230‧‧‧Additional array
400‧‧‧Read instructions
500‧‧‧fast read command
602‧‧‧Is there a read command received?
604‧‧‧ First or second access mode?
606‧‧‧First access mode
608‧‧‧Read operation according to the first access mode
610‧‧‧Second access mode
612‧‧‧Read operation according to the second access mode
702‧‧‧Load access information stored in non-volatile memory into internal registers
704‧‧‧Set the built-in access mode based on the access information in the internal registers
706‧‧‧Is there a read command received?
708‧‧‧Read operations based on built-in access mode
710‧‧‧ Have you received an instruction to change the access information in the internal registers?
712‧‧‧Change access information in internal registers
714‧‧‧Set the built-in access mode based on the changed access information in the internal registers
800‧‧ ‧ page write command
810‧‧ ‧ page write command
902‧‧‧ Is there a write command received?
904‧‧‧ First or second access mode?
906‧‧‧First access mode
908‧‧‧Write operation according to the first access mode
910‧‧‧Second access mode
912‧‧‧Write operation according to the second access mode
1002‧‧‧Load access information stored in non-volatile memory into internal registers
1004‧‧‧Set the built-in access mode based on the access information in the internal registers
1006‧‧‧Is there a write command received?
1008‧‧‧Write operation according to built-in access mode
1010‧‧‧Do you receive an instruction to change the access information in the internal registers?
1012‧‧‧Change access information in internal registers
1014‧‧‧Set the built-in access mode based on the changed access information in the internal registers
1100‧‧‧Erase instructions
A0-A23‧‧‧ address bit
AD1-AD3‧‧‧ address segment

【0007】

1 is a block diagram of a memory device having an additional array of resizable sizes according to an embodiment of the invention;
2 is a block diagram showing an array structure of a memory array according to an embodiment of the invention;
FIG. 3A is a first access mode according to an embodiment of the present invention, showing an access sequence of the memory array of FIG. 2;
FIG. 3B is a second access mode according to an embodiment of the present invention, showing an access sequence of the memory array of FIG. 2;
4 is a read instruction for performing a read operation according to an embodiment of the invention;
Figure 5 is a diagram showing a fast read command for performing a fast read operation in accordance with an embodiment of the present invention;
Figure 6 is a flow chart showing a read operation performed by a logic unit, in accordance with an embodiment of the present invention;
Figure 7 is a flow chart showing a read operation performed by a logic unit in accordance with another embodiment of the present invention;
8A is a diagram showing a page write instruction for performing a page write operation in a first access mode, in accordance with an embodiment of the present invention;
8B is a diagram illustrating a page write instruction for performing a page write operation in a second access mode, in accordance with an embodiment of the present invention;
Figure 9 is a flow chart showing a write operation performed by a logic unit in accordance with still another embodiment of the present invention;
10 is a flow chart showing a write operation performed by a logic unit according to still another embodiment of the present invention; and FIG. 11 is a view showing a wipe for performing an erase operation according to an embodiment of the present invention. Except instructions.

[0008]

The embodiments of the present description will be described in detail in conjunction with the drawings. In the different embodiments and the drawings, the same elements will be denoted by the same element symbols as much as possible.

【0009】

1 is a block diagram of a memory device 100 having an additional array of resizable dimensions, in accordance with an embodiment of the invention. The memory device 100 includes an input/output (I/O) interface 110, a logic unit 120 connected to the input/output interface 110, a memory array 130 connected to the logic unit 120, and a connection. A non-volatile memory 140 to the logic unit 120. The input/output interface 110 includes a plurality of pins (not shown) connected to an external circuit (not shown). The input/output interface 110 receives different instructions and data to be written, i.e., to be written to the memory array 130 from an external circuit. The input/output interface 110 also outputs data read from the memory array 130 to an external circuit. Logic unit 120 receives instructions and data from input/output interface 110 and performs different operations (e.g., read, write, erase, etc.) on memory array 130 in accordance with the received instructions. The logic unit 120 includes a process circuit 122 and an internal register 124. Processing circuit 122 includes logic circuitry that controls the overall operation of logic unit 120. The internal register 124 stores the temporary data used by the processing circuit 122. The internal register 124 can be implemented by volatile memory such as static random access memory (SRAM), random-access memory (RAM), and dynamic random access memory (dynamic). Random-access memory, DRAM), to achieve. The non-volatile memory 140 stores the permanent data used by the processing circuit 122. The non-volatile memory 140 also stores information about the wafer configuration of the memory device 100. The non-volatile memory 140 can be a flash memory, a read-only memory (ROM), or a ferroelectric random-access memory (F-RAM). , magnetic computer storage device (magnetic computer storage device) or optical disc (optical disc) to achieve. The memory array 130 is a non-volatile memory such as a flash memory, a read only memory, a ferroelectric random access memory, a magnetic disk storage device, or a compact disk.

[0010]

In some embodiments, internal register 124 of logic unit 120 stores a plurality of command codes and their corresponding operations. When the logic unit 120 receives an instruction from an external circuit via the input/output interface 110, the processing circuit 122 of the logic unit 120 parses the instruction to identify the command code, and stores the identified command code in the internal register 124. A plurality of command codes are compared to find an operation corresponding to the recognized command code, and the operation is performed.

[0011]

FIG. 2 is a block diagram showing an array structure of a memory array 130 according to an embodiment of the invention. The memory array 130 includes a plurality of array blocks 200, and a plurality of additional array blocks 210. Each additional array block 210 corresponds to one of the plurality of array blocks 200. That is, the additional array block 0 corresponds to the array block 0; the additional array block 1 corresponds to the array block 1....; and the additional array block n corresponds to the array block n. Each array block 200 includes a plurality of, for example, eight, page 220. Each additional array block 210 includes a plurality, for example, eight, additional arrays 230. Each additional array 230 corresponds to one of the plurality of pages 220. That is, the extra array block 0 corresponds to page 0; the extra array block 1 corresponds to page 1...; and the additional array block 7 corresponds to page 7. Each page 220 has a fixed size, such as 256 bytes. Each additional array 230 has a resizable size, such as 1, 2, or 8 bytes. These plurality of tabs 220 are used to store array data defined by the user. The plurality of additional arrays 230 are used to store additional data associated with the array data stored in the corresponding page 220. For example, additional data stored in the extra array 0 includes Error Checking and Correcting code (ECC code) and/or security content, etc., which are stored in the page 0 associated with the array data. Additional information.

[0012]

The array structure shown in FIG. 2 is a logic array structure of the memory array 130 that can be used by external circuits. The data address (called a "logical address") in the logical array structure can be mapped to the data address in the physical array structure by scramble transfer (called "physical address"). Thus, when the logical array structure of the memory array 130 includes an additional array 230 of resizable size, the physical array structure of the memory array 130 can also be re-applied by encrypted transmission, with the additional array 230 incorporated.

[0013]

FIG. 3A is an access sequence of the memory array 130 illustrated in the first access mode according to an embodiment of the invention. In the first access mode, only the page 220 is accessed in the order of page 0, page 1, page 2, . . . , page n. The extra array 230 is not accessed. The first access mode can be employed when additional material stored in the additional array 230 includes secure content associated with the array data stored in the page 220.

[0014]

FIG. 3B is another access sequence of the memory array 130 depicted in the second access mode in accordance with an embodiment of the present invention. In the second access mode, the page 220 and the additional array 230 are stored in the order of page 0, extra array 0, page 1, extra array 1, page 2, extra array 2 . . . , page n, and extra array n. take.

[0015]

To implement a read operation in the first access mode or the second access mode of the memory device 100, a variety of different interface protocol methods can be used in accordance with different embodiments herein. In one embodiment, the logic unit 120 of the memory device 100 can receive a read command containing access information regarding whether an access operation is performed in the first access mode or the second access mode. When the logic unit 120 performs a read operation in the first access mode, the logic unit 120 reads the array data stored in the page 220 in the order of page 0, page 1, page 2, . . . , page n. Additional material stored in the additional array 230 is excluded from this readout sequence. That is, the additional data stored in the additional array 230 is not read. When the logic unit 120 performs a read operation in the second access mode, the logic unit 120 follows the page 0, the extra array 0, the page 1, the extra array 1, the page 2, the extra array 2 . . . , the page n, the extra The sequence of array n reads out the array data stored in page 220 and the additional data stored in additional array 230.

[0016]

Figure 4 is a diagram of a read command 400 for performing a read operation, in accordance with an embodiment of the present invention. The read command 400 is sent to the logic unit 120 for reading the data stored in the memory array 130. As shown in FIG. 4, the read command 400 includes a total of 4 bytes, namely a 1st byte, a 2nd byte, a 3rd byte, and a 4th byte. The first byte includes a read command code that can be pre-defined to instruct the logic unit 120 to perform a read operation in either the first access mode or the second access mode. And if it is done in the second access mode, the size of each additional array 230 is specified. The second byte includes a first address segment AD1 containing address bits A23 through A16. The third byte includes a second address segment AD2 containing address bits A15 through A8. The fourth byte includes a third address segment AD3 containing address bits A7 through A0. The first address segment AD1, the second address segment AD2, and the third address segment AD3 construct a 24-bit address that represents a start address for a read operation in the memory array 130 (starting address) ). For example, an in-hexadecimal read command code 03 (hereinafter referred to as "03 (hex)") may be pre-defined to instruct the logic unit 120 to perform a read operation in the first access mode. When the logic unit 120 receives an instruction including 03 (hex) and a 24-bit address, the logic unit 120 performs a read operation as shown in FIG. 3A in the first access mode, from having The location of the 24-bit address begins, and the array data stored in the page 220 of the memory array 130 is sequentially read. In another embodiment, the read command code 66 (hex) may be pre-defined to instruct the logic unit 120 to perform a read operation in the second access mode and specify that each additional array 230 has a size of 2 bits. Tuple. When the logic unit 120 receives an instruction including 66 (hex) and a 24-bit address, the logic unit 120 performs a read operation according to the second access mode illustrated in FIG. 3B, from having 24 The location of the bit address begins by sequentially reading the array data stored in the page 220 of the memory array 130 and the additional data stored in the 2 bytes of each additional array 230. In still another embodiment, the read command code 68 (hex) may be pre-defined to instruct the logic unit 120 to perform a read operation in the second access mode and specify that each additional array 230 has a size of 4 bits. Tuple. When the logic unit 120 receives an instruction including 68 (hex) and a 24-bit address, the logic unit 120 performs a read operation according to the second access mode illustrated in FIG. 3B, from having the 24 The location of the bit address begins by sequentially reading the array data stored in the page 220 of the memory array 130 and the additional data stored in the 4 bytes of each additional array 230 of the memory array 130.

[0017]

Figure 5 illustrates a fast read command 500 for performing a fast read operation in accordance with an embodiment of the present invention. The fast read command 500 is sent to the logic unit 120 for quickly reading the data stored in the memory array 130. In contrast to the read command 400 illustrated in FIG. 4, the fast read command 500 additionally includes a fifth byte, which is a dummy byte. The virtual byte provides the extra time margin required to sense the data. The read command code located in the 1st byte may be pre-defined to instruct the logic unit 120 to perform a fast read operation in the first access mode or the second access mode and specify the size of each additional array 230 . For example, the read command code 0B (hex) may be pre-defined to instruct the logic unit 120 to perform a fast read operation in the first access mode. When the logic unit 120 receives an instruction including 0B (hex) and a 24-bit address, the logic unit 120 performs a fast read operation as shown in FIG. 3A in the first access mode. Starting with the location of the 24-bit address, the array data stored in the page 220 of the memory array 130 is sequentially read. In another embodiment, the read command code 67 (hex) may be pre-defined to instruct the logic unit 120 to perform a fast read operation in the second access mode and specify that each additional array 230 has a size of two Bytes. When the logic unit 120 receives an instruction including 67 (hex) and a 24-bit address, the logic unit 120 performs the fast read operation as shown in FIG. 3B in the second access mode. Starting with the location of the 24-bit address, the array data stored in the page 220 of the memory array 130 and the additional data stored in the 2 bytes of each additional array 230 of the memory array 130 are sequentially read. .

[0018]

Figure 6 is a flow chart showing the read operation performed by logic unit 120, in accordance with an embodiment of the present invention. When the power of the memory device 100 is turned on, the logic unit 120 determines whether a read command has been received (step 602). If a read command is not received (step 602: No), logic unit 120 periodically performs step 602 until a read command is received. If a read command is received (step 602: Yes), logic unit 120 analyzes the received read command and determines whether the read command specifies a first access mode or a second access mode (step 604). For example, the logic unit 120 determines whether the read command code in the read command is 03 (hex) or 66 (hex). If the read command code is 03 (hex), logic unit 120 determines that the read command specifies the first access mode (step 606). The result logic unit 120 performs a read operation in the first access mode (step 608). If the read command code is 66 (hex), the logic unit 120 determines that the read command specifies the second access mode (step 610). The result logic unit 120 performs a read operation in the second access mode (step 612). Subsequently, logic unit 120 returns to step 602 to determine if a read command has been received.

[0019]

In some embodiments, the logic unit 120 may be related to whether a memory access operation is performed in the first access mode or the second access mode, and access information regarding the size of each of the additional arrays 230, Stored in non-volatile memory 140. FIG. 7 is a flow chart showing a read operation performed by logic unit 120, in accordance with another embodiment of the present invention.

[0020]

Referring to FIG. 7, when the power of the memory device 100 is turned on, the logic unit 120 loads the access information stored in the non-volatile memory 140 into the internal register 124 of the logic unit 120 (step 702). . The logic unit 120 then sets a default access mode based on the access information in the internal register 124 (step 704). For example, when the access information in the internal register 124 specifies that the built-in access mode is the first access mode illustrated in FIG. 3A, the logic unit 120 sets its built-in access mode to the first access mode. In another embodiment, the access information in the internal register 124 specifies that the built-in access mode is the second access mode illustrated in FIG. 3B, and each additional array 230 has a size of 2 bytes. Logic unit 120 sets its built-in access mode to a second access mode with an additional array 230 of 2 bytes. The logic unit 120 determines whether a read command has been received (step 706). If the read command is not received (step 706: No), the logic unit 120 moves directly to step 710. If a read command is received (step 708: Yes), logic unit 120 performs a read operation in accordance with the built-in access mode (step 708). Since the internal register 124 already contains access information about whether to operate in the first access mode or the second access mode, in this embodiment, no read instruction is required to specify whether it is in the first access mode. Or a read operation in the second access mode. The logic unit 120 then determines whether a read command to change the access information in the internal register 124 is received (step 710). If a read command to change the access information in the internal register 124 is not received (step 710: No), the logic unit 120 returns to step 706 to determine whether a read command has been received. If a read command to change the access information in the internal register 124 is received (step 710: Yes), the logic unit 120 changes the access information according to the received command (step 712). Thereafter, logic unit 120 sets the built-in access mode based on the changed access information in internal register 124 (step 714). For example, the read command received in step 710 instructs the logic unit 120 to change the access information, and the first access mode is changed to the second access mode. The logic unit 120 sets the built-in access mode in the internal register 124 to be the first. Two access modes. Thereafter, logic unit 120 returns to step 706 to determine if a read command has been received.

[0021]

In some embodiments, to perform a write operation in the first access mode or the second access mode, the logic unit 120 of the memory device 100 can receive a inclusion regarding whether in the first access mode or the second access. A write command to access information for a write operation in the mode.

[0022]

Figure 8A illustrates a paged write instruction 800 for performing a paged write operation, i.e., writing a page, in a first access mode, in accordance with an embodiment of the present invention. In the present embodiment, it is assumed that each page 220 has a fixed size of 256 bytes. As depicted in FIG. 8A, the page write instruction 800 has a total of 256 bytes. The first byte includes a page program command code, which may be pre-defined to instruct the logic unit 120 to perform a page write operation in the first access mode. The second to fourth bytes include three address segments AD1, AD2, and AD3, respectively. The three address segments AD1, AD2, and AD3 construct a 24-bit address that represents the location of a page that is selected for the write operation. The 5th to 260th byte includes 256 bytes to be written to the array data of the selected page. For example, the write command code 02 (hex) may be pre-defined to instruct the logic unit 120 to perform a page write operation in the first access mode. When the logic unit 120 receives an instruction including 02 (hex) and accompanying a 24-bit address and 256 byte data, the logic unit 120 performs a page write operation in the first access mode, This data containing 256 bytes is written into the page 220 of the memory array 130 having the 24-bit address.

[0023]

FIG. 8B illustrates a page write instruction 810 for performing a page write operation in a second access mode, in accordance with an embodiment of the present invention. In the present embodiment, it is assumed that each page 220 has a size of 256 bytes, and each additional array 230 has a size of 8 bytes. As depicted in FIG. 8B, the page write instruction 810 has a total of 256 bytes. The first byte includes a page write command code, which may be pre-defined to instruct the logic unit 120 to perform a page write operation in the second access mode. The second to fourth bytes include three address segments AD1, AD2, and AD3, respectively. The three address segments AD1, AD2, and AD3 construct a 24-bit address that represents the location of a page that is selected for the write operation. The 5th to 260th byte includes 256 bytes to be written to the selected page data; the 261th to 268th bytes include to be written to the additional array 230 attached to the selected page. Additional information for 8 bytes. For example, the write command code 37 (hex) may be pre-defined to instruct the logic unit 120 to perform a page write operation in the second access mode. Each of the additional arrays 230 has a size of 8 bytes. When the logic unit 120 receives an instruction containing 37 (hex) and following a 24-bit address and 256 byte data, the logic unit 120 performs a page write operation in the second access mode, The received 256 byte data is written into the page 220 of the memory array 130 having the 24-bit address; and the remaining 8 byte data is written to the additional array 230 corresponding to the selected page 220. in.

[0024]

FIG. 9 is a flow chart showing a write operation performed by logic unit 120, in accordance with yet another embodiment of the present invention. When the power of the memory device 100 is turned on, the logic unit 120 determines whether a write command has been received (step 902). If the write command is not received (step 902: No), logic unit 120 periodically performs step 902 until a write command is received. If a write command is received (step 902: Yes), logic unit 120 analyzes the received write command and determines whether the write command specifies a first access mode or a second access mode (step 904). For example, logic unit 120 determines that the write command code in the write command is 02 (hex) or 37 (hex). If the write command code is 02 (hex), logic unit 120 determines that the write command specifies the first access mode (step 906). The result logic unit 120 performs a page write operation in the first access mode (step 908). If the read command code is 37 (hex), the logic unit 120 determines that the write command specifies the second access mode (step 910). The result logic unit 120 performs a page write operation in the second access mode (step 912). Subsequently, logic unit 120 returns to step 902 to determine if a read command has been received.

[0025]

In some embodiments, logic unit 120 may perform a write operation based on access information stored in non-volatile memory 140 and loaded into internal registers 124. FIG. 10 is a flow chart showing a write operation performed by logic unit 120, in accordance with still another embodiment of the present invention.

[0026]

Referring to FIG. 10, when the power of the memory device 100 is turned on, the logic unit 120 loads the access information stored in the non-volatile memory 140 into the internal register 124 of the logic unit 120 (step 1002). The logic unit 120 then sets the built-in access mode based on the access information in the internal register 124 (step 1004). The logic unit 120 determines whether a write command has been received (step 1006). If the write command has not been received (step 1006: No), the logic unit 120 moves directly to step 1010. If a write command is received (step 1008: Yes), logic unit 120 performs a write operation in accordance with the built-in access mode (step 1008). Since the internal register 124 already contains access information about whether to operate in the first access mode or the second access mode, in the present embodiment, it is not necessary to specify whether the first access is by the write command. The read operation is performed in the mode or the second access mode. The logic unit 120 then determines whether an instruction to change the access information in the internal register 124 is received (step 1010). If an instruction to change the access information in the internal register 124 is not received (step 1010: No), the logic unit 120 returns to step 1006 to determine whether a write command has been received. If an instruction to change the access information in the internal register 124 is received (step 1010: Yes), the logic unit 120 changes the access information according to the received instruction (step 1012). Thereafter, logic unit 120 sets the built-in access mode based on the changed access information in internal register 124 (step 1014). After that, the logic unit 120 returns to step 1006 to determine whether a write command has been received.

[0027]

In some embodiments, in order to perform an erase operation in the memory device 100 including the array block 200 and the additional array block 210, the logic unit 120 of the memory device 100 can receive one containing whether or not to erase one The selected array block 200, whether to erase a selected additional array block 210, or whether to erase the information of a selected array block 200 and a selected additional array block 210 at the same time. Figure 11 illustrates an erase command 1100 for performing an erase operation, in accordance with an embodiment of the present invention.

[0028]

As shown in FIG. 11, the read command 1100 includes a total of 4 bytes, namely a 1st byte, a 1st byte, a 3rd byte, and a 4th byte. The first byte includes an erase command code, which can be pre-defined to instruct the logic unit 120 to perform an erase operation, thereby erasing a selected array block 200, erasing a selected additional array block 210, or erasing one at the same time. Array block 200 and a selected additional array block 210 are selected. The second to fourth bytes include three address segments AD1, AD2, and AD3, respectively. The three address segments AD1, AD2, and AD3 construct a 24-bit address that represents the location of a block selected to be erased. For example, the erase command code 52 (hex) can be pre-defined to instruct the logic unit 120 to perform an erase operation to erase the selected array block 200. When the logic unit 120 receives an instruction containing 52 (hex) and accompanying a 24-bit address and 256 byte data, the logic unit 120 performs an erase operation, which will have the 24-bit address. Array block 200 is erased. In another embodiment, the erase command code 53 (hex) may be pre-defined to instruct the logic unit 120 to perform an erase operation to erase the selected additional array block 210. When the logic unit 120 receives an instruction containing 53 (hex) followed by a 24-bit address, the logic unit 120 performs an erase operation to erase the additional array block 210 having the 24-bit address. except. In yet another embodiment, the erase command code 54 (hex) may be pre-defined to instruct the logic unit 120 to perform an erase operation to simultaneously erase the selected array block 200 and corresponding to the selected array block. An additional array block 210 of 200. When the logic unit 120 receives an instruction including 54 (hex) and a 24-bit address, the logic unit 120 performs an erase operation, and the array block 200 having the 24-bit address and the corresponding The additional array block 210 of the selected array block 200 is erased.

[0029]

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

602‧‧‧Is there a read command received?

604‧‧‧ First or second access mode?

606‧‧‧First access mode

608‧‧‧Read operation according to the first access mode

610‧‧‧Second access mode

612‧‧‧Read operation according to the second access mode

Claims (16)

[Item 1] A memory device comprising:
A memory array comprising a plurality of pages for storing array data and a plurality of additional arrays corresponding to respective pages for storing additional data;
A logic unit, connected to the memory array, is constructed to:
Receiving a read instruction; and performing a read operation in a first access mode or a second access;
In the first access mode, the logic unit sequentially reads the array data stored in the paging pages; and in the second access mode, the logic unit is stored in the paging pages. The array data and additional data stored in the additional arrays are sequentially read.
[Item 2] The memory device of claim 1, wherein the read instruction specifies whether the read operation is performed in the first access mode or the second access; the read command includes a read command a read command code and a starting address of the read operation, and the read command code is one of a first read command code and a second read command code; The first read command code is used to specify the first access mode; the second read command code is used to specify the second access mode and a size of each of the additional arrays.
[Item 3] The memory device of claim 2, wherein the logic unit is constructed:
Determining, in the read command, the read command code is the first read command code or the second read command code;
If the read command code is determined to be the first read command code, the read operation is performed in the first access mode; and if the read command code is determined to be the second read command code, The read operation is then performed in the second access mode.
[Item 4] The memory device of claim 1, further comprising a non-volatile memory for storing whether the first access mode or the second access mode is specified Performing access information for a memory access operation, the logic unit including an internal register
Where the logical unit is constructed:
The access information is loaded into the internal register by the non-volatile memory; and a default access mode is set according to the access information in the internal register.
[Item 5] The memory device of claim 4, wherein the logic unit is constructed:
Performing the read operation in the built-in access mode;
Receiving an instruction to change the access information in the internal register;
And changing the access information in the internal register according to the received instruction; and setting the built-in access mode according to the changed access information in the internal register.
[Item 6] The memory device of claim 4, wherein the logic unit is constructed:
Receiving a program instruction including an address of a selected page and a material to be written; and performing a write operation in the built-in access mode ( Program operation).
[Item 7] The memory device of claim 1, wherein the logic unit is constructed:
Receiving a write command including a page address of the selected page and the material to be written; and performing a write operation in the first access mode or the second access;
Wherein, in the first access mode, the logic unit writes the received data into the selected page; and in the second access mode, the logic unit writes the received data to the Select the pagination and the additional array that should be selected for pagination.
[Item 8] The memory device of claim 7, wherein the write command includes a program command code; and the write command code is a first write command code and a second write One of the command codes; wherein the first write command code is used to specify the first access mode; the second write command code is used to specify the second access mode and each One size of these additional arrays.
[Item 9] The memory device of claim 8, wherein the logic unit is constructed:
Determining, by the write command code in the write command, the first write command code or the second write command code;
If the write command code is determined to be the first write command code, the write operation is performed in the first access mode; and if the write command code is determined to be the second write command code, The write operation is then performed in the second access mode.
[Item 10] The memory device of claim 1, wherein the logic unit is constructed:
Receiving a erase command that includes an address;
Determining whether the write command specifies to erase a selected array block, a selected additional array block, or whether to simultaneously erase a selected array block and a selected additional array block; and perform an erase operation according to the determination.
[Item 11] A memory device comprising:
A memory array comprising a plurality of pages for storing array data and a plurality of additional arrays corresponding to respective pages for storing additional data;
A logic unit, connected to the memory array, is constructed to:
Receiving a write command comprising a page address of the selected page and the data to be written; and performing a read operation in a first access mode or a second access;
Wherein, in the first access mode, the logic unit writes the received data into the selected page; and in the second access mode, the logic unit writes the received data to the Select the pagination and the additional array that should be selected for pagination.
[Item 12] The memory device of claim 11, wherein the write instruction specifies whether the write operation is performed in the first access mode or the second access; the write command includes a write command And the write command code is one of a first write command code and a second write command code; wherein the first write command code is used to specify the first access mode The second write command code is used to specify the second access mode and a size of each of the additional arrays.
[Item 13] The memory device of claim 12, wherein the logic unit is constructed:
Determining, by the write command code in the write command, the first write command code or the second write command code;
If the write command code is determined to be the first write command code, the write operation is performed in the first access mode; and if the write command code is determined to be the second write command code, The write operation is then performed in the second access mode.
[Item 14] The memory device of claim 11, further comprising a non-volatile memory for storing whether to perform a memory access in the first access mode or the second access mode. Access information for operations; wherein the logic unit includes an internal register, and the logic unit is constructed to:
Loading the access information from the non-volatile memory into the internal register;
Setting a built-in access mode according to the access information in the internal register; and performing the write operation according to the built-in access mode.
[Item 15] The memory device of claim 14, wherein the logic unit is constructed:
Receiving an instruction to change the access information in the internal register;
And changing the access information in the internal register according to the received instruction; and setting the built-in access mode according to the changed access information in the internal register.
[Item 16] A method of operating a memory device, the memory device comprising a plurality of array blocks for storing array data, and a plurality of additional array blocks corresponding to the array blocks for storing additional data, the method include:
Receiving a read command including a read command code;
Determining whether the read command code is a first read command code or a second read command code;
If the read command code is determined to be the first read command code, sequentially reading the array data stored in the array blocks; and if the read command code is determined to be the second read The command code sequentially reads the array data stored in the array blocks and the additional data stored in the additional array blocks.