TW201630480A - Circuit layout structure, circuit board and electronic assembly - Google Patents

Abstract

A circuit layout structure is suitable for a circuit board and includes the following elements. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside thereof through the first patterned conductive layer respectively, and extend between the chip area and a port area of the circuit board through the second patterned conductive layer respectively. The first ground plane is constructed by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair relative to the first patterned conductive layer overlap the first ground plane.

Description

Line layout structure, circuit board and electronic assembly

The present invention relates to a circuit board, and more particularly to a circuit layout structure suitable for a circuit board for reducing signal interference, and a circuit board and an electronic assembly using the circuit layout structure.

The application of USB 3.0 is quite popular today, but electromagnetic interference (EMI) / radio frequency interference (RFI) problems may occur at frequencies around 2.5 GHz. This is because USB 3.0 has a data rate of 5 Gbps and its clock frequency falls at 2.5 GHz. Therefore, devices operating at approximately 2.5 GHz (such as the wireless module of a wireless mouse) may be disabled by the USB 3.0 signal.

For example, a USB 3.0 hub has a circuit board and a USB 3.0 chip and a USB 3.0 electrical connector mounted on the circuit board, while a USB 3.0 chip typically connects the USB 3.0 electrical connector via a surface line of the circuit board. . When the USB 3.0 hub is made of plastic and does not have a proper metal shield, the RF interference from the USB 3.0 signal (2.5 GHz) transmitted by the surface line of the board falls to approximately 2.5 GHz. . Such electromagnetic interference/radio frequency interference may affect the wireless module of a wireless mouse operating at 2.4 GHz.

The invention provides a circuit layout structure, which is suitable for a circuit board, and is used for reducing external interference generated when transmitting signals.

The invention provides a circuit board for reducing external interference generated when transmitting signals.

The invention provides an electronic assembly for reducing external interference generated when transmitting signals.

A circuit layout structure of the present invention is applicable to a circuit board. The circuit board has a wafer area, a port area, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer and a plurality of conductive vias. The first patterned conductive layer and the second patterned conductive layer are separated by a dielectric layer. The conductive vias are electrically connected to the first patterned conductive layer and the second patterned conductive layer. The circuit layout structure includes a first differential pair, a second differential pair, a first ground plane, and a second ground plane. A first differential pair extends from the wafer region to the outside of the wafer region via the first patterned conductive layer and extends between the wafer region and the port region via the second patterned conductive layer. A second differential pair extends from the wafer region to the outside of the wafer region via the first patterned conductive layer and extends between the wafer region and the port region via the second patterned conductive layer. The first ground plane is formed from the first patterned conductive layer. An orthographic projection of the first differential pair on the second patterned conductive layer overlaps the first ground plane. An orthographic projection of the second differential pair on the second patterned conductive layer overlaps the first ground plane. The second ground plane is formed from the second patterned conductive layer and has a first opening and a second opening. The first differential pair and the second differential pair extend through the second patterned conductive layer in the first opening and the second opening, respectively.

A circuit board of the present invention includes a plurality of patterned conductive layers, a plurality of dielectric layers alternately stacked with the patterned conductive layers, and through the dielectric layers to connect the patterned conductive layers. These members constitute the above-described line layout structure.

An electronic assembly of the present invention includes a circuit board having a wafer area and a port area, a wafer mounted to the wafer area, and an electrical connector mounted to the port area. The circuit board has the above-described line layout structure.

Based on the above, in the present invention, the first differential pair and the second differential pair originally disposed on the first patterned conductive layer are lowered to the second patterned conductive layer, and are vertically blocked by the first ground plane and The horizontal occlusion of the second ground plane reduces the external interference generated by the first differential pair and the second differential when transmitting the signal.

The above described features and advantages of the invention will be apparent from the following description.

Referring to FIG. 1 , in the embodiment, the electronic assembly 10 includes a wafer 12 , an electrical connector 14 , and a circuit board 50 . The circuit board 50 has a wafer area 50a and a port area 50b. A wafer 12, such as a USB 3.0 or 3.1 wafer, is mounted to the wafer area 50a. An electrical connector 14 (such as a USB 3.0 or 3.1 electrical connector) is mounted to port area 50b. Thus, the wafer 12 positioned in the wafer region 50a can be electrically connected via the wiring board 50 to the electrical connector 14 located in the port region 50b.

Referring to FIG. 2, in the embodiment, the circuit board 50 includes a plurality of patterned conductive layers, a plurality of dielectric layers, and a plurality of conductive vias. The patterned conductive layers and the dielectric layers are alternately stacked, and the conductive vias pass through the dielectric layers to connect the patterned conductive layers.

The patterned conductive layers include a first patterned conductive layer 51-1, a second patterned conductive layer 51-2, a third patterned conductive layer 51-3, and a fourth patterned conductive layer 51-4. The dielectric layers include a dielectric core layer 52-0, a first dielectric layer 52-1, and a second dielectric layer 52-2. These conductive vias include a plurality of conductive vias 53-1, 53-2, and 53-3. The dielectric core layer 52-0 is located between the second patterned conductive layer 51-2 and the third patterned conductive layer 51-3, and is electrically connected to the second patterned conductive layer 51-2 by the conductive via 53-1. And a third patterned conductive layer 51-3. The first dielectric layer 52-1 is located between the first patterned conductive layer 51-1 and the second patterned conductive layer 51-2, and is electrically connected to the first patterned conductive layer 51 by conductive vias 53-2. 1 and a second patterned conductive layer 51-2. The second dielectric layer 52-2 is located between the third patterned conductive layer 51-3 and the fourth patterned conductive layer 51-4, and electrically connected to the third patterned conductive layer 51 by the conductive vias 53-3. 3 and a fourth patterned conductive layer 51-4. The thickness of the dielectric core layer 52-0 is greater than the thickness of the first dielectric layer 52-1 and the second dielectric layer 52-2. The first solder mask layer 52-3 covers the first patterned conductive layer 51-1. The second solder mask layer 52-4 covers the fourth patterned conductive layer 51-4. In this embodiment, the third patterned conductive layer 51-3 substantially constitutes a power plane. In another embodiment, the third patterned conductive layer 51-3 substantially constitutes a non-ground plane. Such as the signal plane. In the present embodiment, the circuit board 50 can be regarded as a four-layer board. In this embodiment, the plurality of conductive vias 53-1, 53-2, and 53-3 directly penetrate the first patterned conductive layer 51-1, the second patterned conductive layer 51-2, and the third patterned conductive Layer 51-3 and fourth patterned conductive layer 51-4. In other embodiments, the plurality of conductive vias are not directly through the patterned conductive layers (not shown).

The circuit board 50 further includes a line layout structure 100 including a first differential pair 110, a second differential pair 120, and a third differential pair 130. The first differential pair 110 includes a pair of signal paths, such as a transmit differential pair Tx+ and Tx- that is compatible with USB 3.0 or USB 3.1. The second differential pair 120 includes a pair of signal paths, such as a receive differential pair Rx+ and Rx- that are compatible with USB 3.0 or USB 3.1. It should be noted that the positions of the first differential pair 110 and the second differential pair 120 in FIG. 4 are only examples, and are not intended to limit the present invention. The third differential pair 130 includes a pair of signal paths, such as a transmit/receive differential pair D+ and D- that are compatible with USB 1.0 or USB 2.0. In general, the transmit/receive differential signal terminals (D+ and D-) are half-duplex transmission mode, that is, the transmission or reception of signals can only be performed one by one. That is to say, when data transmission is performed, data reception cannot be performed, and when data reception is performed, data transmission cannot be performed. In addition, in the USB 3.0 or USB 3.1 architecture, the differential signal terminals (Tx+ and Tx-) and the receiving differential signal terminals (Rx+ and Rx-) are in a full-duplex transmission mode, that is, the transmission or reception of signals can be Directly.

It is worth noting that in the currently known circuit boards, for the line layout structure connected between the USB 3.0 chip and the USB 3.0 electrical connector, the three pairs of differential pairs are arranged in a non-ground patterned conductive layer ( For example, the first patterned conductive layer 51-1) of FIG. 2 has a ground plane adjacent thereto (eg, the second patterned conductive layer 51-2 of FIG. 2). However, the USB 3.0 or USB 3.1 transmission differential pair or receiving differential pair located in the ungrounded patterned conductive layer may be in the process of signal transmission or reception, for other components (eg wireless mouse wireless module) ) Causes electromagnetic interference (EMI) / radio frequency interference (RFI). Accordingly, the present invention proposes a new circuit layout structure to improve the above problems.

Referring to FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the first differential pair 110 extends from the inside of the wafer region 50a to the outside of the wafer region 50a via a pair of traces T1 of the first patterned conductive layer 51-1, and The second patterned conductive layer 51-2 is connected downward via a pair of conductive vias 53-2. Next, the first differential pair 110 extends between the wafer region 50a and the port region 50b via a pair of traces T2 of the second patterned conductive layer 51-2, and is connected upward via another pair of conductive vias 53-2. A patterned conductive layer 51-1 is patterned. Finally, the first differential pair 110 extends from the outside of the port region 50b (eg, the component region) to the port region 50b via another pair of traces T1 of the first patterned conductive layer 51-1. In the present embodiment, the circuit board 50 further has an element region 50c, and the first differential pair 110 can extend through the element region 50c via the at least one pair of traces T1 of the first patterned conductive layer 51-1, and then from the port The area 50b extends outside the port area 50b. The element region 50c may be provided with a capacitor, an electrostatic discharge protection device, or the like. In another embodiment, the first patterned conductive layer 51-1 is not configured with the element region 50c, and the first differential pair 110 is in the wafer region 50a via a pair of traces T2 of the second patterned conductive layer 51-2. Extending from between the port region 50b, and connecting the first patterned conductive layer 51-1 upward through the other pair of conductive vias 53-2 in the port region 50b.

Referring to FIG. 2, FIG. 3, FIG. 4 and FIG. 5, similar to the first differential pair 110, the second differential pair 120 is from the wafer region 50a via a pair of traces T1 of the first patterned conductive layer 51-1. The film region 50a is extended outside and connected to the second patterned conductive layer 51-2 via a pair of conductive vias 53-2. Next, the second differential pair 120 extends between the wafer region 50a and the port region 50b via a pair of traces T2 of the second patterned conductive layer 51-2, and is connected upward via another pair of conductive vias 53-2. A patterned conductive layer 51-1 is patterned. Finally, the second differential pair 120 extends from the outside of the port region 50b (eg, the component region) to the port region 50b via the other pair of traces T1 of the first patterned conductive layer 51-1. In the present embodiment, the second differential pair 120 may extend through the element region 50c via at least one pair of traces T1 of the first patterned conductive layer 51-1 and extend from the outside of the port region 50b into the port region 50b. The element region 50c may be provided with a capacitor, an electrostatic discharge protection device, or the like. In another embodiment, the first patterned conductive layer 51-1 is not configured with the element region 50c, and the second differential pair 120 is in the wafer region 50a via the pair of traces T2 of the second patterned conductive layer 51-2. Extending from between the port region 50b, and connecting the first patterned conductive layer 51-1 upward through the other pair of conductive vias 53-2 in the port region 50b.

Referring to FIG. 3, FIG. 4 and FIG. 5, the first differential pair 110 extends to a portion of the first patterned conductive layer 51-1 (ie, a pair of traces T1) to the outside of the wafer region 50a, and then through the second patterning. A portion of the conductive layer 51-2 (i.e., a pair of traces T2) continues to extend, and finally extends to a port region 50b via a portion of the first patterned conductive layer 51-1 (i.e., another pair of traces T1). The second differential pair 120 has an extension similar to the first differential pair 110. Referring to FIG. 3, FIG. 4 and FIG. 6, different from the first differential pair 110 and the second differential pair 120, the third differential pair 130 passes through a portion of the first patterned conductive layer 51-1 (ie, a pair) The trace T1) extends directly from the wafer region 50a to the port region 50b. The main extension of the first differential pair 110 and the second differential pair 120 is moved from the first patterned conductive layer 51-1 to the second patterned conductive layer 51-2, in addition to reducing the congestion of the traces, It can be shielded by the ground plane G of the first patterned conductive layer 51-1, and is reduced by external interference generated when the signal is transmitted, such as electromagnetic interference/radio frequency interference. For a more detailed description of the ground plane G, refer to the following description.

Referring to FIG. 2 , FIG. 3 and FIG. 4 , the circuit layout structure 100 further includes a first ground plane 150 and a second ground plane 160 . The first ground plane 150 is formed from the first patterned conductive layer 51-1. The orthographic projection of the first differential pair 110 on the second patterned conductive layer 51-2 overlaps the first ground plane 150. The orthographic projection of the second differential pair 120 on the second patterned conductive layer 51-2 overlaps the first ground plane 150. The second ground plane 160 is formed from the second patterned conductive layer 51-2 and has a first opening 160a and a second opening 160b. The first differential pair 110 extends within the first opening 160a via the second patterned conductive layer 51-2. The second differential pair 120 extends within the second opening 160b via the second patterned conductive layer 51-2. In other words, each opening 160a, 160b passes through only one pair of differential pairs 110 or 120, rather than two pairs of differential pairs sharing the same opening. A portion of the second ground plane 160 is further located between the first differential pair 110 and the second differential pair 120. In other words, a portion of the second ground plane 160 is disposed between the first opening 160a and the second opening 160b. Therefore, in the embodiment of the present invention, the differential pairs 110 and 120 for transmitting signals are disposed on the ground plane, and the first differential pair 110 and the second differential pair 120 are vertically blocked by the first ground plane 150 and The horizontal occlusion of the two ground planes 160 can reduce the external interference generated when transmitting signals, such as electromagnetic interference/radio frequency interference.

Referring to FIG. 3 and FIG. 4 , some conductive vias 53 - 2 are located beside the first differential pair 110 and the second differential pair 120 . In addition, some of the conductive vias 53-2 are located between the first differential pair 110 and the second differential pair 120. In other words, the conductive vias 53-2 extend along the extending direction of the first differential pair 110 in the first opening 160a of the second patterned conductive layer 51-2; the conductive vias 53-2 are along the second The differential pair 120 extends in a direction extending in the second opening 160b of the second patterned conductive layer 51-2. It is worth mentioning that the conductive vias 53-2 are located beside the first differential pair 110 and the second differential pair 120, or between the first differential pair 110 and the second differential pair 120, It helps to improve the shielding effect of the first ground plane 150 and the second ground plane 160.

Moreover, in the present embodiment, the first differential pair 110 can be a transmit differential pair Tx+ and Tx- compatible with USB 3.0 or USB 3.1. The second differential pair 120 can be a receiving differential pair Rx+ and Rx- compatible with USB 3.0 or USB 3.1, and the third differential pair 130 can be a transmission/reception difference compatible with USB 1.0 or USB 2.0. Move to D+ and D-. Further, the first extension pair 110 and the main extension trace T2 of the second differential pair 120 are disposed on the second patterned conductive layer 51-2, and the main extension trace T1 of the third differential pair 130 is disposed in the first A patterned conductive layer 51-1 is patterned. In other words, the first differential pair 110 and the second differential pair 120 are in the same layer as the ground, and the first differential pair 110 or the second differential pair 120 and the third differential pair 130 are in different layers. Therefore, when the first differential pair 110 and the second differential pair 120 transmit a USB 3.0 or USB 3.1 signal (a clock frequency of about 2.5 GHz), external interference (such as electromagnetic interference/radio frequency interference) may be received. The vertical occlusion of the first ground plane 150 and the horizontal occlusion of the second ground plane 160 are reduced. In addition, the third differential pair 130 has a problem of no specific frequency interference due to the transmission of the USB 1.0 or USB 2.0 signal, and thus can be configured on the uppermost layer as in the prior art (eg, the first patterned conductive layer 51-1 of the present case). .

Referring to FIG. 1 , FIG. 3 and FIG. 4 , in the embodiment, the electrical connector 14 can be plugged into a wireless module 20 corresponding to a wireless mouse 30 . The wireless module 20 and the wireless mouse 30 wirelessly transmit signals. When the clock frequency (2.5 GHz) of the signal transmitted by the first differential pair 110 and the second differential pair 120 of FIG. 4 is substantially equal to or close to the operating frequency (2.4 GHz) of the wireless module 20, the first difference is The electromagnetic waves generated by the movable pair 110 and the second differential pair 120 may be vertically blocked by the first ground plane 150 and horizontally blocked by the second ground plane 160 to reduce radio frequency interference to the wireless module 20, so that the wireless sliding Rat 30 can function normally.

In summary, in the present invention, the first differential pair and the second differential originally disposed on the ungrounded patterned conductive layer are adjusted to the patterned conductive layer for grounding, and by the first ground plane The vertical occlusion and the horizontal occlusion of the second ground plane reduce the external interference caused by the first differential pair and the second differential when transmitting the signal.

For devices using USB 3.0 (clock frequency at 2.5 GHz) as a transport protocol (such as a hub) and devices with a current operating frequency of 2.5 GHz, the present invention can reduce the external interference generated by the device itself to reduce the operating frequency. Radio frequency interference at 2.4 GHz (close to 2.5 GHz) wireless devices (such as wireless modules for wireless mice).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Electronic assembly
12‧‧‧ wafer
14‧‧‧Electrical connector
20‧‧‧Wireless Module
30‧‧‧Wireless mouse
50‧‧‧ circuit board
50a‧‧‧ wafer area
50b‧‧‧Port Area
50c‧‧‧Component area
51-1‧‧‧First patterned conductive layer
51-2‧‧‧Second patterned conductive layer
51-3‧‧‧ Third patterned conductive layer
51-4‧‧‧The fourth patterned conductive layer
52-0‧‧‧ dielectric core layer
52-1‧‧‧First dielectric layer
52-2‧‧‧Second dielectric layer
52-3‧‧‧First welding cap layer
52-4‧‧‧Second welding cap
53-1‧‧‧ conductive through hole
53-2‧‧‧ conductive through hole
53-3‧‧‧Electrical through hole
100‧‧‧Line layout structure
110‧‧‧First differential pair
120‧‧‧Second differential pair
130‧‧‧ third differential pair
150‧‧‧First ground plane
160‧‧‧Second ground plane
160a‧‧‧first opening
160b‧‧‧ second opening
G‧‧‧ Ground plane
T1, T2‧‧‧ trace

1 is a schematic diagram of an electronic assembly in accordance with an embodiment of the present invention. 2 is a schematic cross-sectional view of the wiring board of FIG. 1. 3 is a partial plan view of the first patterned conductive layer of FIG. 2. 4 is a partial plan view of the second patterned conductive layer of FIG. 2. FIG. 5 is a partial plan view showing a signal path of the first differential pair of FIG. 1. FIG. 6 is a partial plan view showing a signal path of the third differential pair of FIG. 1.

50a‧‧‧ wafer area

50b‧‧‧Port Area

50c‧‧‧Component area

51-1‧‧‧First patterned conductive layer

53-2‧‧‧ conductive through hole

100‧‧‧Line layout structure

110‧‧‧First differential pair

120‧‧‧Second differential pair

130‧‧‧ third differential pair

150‧‧‧First ground plane

T1‧‧‧Wiring

Claims (22)

A circuit layout structure is applicable to a circuit board having a wafer area, a port area, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer and a plurality of conductive vias. The first patterned conductive layer and the second patterned conductive layer are separated by the dielectric layer, and the conductive vias are electrically connected to the first patterned conductive layer and the second patterned conductive layer, and the circuit layout structure The method includes: a first differential pair extending from the wafer region to the outside of the wafer region via the first patterned conductive layer, the first differential pair being in the wafer region and the port via the second patterned conductive layer Extending between the regions; a second differential pair extending from the wafer region to the outside of the wafer region via the first patterned conductive layer, the second differential pair being in the wafer region via the second patterned conductive layer Extending from the port region; a first ground plane formed from the first patterned conductive layer, an orthographic projection of the first differential pair on the second patterned conductive layer overlapping the first ground plane, And the second differential pair is on the second patterned conductive layer The front projection overlaps the first ground plane; and a second ground plane is formed from the second patterned conductive layer and has a first opening and a second opening, the first differential pair and the second The differential pair extends within the first opening and the second opening via the second patterned conductive layer. The circuit layout structure of claim 1, further comprising a third differential pair, wherein the third differential pair and the first differential pair and/or the second differential pair are respectively disposed in different layers. The line layout structure according to claim 2, wherein the first differential pair is a transmission differential pair Tx+ and Tx- compatible with USB 3.0 or USB 3.1, and the second differential pair is compatible. A differential pair Rx+ and Rx- is received in USB 3.0 or USB 3.1, and the third differential pair is a transmit/receive differential pair D+ and D- compatible with USB 1.0 or USB 2.0. The circuit layout structure of claim 1, wherein the conductive vias are located adjacent to the first differential pair and the second differential pair, the conductive vias are located in the first differential pair and the A combination of the second differential pair or a combination of the two. The circuit layout structure of claim 1, wherein the first differential pair extends from outside the port area to the port area via the first patterned wire layer, and the second differential pair passes through the A first patterned wire layer extends from outside the port region to the port region. The circuit layout structure of claim 1, wherein a portion of the second ground plane is between the first differential pair and the second differential pair. A circuit board suitable for mounting a chip and an electrical connector, the circuit board having a wafer area on which the wafer is mounted and a port area on which the electrical connector is mounted, the circuit board comprising: a plurality of patterned conductive layers, including a first patterned conductive layer and a second patterned conductive layer, wherein the first patterned conductive layer is located at an outermost side of the patterned conductive layers, and the second patterned conductive layer and the first patterned Adjacent to the conductive layer; a plurality of dielectric layers alternately overlapping the patterned conductive layers; a plurality of conductive vias passing through the dielectric layers to connect the patterned conductive layers; and a line layout structure The method includes: a first differential pair extending from the wafer region to the outside of the wafer region via the first patterned conductive layer, the first differential pair being in the wafer region via the second patterned conductive layer Extending between the port regions; a second differential pair extending from the wafer region to the outside of the wafer region via the first patterned conductive layer, the second differential pair being on the wafer via the second patterned conductive layer Extending between the zone and the port zone; a ground plane formed from the first patterned conductive layer, an orthographic projection of the first differential pair on the second patterned conductive layer is overlapped with the first ground plane, and the second differential pair is at the second An orthographic projection on the patterned conductive layer is overlapped with the first ground plane; and a second ground plane is formed from the second patterned conductive layer and has a first opening and a second opening, the first differential And the second differential pair extends through the second patterned conductive layer in the first opening and the second opening, respectively. The circuit board structure of claim 7 further comprising a third differential pair, wherein the third differential pair and the first differential pair and/or the second differential pair are respectively disposed at Different layers. The circuit board of claim 8, wherein the first differential pair is a transmission differential pair Tx+ and Tx- compatible with USB 3.0 or USB 3.1, and the second differential pair is compatible with A receiving differential pair Rx+ and Rx- of USB 3.0 or USB 3.1, and the third differential pair is a transmit/receive differential pair D+ and D- compatible with USB 1.0 or USB 2.0. The circuit board of claim 7, wherein the conductive vias are located adjacent to the first differential pair and the second differential pair, and the conductive vias are located in the first differential pair and the first A combination of two differential pairs or a combination of the two. The circuit board of claim 7, wherein the first differential pair extends from outside the port area to the port area via the first patterned wire layer, and the second differential pair is via the first A patterned wire layer extends from outside the port region to the port region. The circuit board of claim 7, wherein a portion of the second ground plane is between the first differential pair and the second differential pair. The circuit board of claim 7, wherein the patterned conductive layer further comprises a third patterned conductive layer and a fourth patterned conductive layer, the dielectric layers comprising a dielectric core layer, a first dielectric layer and a second dielectric layer, the first dielectric layer is between the first patterned conductive layer and the second patterned conductive layer, and the dielectric core layer is located in the second patterned Between the conductive layer and the third patterned conductive layer, the second dielectric layer is located between the third patterned conductive layer and the fourth patterned conductive layer, and the thickness of the dielectric core layer is greater than the The thickness of the first dielectric layer and the second dielectric layer. The circuit board of claim 13, wherein the third patterned conductive layer substantially constitutes a power plane. An electronic assembly comprising: a circuit board having a wafer area and a port area, the circuit board comprising: a plurality of patterned conductive layers, including a first patterned conductive layer and a second patterned conductive layer, wherein The first patterned conductive layer is located at an outermost side of the patterned conductive layers, and the second patterned conductive layer is adjacent to the first patterned conductive layer; a plurality of dielectric layers, and the patterned conductive layers The layers are alternately stacked; a plurality of conductive vias passing through the dielectric layers to connect the patterned conductive layers; and a line layout structure comprising: a first differential pair via which the first patterned conductive a layer extending from the wafer region to outside the wafer region, the first differential pair extending between the wafer region and the port region via the second patterned conductive layer, and the first differential pair is via the first a patterned wire layer extending from outside the port region to the port region; a second differential pair extending from the wafer region to the outside of the wafer region via the first patterned conductive layer, the second differential pair being The second patterned conductive layer is in the wafer area and the port Extending between the regions, and the second differential pair extends from outside the port region to the port region via the first patterned wire layer; a first ground plane formed from the first patterned conductive layer, the first An orthographic projection of a differential pair on the second patterned conductive layer overlaps the first ground plane, and an orthographic projection of the second differential pair on the second patterned conductive layer overlaps the first ground plane And a second ground plane formed from the second patterned conductive layer and having a first opening and a second opening, the first differential pair and the second differential pair being electrically conductive via the second pattern Layers extend in the first opening and the second opening, respectively; a wafer mounted on the wafer area of the circuit board; and an electrical connector mounted in the port area of the circuit board. The electronic assembly of claim 15, wherein the line layout structure further comprises a third differential pair, the third differential pair and the first differential pair and/or the second differential pair respectively Configured at different layers. The electronic assembly of claim 16, wherein the first differential pair is a transmission differential pair Tx+ and Tx- compatible with USB 3.0 or USB 3.1, the second differential pair being compatible A differential pair Rx+ and Rx- is received in USB 3.0 or USB 3.1, and the third differential pair is a transmit/receive differential pair D+ and D- compatible with USB 1.0 or USB 2.0. The electronic assembly of claim 15, wherein the conductive vias are located adjacent to the first differential pair and the second differential pair, the conductive vias are located at the first differential pair and A combination of the second differential pair or a combination of the two. The electronic assembly of claim 15, wherein the first differential pair extends from outside the port region to the port region via the first patterned wire layer, and the second differential pair passes through the port A first patterned wire layer extends from outside the port region to the port region. The electronic assembly of claim 15, wherein a portion of the second ground plane is between the first differential pair and the second differential pair. The electronic assembly of claim 15, wherein the patterned conductive layer further comprises a third patterned conductive layer and a fourth patterned conductive layer, the dielectric layers comprising a dielectric core layer a first dielectric layer and a second dielectric layer, the first dielectric layer is between the first patterned conductive layer and the second patterned conductive layer, and the dielectric core layer is located in the second pattern Between the conductive layer and the third patterned conductive layer, the second dielectric layer is located between the third patterned conductive layer and the fourth patterned conductive layer, and the thickness of the dielectric core layer is greater than The thickness of the first dielectric layer and the second dielectric layer. The electronic assembly of claim 15, wherein the electrical connector is adapted to be plugged into a wireless module, and the operating frequency of the wireless module is substantially the same as the first differential pair or the second The clock frequency of the transmitted signal.