TW201630114A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as and a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

Description

Semiconductor structure and method of manufacturing same 【0001】

The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor structure including two sets of tandem select lines and a method of fabricating the same.

【0002】

In order to reduce the size, reduce the weight, increase the power density, and improve the portability, researchers and engineers have tried their best to increase the density of semiconductor devices. One such method is to replace the traditional 2D structure with a 3D structure. Another approach is to reduce the size of each component in the device. Both of these methods have their technical bottlenecks that need to be broken.

[0003]

The present invention relates to a semiconductor structure and a method of fabricating the same, whereby a two-dimensional structure on a physical basis can be achieved.

[0004]

According to an embodiment, a semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of stacked layers, a blocking layer-trapping layer-tunneling layer structure, a plurality of channel layers, a first insulating material, and a Dielectric layer. The stack is formed on the substrate. The stacks respectively comprise a set of alternating stacked conductive strips and insulating strips and a first series of select lines, the first series of select lines being formed on the set of alternating stacked conductive strips and insulating strips. Barrier Layer - Capture Layer - The tunneling layer structure is formed on the stack. The barrier layer-capture layer-tunnel layer structure is conformal to the stack. The channel layer is formed on the barrier layer-capture layer-tunnel layer structure. The channel layer is conformal to the stack. A first insulating material is formed between the stacks. The first insulating material covers a portion of the channel layer. A dielectric layer is formed on a portion of the channel layer that is not covered by the first insulating material. The semiconductor structure further includes a plurality of second series select lines. A second series of select lines are formed between the stacks on the first insulating material. The second series of select lines are separated from the channel layer by a dielectric layer.

[0005]

According to an embodiment, a method of fabricating a semiconductor structure is provided. This manufacturing method includes the following steps. A substrate is provided. Forming a plurality of stacked on the substrate. The stacks respectively comprise a set of alternating stacked conductive strips and insulating strips and a first series of select lines, the first series of select lines being formed on the set of alternating stacked conductive strips and insulating strips. A barrier layer-capture layer-through tunnel layer structure is formed on the stack. The barrier layer-capture layer-tunnel layer structure is conformal to the stack. A plurality of channel layers are formed on the barrier layer-capture layer-tunnel layer structure. The channel layer is conformal to the stack. A first insulating material is formed between the stacks. The first insulating material covers a portion of the channel layer. A dielectric layer is formed over a portion of the channel layer that is not covered by the first insulating material. Forming a plurality of second series of select lines between the stacks on the first insulating material. The second series of select lines are separated from the channel layer by a dielectric layer.

[0006]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0040]

102, 202‧‧‧ substrate
104‧‧‧ buried layer
106, 206‧‧‧
108, 208‧‧‧ Conductive strips
110, 210‧‧‧Insulation strip
112, 212, 1120‧‧‧ first insulation
114, 114-1, 114-2, 214, 214-1, 214-2‧‧‧ first string selection line
116, 216, 1160‧‧‧ second insulation layer
118, 218, 1180‧‧‧ third insulation
120, 220‧ ‧ ‧ barrier layer - capture layer - tunneling structure
122, 222‧‧‧ channel layer
124, 224, 1240, 1241‧‧‧ first insulating material
126, 226, 1260‧ ‧ second insulation material
128, 228‧‧‧ dielectric layer
130, 130-1, 130-2, 130-3, 230, 230-1, 230-2, 230-3‧‧‧ second serial selection line
132, 232‧‧‧ interlayer dielectric
134, 234‧‧‧ bit line
136, 236‧‧‧ source line
138‧‧‧Perforation
140‧‧‧Perforation
142, 242‧‧‧Insulated embolization
1080‧‧‧ Conductive layer
1110‧‧‧Insulation
1140‧‧‧First string selection layer
H1, h2‧‧‧ hole

【0007】

1 and 2 illustrate a semiconductor structure in accordance with an embodiment.
3 to 15C illustrate steps of a method of fabricating a semiconductor structure in accordance with an embodiment.
16 and 17 illustrate a semiconductor structure in accordance with another embodiment.
FIGS. 18A to 18B and 19A to 19C illustrate steps of a method of fabricating a semiconductor structure according to another embodiment.

[0008]

Please refer to FIG. 1 and FIG. 2, which illustrate a semiconductor structure in accordance with an embodiment. For convenience of description, the semiconductor structure is illustrated as a 3D vertical channel NAND memory structure, but is not limited thereto. The semiconductor structure includes a substrate 102, a plurality of stacks (106-118), a barrier layer-capture layer-tunnel layer structure 120, a plurality of channel layers 122, a first insulating material 124, and a dielectric layer 128.

【0009】

The stack is formed on the substrate 102. The stacks respectively include a set of 106 alternating strips of conductive strips 108 and insulating strips 110 and a first series of select lines 114 formed on the strips 108 and the strips 110 of the stack 106 that are alternately stacked. . The conductive strips 108 may be formed of polysilicon and the insulating strips 110 may be formed of an oxide. The stacks further include a first insulating layer 112, a second insulating layer 116, and a third insulating layer 118, respectively. The first insulating layer 112 is formed between the first series selection line 114 and the conductive strips 108 and the insulating strips 110 which are alternately stacked by the group 106. A second insulating layer 116 is formed on the first series select line 114. The third insulating layer 118 is formed on the second insulating layer 116. The first insulating layer 112 may be formed of an oxide, the second insulating layer 116 may be formed of an oxide, and the third insulating layer 118 may be formed of a nitride (eg, SiN).

[0010]

Barrier Layer - Capture Layer - Tunneling Layer Structure 120 is formed on the stack. Barrier Layer - Capture Layer - The tunneling layer structure 120 is conformal to the stack. In the barrier layer-capture layer-tunnel layer structure 120, the barrier layer is closest to the stack, and the tunnel layer is farthest from the stack. The barrier layer-capture layer-tunnel layer structure 120 can be an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide-nitride-oxide (ONONO) structure, or an oxide-nitrogen A compound-oxide-nitride-oxide-nitride-oxide (ONONONO) structure or the like.

[0011]

The channel layer 122 is formed on the barrier layer-capture layer-tunnel layer structure 120. Channel layer 122 is conformal to the stack. In this embodiment, the channel layers 122 on different stacks are connected to one another. Channel layer 122 may be formed of polysilicon.

[0012]

A first insulating material 124 is formed between the stacks. The first insulating material 124 covers a portion of the channel layer 122. The first insulating material 124 may have a plurality of holes h1 therein. A hole h1 (also referred to as an air gap) extends in the height direction of the stack. The presence of the hole h1 is advantageous for reducing the coupling probability of the two adjacent channel layers 122.

[0013]

Dielectric layer 128 is formed on a portion of channel layer 122 that is not covered by first insulating material 124. More specifically, the dielectric layer 128 can be conformal to the stack and the first insulating material 124 formed between the stacks.

[0014]

The semiconductor structure further includes a plurality of second series select lines 130. A second string select line 130 is formed between the stacks on the first insulating material 124. The second series of select lines 130 and the channel layer 122 are separated by a dielectric layer 128. Dielectric layer 128 acts as a gate oxide for second series select line 130. The first string select line 114 and the second string select line 130 may be connected in opposite directions to the metal lines passing over the structure to facilitate ease of fabrication of the microstructure.

[0015]

The semiconductor structure may further include a second insulating material 126, as shown in FIGS. 15A-15C, and a second insulating material 126 is formed between the stacks. The first insulating material 124 and the second insulating material 126 are adjacent to each other in the extending direction of the stack. The second insulating material 126 may have a plurality of holes h2 therein.

[0016]

The semiconductor structure may further include a buried layer 104 formed on the substrate 102 and stacked on the buried layer 104. The semiconductor structure can further include an interlevel dielectric 132 formed over the stack and the second string select line 130. In this embodiment, one of the two adjacent stacks in the stack is connected to one bit line 134 and the other is connected to a source line 136.

[0017]

In this embodiment, the first series select line 114 and the second series select line 130 together control the current through the channel layer 122, as shown in FIG. In FIG. 2, the first string select lines 114-1, 114-2 and the second string select line 130-2 are turned on, and the second string select lines 130-1, 130- 3 is turned off. Only when both the first string selection line 114-1/114-2 and the second string selection line 130-2 which are close to each other are turned on, current can pass through the channel layer 122 controlled by the two series selection lines. . In this embodiment, the current path is U-shaped. Current can be from the bit line 134 on a stack, through the channel layer 122 on the stack, the connection portion of the channel layer 122 between the stacks, and the channel layer 122 on the adjacent stack to reach the adjacent stack Source line 136 on.

[0018]

FIGS. 3 to 15C illustrate the steps of the method of manufacturing the semiconductor structure as shown in FIGS. 1 to 2 . The maps indicated by "B" and "C" are the cross-sectional views taken from the lines 1-1' and 2-2' in the figure indicated by "A".

[0019]

Referring to FIG. 3, a substrate 102 is provided. A buried layer 104 is selectively formed on the substrate 102 (i.e., this layer may or may not be formed). Then, a set of 1060 alternately stacked conductive layers 1080 and an insulating layer 1100, a first insulating layer 1120, a first tandem select line layer 1140 and a second insulating layer 1160 are sequentially formed on the buried layer 104. The conductive layer 1080 may be formed of a P+ type polysilicon or an N+ type polysilicon, preferably a P+ type polysilicon. The insulating layer 1100 may be formed of an oxide. The first insulating layer 112 may be formed of an oxide. The first series of select line layers 1140 may be formed of polysilicon. The second insulating layer 116 may be formed of an oxide. A third insulating layer 1180 is selectively formed on the second insulating layer 1160. The third insulating layer 1180 may be formed of a nitride such as SiN. The SiN layer is a tensile layer and the underlying oxide/polycrystalline layer is a compressive layer. Therefore, the SiN layer can compensate for film stress and avoid collapse or bending of the wire.

[0020]

Referring to FIG. 4A to FIG. 4B, the conductive layer 1080 and the insulating layer 1100, the first insulating layer 1120, the first tandem selection line layer 1140, the second insulating layer 1160, and the third insulation which are alternately stacked in the group 1060 are patterned. Layer 1180 is stacked on substrate 102 to form a plurality. Each of the stacks 106 includes a plurality of conductive strips 108 and an insulating strip 110 alternately stacked, a conductive strip 108 alternately stacked on the set 106, and a first insulating layer 112 formed on the insulating strip 110. The first insulating layer 112 is formed on the first insulating layer 112. A first series select line 114, a second insulating layer 116 formed on the first string select line 114, and a third insulating layer 118 formed on the second insulating layer 116.

[0021]

Referring to FIGS. 5A-5B, a barrier layer-capture layer-tunnel layer structure 120 is formed on the stack. Barrier Layer - Capture Layer - The tunneling layer structure 120 is conformal to the stack. The barrier layer is closest to the stack and the tunneling layer is farthest from the stack. The barrier layer-capture layer-tunnel layer structure 120 can be an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide-nitride-oxide (ONONO) structure, or an oxide-nitrogen A compound-oxide-nitride-oxide-nitride-oxide (ONONONO) structure. Other films used as barrier layer-capture layer-tunnel layer structures are also suitable for this application.

[0022]

Referring to FIGS. 6A-6B, a plurality of channel layers 122 are formed on the barrier layer-capture layer-tunnel layer structure 120. Channel layer 122 is conformal to the stack. Channel layer 122 is separated from first string select line 114 by barrier layer-capture layer-tunnel layer structure 120. In this embodiment, the channel layers 122 are connected to each other. Channel layer 122 may be formed of undoped or intrinsic polycrystalline germanium.

[0023]

Referring to FIGS. 7A to 7B, a first insulating material 1240 is formed. The first insulating material 1240 is filled into the trenches between the stacks. The first insulating material 1240 can be an oxide. The first insulating material 1240 may have a plurality of holes h1 therein. This can be achieved by using a non-conformal oxide. The hole h1 extends in the height direction of the stack, but the height of the hole h1 does not exceed the second insulating layer 116. The presence of the hole h1 is advantageous for reducing the coupling probability of the two adjacent channel layers 122.

[0024]

Referring to FIGS. 8A to 8C, a plurality of through holes 138 are formed in the first insulating material 1240. The elliptical perforations 138 are arranged in a direction perpendicular to the direction in which the stack extends. The through hole 138 is surrounded by the first insulating material 1241 and penetrates through the first insulating material 1241. When the perforations 138 are formed, a portion of the channel layer 122 is removed. Therefore, the channel layer 122 is not left in the perforations 138. In addition, it is also possible to remove a portion of the barrier layer-capture layer-tunnel layer structure 120.

[0025]

Referring to FIGS. 9A to 9C, a second insulating material 1260 is formed. A second insulating material 1260 is filled into the perforations 138. As such, the second insulating material 1260 is formed as a series of elliptical islands arranged in a direction perpendicular to the direction in which the stack extends. The second insulating material 1260 can be an oxide. The second insulating material 1260 may have a plurality of holes h2 therein. This can be achieved by using a non-conformal oxide. Similar to the hole h1, the hole h2 extends in the height direction of the stack, but the height of the hole h2 does not exceed the second insulating layer 116. If necessary, a Chemical-Mechanical Polishing (CMP) process can be performed.

[0026]

Please refer to the 10A to 10C drawings for an etching-back process. This etchback process is highly selective for polysilicon and will stop at the polysilicon. By this step, the first insulating material 124 leaves only the portion between the stacks, and the second insulating material 126 leaves only the portion between the stacks. The first insulating material 124 covers a portion of the channel layer 122. The first insulating material 124 and the second insulating material 126 are adjacent to each other in the extending direction of the stack. The holes h1 and h2 are not exposed by the etch back process. In one embodiment, dilute hydrofluoric acid can be used to remove sidewall oxide.

[0027]

Referring to FIGS. 11A-11C, a dielectric layer 128 is formed on a portion of the channel layer 122 that is not covered by the first insulating material 124. Dielectric layer 128 may be formed of an oxide. Dielectric layer 128 may be formed by polysilicon of oxide channel layer 122 or may be formed by conformal deposition of an oxide layer. If the hole h1 or h2 is exposed by the previous step, it must be sealed with a conformal deposited oxide at this step. The dielectric layer 128 serves as a gate oxide of the second series select line 130 formed in the next step.

[0028]

Referring to FIGS. 12A to 12C, a plurality of second series selection lines 130 are formed between the stacks on the first insulating material 124. The second series of select lines 130 can be formed by deposition and etching. The second series of select lines 130 and the channel layer 122 are separated by a dielectric layer 128. The second string select line 130 and the first string select line 114 collectively control the channel layer 122.

[0029]

Referring to FIG. 13A to FIG. 13C, an interlayer dielectric 132 may be formed on the stack and the second string selection line 130. The interlayer dielectric 132 can be an oxide and formed by deposition. If necessary, a CMP process can be performed.

[0030]

Referring to FIGS. 14A-14C, a via 140 is formed in the interlayer dielectric 132 on one of two adjacent stacks in the stack, the location of the vias 140 corresponding to the second insulating material 126.

[0031]

Referring to FIGS. 15A to 15C, an insulating plug 142 is formed in the through hole 140. In other words, the insulating plug 142 is formed in the interlayer dielectric 132 on one of two adjacent stacks in the stack, the position of the insulating plug 142 corresponding to the second insulating material 126. The insulating plug 142 can be formed of an oxide. Such a structure is used to isolate the two-way layer 122 on a stack. The channel layer 122 on the other stack remains connected for the source line.

[0032]

Referring now to Figures 16 and 17, there is illustrated a semiconductor structure in accordance with another embodiment. For convenience of description, the semiconductor structure is illustrated as a 3D vertical channel NAND memory structure, but is not limited thereto. In addition to the portions mentioned below, the substrate 202, the conductive strips 208 and the insulating strips 210, the first insulating layer 212, the first series select line 214, the second insulating layer 216, and the third insulating layer are alternately stacked. 218, barrier layer-capture layer-tunnel layer structure 220, channel layer 222, first insulating material 224, hole h1, second insulating material 226, hole h2, dielectric layer 228, second string selection line 230, The method, material, and arrangement of the interlayer dielectric 232, the bit line 234, and the source line 236 are similar to the substrate 102, the conductive strips 108 and the insulating strips 110, the first insulating layer 112, and the first stacked layers 106, respectively. a string of select lines 114, a second insulating layer 116, a third insulating layer 118, a barrier layer-capturing layer-tunneling layer structure 120, a channel layer 122, a first insulating material 124, a hole h1, and a second insulating material 126 The hole h2, the dielectric layer 128, the second series select line 130, the interlayer dielectric 132, the bit line 134, and the source line 136.

[0033]

In this embodiment, the buried layer 204 can be formed on the substrate 202. In this embodiment, the channel layers 222 on different stacks are not connected to each other. In this embodiment, two adjacent stacks in the stack are connected to one bit line 234. The semiconductor structure can further include a source line 236 formed on the substrate 202. The source line 236 can be formed under the stack as shown in FIGS. 16 and 17. Alternatively, source line 236 can be formed at a location that is not in direct contact with the stack.

[0034]

In this embodiment, the first string select line 214 and the second string select line 230 collectively control the current through the channel layer 222, as shown in FIG. In FIG. 17, the first string selection line 214-1 and the second string selection line 230-2 are turned on, and the first string selection line 214-2 and the second string selection line 230-1, 230-3 is blocked. Only when both the first string selection line 214-1 and the second string selection line 230-2 which are close to each other are turned on, current can pass through the channel layer 222 controlled by the two series selection lines. In this embodiment, the current path is I-shaped. Current can flow from the bit line 234 on a stack through the channel layer 222 on the stack to the source line 236 under the stack.

[0035]

FIGS. 18A to 19C illustrate the steps of the method of manufacturing the semiconductor structure as shown in FIGS. 16 to 17. The maps indicated by "B" and "C" are the cross-sectional views taken from the lines 1-1' and 2-2' in the figure indicated by "A". This method is similar to the method described with reference to FIGS. 3 to 15C. Therefore, for the sake of brevity, only the steps which are partially different from the steps described with reference to FIGS. 3 to 15C are shown.

[0036]

Please refer to Fig. 18A to Fig. 18B. This step will replace the steps shown in Fig. 6A to Fig. 6B. In this step, a plurality of channel layers 222 are formed on the barrier-capture layer-tunnel layer structure 220. Unlike the steps shown in FIGS. 6A to 6B, the channel layers 222 on different stacks are not connected to each other.

[0037]

Please refer to Fig. 19A to Fig. 19C. This step will replace the steps shown in Fig. 15A to Fig. 15C. Different from the steps shown in FIG. 15A to FIG. 15C, two insulating plugs 242 are formed in the interlayer dielectric 232 on two adjacent stacks in the stack, and the position of the insulating plug 242 corresponds to the second insulating material 226.

[0038]

In summary, in the semiconductor structure according to the above embodiment, the two second series selection lines are disposed on both sides of the channel layer by a self-aligned process. In this way, the channel layer is divided into one of the first series selection line and the two second series selection lines, and the first series selection line and the two second series selection lines. The second part controlled by the other. Therefore, a two-dimensional structure on the entity can be achieved. It may be noted that the first string select line and the second string select line controlling the one channel layer should be arranged on different sides of the channel layer to avoid poor design rules. For example, the first tandem select line 114-1/214-1 is disposed on the right side, and the second tandem select line 130-1/230-1 is disposed on the left side.

[0039]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧Substrate

104‧‧‧ buried layer

106‧‧‧ group

108‧‧‧ Conductive strip

110‧‧‧Insulation strip

112‧‧‧First insulation

114‧‧‧First string selection line

116‧‧‧Second insulation

118‧‧‧ third insulation

120‧‧‧Block layer-capture layer-tunneling structure

122‧‧‧Channel layer

124‧‧‧First insulation material

128‧‧‧ dielectric layer

130‧‧‧Second serial selection line

132‧‧‧Interlayer dielectric

134‧‧‧ bit line

136‧‧‧ source line

H1‧‧‧ hole

Claims (10)

[Item 1] A semiconductor structure comprising:
a substrate;
A plurality of stacked layers are formed on the substrate, and the stacks respectively include:
a set of alternating conductive strips and insulating strips; and a first series of select lines formed on the alternating stack of conductive strips and insulating strips;
a barrier layer-capture layer-tunnel layer structure formed on the stacks, the barrier layer-capture layer-tunnel layer structure being conformal to the stacks;
a plurality of channel layers formed on the barrier layer-capture layer-tunnel layer structure, the channel layers being conformal to the stacks;
a first insulating material formed between the stacks, the first insulating material covering a portion of the channel layers;
a dielectric layer formed on a portion of the channel layer not covered by the first insulating material; and a plurality of second series selection lines formed between the stacks, the first insulating material, wherein the The second series of select lines are separated from the channel layers by the dielectric layer. [Item 2] The semiconductor structure of claim 1, wherein the first insulating material has a plurality of holes therein. [Item 3] The semiconductor structure of claim 1 further includes:
A second insulating material is formed between the stacks, and the first insulating material and the second insulating material are adjacent to each other in an extending direction of the stacks. [Item 4] The semiconductor structure of claim 3, wherein the second insulating material has a plurality of holes therein. [Item 5] The semiconductor structure of claim 1, wherein the channel layers are connected to each other, and the semiconductor structure further comprises:
A buried layer is formed on the substrate, wherein the stacked layers are formed on the buried layer. [Item 6] A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a plurality of stacked on the substrate, wherein the stacks respectively comprise:
a set of alternating conductive strips and insulating strips; and a first series of select lines formed on the alternating stack of conductive strips and insulating strips;
Forming a barrier layer-capture layer-tunnel layer structure on the stack, the barrier layer-capture layer-tunnel layer structure being conformal to the stacks;
Forming a plurality of channel layers on the barrier layer-capture layer-tunnel layer structure, the channel layers being conformal to the stacks;
Forming a first insulating material between the stacks, the first insulating material covering a portion of the channel layers;
Forming a dielectric layer on a portion of the channel layers not covered by the first insulating material; and forming a plurality of second series select lines between the stacks, the first insulating material, wherein the second The tandem select lines are separated from the channel layers by the dielectric layer.
[Item 7] A method of fabricating a semiconductor structure according to claim 6, wherein the first insulating material has a plurality of holes therein. [Item 8] The manufacturing method of the semiconductor structure of claim 6, after forming the first insulating material and before forming the dielectric layer, further comprising:
Forming a second insulating material between the stacks, wherein the first insulating material and the second insulating material are adjacent to each other in an extending direction of the stacks. [Item 9] A method of fabricating a semiconductor structure according to claim 8, wherein the second insulating material has a plurality of holes therein. [Item 10] A method of fabricating a semiconductor structure according to claim 8, wherein the second insulating material is formed as a series of elliptical islands arranged in a direction perpendicular to an extending direction of the stacks.